1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2014-2015 Hisilicon Limited.
4 */
5
6 #include <linux/cdev.h>
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <asm/cacheflush.h>
13 #include <linux/platform_device.h>
14 #include <linux/spinlock.h>
15
16 #include "hns_dsaf_main.h"
17 #include "hns_dsaf_ppe.h"
18 #include "hns_dsaf_rcb.h"
19
20 #define RCB_COMMON_REG_OFFSET 0x80000
21 #define TX_RING 0
22 #define RX_RING 1
23
24 #define RCB_RESET_WAIT_TIMES 30
25 #define RCB_RESET_TRY_TIMES 10
26
27 /* Because default mtu is 1500, rcb buffer size is set to 2048 enough */
28 #define RCB_DEFAULT_BUFFER_SIZE 2048
29
30 /**
31 *hns_rcb_wait_fbd_clean - clean fbd
32 *@qs: ring struct pointer array
33 *@q_num: num of array
34 *@flag: tx or rx flag
35 */
hns_rcb_wait_fbd_clean(struct hnae_queue ** qs,int q_num,u32 flag)36 void hns_rcb_wait_fbd_clean(struct hnae_queue **qs, int q_num, u32 flag)
37 {
38 int i, wait_cnt;
39 u32 fbd_num;
40
41 for (wait_cnt = i = 0; i < q_num; wait_cnt++) {
42 usleep_range(200, 300);
43 fbd_num = 0;
44 if (flag & RCB_INT_FLAG_TX)
45 fbd_num += dsaf_read_dev(qs[i],
46 RCB_RING_TX_RING_FBDNUM_REG);
47 if (flag & RCB_INT_FLAG_RX)
48 fbd_num += dsaf_read_dev(qs[i],
49 RCB_RING_RX_RING_FBDNUM_REG);
50 if (!fbd_num)
51 i++;
52 if (wait_cnt >= 10000)
53 break;
54 }
55
56 if (i < q_num)
57 dev_err(qs[i]->handle->owner_dev,
58 "queue(%d) wait fbd(%d) clean fail!!\n", i, fbd_num);
59 }
60
hns_rcb_wait_tx_ring_clean(struct hnae_queue * qs)61 int hns_rcb_wait_tx_ring_clean(struct hnae_queue *qs)
62 {
63 u32 head, tail;
64 int wait_cnt;
65
66 tail = dsaf_read_dev(&qs->tx_ring, RCB_REG_TAIL);
67 wait_cnt = 0;
68 while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
69 head = dsaf_read_dev(&qs->tx_ring, RCB_REG_HEAD);
70 if (tail == head)
71 break;
72
73 usleep_range(100, 200);
74 }
75
76 if (wait_cnt >= HNS_MAX_WAIT_CNT) {
77 dev_err(qs->dev->dev, "rcb wait timeout, head not equal to tail.\n");
78 return -EBUSY;
79 }
80
81 return 0;
82 }
83
84 /**
85 *hns_rcb_reset_ring_hw - ring reset
86 *@q: ring struct pointer
87 */
hns_rcb_reset_ring_hw(struct hnae_queue * q)88 void hns_rcb_reset_ring_hw(struct hnae_queue *q)
89 {
90 u32 wait_cnt;
91 u32 try_cnt = 0;
92 u32 could_ret;
93
94 u32 tx_fbd_num;
95
96 while (try_cnt++ < RCB_RESET_TRY_TIMES) {
97 usleep_range(100, 200);
98 tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG);
99 if (tx_fbd_num)
100 continue;
101
102 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0);
103
104 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
105
106 msleep(20);
107 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
108
109 wait_cnt = 0;
110 while (!could_ret && (wait_cnt < RCB_RESET_WAIT_TIMES)) {
111 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
112
113 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
114
115 msleep(20);
116 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
117
118 wait_cnt++;
119 }
120
121 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
122
123 if (could_ret)
124 break;
125 }
126
127 if (try_cnt >= RCB_RESET_TRY_TIMES)
128 dev_err(q->dev->dev, "port%d reset ring fail\n",
129 hns_ae_get_vf_cb(q->handle)->port_index);
130 }
131
132 /**
133 *hns_rcb_int_ctrl_hw - rcb irq enable control
134 *@q: hnae queue struct pointer
135 *@flag:ring flag tx or rx
136 *@mask:mask
137 */
hns_rcb_int_ctrl_hw(struct hnae_queue * q,u32 flag,u32 mask)138 void hns_rcb_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)
139 {
140 u32 int_mask_en = !!mask;
141
142 if (flag & RCB_INT_FLAG_TX) {
143 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
144 dsaf_write_dev(q, RCB_RING_INTMSK_TX_OVERTIME_REG,
145 int_mask_en);
146 }
147
148 if (flag & RCB_INT_FLAG_RX) {
149 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
150 dsaf_write_dev(q, RCB_RING_INTMSK_RX_OVERTIME_REG,
151 int_mask_en);
152 }
153 }
154
hns_rcb_int_clr_hw(struct hnae_queue * q,u32 flag)155 void hns_rcb_int_clr_hw(struct hnae_queue *q, u32 flag)
156 {
157 if (flag & RCB_INT_FLAG_TX) {
158 dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, 1);
159 dsaf_write_dev(q, RCB_RING_INTSTS_TX_OVERTIME_REG, 1);
160 }
161
162 if (flag & RCB_INT_FLAG_RX) {
163 dsaf_write_dev(q, RCB_RING_INTSTS_RX_RING_REG, 1);
164 dsaf_write_dev(q, RCB_RING_INTSTS_RX_OVERTIME_REG, 1);
165 }
166 }
167
hns_rcbv2_int_ctrl_hw(struct hnae_queue * q,u32 flag,u32 mask)168 void hns_rcbv2_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)
169 {
170 u32 int_mask_en = !!mask;
171
172 if (flag & RCB_INT_FLAG_TX)
173 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
174
175 if (flag & RCB_INT_FLAG_RX)
176 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
177 }
178
hns_rcbv2_int_clr_hw(struct hnae_queue * q,u32 flag)179 void hns_rcbv2_int_clr_hw(struct hnae_queue *q, u32 flag)
180 {
181 if (flag & RCB_INT_FLAG_TX)
182 dsaf_write_dev(q, RCBV2_TX_RING_INT_STS_REG, 1);
183
184 if (flag & RCB_INT_FLAG_RX)
185 dsaf_write_dev(q, RCBV2_RX_RING_INT_STS_REG, 1);
186 }
187
188 /**
189 *hns_rcb_ring_enable_hw - enable ring
190 *@q: rcb ring
191 *@val: value to write
192 */
hns_rcb_ring_enable_hw(struct hnae_queue * q,u32 val)193 void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val)
194 {
195 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val);
196 }
197
198 /**
199 *hns_rcb_common_init_commit_hw - make rcb common init completed
200 *@rcb_common: rcb common device
201 */
hns_rcb_common_init_commit_hw(struct rcb_common_cb * rcb_common)202 void hns_rcb_common_init_commit_hw(struct rcb_common_cb *rcb_common)
203 {
204 wmb(); /* Sync point before breakpoint */
205 dsaf_write_dev(rcb_common, RCB_COM_CFG_SYS_FSH_REG, 1);
206 wmb(); /* Sync point after breakpoint */
207 }
208
209 /* hns_rcb_set_tx_ring_bs - init rcb ring buf size regester
210 *@q: hnae_queue
211 *@buf_size: buffer size set to hw
212 */
hns_rcb_set_tx_ring_bs(struct hnae_queue * q,u32 buf_size)213 void hns_rcb_set_tx_ring_bs(struct hnae_queue *q, u32 buf_size)
214 {
215 u32 bd_size_type = hns_rcb_buf_size2type(buf_size);
216
217 dsaf_write_dev(q, RCB_RING_TX_RING_BD_LEN_REG,
218 bd_size_type);
219 }
220
221 /* hns_rcb_set_rx_ring_bs - init rcb ring buf size regester
222 *@q: hnae_queue
223 *@buf_size: buffer size set to hw
224 */
hns_rcb_set_rx_ring_bs(struct hnae_queue * q,u32 buf_size)225 void hns_rcb_set_rx_ring_bs(struct hnae_queue *q, u32 buf_size)
226 {
227 u32 bd_size_type = hns_rcb_buf_size2type(buf_size);
228
229 dsaf_write_dev(q, RCB_RING_RX_RING_BD_LEN_REG,
230 bd_size_type);
231 }
232
233 /**
234 *hns_rcb_ring_init - init rcb ring
235 *@ring_pair: ring pair control block
236 *@ring_type: ring type, RX_RING or TX_RING
237 */
hns_rcb_ring_init(struct ring_pair_cb * ring_pair,int ring_type)238 static void hns_rcb_ring_init(struct ring_pair_cb *ring_pair, int ring_type)
239 {
240 struct hnae_queue *q = &ring_pair->q;
241 struct hnae_ring *ring =
242 (ring_type == RX_RING) ? &q->rx_ring : &q->tx_ring;
243 dma_addr_t dma = ring->desc_dma_addr;
244
245 if (ring_type == RX_RING) {
246 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_L_REG,
247 (u32)dma);
248 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_H_REG,
249 (u32)((dma >> 31) >> 1));
250
251 hns_rcb_set_rx_ring_bs(q, ring->buf_size);
252
253 dsaf_write_dev(q, RCB_RING_RX_RING_BD_NUM_REG,
254 ring_pair->port_id_in_comm);
255 dsaf_write_dev(q, RCB_RING_RX_RING_PKTLINE_REG,
256 ring_pair->port_id_in_comm);
257 } else {
258 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_L_REG,
259 (u32)dma);
260 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_H_REG,
261 (u32)((dma >> 31) >> 1));
262
263 hns_rcb_set_tx_ring_bs(q, ring->buf_size);
264
265 dsaf_write_dev(q, RCB_RING_TX_RING_BD_NUM_REG,
266 ring_pair->port_id_in_comm);
267 dsaf_write_dev(q, RCB_RING_TX_RING_PKTLINE_REG,
268 ring_pair->port_id_in_comm + HNS_RCB_TX_PKTLINE_OFFSET);
269 }
270 }
271
272 /**
273 *hns_rcb_init_hw - init rcb hardware
274 *@ring: rcb ring
275 */
hns_rcb_init_hw(struct ring_pair_cb * ring)276 void hns_rcb_init_hw(struct ring_pair_cb *ring)
277 {
278 hns_rcb_ring_init(ring, RX_RING);
279 hns_rcb_ring_init(ring, TX_RING);
280 }
281
282 /**
283 *hns_rcb_set_port_desc_cnt - set rcb port description num
284 *@rcb_common: rcb_common device
285 *@port_idx:port index
286 *@desc_cnt:BD num
287 */
hns_rcb_set_port_desc_cnt(struct rcb_common_cb * rcb_common,u32 port_idx,u32 desc_cnt)288 static void hns_rcb_set_port_desc_cnt(struct rcb_common_cb *rcb_common,
289 u32 port_idx, u32 desc_cnt)
290 {
291 dsaf_write_dev(rcb_common, RCB_CFG_BD_NUM_REG + port_idx * 4,
292 desc_cnt);
293 }
294
hns_rcb_set_port_timeout(struct rcb_common_cb * rcb_common,u32 port_idx,u32 timeout)295 static void hns_rcb_set_port_timeout(
296 struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout)
297 {
298 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {
299 dsaf_write_dev(rcb_common, RCB_CFG_OVERTIME_REG,
300 timeout * HNS_RCB_CLK_FREQ_MHZ);
301 } else if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) {
302 if (timeout > HNS_RCB_DEF_GAP_TIME_USECS)
303 dsaf_write_dev(rcb_common,
304 RCB_PORT_INT_GAPTIME_REG + port_idx * 4,
305 HNS_RCB_DEF_GAP_TIME_USECS);
306 else
307 dsaf_write_dev(rcb_common,
308 RCB_PORT_INT_GAPTIME_REG + port_idx * 4,
309 timeout);
310
311 dsaf_write_dev(rcb_common,
312 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4,
313 timeout);
314 } else {
315 dsaf_write_dev(rcb_common,
316 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4,
317 timeout);
318 }
319 }
320
hns_rcb_common_get_port_num(struct rcb_common_cb * rcb_common)321 static int hns_rcb_common_get_port_num(struct rcb_common_cb *rcb_common)
322 {
323 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))
324 return HNS_RCB_SERVICE_NW_ENGINE_NUM;
325 else
326 return HNS_RCB_DEBUG_NW_ENGINE_NUM;
327 }
328
329 /*clr rcb comm exception irq**/
hns_rcb_comm_exc_irq_en(struct rcb_common_cb * rcb_common,int en)330 static void hns_rcb_comm_exc_irq_en(
331 struct rcb_common_cb *rcb_common, int en)
332 {
333 u32 clr_vlue = 0xfffffffful;
334 u32 msk_vlue = en ? 0 : 0xfffffffful;
335
336 /* clr int*/
337 dsaf_write_dev(rcb_common, RCB_COM_INTSTS_ECC_ERR_REG, clr_vlue);
338
339 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_RING_STS, clr_vlue);
340
341 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_BD_RINT_STS, clr_vlue);
342
343 dsaf_write_dev(rcb_common, RCB_COM_RINT_TX_PKT_REG, clr_vlue);
344 dsaf_write_dev(rcb_common, RCB_COM_AXI_ERR_STS, clr_vlue);
345
346 /*en msk*/
347 dsaf_write_dev(rcb_common, RCB_COM_INTMASK_ECC_ERR_REG, msk_vlue);
348
349 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_RING, msk_vlue);
350
351 /*for tx bd neednot cacheline, so msk sf_txring_fbd_intmask (bit 1)**/
352 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_BD, msk_vlue | 2);
353
354 dsaf_write_dev(rcb_common, RCB_COM_INTMSK_TX_PKT_REG, msk_vlue);
355 dsaf_write_dev(rcb_common, RCB_COM_AXI_WR_ERR_INTMASK, msk_vlue);
356 }
357
358 /**
359 *hns_rcb_common_init_hw - init rcb common hardware
360 *@rcb_common: rcb_common device
361 *retuen 0 - success , negative --fail
362 */
hns_rcb_common_init_hw(struct rcb_common_cb * rcb_common)363 int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common)
364 {
365 u32 reg_val;
366 int i;
367 int port_num = hns_rcb_common_get_port_num(rcb_common);
368
369 hns_rcb_comm_exc_irq_en(rcb_common, 0);
370
371 reg_val = dsaf_read_dev(rcb_common, RCB_COM_CFG_INIT_FLAG_REG);
372 if (0x1 != (reg_val & 0x1)) {
373 dev_err(rcb_common->dsaf_dev->dev,
374 "RCB_COM_CFG_INIT_FLAG_REG reg = 0x%x\n", reg_val);
375 return -EBUSY;
376 }
377
378 for (i = 0; i < port_num; i++) {
379 hns_rcb_set_port_desc_cnt(rcb_common, i, rcb_common->desc_num);
380 hns_rcb_set_rx_coalesced_frames(
381 rcb_common, i, HNS_RCB_DEF_RX_COALESCED_FRAMES);
382 if (!AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver) &&
383 !HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))
384 hns_rcb_set_tx_coalesced_frames(
385 rcb_common, i, HNS_RCB_DEF_TX_COALESCED_FRAMES);
386 hns_rcb_set_port_timeout(
387 rcb_common, i, HNS_RCB_DEF_COALESCED_USECS);
388 }
389
390 dsaf_write_dev(rcb_common, RCB_COM_CFG_ENDIAN_REG,
391 HNS_RCB_COMMON_ENDIAN);
392
393 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {
394 dsaf_write_dev(rcb_common, RCB_COM_CFG_FNA_REG, 0x0);
395 dsaf_write_dev(rcb_common, RCB_COM_CFG_FA_REG, 0x1);
396 } else {
397 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,
398 RCB_COM_CFG_FNA_B, false);
399 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,
400 RCB_COM_CFG_FA_B, true);
401 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_TSO_MODE_REG,
402 RCB_COM_TSO_MODE_B, HNS_TSO_MODE_8BD_32K);
403 }
404
405 return 0;
406 }
407
hns_rcb_buf_size2type(u32 buf_size)408 int hns_rcb_buf_size2type(u32 buf_size)
409 {
410 int bd_size_type;
411
412 switch (buf_size) {
413 case 512:
414 bd_size_type = HNS_BD_SIZE_512_TYPE;
415 break;
416 case 1024:
417 bd_size_type = HNS_BD_SIZE_1024_TYPE;
418 break;
419 case 2048:
420 bd_size_type = HNS_BD_SIZE_2048_TYPE;
421 break;
422 case 4096:
423 bd_size_type = HNS_BD_SIZE_4096_TYPE;
424 break;
425 default:
426 bd_size_type = -EINVAL;
427 }
428
429 return bd_size_type;
430 }
431
hns_rcb_ring_get_cfg(struct hnae_queue * q,int ring_type)432 static void hns_rcb_ring_get_cfg(struct hnae_queue *q, int ring_type)
433 {
434 struct hnae_ring *ring;
435 struct rcb_common_cb *rcb_common;
436 struct ring_pair_cb *ring_pair_cb;
437 u16 desc_num, mdnum_ppkt;
438 bool irq_idx, is_ver1;
439
440 ring_pair_cb = container_of(q, struct ring_pair_cb, q);
441 is_ver1 = AE_IS_VER1(ring_pair_cb->rcb_common->dsaf_dev->dsaf_ver);
442 if (ring_type == RX_RING) {
443 ring = &q->rx_ring;
444 ring->io_base = ring_pair_cb->q.io_base;
445 irq_idx = HNS_RCB_IRQ_IDX_RX;
446 mdnum_ppkt = HNS_RCB_RING_MAX_BD_PER_PKT;
447 } else {
448 ring = &q->tx_ring;
449 ring->io_base = ring_pair_cb->q.io_base +
450 HNS_RCB_TX_REG_OFFSET;
451 irq_idx = HNS_RCB_IRQ_IDX_TX;
452 mdnum_ppkt = is_ver1 ? HNS_RCB_RING_MAX_TXBD_PER_PKT :
453 HNS_RCBV2_RING_MAX_TXBD_PER_PKT;
454 }
455
456 rcb_common = ring_pair_cb->rcb_common;
457 desc_num = rcb_common->dsaf_dev->desc_num;
458
459 ring->desc = NULL;
460 ring->desc_cb = NULL;
461
462 ring->irq = ring_pair_cb->virq[irq_idx];
463 ring->desc_dma_addr = 0;
464
465 ring->buf_size = RCB_DEFAULT_BUFFER_SIZE;
466 ring->desc_num = desc_num;
467 ring->max_desc_num_per_pkt = mdnum_ppkt;
468 ring->max_raw_data_sz_per_desc = HNS_RCB_MAX_PKT_SIZE;
469 ring->max_pkt_size = HNS_RCB_MAX_PKT_SIZE;
470 ring->next_to_use = 0;
471 ring->next_to_clean = 0;
472 }
473
hns_rcb_ring_pair_get_cfg(struct ring_pair_cb * ring_pair_cb)474 static void hns_rcb_ring_pair_get_cfg(struct ring_pair_cb *ring_pair_cb)
475 {
476 ring_pair_cb->q.handle = NULL;
477
478 hns_rcb_ring_get_cfg(&ring_pair_cb->q, RX_RING);
479 hns_rcb_ring_get_cfg(&ring_pair_cb->q, TX_RING);
480 }
481
hns_rcb_get_port_in_comm(struct rcb_common_cb * rcb_common,int ring_idx)482 static int hns_rcb_get_port_in_comm(
483 struct rcb_common_cb *rcb_common, int ring_idx)
484 {
485 return ring_idx / (rcb_common->max_q_per_vf * rcb_common->max_vfn);
486 }
487
488 #define SERVICE_RING_IRQ_IDX(v1) \
489 ((v1) ? HNS_SERVICE_RING_IRQ_IDX : HNSV2_SERVICE_RING_IRQ_IDX)
hns_rcb_get_base_irq_idx(struct rcb_common_cb * rcb_common)490 static int hns_rcb_get_base_irq_idx(struct rcb_common_cb *rcb_common)
491 {
492 bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver);
493
494 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))
495 return SERVICE_RING_IRQ_IDX(is_ver1);
496 else
497 return HNS_DEBUG_RING_IRQ_IDX;
498 }
499
500 #define RCB_COMM_BASE_TO_RING_BASE(base, ringid)\
501 ((base) + 0x10000 + HNS_RCB_REG_OFFSET * (ringid))
502 /**
503 *hns_rcb_get_cfg - get rcb config
504 *@rcb_common: rcb common device
505 */
hns_rcb_get_cfg(struct rcb_common_cb * rcb_common)506 int hns_rcb_get_cfg(struct rcb_common_cb *rcb_common)
507 {
508 struct ring_pair_cb *ring_pair_cb;
509 u32 i;
510 u32 ring_num = rcb_common->ring_num;
511 int base_irq_idx = hns_rcb_get_base_irq_idx(rcb_common);
512 struct platform_device *pdev =
513 to_platform_device(rcb_common->dsaf_dev->dev);
514 bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver);
515
516 for (i = 0; i < ring_num; i++) {
517 ring_pair_cb = &rcb_common->ring_pair_cb[i];
518 ring_pair_cb->rcb_common = rcb_common;
519 ring_pair_cb->dev = rcb_common->dsaf_dev->dev;
520 ring_pair_cb->index = i;
521 ring_pair_cb->q.io_base =
522 RCB_COMM_BASE_TO_RING_BASE(rcb_common->io_base, i);
523 ring_pair_cb->port_id_in_comm =
524 hns_rcb_get_port_in_comm(rcb_common, i);
525 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] =
526 is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2) :
527 platform_get_irq(pdev, base_irq_idx + i * 3 + 1);
528 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] =
529 is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2 + 1) :
530 platform_get_irq(pdev, base_irq_idx + i * 3);
531 if ((ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] == -EPROBE_DEFER) ||
532 (ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] == -EPROBE_DEFER))
533 return -EPROBE_DEFER;
534
535 ring_pair_cb->q.phy_base =
536 RCB_COMM_BASE_TO_RING_BASE(rcb_common->phy_base, i);
537 hns_rcb_ring_pair_get_cfg(ring_pair_cb);
538 }
539
540 return 0;
541 }
542
543 /**
544 *hns_rcb_get_rx_coalesced_frames - get rcb port rx coalesced frames
545 *@rcb_common: rcb_common device
546 *@port_idx:port id in comm
547 *
548 *Returns: coalesced_frames
549 */
hns_rcb_get_rx_coalesced_frames(struct rcb_common_cb * rcb_common,u32 port_idx)550 u32 hns_rcb_get_rx_coalesced_frames(
551 struct rcb_common_cb *rcb_common, u32 port_idx)
552 {
553 return dsaf_read_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4);
554 }
555
556 /**
557 *hns_rcb_get_tx_coalesced_frames - get rcb port tx coalesced frames
558 *@rcb_common: rcb_common device
559 *@port_idx:port id in comm
560 *
561 *Returns: coalesced_frames
562 */
hns_rcb_get_tx_coalesced_frames(struct rcb_common_cb * rcb_common,u32 port_idx)563 u32 hns_rcb_get_tx_coalesced_frames(
564 struct rcb_common_cb *rcb_common, u32 port_idx)
565 {
566 u64 reg;
567
568 reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4;
569 return dsaf_read_dev(rcb_common, reg);
570 }
571
572 /**
573 *hns_rcb_get_coalesce_usecs - get rcb port coalesced time_out
574 *@rcb_common: rcb_common device
575 *@port_idx:port id in comm
576 *
577 *Returns: time_out
578 */
hns_rcb_get_coalesce_usecs(struct rcb_common_cb * rcb_common,u32 port_idx)579 u32 hns_rcb_get_coalesce_usecs(
580 struct rcb_common_cb *rcb_common, u32 port_idx)
581 {
582 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver))
583 return dsaf_read_dev(rcb_common, RCB_CFG_OVERTIME_REG) /
584 HNS_RCB_CLK_FREQ_MHZ;
585 else
586 return dsaf_read_dev(rcb_common,
587 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4);
588 }
589
590 /**
591 *hns_rcb_set_coalesce_usecs - set rcb port coalesced time_out
592 *@rcb_common: rcb_common device
593 *@port_idx:port id in comm
594 *@timeout:tx/rx time for coalesced time_out
595 *
596 * Returns:
597 * Zero for success, or an error code in case of failure
598 */
hns_rcb_set_coalesce_usecs(struct rcb_common_cb * rcb_common,u32 port_idx,u32 timeout)599 int hns_rcb_set_coalesce_usecs(
600 struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout)
601 {
602 u32 old_timeout = hns_rcb_get_coalesce_usecs(rcb_common, port_idx);
603
604 if (timeout == old_timeout)
605 return 0;
606
607 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {
608 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) {
609 dev_err(rcb_common->dsaf_dev->dev,
610 "error: not support coalesce_usecs setting!\n");
611 return -EINVAL;
612 }
613 }
614 if (timeout > HNS_RCB_MAX_COALESCED_USECS || timeout == 0) {
615 dev_err(rcb_common->dsaf_dev->dev,
616 "error: coalesce_usecs setting supports 1~1023us\n");
617 return -EINVAL;
618 }
619 hns_rcb_set_port_timeout(rcb_common, port_idx, timeout);
620 return 0;
621 }
622
623 /**
624 *hns_rcb_set_tx_coalesced_frames - set rcb coalesced frames
625 *@rcb_common: rcb_common device
626 *@port_idx:port id in comm
627 *@coalesced_frames:tx/rx BD num for coalesced frames
628 *
629 * Returns:
630 * Zero for success, or an error code in case of failure
631 */
hns_rcb_set_tx_coalesced_frames(struct rcb_common_cb * rcb_common,u32 port_idx,u32 coalesced_frames)632 int hns_rcb_set_tx_coalesced_frames(
633 struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames)
634 {
635 u32 old_waterline =
636 hns_rcb_get_tx_coalesced_frames(rcb_common, port_idx);
637 u64 reg;
638
639 if (coalesced_frames == old_waterline)
640 return 0;
641
642 if (coalesced_frames != 1) {
643 dev_err(rcb_common->dsaf_dev->dev,
644 "error: not support tx coalesce_frames setting!\n");
645 return -EINVAL;
646 }
647
648 reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4;
649 dsaf_write_dev(rcb_common, reg, coalesced_frames);
650 return 0;
651 }
652
653 /**
654 *hns_rcb_set_rx_coalesced_frames - set rcb rx coalesced frames
655 *@rcb_common: rcb_common device
656 *@port_idx:port id in comm
657 *@coalesced_frames:tx/rx BD num for coalesced frames
658 *
659 * Returns:
660 * Zero for success, or an error code in case of failure
661 */
hns_rcb_set_rx_coalesced_frames(struct rcb_common_cb * rcb_common,u32 port_idx,u32 coalesced_frames)662 int hns_rcb_set_rx_coalesced_frames(
663 struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames)
664 {
665 u32 old_waterline =
666 hns_rcb_get_rx_coalesced_frames(rcb_common, port_idx);
667
668 if (coalesced_frames == old_waterline)
669 return 0;
670
671 if (coalesced_frames >= rcb_common->desc_num ||
672 coalesced_frames > HNS_RCB_MAX_COALESCED_FRAMES ||
673 coalesced_frames < HNS_RCB_MIN_COALESCED_FRAMES) {
674 dev_err(rcb_common->dsaf_dev->dev,
675 "error: not support coalesce_frames setting!\n");
676 return -EINVAL;
677 }
678
679 dsaf_write_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4,
680 coalesced_frames);
681 return 0;
682 }
683
684 /**
685 *hns_rcb_get_queue_mode - get max VM number and max ring number per VM
686 * accordding to dsaf mode
687 *@dsaf_mode: dsaf mode
688 *@max_vfn : max vfn number
689 *@max_q_per_vf:max ring number per vm
690 */
hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode,u16 * max_vfn,u16 * max_q_per_vf)691 void hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode, u16 *max_vfn,
692 u16 *max_q_per_vf)
693 {
694 switch (dsaf_mode) {
695 case DSAF_MODE_DISABLE_6PORT_0VM:
696 *max_vfn = 1;
697 *max_q_per_vf = 16;
698 break;
699 case DSAF_MODE_DISABLE_FIX:
700 case DSAF_MODE_DISABLE_SP:
701 *max_vfn = 1;
702 *max_q_per_vf = 1;
703 break;
704 case DSAF_MODE_DISABLE_2PORT_64VM:
705 *max_vfn = 64;
706 *max_q_per_vf = 1;
707 break;
708 case DSAF_MODE_DISABLE_6PORT_16VM:
709 *max_vfn = 16;
710 *max_q_per_vf = 1;
711 break;
712 default:
713 *max_vfn = 1;
714 *max_q_per_vf = 16;
715 break;
716 }
717 }
718
hns_rcb_get_ring_num(struct dsaf_device * dsaf_dev)719 static int hns_rcb_get_ring_num(struct dsaf_device *dsaf_dev)
720 {
721 switch (dsaf_dev->dsaf_mode) {
722 case DSAF_MODE_ENABLE_FIX:
723 case DSAF_MODE_DISABLE_SP:
724 return 1;
725
726 case DSAF_MODE_DISABLE_FIX:
727 return 6;
728
729 case DSAF_MODE_ENABLE_0VM:
730 return 32;
731
732 case DSAF_MODE_DISABLE_6PORT_0VM:
733 case DSAF_MODE_ENABLE_16VM:
734 case DSAF_MODE_DISABLE_6PORT_2VM:
735 case DSAF_MODE_DISABLE_6PORT_16VM:
736 case DSAF_MODE_DISABLE_6PORT_4VM:
737 case DSAF_MODE_ENABLE_8VM:
738 return 96;
739
740 case DSAF_MODE_DISABLE_2PORT_16VM:
741 case DSAF_MODE_DISABLE_2PORT_8VM:
742 case DSAF_MODE_ENABLE_32VM:
743 case DSAF_MODE_DISABLE_2PORT_64VM:
744 case DSAF_MODE_ENABLE_128VM:
745 return 128;
746
747 default:
748 dev_warn(dsaf_dev->dev,
749 "get ring num fail,use default!dsaf_mode=%d\n",
750 dsaf_dev->dsaf_mode);
751 return 128;
752 }
753 }
754
hns_rcb_common_get_vaddr(struct rcb_common_cb * rcb_common)755 static u8 __iomem *hns_rcb_common_get_vaddr(struct rcb_common_cb *rcb_common)
756 {
757 struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev;
758
759 return dsaf_dev->ppe_base + RCB_COMMON_REG_OFFSET;
760 }
761
hns_rcb_common_get_paddr(struct rcb_common_cb * rcb_common)762 static phys_addr_t hns_rcb_common_get_paddr(struct rcb_common_cb *rcb_common)
763 {
764 struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev;
765
766 return dsaf_dev->ppe_paddr + RCB_COMMON_REG_OFFSET;
767 }
768
hns_rcb_common_get_cfg(struct dsaf_device * dsaf_dev,int comm_index)769 int hns_rcb_common_get_cfg(struct dsaf_device *dsaf_dev,
770 int comm_index)
771 {
772 struct rcb_common_cb *rcb_common;
773 enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;
774 u16 max_vfn;
775 u16 max_q_per_vf;
776 int ring_num = hns_rcb_get_ring_num(dsaf_dev);
777
778 rcb_common =
779 devm_kzalloc(dsaf_dev->dev,
780 struct_size(rcb_common, ring_pair_cb, ring_num),
781 GFP_KERNEL);
782 if (!rcb_common) {
783 dev_err(dsaf_dev->dev, "rcb common devm_kzalloc fail!\n");
784 return -ENOMEM;
785 }
786 rcb_common->comm_index = comm_index;
787 rcb_common->ring_num = ring_num;
788 rcb_common->dsaf_dev = dsaf_dev;
789
790 rcb_common->desc_num = dsaf_dev->desc_num;
791
792 hns_rcb_get_queue_mode(dsaf_mode, &max_vfn, &max_q_per_vf);
793 rcb_common->max_vfn = max_vfn;
794 rcb_common->max_q_per_vf = max_q_per_vf;
795
796 rcb_common->io_base = hns_rcb_common_get_vaddr(rcb_common);
797 rcb_common->phy_base = hns_rcb_common_get_paddr(rcb_common);
798
799 dsaf_dev->rcb_common[comm_index] = rcb_common;
800 return 0;
801 }
802
hns_rcb_common_free_cfg(struct dsaf_device * dsaf_dev,u32 comm_index)803 void hns_rcb_common_free_cfg(struct dsaf_device *dsaf_dev,
804 u32 comm_index)
805 {
806 dsaf_dev->rcb_common[comm_index] = NULL;
807 }
808
hns_rcb_update_stats(struct hnae_queue * queue)809 void hns_rcb_update_stats(struct hnae_queue *queue)
810 {
811 struct ring_pair_cb *ring =
812 container_of(queue, struct ring_pair_cb, q);
813 struct dsaf_device *dsaf_dev = ring->rcb_common->dsaf_dev;
814 struct ppe_common_cb *ppe_common
815 = dsaf_dev->ppe_common[ring->rcb_common->comm_index];
816 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;
817
818 hw_stats->rx_pkts += dsaf_read_dev(queue,
819 RCB_RING_RX_RING_PKTNUM_RECORD_REG);
820 dsaf_write_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG, 0x1);
821
822 hw_stats->ppe_rx_ok_pkts += dsaf_read_dev(ppe_common,
823 PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 4 * ring->index);
824 hw_stats->ppe_rx_drop_pkts += dsaf_read_dev(ppe_common,
825 PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 4 * ring->index);
826
827 hw_stats->tx_pkts += dsaf_read_dev(queue,
828 RCB_RING_TX_RING_PKTNUM_RECORD_REG);
829 dsaf_write_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG, 0x1);
830
831 hw_stats->ppe_tx_ok_pkts += dsaf_read_dev(ppe_common,
832 PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 4 * ring->index);
833 hw_stats->ppe_tx_drop_pkts += dsaf_read_dev(ppe_common,
834 PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 4 * ring->index);
835 }
836
837 /**
838 *hns_rcb_get_stats - get rcb statistic
839 *@queue: rcb ring
840 *@data:statistic value
841 */
hns_rcb_get_stats(struct hnae_queue * queue,u64 * data)842 void hns_rcb_get_stats(struct hnae_queue *queue, u64 *data)
843 {
844 u64 *regs_buff = data;
845 struct ring_pair_cb *ring =
846 container_of(queue, struct ring_pair_cb, q);
847 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;
848
849 regs_buff[0] = hw_stats->tx_pkts;
850 regs_buff[1] = hw_stats->ppe_tx_ok_pkts;
851 regs_buff[2] = hw_stats->ppe_tx_drop_pkts;
852 regs_buff[3] =
853 dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);
854
855 regs_buff[4] = queue->tx_ring.stats.tx_pkts;
856 regs_buff[5] = queue->tx_ring.stats.tx_bytes;
857 regs_buff[6] = queue->tx_ring.stats.tx_err_cnt;
858 regs_buff[7] = queue->tx_ring.stats.io_err_cnt;
859 regs_buff[8] = queue->tx_ring.stats.sw_err_cnt;
860 regs_buff[9] = queue->tx_ring.stats.seg_pkt_cnt;
861 regs_buff[10] = queue->tx_ring.stats.restart_queue;
862 regs_buff[11] = queue->tx_ring.stats.tx_busy;
863
864 regs_buff[12] = hw_stats->rx_pkts;
865 regs_buff[13] = hw_stats->ppe_rx_ok_pkts;
866 regs_buff[14] = hw_stats->ppe_rx_drop_pkts;
867 regs_buff[15] =
868 dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);
869
870 regs_buff[16] = queue->rx_ring.stats.rx_pkts;
871 regs_buff[17] = queue->rx_ring.stats.rx_bytes;
872 regs_buff[18] = queue->rx_ring.stats.rx_err_cnt;
873 regs_buff[19] = queue->rx_ring.stats.io_err_cnt;
874 regs_buff[20] = queue->rx_ring.stats.sw_err_cnt;
875 regs_buff[21] = queue->rx_ring.stats.seg_pkt_cnt;
876 regs_buff[22] = queue->rx_ring.stats.reuse_pg_cnt;
877 regs_buff[23] = queue->rx_ring.stats.err_pkt_len;
878 regs_buff[24] = queue->rx_ring.stats.non_vld_descs;
879 regs_buff[25] = queue->rx_ring.stats.err_bd_num;
880 regs_buff[26] = queue->rx_ring.stats.l2_err;
881 regs_buff[27] = queue->rx_ring.stats.l3l4_csum_err;
882 }
883
884 /**
885 *hns_rcb_get_ring_sset_count - rcb string set count
886 *@stringset:ethtool cmd
887 *return rcb ring string set count
888 */
hns_rcb_get_ring_sset_count(int stringset)889 int hns_rcb_get_ring_sset_count(int stringset)
890 {
891 if (stringset == ETH_SS_STATS)
892 return HNS_RING_STATIC_REG_NUM;
893
894 return 0;
895 }
896
897 /**
898 *hns_rcb_get_common_regs_count - rcb common regs count
899 *return regs count
900 */
hns_rcb_get_common_regs_count(void)901 int hns_rcb_get_common_regs_count(void)
902 {
903 return HNS_RCB_COMMON_DUMP_REG_NUM;
904 }
905
906 /**
907 *hns_rcb_get_ring_regs_count - rcb ring regs count
908 *return regs count
909 */
hns_rcb_get_ring_regs_count(void)910 int hns_rcb_get_ring_regs_count(void)
911 {
912 return HNS_RCB_RING_DUMP_REG_NUM;
913 }
914
915 /**
916 *hns_rcb_get_strings - get rcb string set
917 *@stringset:string set index
918 *@data:strings name value
919 *@index:queue index
920 */
hns_rcb_get_strings(int stringset,u8 ** data,int index)921 void hns_rcb_get_strings(int stringset, u8 **data, int index)
922 {
923 if (stringset != ETH_SS_STATS)
924 return;
925
926 ethtool_sprintf(data, "tx_ring%d_rcb_pkt_num", index);
927 ethtool_sprintf(data, "tx_ring%d_ppe_tx_pkt_num", index);
928 ethtool_sprintf(data, "tx_ring%d_ppe_drop_pkt_num", index);
929 ethtool_sprintf(data, "tx_ring%d_fbd_num", index);
930
931 ethtool_sprintf(data, "tx_ring%d_pkt_num", index);
932 ethtool_sprintf(data, "tx_ring%d_bytes", index);
933 ethtool_sprintf(data, "tx_ring%d_err_cnt", index);
934 ethtool_sprintf(data, "tx_ring%d_io_err", index);
935 ethtool_sprintf(data, "tx_ring%d_sw_err", index);
936 ethtool_sprintf(data, "tx_ring%d_seg_pkt", index);
937 ethtool_sprintf(data, "tx_ring%d_restart_queue", index);
938 ethtool_sprintf(data, "tx_ring%d_tx_busy", index);
939
940 ethtool_sprintf(data, "rx_ring%d_rcb_pkt_num", index);
941 ethtool_sprintf(data, "rx_ring%d_ppe_pkt_num", index);
942 ethtool_sprintf(data, "rx_ring%d_ppe_drop_pkt_num", index);
943 ethtool_sprintf(data, "rx_ring%d_fbd_num", index);
944
945 ethtool_sprintf(data, "rx_ring%d_pkt_num", index);
946 ethtool_sprintf(data, "rx_ring%d_bytes", index);
947 ethtool_sprintf(data, "rx_ring%d_err_cnt", index);
948 ethtool_sprintf(data, "rx_ring%d_io_err", index);
949 ethtool_sprintf(data, "rx_ring%d_sw_err", index);
950 ethtool_sprintf(data, "rx_ring%d_seg_pkt", index);
951 ethtool_sprintf(data, "rx_ring%d_reuse_pg", index);
952 ethtool_sprintf(data, "rx_ring%d_len_err", index);
953 ethtool_sprintf(data, "rx_ring%d_non_vld_desc_err", index);
954 ethtool_sprintf(data, "rx_ring%d_bd_num_err", index);
955 ethtool_sprintf(data, "rx_ring%d_l2_err", index);
956 ethtool_sprintf(data, "rx_ring%d_l3l4csum_err", index);
957 }
958
hns_rcb_get_common_regs(struct rcb_common_cb * rcb_com,void * data)959 void hns_rcb_get_common_regs(struct rcb_common_cb *rcb_com, void *data)
960 {
961 u32 *regs = data;
962 bool is_ver1 = AE_IS_VER1(rcb_com->dsaf_dev->dsaf_ver);
963 bool is_dbg = HNS_DSAF_IS_DEBUG(rcb_com->dsaf_dev);
964 u32 reg_tmp;
965 u32 reg_num_tmp;
966 u32 i;
967
968 /*rcb common registers */
969 regs[0] = dsaf_read_dev(rcb_com, RCB_COM_CFG_ENDIAN_REG);
970 regs[1] = dsaf_read_dev(rcb_com, RCB_COM_CFG_SYS_FSH_REG);
971 regs[2] = dsaf_read_dev(rcb_com, RCB_COM_CFG_INIT_FLAG_REG);
972
973 regs[3] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_REG);
974 regs[4] = dsaf_read_dev(rcb_com, RCB_COM_CFG_RINVLD_REG);
975 regs[5] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FNA_REG);
976 regs[6] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FA_REG);
977 regs[7] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_TC_BP_REG);
978 regs[8] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PPE_TNL_CLKEN_REG);
979
980 regs[9] = dsaf_read_dev(rcb_com, RCB_COM_INTMSK_TX_PKT_REG);
981 regs[10] = dsaf_read_dev(rcb_com, RCB_COM_RINT_TX_PKT_REG);
982 regs[11] = dsaf_read_dev(rcb_com, RCB_COM_INTMASK_ECC_ERR_REG);
983 regs[12] = dsaf_read_dev(rcb_com, RCB_COM_INTSTS_ECC_ERR_REG);
984 regs[13] = dsaf_read_dev(rcb_com, RCB_COM_EBD_SRAM_ERR_REG);
985 regs[14] = dsaf_read_dev(rcb_com, RCB_COM_RXRING_ERR_REG);
986 regs[15] = dsaf_read_dev(rcb_com, RCB_COM_TXRING_ERR_REG);
987 regs[16] = dsaf_read_dev(rcb_com, RCB_COM_TX_FBD_ERR_REG);
988 regs[17] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK_EN_REG);
989 regs[18] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK0_REG);
990 regs[19] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK1_REG);
991 regs[20] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK2_REG);
992 regs[21] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK3_REG);
993 regs[22] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK4_REG);
994 regs[23] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK5_REG);
995 regs[24] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR0_REG);
996 regs[25] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR3_REG);
997 regs[26] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR4_REG);
998 regs[27] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR5_REG);
999
1000 regs[28] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_RING);
1001 regs[29] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING_STS);
1002 regs[30] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING);
1003 regs[31] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_BD);
1004 regs[32] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_BD_RINT_STS);
1005 regs[33] = dsaf_read_dev(rcb_com, RCB_COM_RCB_RD_BD_BUSY);
1006 regs[34] = dsaf_read_dev(rcb_com, RCB_COM_RCB_FBD_CRT_EN);
1007 regs[35] = dsaf_read_dev(rcb_com, RCB_COM_AXI_WR_ERR_INTMASK);
1008 regs[36] = dsaf_read_dev(rcb_com, RCB_COM_AXI_ERR_STS);
1009 regs[37] = dsaf_read_dev(rcb_com, RCB_COM_CHK_TX_FBD_NUM_REG);
1010
1011 /* rcb common entry registers */
1012 for (i = 0; i < 16; i++) { /* total 16 model registers */
1013 regs[38 + i]
1014 = dsaf_read_dev(rcb_com, RCB_CFG_BD_NUM_REG + 4 * i);
1015 regs[54 + i]
1016 = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_REG + 4 * i);
1017 }
1018
1019 reg_tmp = is_ver1 ? RCB_CFG_OVERTIME_REG : RCB_PORT_CFG_OVERTIME_REG;
1020 reg_num_tmp = (is_ver1 || is_dbg) ? 1 : 6;
1021 for (i = 0; i < reg_num_tmp; i++)
1022 regs[70 + i] = dsaf_read_dev(rcb_com, reg_tmp);
1023
1024 regs[76] = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_INT_NUM_REG);
1025 regs[77] = dsaf_read_dev(rcb_com, RCB_CFG_OVERTIME_INT_NUM_REG);
1026
1027 /* mark end of rcb common regs */
1028 for (i = 78; i < 80; i++)
1029 regs[i] = 0xcccccccc;
1030 }
1031
hns_rcb_get_ring_regs(struct hnae_queue * queue,void * data)1032 void hns_rcb_get_ring_regs(struct hnae_queue *queue, void *data)
1033 {
1034 u32 *regs = data;
1035 struct ring_pair_cb *ring_pair
1036 = container_of(queue, struct ring_pair_cb, q);
1037 u32 i;
1038
1039 /*rcb ring registers */
1040 regs[0] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_L_REG);
1041 regs[1] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_H_REG);
1042 regs[2] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_NUM_REG);
1043 regs[3] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_LEN_REG);
1044 regs[4] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTLINE_REG);
1045 regs[5] = dsaf_read_dev(queue, RCB_RING_RX_RING_TAIL_REG);
1046 regs[6] = dsaf_read_dev(queue, RCB_RING_RX_RING_HEAD_REG);
1047 regs[7] = dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);
1048 regs[8] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG);
1049
1050 regs[9] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_L_REG);
1051 regs[10] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_H_REG);
1052 regs[11] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_NUM_REG);
1053 regs[12] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_LEN_REG);
1054 regs[13] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTLINE_REG);
1055 regs[15] = dsaf_read_dev(queue, RCB_RING_TX_RING_TAIL_REG);
1056 regs[16] = dsaf_read_dev(queue, RCB_RING_TX_RING_HEAD_REG);
1057 regs[17] = dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);
1058 regs[18] = dsaf_read_dev(queue, RCB_RING_TX_RING_OFFSET_REG);
1059 regs[19] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG);
1060
1061 regs[20] = dsaf_read_dev(queue, RCB_RING_PREFETCH_EN_REG);
1062 regs[21] = dsaf_read_dev(queue, RCB_RING_CFG_VF_NUM_REG);
1063 regs[22] = dsaf_read_dev(queue, RCB_RING_ASID_REG);
1064 regs[23] = dsaf_read_dev(queue, RCB_RING_RX_VM_REG);
1065 regs[24] = dsaf_read_dev(queue, RCB_RING_T0_BE_RST);
1066 regs[25] = dsaf_read_dev(queue, RCB_RING_COULD_BE_RST);
1067 regs[26] = dsaf_read_dev(queue, RCB_RING_WRR_WEIGHT_REG);
1068
1069 regs[27] = dsaf_read_dev(queue, RCB_RING_INTMSK_RXWL_REG);
1070 regs[28] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_RING_REG);
1071 regs[29] = dsaf_read_dev(queue, RCB_RING_INTMSK_TXWL_REG);
1072 regs[30] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_RING_REG);
1073 regs[31] = dsaf_read_dev(queue, RCB_RING_INTMSK_RX_OVERTIME_REG);
1074 regs[32] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_OVERTIME_REG);
1075 regs[33] = dsaf_read_dev(queue, RCB_RING_INTMSK_TX_OVERTIME_REG);
1076 regs[34] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_OVERTIME_REG);
1077
1078 /* mark end of ring regs */
1079 for (i = 35; i < 40; i++)
1080 regs[i] = 0xcccccc00 + ring_pair->index;
1081 }
1082