1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef __SOC_HDMI_H__ 4 #define __SOC_HDMI_H__ 5 6 #include <types.h> 7 8 #define HDMI_EDID_BLOCK_SIZE 128 9 10 struct rk3288_hdmi_regs { 11 u32 reserved0[0x100]; 12 u32 ih_fc_stat0; 13 u32 ih_fc_stat1; 14 u32 ih_fc_stat2; 15 u32 ih_as_stat0; 16 u32 ih_phy_stat0; 17 u32 ih_i2cm_stat0; 18 u32 ih_cec_stat0; 19 u32 ih_vp_stat0; 20 u32 ih_i2cmphy_stat0; 21 u32 ih_ahbdmaaud_stat0; 22 u32 reserved1[0x17f-0x109]; 23 u32 ih_mute_fc_stat0; 24 u32 ih_mute_fc_stat1; 25 u32 ih_mute_fc_stat2; 26 u32 ih_mute_as_stat0; 27 u32 ih_mute_phy_stat0; 28 u32 ih_mute_i2cm_stat0; 29 u32 ih_mute_cec_stat0; 30 u32 ih_mute_vp_stat0; 31 u32 ih_mute_i2cmphy_stat0; 32 u32 ih_mute_ahbdmaaud_stat0; 33 u32 reserved2[0x1fe - 0x189]; 34 u32 ih_mute; 35 u32 tx_invid0; 36 u32 tx_instuffing; 37 u32 tx_gydata0; 38 u32 tx_gydata1; 39 u32 tx_rcrdata0; 40 u32 tx_rcrdata1; 41 u32 tx_bcbdata0; 42 u32 tx_bcbdata1; 43 u32 reserved3[0x7ff-0x207]; 44 u32 vp_status; 45 u32 vp_pr_cd; 46 u32 vp_stuff; 47 u32 vp_remap; 48 u32 vp_conf; 49 u32 vp_stat; 50 u32 vp_int; 51 u32 vp_mask; 52 u32 vp_pol; 53 u32 reserved4[0xfff-0x808]; 54 u32 fc_invidconf; 55 u32 fc_inhactv0; 56 u32 fc_inhactv1; 57 u32 fc_inhblank0; 58 u32 fc_inhblank1; 59 u32 fc_invactv0; 60 u32 fc_invactv1; 61 u32 fc_invblank; 62 u32 fc_hsyncindelay0; 63 u32 fc_hsyncindelay1; 64 u32 fc_hsyncinwidth0; 65 u32 fc_hsyncinwidth1; 66 u32 fc_vsyncindelay; 67 u32 fc_vsyncinwidth; 68 u32 fc_infreq0; 69 u32 fc_infreq1; 70 u32 fc_infreq2; 71 u32 fc_ctrldur; 72 u32 fc_exctrldur; 73 u32 fc_exctrlspac; 74 u32 fc_ch0pream; 75 u32 fc_ch1pream; 76 u32 fc_ch2pream; 77 u32 fc_aviconf3; 78 u32 fc_gcp; 79 u32 fc_aviconf0; 80 u32 fc_aviconf1; 81 u32 fc_aviconf2; 82 u32 fc_avivid; 83 u32 fc_avietb0; 84 u32 fc_avietb1; 85 u32 fc_avisbb0; 86 u32 fc_avisbb1; 87 u32 fc_avielb0; 88 u32 fc_avielb1; 89 u32 fc_avisrb0; 90 u32 fc_avisrb1; 91 u32 fc_audiconf0; 92 u32 fc_audiconf1; 93 u32 fc_audiconf2; 94 u32 fc_audiconf3; 95 u32 fc_vsdieeeid0; 96 u32 fc_vsdsize; 97 u32 reserved7[0x2fff-0x102a]; 98 u32 phy_conf0; 99 u32 phy_tst0; 100 u32 phy_tst1; 101 u32 phy_tst2; 102 u32 phy_stat0; 103 u32 phy_int0; 104 u32 phy_mask0; 105 u32 phy_pol0; 106 u32 reserved8[0x301f-0x3007]; 107 u32 phy_i2cm_slave_addr; 108 u32 phy_i2cm_address_addr; 109 u32 phy_i2cm_datao_1_addr; 110 u32 phy_i2cm_datao_0_addr; 111 u32 phy_i2cm_datai_1_addr; 112 u32 phy_i2cm_datai_0_addr; 113 u32 phy_i2cm_operation_addr; 114 u32 phy_i2cm_int_addr; 115 u32 phy_i2cm_ctlint_addr; 116 u32 phy_i2cm_div_addr; 117 u32 phy_i2cm_softrstz_addr; 118 u32 phy_i2cm_ss_scl_hcnt_1_addr; 119 u32 phy_i2cm_ss_scl_hcnt_0_addr; 120 u32 phy_i2cm_ss_scl_lcnt_1_addr; 121 u32 phy_i2cm_ss_scl_lcnt_0_addr; 122 u32 phy_i2cm_fs_scl_hcnt_1_addr; 123 u32 phy_i2cm_fs_scl_hcnt_0_addr; 124 u32 phy_i2cm_fs_scl_lcnt_1_addr; 125 u32 phy_i2cm_fs_scl_lcnt_0_addr; 126 u32 reserved9[0x30ff-0x3032]; 127 u32 aud_conf0; 128 u32 aud_conf1; 129 u32 aud_int; 130 u32 aud_conf2; 131 u32 aud_int1; 132 u32 reserved32[0x31ff-0x3104]; 133 u32 aud_n1; 134 u32 aud_n2; 135 u32 aud_n3; 136 u32 aud_cts1; 137 u32 aud_cts2; 138 u32 aud_cts3; 139 u32 aud_inputclkfs; 140 u32 reserved12[0x3fff-0x3206]; 141 u32 mc_sfrdiv; 142 u32 mc_clkdis; 143 u32 mc_swrstz; 144 u32 mc_opctrl; 145 u32 mc_flowctrl; 146 u32 mc_phyrstz; 147 u32 mc_lockonclock; 148 u32 mc_heacphy_rst; 149 u32 reserved13[0x40ff-0x4007]; 150 u32 csc_cfg; 151 u32 csc_scale; 152 struct { 153 u32 msb; 154 u32 lsb; 155 } csc_coef[3][4]; 156 u32 reserved17[0x7dff-0x4119]; 157 u32 i2cm_slave; 158 u32 i2cmess; 159 u32 i2cm_datao; 160 u32 i2cm_datai; 161 u32 i2cm_operation; 162 u32 i2cm_int; 163 u32 i2cm_ctlint; 164 u32 i2cm_div; 165 u32 i2cm_segaddr; 166 u32 i2cm_softrstz; 167 u32 i2cm_segptr; 168 u32 i2cm_ss_scl_hcnt_1_addr; 169 u32 i2cm_ss_scl_hcnt_0_addr; 170 u32 i2cm_ss_scl_lcnt_1_addr; 171 u32 i2cm_ss_scl_lcnt_0_addr; 172 u32 i2cm_fs_scl_hcnt_1_addr; 173 u32 i2cm_fs_scl_hcnt_0_addr; 174 u32 i2cm_fs_scl_lcnt_1_addr; 175 u32 i2cm_fs_scl_lcnt_0_addr; 176 u32 reserved18[0x7e1f-0x7e12]; 177 u32 i2cm_buf0; 178 }; 179 check_member(rk3288_hdmi_regs, i2cm_buf0, 0x1f880); 180 181 enum { 182 /* HDMI PHY registers define */ 183 PHY_OPMODE_PLLCFG = 0x06, 184 PHY_CKCALCTRL = 0x05, 185 PHY_CKSYMTXCTRL = 0x09, 186 PHY_VLEVCTRL = 0x0e, 187 PHY_PLLCURRCTRL = 0x10, 188 PHY_PLLPHBYCTRL = 0x13, 189 PHY_PLLGMPCTRL = 0x15, 190 PHY_PLLCLKBISTPHASE = 0x17, 191 PHY_TXTERM = 0x19, 192 193 /* ih_phy_stat0 field values */ 194 HDMI_IH_PHY_STAT0_HPD = 0x1, 195 196 /* ih_mute field values */ 197 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, 198 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, 199 200 /* tx_invid0 field values */ 201 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, 202 HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f, 203 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, 204 205 /* tx_instuffing field values */ 206 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, 207 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, 208 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, 209 210 /* vp_pr_cd field values */ 211 HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0, 212 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, 213 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f, 214 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, 215 216 /* vp_stuff field values */ 217 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, 218 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, 219 HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, 220 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, 221 HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, 222 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, 223 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, 224 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, 225 226 /* vp_conf field values */ 227 HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, 228 HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, 229 HDMI_VP_CONF_PP_EN_ENMASK = 0x20, 230 HDMI_VP_CONF_PP_EN_DISABLE = 0x00, 231 HDMI_VP_CONF_PR_EN_MASK = 0x10, 232 HDMI_VP_CONF_PR_EN_DISABLE = 0x00, 233 HDMI_VP_CONF_YCC422_EN_MASK = 0x8, 234 HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, 235 HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, 236 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, 237 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, 238 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, 239 240 /* vp_remap field values */ 241 HDMI_VP_REMAP_YCC422_16BIT = 0x0, 242 243 /* fc_invidconf field values */ 244 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, 245 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, 246 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, 247 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, 248 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, 249 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 250 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, 251 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, 252 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 253 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, 254 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, 255 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, 256 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, 257 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, 258 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, 259 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, 260 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, 261 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, 262 HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, 263 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, 264 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, 265 266 /* fc_aviconf0-fc_aviconf3 field values */ 267 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, 268 HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, 269 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, 270 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, 271 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, 272 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, 273 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, 274 HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c, 275 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, 276 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, 277 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, 278 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c, 279 HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, 280 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, 281 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, 282 HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, 283 284 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f, 285 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, 286 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, 287 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a, 288 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b, 289 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, 290 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, 291 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, 292 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, 293 HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0, 294 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, 295 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, 296 HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, 297 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0, 298 299 HDMI_FC_AVICONF2_SCALING_MASK = 0x03, 300 HDMI_FC_AVICONF2_SCALING_NONE = 0x00, 301 HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, 302 HDMI_FC_AVICONF2_SCALING_VERT = 0x02, 303 HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03, 304 HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c, 305 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, 306 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, 307 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, 308 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, 309 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, 310 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, 311 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, 312 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, 313 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, 314 HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, 315 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, 316 HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, 317 318 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, 319 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, 320 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, 321 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, 322 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, 323 HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c, 324 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, 325 HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, 326 327 /* fc_gcp field values*/ 328 HDMI_FC_GCP_SET_AVMUTE = 0x02, 329 HDMI_FC_GCP_CLEAR_AVMUTE = 0x01, 330 331 /* phy_conf0 field values */ 332 HDMI_PHY_CONF0_PDZ_MASK = 0x80, 333 HDMI_PHY_CONF0_PDZ_OFFSET = 7, 334 HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, 335 HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, 336 HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, 337 HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, 338 HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, 339 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, 340 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, 341 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, 342 HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, 343 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, 344 HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, 345 HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, 346 347 /* phy_tst0 field values */ 348 HDMI_PHY_TST0_TSTCLR_MASK = 0x20, 349 HDMI_PHY_TST0_TSTCLR_OFFSET = 5, 350 351 /* phy_stat0 field values */ 352 HDMI_PHY_HPD = 0x02, 353 HDMI_PHY_TX_PHY_LOCK = 0x01, 354 355 /* phy_i2cm_slave_addr field values */ 356 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, 357 358 /* phy_i2cm_operation_addr field values */ 359 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, 360 361 /* hdmi_phy_i2cm_int_addr */ 362 HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, 363 364 /* hdmi_phy_i2cm_ctlint_addr */ 365 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, 366 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, 367 368 /* aud_conf0 field values */ 369 HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80, 370 HDMI_AUD_CONF0_I2S_SELECT = 0x20, 371 HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01, 372 HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02, 373 HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04, 374 HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08, 375 376 /* aud_conf0 field values */ 377 HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0, 378 HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10, 379 380 /* aud_n3 field values */ 381 HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80, 382 HDMI_AUD_N3_AUDN19_16_MASK = 0x0f, 383 384 /* aud_cts3 field values */ 385 HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, 386 HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, 387 HDMI_AUD_CTS3_N_SHIFT_1 = 0, 388 HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, 389 HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, 390 HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, 391 HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, 392 HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, 393 HDMI_AUD_CTS3_CTS_MANUAL = 0x10, 394 HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, 395 396 /* aud_inputclkfs filed values */ 397 HDMI_AUD_INPUTCLKFS_128 = 0x0, 398 399 /* mc_clkdis field values */ 400 HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, 401 HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, 402 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, 403 404 /* mc_swrstz field values */ 405 HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08, 406 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, 407 408 /* mc_flowctrl field values */ 409 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, 410 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, 411 412 /* mc_phyrstz field values */ 413 HDMI_MC_PHYRSTZ_ASSERT = 0x0, 414 HDMI_MC_PHYRSTZ_DEASSERT = 0x1, 415 416 /* mc_heacphy_rst field values */ 417 HDMI_MC_HEACPHY_RST_ASSERT = 0x1, 418 419 /* csc_cfg field values */ 420 HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, 421 422 /* csc_scale field values */ 423 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0, 424 HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, 425 HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, 426 HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, 427 HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, 428 HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, 429 430 /* i2cm filed values */ 431 HDMI_I2CM_SLAVE_DDC_ADDR = 0x50, 432 HDMI_I2CM_SEGADDR_DDC = 0x30, 433 HDMI_I2CM_OPT_RD8_EXT = 0x8, 434 HDMI_I2CM_OPT_RD8 = 0x4, 435 HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, 436 HDMI_I2CM_DIV_FAST_MODE = 0x8, 437 HDMI_I2CM_DIV_STD_MODE = 0x0, 438 HDMI_I2CM_SOFTRSTZ = 0x1, 439 }; 440 441 int rk_hdmi_init(u32 vop_id); 442 int rk_hdmi_enable(const struct edid *edid); 443 int rk_hdmi_get_edid(struct edid *edid); 444 445 #endif /* __SOC_HDMI_H__ */ 446