1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ops.h>
7 #include "i82801gx.h"
8 #include "sata.h"
9
ich_hide_devfn(unsigned int devfn)10 static void ich_hide_devfn(unsigned int devfn)
11 {
12 switch (devfn) {
13 case PCI_DEVFN(27, 0): /* HD Audio Controller */
14 RCBA32_OR(FD, FD_HDAUD);
15 break;
16 case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
17 case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
18 case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
19 case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
20 case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
21 case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
22 RCBA32_OR(FD, ICH_DISABLE_PCIE(PCI_FUNC(devfn)));
23 break;
24 case PCI_DEVFN(29, 0): /* UHCI #1 */
25 case PCI_DEVFN(29, 1): /* UHCI #2 */
26 case PCI_DEVFN(29, 2): /* UHCI #3 */
27 case PCI_DEVFN(29, 3): /* UHCI #4 */
28 RCBA32_OR(FD, ICH_DISABLE_UHCI(PCI_FUNC(devfn)));
29 break;
30 case PCI_DEVFN(29, 7): /* EHCI #1 */
31 RCBA32_OR(FD, FD_EHCI);
32 break;
33 case PCI_DEVFN(30, 2): /* AC Audio */
34 RCBA32_OR(FD, FD_ACAUD);
35 break;
36 case PCI_DEVFN(30, 3): /* AC Modem */
37 RCBA32_OR(FD, FD_ACMOD);
38 break;
39 case PCI_DEVFN(31, 0): /* LPC */
40 RCBA32_OR(FD, FD_LPCB);
41 break;
42 case PCI_DEVFN(31, 1): /* PATA #1 */
43 RCBA32_OR(FD, FD_PATA);
44 break;
45 case PCI_DEVFN(31, 2): /* SATA #1 */
46 RCBA32_OR(FD, FD_SATA);
47 break;
48 case PCI_DEVFN(31, 3): /* SMBUS */
49 RCBA32_OR(FD, FD_SMBUS);
50 break;
51 }
52 }
53
i82801gx_enable(struct device * dev)54 void i82801gx_enable(struct device *dev)
55 {
56 u16 reg16;
57
58 if (!dev->enabled) {
59 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
60
61 /* Ensure memory, io, and bus master are all disabled */
62 reg16 = pci_read_config16(dev, PCI_COMMAND);
63 reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
64 pci_write_config16(dev, PCI_COMMAND, reg16);
65
66 /* Hide this device if possible */
67 ich_hide_devfn(dev->path.pci.devfn);
68 } else {
69 /* Enable SERR */
70 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
71
72 if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {
73 printk(BIOS_DEBUG, "Set SATA mode early\n");
74 sata_enable(dev);
75 }
76 }
77 }
78
i82801gx_init(void * chip_info)79 static void i82801gx_init(void *chip_info)
80 {
81 /* Disable performance counter */
82 RCBA32_OR(FD, 1);
83 }
84
85 struct chip_operations southbridge_intel_i82801gx_ops = {
86 .name = "Intel ICH7/ICH7-M (82801Gx) Series Southbridge",
87 .enable_dev = i82801gx_enable,
88 .init = i82801gx_init,
89 };
90