1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _IA_CSS_ACC_TYPES_H 8 #define _IA_CSS_ACC_TYPES_H 9 10 /* @file 11 * This file contains types used for acceleration 12 */ 13 14 #include <system_local.h> /* HAS_IRQ_MAP_VERSION_# */ 15 #include <type_support.h> 16 #include <platform_support.h> 17 #include <debug_global.h> 18 #include <linux/bits.h> 19 20 #include "ia_css_types.h" 21 #include "ia_css_frame_format.h" 22 23 /* Should be included without the path. 24 However, that requires adding the path to numerous makefiles 25 that have nothing to do with isp parameters. 26 */ 27 #include "runtime/isp_param/interface/ia_css_isp_param_types.h" 28 29 /* Types for the acceleration API. 30 * These should be moved to sh_css_internal.h once the old acceleration 31 * argument handling has been completed. 32 * After that, interpretation of these structures is no longer needed 33 * in the kernel and HAL. 34 */ 35 36 /* Type of acceleration. 37 */ 38 enum ia_css_acc_type { 39 IA_CSS_ACC_NONE, /** Normal binary */ 40 IA_CSS_ACC_OUTPUT, /** Accelerator stage on output frame */ 41 IA_CSS_ACC_VIEWFINDER, /** Accelerator stage on viewfinder frame */ 42 IA_CSS_ACC_STANDALONE, /** Stand-alone acceleration */ 43 }; 44 45 /* Cells types 46 */ 47 enum ia_css_cell_type { 48 IA_CSS_SP0 = 0, 49 IA_CSS_SP1, 50 IA_CSS_ISP, 51 MAX_NUM_OF_CELLS 52 }; 53 54 /* Firmware types. 55 */ 56 enum ia_css_fw_type { 57 ia_css_sp_firmware, /** Firmware for the SP */ 58 ia_css_isp_firmware, /** Firmware for the ISP */ 59 ia_css_bootloader_firmware, /** Firmware for the BootLoader */ 60 ia_css_acc_firmware /** Firmware for accelrations */ 61 }; 62 63 struct ia_css_blob_descr; 64 65 /* Blob descriptor. 66 * This structure describes an SP or ISP blob. 67 * It describes the test, data and bss sections as well as position in a 68 * firmware file. 69 * For convenience, it contains dynamic data after loading. 70 */ 71 struct ia_css_blob_info { 72 /** Static blob data */ 73 u32 offset; /** Blob offset in fw file */ 74 struct ia_css_isp_param_memory_offsets 75 memory_offsets; /** offset wrt hdr in bytes */ 76 u32 prog_name_offset; /** offset wrt hdr in bytes */ 77 u32 size; /** Size of blob */ 78 u32 padding_size; /** total accumulation of bytes added due to section alignment */ 79 u32 icache_source; /** Position of icache in blob */ 80 u32 icache_size; /** Size of icache section */ 81 u32 icache_padding;/** bytes added due to icache section alignment */ 82 u32 text_source; /** Position of text in blob */ 83 u32 text_size; /** Size of text section */ 84 u32 text_padding; /** bytes added due to text section alignment */ 85 u32 data_source; /** Position of data in blob */ 86 u32 data_target; /** Start of data in SP dmem */ 87 u32 data_size; /** Size of text section */ 88 u32 data_padding; /** bytes added due to data section alignment */ 89 u32 bss_target; /** Start position of bss in SP dmem */ 90 u32 bss_size; /** Size of bss section */ 91 /** Dynamic data filled by loader */ 92 CSS_ALIGN(const void *code, 93 8); /** Code section absolute pointer within fw, code = icache + text */ 94 CSS_ALIGN(const void *data, 95 8); /** Data section absolute pointer within fw, data = data + bss */ 96 }; 97 98 struct ia_css_binary_input_info { 99 u32 min_width; 100 u32 min_height; 101 u32 max_width; 102 u32 max_height; 103 u32 source; /* memory, sensor, variable */ 104 }; 105 106 struct ia_css_binary_output_info { 107 u32 min_width; 108 u32 min_height; 109 u32 max_width; 110 u32 max_height; 111 u32 num_chunks; 112 u32 variable_format; 113 }; 114 115 struct ia_css_binary_internal_info { 116 u32 max_width; 117 u32 max_height; 118 }; 119 120 struct ia_css_binary_bds_info { 121 u32 supported_bds_factors; 122 }; 123 124 struct ia_css_binary_dvs_info { 125 u32 max_envelope_width; 126 u32 max_envelope_height; 127 }; 128 129 struct ia_css_binary_vf_dec_info { 130 u32 is_variable; 131 u32 max_log_downscale; 132 }; 133 134 struct ia_css_binary_s3a_info { 135 u32 s3atbl_use_dmem; 136 u32 fixed_s3a_deci_log; 137 }; 138 139 /* DPC related binary info */ 140 struct ia_css_binary_dpc_info { 141 u32 bnr_lite; /** bnr lite enable flag */ 142 }; 143 144 struct ia_css_binary_iterator_info { 145 u32 num_stripes; 146 u32 row_stripes_height; 147 u32 row_stripes_overlap_lines; 148 }; 149 150 struct ia_css_binary_address_info { 151 u32 isp_addresses; /* Address in ISP dmem */ 152 u32 main_entry; /* Address of entry fct */ 153 u32 in_frame; /* Address in ISP dmem */ 154 u32 out_frame; /* Address in ISP dmem */ 155 u32 in_data; /* Address in ISP dmem */ 156 u32 out_data; /* Address in ISP dmem */ 157 u32 sh_dma_cmd_ptr; /* In ISP dmem */ 158 }; 159 160 struct ia_css_binary_uds_info { 161 u16 bpp; 162 u16 use_bci; 163 u16 use_str; 164 u16 woix; 165 u16 woiy; 166 u16 extra_out_vecs; 167 u16 vectors_per_line_in; 168 u16 vectors_per_line_out; 169 u16 vectors_c_per_line_in; 170 u16 vectors_c_per_line_out; 171 u16 vmem_gdc_in_block_height_y; 172 u16 vmem_gdc_in_block_height_c; 173 /* uint16_t padding; */ 174 }; 175 176 struct ia_css_binary_pipeline_info { 177 u32 mode; 178 u32 isp_pipe_version; 179 u32 pipelining; 180 u32 c_subsampling; 181 u32 top_cropping; 182 u32 left_cropping; 183 u32 variable_resolution; 184 }; 185 186 struct ia_css_binary_block_info { 187 u32 block_width; 188 u32 block_height; 189 u32 output_block_height; 190 }; 191 192 /* Structure describing an ISP binary. 193 * It describes the capabilities of a binary, like the maximum resolution, 194 * support features, dma channels, uds features, etc. 195 * This part is to be used by the SP. 196 * Future refactoring should move binary properties to ia_css_binary_xinfo, 197 * thereby making the SP code more binary independent. 198 */ 199 struct ia_css_binary_info { 200 CSS_ALIGN(u32 id, 8); /* IA_CSS_BINARY_ID_* */ 201 struct ia_css_binary_pipeline_info pipeline; 202 struct ia_css_binary_input_info input; 203 struct ia_css_binary_output_info output; 204 struct ia_css_binary_internal_info internal; 205 struct ia_css_binary_bds_info bds; 206 struct ia_css_binary_dvs_info dvs; 207 struct ia_css_binary_vf_dec_info vf_dec; 208 struct ia_css_binary_s3a_info s3a; 209 struct ia_css_binary_dpc_info dpc_bnr; /** DPC related binary info */ 210 struct ia_css_binary_iterator_info iterator; 211 struct ia_css_binary_address_info addresses; 212 struct ia_css_binary_uds_info uds; 213 struct ia_css_binary_block_info block; 214 struct ia_css_isp_param_isp_segments mem_initializers; 215 /* MW: Packing (related) bools in an integer ?? */ 216 struct { 217 u8 reduced_pipe; 218 u8 vf_veceven; 219 u8 dis; 220 u8 dvs_envelope; 221 u8 uds; 222 u8 dvs_6axis; 223 u8 block_output; 224 u8 streaming_dma; 225 u8 ds; 226 u8 bayer_fir_6db; 227 u8 raw_binning; 228 u8 continuous; 229 u8 s3a; 230 u8 fpnr; 231 u8 sc; 232 u8 macc; 233 u8 output; 234 u8 ref_frame; 235 u8 tnr; 236 u8 xnr; 237 u8 params; 238 u8 ca_gdc; 239 u8 isp_addresses; 240 u8 in_frame; 241 u8 out_frame; 242 u8 high_speed; 243 u8 dpc; 244 u8 padding[2]; 245 } enable; 246 struct { 247 /* DMA channel ID: [0,...,HIVE_ISP_NUM_DMA_CHANNELS> */ 248 u8 ref_y_channel; 249 u8 ref_c_channel; 250 u8 tnr_channel; 251 u8 tnr_out_channel; 252 u8 dvs_coords_channel; 253 u8 output_channel; 254 u8 c_channel; 255 u8 vfout_channel; 256 u8 vfout_c_channel; 257 u8 vfdec_bits_per_pixel; 258 u8 claimed_by_isp; 259 u8 padding[2]; 260 } dma; 261 }; 262 263 /* Structure describing an ISP binary. 264 * It describes the capabilities of a binary, like the maximum resolution, 265 * support features, dma channels, uds features, etc. 266 */ 267 struct ia_css_binary_xinfo { 268 /* Part that is of interest to the SP. */ 269 struct ia_css_binary_info sp; 270 271 /* Rest of the binary info, only interesting to the host. */ 272 enum ia_css_acc_type type; 273 274 CSS_ALIGN(s32 num_output_formats, 8); 275 enum ia_css_frame_format output_formats[IA_CSS_FRAME_FORMAT_NUM]; 276 277 CSS_ALIGN(s32 num_vf_formats, 8); /** number of supported vf formats */ 278 enum ia_css_frame_format 279 vf_formats[IA_CSS_FRAME_FORMAT_NUM]; /** types of supported vf formats */ 280 u8 num_output_pins; 281 ia_css_ptr xmem_addr; 282 283 CSS_ALIGN(const struct ia_css_blob_descr *blob, 8); 284 CSS_ALIGN(u32 blob_index, 8); 285 CSS_ALIGN(union ia_css_all_memory_offsets mem_offsets, 8); 286 CSS_ALIGN(struct ia_css_binary_xinfo *next, 8); 287 }; 288 289 /* Structure describing the Bootloader (an ISP binary). 290 * It contains several address, either in ddr, isp_dmem or 291 * the entry function in icache. 292 */ 293 struct ia_css_bl_info { 294 u32 num_dma_cmds; /** Number of cmds sent by CSS */ 295 u32 dma_cmd_list; /** Dma command list sent by CSS */ 296 u32 sw_state; /** Polled from css */ 297 /* Entry functions */ 298 u32 bl_entry; /** The SP entry function */ 299 }; 300 301 /* Structure describing the SP binary. 302 * It contains several address, either in ddr, sp_dmem or 303 * the entry function in pmem. 304 */ 305 struct ia_css_sp_info { 306 u32 init_dmem_data; /** data sect config, stored to dmem */ 307 u32 per_frame_data; /** Per frame data, stored to dmem */ 308 u32 group; /** Per pipeline data, loaded by dma */ 309 u32 output; /** SP output data, loaded by dmem */ 310 u32 host_sp_queue; /** Host <-> SP queues */ 311 u32 host_sp_com;/** Host <-> SP commands */ 312 u32 isp_started; /** Polled from sensor thread, csim only */ 313 u32 sw_state; /** Polled from css */ 314 u32 host_sp_queues_initialized; /** Polled from the SP */ 315 u32 sleep_mode; /** different mode to halt SP */ 316 u32 invalidate_tlb; /** inform SP to invalidate mmu TLB */ 317 318 /* ISP2400 */ 319 u32 stop_copy_preview; /** suspend copy and preview pipe when capture */ 320 321 u32 debug_buffer_ddr_address; /** inform SP the address 322 of DDR debug queue */ 323 u32 perf_counter_input_system_error; /** input system perf 324 counter array */ 325 326 u32 threads_stack; /** sp thread's stack pointers */ 327 u32 threads_stack_size; /** sp thread's stack sizes */ 328 u32 curr_binary_id; /** current binary id */ 329 u32 raw_copy_line_count; /** raw copy line counter */ 330 u32 ddr_parameter_address; /** acc param ddrptr, sp dmem */ 331 u32 ddr_parameter_size; /** acc param size, sp dmem */ 332 /* Entry functions */ 333 u32 sp_entry; /** The SP entry function */ 334 u32 tagger_frames_addr; /** Base address of tagger state */ 335 }; 336 337 /* The following #if is there because this header file is also included 338 by SP and ISP code but they do not need this data and HIVECC has alignment 339 issue with the firmware struct/union's. 340 More permanent solution will be to refactor this include. 341 */ 342 343 /* Accelerator firmware information. 344 */ 345 struct ia_css_acc_info { 346 u32 per_frame_data; /** Dummy for now */ 347 }; 348 349 /* Firmware information. 350 */ 351 union ia_css_fw_union { 352 struct ia_css_binary_xinfo isp; /** ISP info */ 353 struct ia_css_sp_info sp; /** SP info */ 354 struct ia_css_bl_info bl; /** Bootloader info */ 355 struct ia_css_acc_info acc; /** Accelerator info */ 356 }; 357 358 /* Firmware information. 359 */ 360 struct ia_css_fw_info { 361 size_t header_size; /** size of fw header */ 362 363 CSS_ALIGN(u32 type, 8); 364 union ia_css_fw_union info; /** Binary info */ 365 struct ia_css_blob_info blob; /** Blob info */ 366 /* Dynamic part */ 367 struct ia_css_fw_info *next; 368 369 CSS_ALIGN(u32 loaded, 8); /** Firmware has been loaded */ 370 CSS_ALIGN(const u8 *isp_code, 8); /** ISP pointer to code */ 371 /** Firmware handle between user space and kernel */ 372 CSS_ALIGN(u32 handle, 8); 373 /** Sections to copy from/to ISP */ 374 struct ia_css_isp_param_css_segments mem_initializers; 375 /** Initializer for local ISP memories */ 376 }; 377 378 struct ia_css_blob_descr { 379 const unsigned char *blob; 380 struct ia_css_fw_info header; 381 const char *name; 382 union ia_css_all_memory_offsets mem_offsets; 383 }; 384 385 struct ia_css_acc_fw; 386 387 /* Structure describing the SP binary of a stand-alone accelerator. 388 */ 389 struct ia_css_acc_sp { 390 void (*init)(struct ia_css_acc_fw *); /** init for crun */ 391 u32 sp_prog_name_offset; /** program name offset wrt hdr in bytes */ 392 u32 sp_blob_offset; /** blob offset wrt hdr in bytes */ 393 void *entry; /** Address of sp entry point */ 394 u32 *css_abort; /** SP dmem abort flag */ 395 void *isp_code; /** SP dmem address holding xmem 396 address of isp code */ 397 struct ia_css_fw_info fw; /** SP fw descriptor */ 398 const u8 *code; /** ISP pointer of allocated SP code */ 399 }; 400 401 /* Acceleration firmware descriptor. 402 * This descriptor describes either SP code (stand-alone), or 403 * ISP code (a separate pipeline stage). 404 */ 405 struct ia_css_acc_fw_hdr { 406 enum ia_css_acc_type type; /** Type of accelerator */ 407 u32 isp_prog_name_offset; /** program name offset wrt 408 header in bytes */ 409 u32 isp_blob_offset; /** blob offset wrt header 410 in bytes */ 411 u32 isp_size; /** Size of isp blob */ 412 const u8 *isp_code; /** ISP pointer to code */ 413 struct ia_css_acc_sp sp; /** Standalone sp code */ 414 /** Firmware handle between user space and kernel */ 415 u32 handle; 416 struct ia_css_data parameters; /** Current SP parameters */ 417 }; 418 419 /* Firmware structure. 420 * This contains the header and actual blobs. 421 * For standalone, it contains SP and ISP blob. 422 * For a pipeline stage accelerator, it contains ISP code only. 423 * Since its members are variable size, their offsets are described in the 424 * header and computed using the access macros below. 425 */ 426 struct ia_css_acc_fw { 427 struct ia_css_acc_fw_hdr header; /** firmware header */ 428 /* 429 int8_t isp_progname[]; **< ISP program name 430 int8_t sp_progname[]; **< SP program name, stand-alone only 431 uint8_t sp_code[]; **< SP blob, stand-alone only 432 uint8_t isp_code[]; **< ISP blob 433 */ 434 }; 435 436 /* Access macros for firmware */ 437 #define IA_CSS_ACC_OFFSET(t, f, n) ((t)((uint8_t *)(f) + (f->header.n))) 438 #define IA_CSS_ACC_SP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ 439 sp.sp_prog_name_offset) 440 #define IA_CSS_ACC_ISP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ 441 isp_prog_name_offset) 442 #define IA_CSS_ACC_SP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t *, f, \ 443 sp.sp_blob_offset) 444 #define IA_CSS_ACC_SP_DATA(f) (IA_CSS_ACC_SP_CODE(f) + \ 445 (f)->header.sp.fw.blob.data_source) 446 #define IA_CSS_ACC_ISP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t*, f,\ 447 isp_blob_offset) 448 #define IA_CSS_ACC_ISP_SIZE(f) ((f)->header.isp_size) 449 450 /* Binary name follows header immediately */ 451 #define IA_CSS_EXT_ISP_PROG_NAME(f) ((const char *)(f) + (f)->blob.prog_name_offset) 452 #define IA_CSS_EXT_ISP_MEM_OFFSETS(f) \ 453 ((const struct ia_css_memory_offsets *)((const char *)(f) + (f)->blob.mem_offsets)) 454 455 enum ia_css_sp_sleep_mode { 456 SP_DISABLE_SLEEP_MODE = 0, 457 SP_SLEEP_AFTER_FRAME = BIT(0), 458 SP_SLEEP_AFTER_IRQ = BIT(1), 459 }; 460 #endif /* _IA_CSS_ACC_TYPES_H */ 461