1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "drm-uapi/drm_fourcc.h"
46 #include "util/compiler.h"
47 #include "util/macros.h"
48 #include "util/format/u_format.h"
49
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
53
54 struct intel_device_info;
55
56 #ifndef ISL_GFX_VER
57 /**
58 * Get the hardware generation of isl_device.
59 *
60 * You can define this as a compile-time constant in the CFLAGS. For example,
61 * ``gcc -DISL_GFX_VER(dev)=9 ...``.
62 */
63 #define ISL_GFX_VER(__dev) ((__dev)->info->ver)
64 #define ISL_GFX_VERX10(__dev) ((__dev)->info->verx10)
65 #define ISL_GFX_VER_SANITIZE(__dev)
66 #else
67 #define ISL_GFX_VER_SANITIZE(__dev) \
68 (assert(ISL_GFX_VER(__dev) == (__dev)->info->ver) && \
69 ISL_GFX_VERX10(__dev) == (__dev)->info->verx10))
70 #endif
71
72 #ifndef ISL_DEV_IS_G4X
73 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->platform == INTEL_PLATFORM_G4X)
74 #endif
75
76 #ifndef ISL_DEV_IS_HASWELL
77 /**
78 * @brief Get the hardware generation of isl_device.
79 *
80 * You can define this as a compile-time constant in the CFLAGS. For example,
81 * ``gcc -DISL_GFX_VER(dev)=9 ...``.
82 */
83 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->platform == INTEL_PLATFORM_HSW)
84 #endif
85
86 #ifndef ISL_DEV_IS_BAYTRAIL
87 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->platform == INTEL_PLATFORM_BYT)
88 #endif
89
90 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
91 /**
92 * You can define this as a compile-time constant in the CFLAGS. For example,
93 * ``gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...``.
94 */
95 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
96 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
97 #else
98 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
99 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
100 #endif
101
102 /**
103 * Hardware enumeration SURFACE_FORMAT.
104 *
105 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
106 * Enumerations: SURFACE_FORMAT.
107 */
108 enum isl_format {
109 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
110 ISL_FORMAT_R32G32B32A32_SINT = 1,
111 ISL_FORMAT_R32G32B32A32_UINT = 2,
112 ISL_FORMAT_R32G32B32A32_UNORM = 3,
113 ISL_FORMAT_R32G32B32A32_SNORM = 4,
114 ISL_FORMAT_R64G64_FLOAT = 5,
115 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
116 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
117 ISL_FORMAT_R32G32B32A32_USCALED = 8,
118 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
119 ISL_FORMAT_R64G64_PASSTHRU = 33,
120 ISL_FORMAT_R32G32B32_FLOAT = 64,
121 ISL_FORMAT_R32G32B32_SINT = 65,
122 ISL_FORMAT_R32G32B32_UINT = 66,
123 ISL_FORMAT_R32G32B32_UNORM = 67,
124 ISL_FORMAT_R32G32B32_SNORM = 68,
125 ISL_FORMAT_R32G32B32_SSCALED = 69,
126 ISL_FORMAT_R32G32B32_USCALED = 70,
127 ISL_FORMAT_R32G32B32_SFIXED = 80,
128 ISL_FORMAT_R16G16B16A16_UNORM = 128,
129 ISL_FORMAT_R16G16B16A16_SNORM = 129,
130 ISL_FORMAT_R16G16B16A16_SINT = 130,
131 ISL_FORMAT_R16G16B16A16_UINT = 131,
132 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
133 ISL_FORMAT_R32G32_FLOAT = 133,
134 ISL_FORMAT_R32G32_SINT = 134,
135 ISL_FORMAT_R32G32_UINT = 135,
136 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
137 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
138 ISL_FORMAT_L32A32_FLOAT = 138,
139 ISL_FORMAT_R32G32_UNORM = 139,
140 ISL_FORMAT_R32G32_SNORM = 140,
141 ISL_FORMAT_R64_FLOAT = 141,
142 ISL_FORMAT_R16G16B16X16_UNORM = 142,
143 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
144 ISL_FORMAT_A32X32_FLOAT = 144,
145 ISL_FORMAT_L32X32_FLOAT = 145,
146 ISL_FORMAT_I32X32_FLOAT = 146,
147 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
148 ISL_FORMAT_R16G16B16A16_USCALED = 148,
149 ISL_FORMAT_R32G32_SSCALED = 149,
150 ISL_FORMAT_R32G32_USCALED = 150,
151 ISL_FORMAT_R32G32_FLOAT_LD = 151,
152 ISL_FORMAT_R32G32_SFIXED = 160,
153 ISL_FORMAT_R64_PASSTHRU = 161,
154 ISL_FORMAT_B8G8R8A8_UNORM = 192,
155 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
156 ISL_FORMAT_R10G10B10A2_UNORM = 194,
157 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
158 ISL_FORMAT_R10G10B10A2_UINT = 196,
159 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
160 ISL_FORMAT_R8G8B8A8_UNORM = 199,
161 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
162 ISL_FORMAT_R8G8B8A8_SNORM = 201,
163 ISL_FORMAT_R8G8B8A8_SINT = 202,
164 ISL_FORMAT_R8G8B8A8_UINT = 203,
165 ISL_FORMAT_R16G16_UNORM = 204,
166 ISL_FORMAT_R16G16_SNORM = 205,
167 ISL_FORMAT_R16G16_SINT = 206,
168 ISL_FORMAT_R16G16_UINT = 207,
169 ISL_FORMAT_R16G16_FLOAT = 208,
170 ISL_FORMAT_B10G10R10A2_UNORM = 209,
171 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
172 ISL_FORMAT_R11G11B10_FLOAT = 211,
173 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
174 ISL_FORMAT_R32_SINT = 214,
175 ISL_FORMAT_R32_UINT = 215,
176 ISL_FORMAT_R32_FLOAT = 216,
177 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
178 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
179 ISL_FORMAT_L32_UNORM = 221,
180 ISL_FORMAT_A32_UNORM = 222,
181 ISL_FORMAT_L16A16_UNORM = 223,
182 ISL_FORMAT_I24X8_UNORM = 224,
183 ISL_FORMAT_L24X8_UNORM = 225,
184 ISL_FORMAT_A24X8_UNORM = 226,
185 ISL_FORMAT_I32_FLOAT = 227,
186 ISL_FORMAT_L32_FLOAT = 228,
187 ISL_FORMAT_A32_FLOAT = 229,
188 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
189 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
190 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
191 ISL_FORMAT_B8G8R8X8_UNORM = 233,
192 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
193 ISL_FORMAT_R8G8B8X8_UNORM = 235,
194 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
195 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
196 ISL_FORMAT_B10G10R10X2_UNORM = 238,
197 ISL_FORMAT_L16A16_FLOAT = 240,
198 ISL_FORMAT_R32_UNORM = 241,
199 ISL_FORMAT_R32_SNORM = 242,
200 ISL_FORMAT_R10G10B10X2_USCALED = 243,
201 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
202 ISL_FORMAT_R8G8B8A8_USCALED = 245,
203 ISL_FORMAT_R16G16_SSCALED = 246,
204 ISL_FORMAT_R16G16_USCALED = 247,
205 ISL_FORMAT_R32_SSCALED = 248,
206 ISL_FORMAT_R32_USCALED = 249,
207 ISL_FORMAT_B5G6R5_UNORM = 256,
208 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
209 ISL_FORMAT_B5G5R5A1_UNORM = 258,
210 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
211 ISL_FORMAT_B4G4R4A4_UNORM = 260,
212 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
213 ISL_FORMAT_R8G8_UNORM = 262,
214 ISL_FORMAT_R8G8_SNORM = 263,
215 ISL_FORMAT_R8G8_SINT = 264,
216 ISL_FORMAT_R8G8_UINT = 265,
217 ISL_FORMAT_R16_UNORM = 266,
218 ISL_FORMAT_R16_SNORM = 267,
219 ISL_FORMAT_R16_SINT = 268,
220 ISL_FORMAT_R16_UINT = 269,
221 ISL_FORMAT_R16_FLOAT = 270,
222 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
223 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
224 ISL_FORMAT_I16_UNORM = 273,
225 ISL_FORMAT_L16_UNORM = 274,
226 ISL_FORMAT_A16_UNORM = 275,
227 ISL_FORMAT_L8A8_UNORM = 276,
228 ISL_FORMAT_I16_FLOAT = 277,
229 ISL_FORMAT_L16_FLOAT = 278,
230 ISL_FORMAT_A16_FLOAT = 279,
231 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
232 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
233 ISL_FORMAT_B5G5R5X1_UNORM = 282,
234 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
235 ISL_FORMAT_R8G8_SSCALED = 284,
236 ISL_FORMAT_R8G8_USCALED = 285,
237 ISL_FORMAT_R16_SSCALED = 286,
238 ISL_FORMAT_R16_USCALED = 287,
239 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
240 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
241 ISL_FORMAT_A1B5G5R5_UNORM = 292,
242 ISL_FORMAT_A4B4G4R4_UNORM = 293,
243 ISL_FORMAT_L8A8_UINT = 294,
244 ISL_FORMAT_L8A8_SINT = 295,
245 ISL_FORMAT_R8_UNORM = 320,
246 ISL_FORMAT_R8_SNORM = 321,
247 ISL_FORMAT_R8_SINT = 322,
248 ISL_FORMAT_R8_UINT = 323,
249 ISL_FORMAT_A8_UNORM = 324,
250 ISL_FORMAT_I8_UNORM = 325,
251 ISL_FORMAT_L8_UNORM = 326,
252 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
253 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
254 ISL_FORMAT_R8_SSCALED = 329,
255 ISL_FORMAT_R8_USCALED = 330,
256 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
257 ISL_FORMAT_L8_UNORM_SRGB = 332,
258 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
259 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
260 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
261 ISL_FORMAT_Y8_UNORM = 336,
262 ISL_FORMAT_L8_UINT = 338,
263 ISL_FORMAT_L8_SINT = 339,
264 ISL_FORMAT_I8_UINT = 340,
265 ISL_FORMAT_I8_SINT = 341,
266 ISL_FORMAT_DXT1_RGB_SRGB = 384,
267 ISL_FORMAT_R1_UNORM = 385,
268 ISL_FORMAT_YCRCB_NORMAL = 386,
269 ISL_FORMAT_YCRCB_SWAPUVY = 387,
270 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
271 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
272 ISL_FORMAT_BC1_UNORM = 390,
273 ISL_FORMAT_BC2_UNORM = 391,
274 ISL_FORMAT_BC3_UNORM = 392,
275 ISL_FORMAT_BC4_UNORM = 393,
276 ISL_FORMAT_BC5_UNORM = 394,
277 ISL_FORMAT_BC1_UNORM_SRGB = 395,
278 ISL_FORMAT_BC2_UNORM_SRGB = 396,
279 ISL_FORMAT_BC3_UNORM_SRGB = 397,
280 ISL_FORMAT_MONO8 = 398,
281 ISL_FORMAT_YCRCB_SWAPUV = 399,
282 ISL_FORMAT_YCRCB_SWAPY = 400,
283 ISL_FORMAT_DXT1_RGB = 401,
284 ISL_FORMAT_FXT1 = 402,
285 ISL_FORMAT_R8G8B8_UNORM = 403,
286 ISL_FORMAT_R8G8B8_SNORM = 404,
287 ISL_FORMAT_R8G8B8_SSCALED = 405,
288 ISL_FORMAT_R8G8B8_USCALED = 406,
289 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
290 ISL_FORMAT_R64G64B64_FLOAT = 408,
291 ISL_FORMAT_BC4_SNORM = 409,
292 ISL_FORMAT_BC5_SNORM = 410,
293 ISL_FORMAT_R16G16B16_FLOAT = 411,
294 ISL_FORMAT_R16G16B16_UNORM = 412,
295 ISL_FORMAT_R16G16B16_SNORM = 413,
296 ISL_FORMAT_R16G16B16_SSCALED = 414,
297 ISL_FORMAT_R16G16B16_USCALED = 415,
298 ISL_FORMAT_BC6H_SF16 = 417,
299 ISL_FORMAT_BC7_UNORM = 418,
300 ISL_FORMAT_BC7_UNORM_SRGB = 419,
301 ISL_FORMAT_BC6H_UF16 = 420,
302 ISL_FORMAT_PLANAR_420_8 = 421,
303 ISL_FORMAT_PLANAR_420_16 = 422,
304 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
305 ISL_FORMAT_ETC1_RGB8 = 425,
306 ISL_FORMAT_ETC2_RGB8 = 426,
307 ISL_FORMAT_EAC_R11 = 427,
308 ISL_FORMAT_EAC_RG11 = 428,
309 ISL_FORMAT_EAC_SIGNED_R11 = 429,
310 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
311 ISL_FORMAT_ETC2_SRGB8 = 431,
312 ISL_FORMAT_R16G16B16_UINT = 432,
313 ISL_FORMAT_R16G16B16_SINT = 433,
314 ISL_FORMAT_R32_SFIXED = 434,
315 ISL_FORMAT_R10G10B10A2_SNORM = 435,
316 ISL_FORMAT_R10G10B10A2_USCALED = 436,
317 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
318 ISL_FORMAT_R10G10B10A2_SINT = 438,
319 ISL_FORMAT_B10G10R10A2_SNORM = 439,
320 ISL_FORMAT_B10G10R10A2_USCALED = 440,
321 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
322 ISL_FORMAT_B10G10R10A2_UINT = 442,
323 ISL_FORMAT_B10G10R10A2_SINT = 443,
324 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
325 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
326 ISL_FORMAT_ETC2_RGB8_PTA = 448,
327 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
328 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
329 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
330 ISL_FORMAT_R8G8B8_UINT = 456,
331 ISL_FORMAT_R8G8B8_SINT = 457,
332 ISL_FORMAT_RAW = 511,
333 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
334 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
335 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
336 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
337 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
338 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
339 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
340 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
341 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
342 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
343 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
344 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
345 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
346 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
347 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
348 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
349 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
350 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
351 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
352 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
353 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
354 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
355 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
356 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
357 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
358 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
359 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
360 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
361 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
362 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
363 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
364 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
365 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
366 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
367 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
368 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
369 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
370 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
371 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
372 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
373 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
374 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
375
376 /* The formats that follow are internal to ISL and as such don't have an
377 * explicit number. We'll just let the C compiler assign it for us. Any
378 * actual hardware formats *must* come before these in the list.
379 */
380
381 /* Formats for the aux-map */
382 ISL_FORMAT_PLANAR_420_10,
383 ISL_FORMAT_PLANAR_420_12,
384
385 /* Formats for auxiliary surfaces */
386 ISL_FORMAT_HIZ,
387 ISL_FORMAT_GFX125_HIZ,
388 ISL_FORMAT_MCS_2X,
389 ISL_FORMAT_MCS_4X,
390 ISL_FORMAT_MCS_8X,
391 ISL_FORMAT_MCS_16X,
392 ISL_FORMAT_GFX7_CCS_32BPP_X,
393 ISL_FORMAT_GFX7_CCS_64BPP_X,
394 ISL_FORMAT_GFX7_CCS_128BPP_X,
395 ISL_FORMAT_GFX7_CCS_32BPP_Y,
396 ISL_FORMAT_GFX7_CCS_64BPP_Y,
397 ISL_FORMAT_GFX7_CCS_128BPP_Y,
398 ISL_FORMAT_GFX9_CCS_32BPP,
399 ISL_FORMAT_GFX9_CCS_64BPP,
400 ISL_FORMAT_GFX9_CCS_128BPP,
401 ISL_FORMAT_GFX12_CCS_8BPP_Y0,
402 ISL_FORMAT_GFX12_CCS_16BPP_Y0,
403 ISL_FORMAT_GFX12_CCS_32BPP_Y0,
404 ISL_FORMAT_GFX12_CCS_64BPP_Y0,
405 ISL_FORMAT_GFX12_CCS_128BPP_Y0,
406
407 /* An upper bound on the supported format enumerations */
408 ISL_NUM_FORMATS,
409
410 /* Hardware doesn't understand this out-of-band value */
411 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
412 };
413
414 /**
415 * Numerical base type for channels of isl_format.
416 */
417 enum ENUM_PACKED isl_base_type {
418 /** Data which takes up space but is ignored */
419 ISL_VOID,
420
421 /** Data in a "raw" form and cannot be easily interpreted */
422 ISL_RAW,
423
424 /**
425 * Unsigned normalized data
426 *
427 * Though stored as an integer, the data is interpreted as a floating-point
428 * number in the range [0, 1] where the conversion from the in-memory
429 * representation to float is given by :math:`\frac{x}{2^{bits} - 1}`.
430 */
431 ISL_UNORM,
432
433 /**
434 * Signed normalized data
435 *
436 * Though stored as an integer, the data is interpreted as a floating-point
437 * number in the range [-1, 1] where the conversion from the in-memory
438 * representation to float is given by
439 * :math:`max\left(\frac{x}{2^{bits - 1} - 1}, -1\right)`.
440 */
441 ISL_SNORM,
442
443 /**
444 * Unsigned floating-point data
445 *
446 * Unlike the standard IEEE floating-point representation, unsigned
447 * floating-point data has no sign bit. This saves a bit of space which is
448 * important if more than one float is required to represent a color value.
449 * As with IEEE floats, the high bits are the exponent and the low bits are
450 * the mantissa. The available bit sizes for unsigned floats are as
451 * follows:
452 *
453 * ===== ========= =========
454 * Bits Mantissa Exponent
455 * ===== ========= =========
456 * 11 6 5
457 * 10 5 5
458 * ===== ========= =========
459 *
460 * In particular, both unsigned floating-point formats are identical to
461 * IEEE float16 except that the sign bit and the bottom mantissa bits are
462 * removed.
463 */
464 ISL_UFLOAT,
465
466 /** Signed floating-point data
467 *
468 * Signed floating-point data is represented as standard IEEE floats with
469 * the usual number of mantissa and exponent bits
470 *
471 * ===== ========= =========
472 * Bits Mantissa Exponent
473 * ===== ========= =========
474 * 64 52 11
475 * 32 23 8
476 * 16 10 5
477 * ===== ========= =========
478 */
479 ISL_SFLOAT,
480
481 /**
482 * Unsigned fixed-point data
483 *
484 * This is a 32-bit unsigned integer that is interpreted as a 16.16
485 * fixed-point value.
486 */
487 ISL_UFIXED,
488
489 /**
490 * Signed fixed-point data
491 *
492 * This is a 32-bit signed integer that is interpreted as a 16.16
493 * fixed-point value.
494 */
495 ISL_SFIXED,
496
497 /** Unsigned integer data */
498 ISL_UINT,
499
500 /** Signed integer data */
501 ISL_SINT,
502
503 /**
504 * Unsigned scaled data
505 *
506 * This is data which is stored as an unsigned integer but interpreted as a
507 * floating-point value by the hardware. The re-interpretation is done via
508 * a simple unsigned integer to float cast. This is typically used as a
509 * vertex format.
510 */
511 ISL_USCALED,
512
513 /**
514 * Signed scaled data
515 *
516 * This is data which is stored as a signed integer but interpreted as a
517 * floating-point value by the hardware. The re-interpretation is done via
518 * a simple signed integer to float cast. This is typically used as a
519 * vertex format.
520 */
521 ISL_SSCALED,
522 };
523
524 /**
525 * Colorspace of isl_format.
526 */
527 enum isl_colorspace {
528 ISL_COLORSPACE_NONE = 0,
529 ISL_COLORSPACE_LINEAR,
530 ISL_COLORSPACE_SRGB,
531 ISL_COLORSPACE_YUV,
532 };
533
534 /**
535 * Texture compression mode of isl_format.
536 */
537 enum isl_txc {
538 ISL_TXC_NONE = 0,
539 ISL_TXC_DXT1,
540 ISL_TXC_DXT3,
541 ISL_TXC_DXT5,
542 ISL_TXC_FXT1,
543 ISL_TXC_RGTC1,
544 ISL_TXC_RGTC2,
545 ISL_TXC_BPTC,
546 ISL_TXC_ETC1,
547 ISL_TXC_ETC2,
548 ISL_TXC_ASTC,
549
550 /* Used for auxiliary surface formats */
551 ISL_TXC_HIZ,
552 ISL_TXC_MCS,
553 ISL_TXC_CCS,
554 };
555
556 /**
557 * Describes the memory tiling of a surface
558 *
559 * This differs from the HW enum values used to represent tiling. The bits
560 * used by hardware have varried significantly over the years from the
561 * "Tile Walk" bit on old pre-Broadwell parts to the "Tile Mode" enum on
562 * Broadwell to the combination of "Tile Mode" and "Tiled Resource Mode" on
563 * Skylake. This enum represents them all in a consistent manner and in one
564 * place.
565 *
566 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
567 * clearly distinguish it from Yf and Ys.
568 */
569 enum isl_tiling {
570 /** Linear, or no tiling */
571 ISL_TILING_LINEAR = 0,
572 /** W tiling */
573 ISL_TILING_W,
574 /** X tiling */
575 ISL_TILING_X,
576 /** Legacy Y tiling */
577 ISL_TILING_Y0,
578 /** Standard 4K tiling. The 'f' means "four". */
579 ISL_TILING_SKL_Yf,
580 /** Standard 64K tiling. The 's' means "sixty-four". */
581 ISL_TILING_SKL_Ys,
582 /** Standard 4K tiling. The 'f' means "four". */
583 ISL_TILING_ICL_Yf,
584 /** Standard 64K tiling. The 's' means "sixty-four". */
585 ISL_TILING_ICL_Ys,
586 /** 4K tiling. */
587 ISL_TILING_4,
588 /** 64K tiling.*/
589 ISL_TILING_64,
590 /** Xe2 64K tiling.*/
591 ISL_TILING_64_XE2,
592 /** Tiling format for HiZ surfaces */
593 ISL_TILING_HIZ,
594 /** Tiling format for CCS surfaces */
595 ISL_TILING_CCS,
596 };
597
598 /**
599 * @defgroup Tiling Flags
600 * @{
601 */
602 typedef uint32_t isl_tiling_flags_t;
603 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
604 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
605 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
606 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
607 #define ISL_TILING_SKL_Yf_BIT (1u << ISL_TILING_SKL_Yf)
608 #define ISL_TILING_SKL_Ys_BIT (1u << ISL_TILING_SKL_Ys)
609 #define ISL_TILING_ICL_Yf_BIT (1u << ISL_TILING_ICL_Yf)
610 #define ISL_TILING_ICL_Ys_BIT (1u << ISL_TILING_ICL_Ys)
611 #define ISL_TILING_4_BIT (1u << ISL_TILING_4)
612 #define ISL_TILING_64_BIT (1u << ISL_TILING_64)
613 #define ISL_TILING_64_XE2_BIT (1u << ISL_TILING_64_XE2)
614 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
615 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
616 #define ISL_TILING_ANY_MASK (~0u)
617 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
618
619 /** Any Y tiling, including legacy Y tiling. */
620 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
621 ISL_TILING_SKL_Yf_BIT | \
622 ISL_TILING_SKL_Ys_BIT | \
623 ISL_TILING_ICL_Yf_BIT | \
624 ISL_TILING_ICL_Ys_BIT)
625
626 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
627 #define ISL_TILING_STD_Y_MASK (ISL_TILING_SKL_Yf_BIT | \
628 ISL_TILING_SKL_Ys_BIT | \
629 ISL_TILING_ICL_Yf_BIT | \
630 ISL_TILING_ICL_Ys_BIT)
631
632 /** Any Tiling 64 */
633 #define ISL_TILING_STD_64_MASK (ISL_TILING_64_BIT | \
634 ISL_TILING_64_XE2_BIT)
635
636 /** @} */
637
638 /**
639 * @brief Logical dimension of surface.
640 *
641 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
642 * as 2D array surfaces.
643 */
644 enum isl_surf_dim {
645 ISL_SURF_DIM_1D,
646 ISL_SURF_DIM_2D,
647 ISL_SURF_DIM_3D,
648 };
649
650 /**
651 * @brief Physical layout of the surface's dimensions.
652 */
653 enum isl_dim_layout {
654 /**
655 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
656 * 6.17.3: 2D Surfaces.
657 *
658 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
659 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
660 *
661 * One-dimensional surfaces are identical to 2D surfaces with height of
662 * one.
663 */
664 ISL_DIM_LAYOUT_GFX4_2D,
665
666 /**
667 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
668 * 6.17.5: 3D Surfaces.
669 *
670 * :invariant: isl_surf::phys_level0_sa::array_len == 1
671 */
672 ISL_DIM_LAYOUT_GFX4_3D,
673
674 /**
675 * Special layout used for HiZ and stencil on Sandy Bridge to work around
676 * the hardware's lack of mipmap support. On gfx6, HiZ and stencil buffers
677 * work the same as on gfx7+ except that they don't technically support
678 * mipmapping. That does not, however, stop us from doing it. As far as
679 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
680 * single miplevel 2D (possibly array) image. The dimensions of that image
681 * are NOT minified.
682 *
683 * In order to implement HiZ and stencil on Sandy Bridge, we create one
684 * full-sized 2D (possibly array) image for every LOD with every image
685 * aligned to a page boundary. When the surface is used with the stencil
686 * or HiZ hardware, we manually offset to the image for the given LOD.
687 *
688 * As a memory saving measure, we pretend that the width of each miplevel
689 * is minified and we place LOD1 and above below LOD0 but horizontally
690 * adjacent to each other. When considered as full-sized images, LOD1 and
691 * above technically overlap. However, since we only write to part of that
692 * image, the hardware will never notice the overlap.
693 *
694 * This layout looks something like this:
695 *
696 * +---------+
697 * | |
698 * | |
699 * +---------+
700 * | |
701 * | |
702 * +---------+
703 *
704 * +----+ +-+ .
705 * | | +-+
706 * +----+
707 *
708 * +----+ +-+ .
709 * | | +-+
710 * +----+
711 */
712 ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ,
713
714 /**
715 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
716 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
717 */
718 ISL_DIM_LAYOUT_GFX9_1D,
719 };
720
721 /**
722 * Enumerates the different forms of auxiliary surface compression
723 */
724 enum isl_aux_usage {
725 /** No Auxiliary surface is used */
726 ISL_AUX_USAGE_NONE,
727
728 /** Hierarchical depth compression
729 *
730 * First introduced on Iron Lake, this compression scheme compresses depth
731 * surfaces by storing alternate forms of the depth value in a HiZ surface.
732 * Possible (not all) compressed forms include:
733 *
734 * - An uncompressed "look at the main surface" value
735 *
736 * - A special value indicating that the main surface data should be
737 * ignored and considered to contain the clear value.
738 *
739 * - The depth for the entire main-surface block as a plane equation
740 *
741 * - The minimum/maximum depth for the main-surface block
742 *
743 * This second one isn't helpful for getting exact depth values but can
744 * still substantially accelerate depth testing if the specified range is
745 * sufficiently small.
746 */
747 ISL_AUX_USAGE_HIZ,
748
749 /** Multisampled color compression
750 *
751 * Introduced on Ivy Bridge, this compression scheme compresses
752 * multisampled color surfaces by storing a mapping from samples to planes
753 * in the MCS surface, allowing for de-duplication of identical samples.
754 * The MCS value of all 1's is reserved to indicate that the pixel contains
755 * the clear color. Exact details about the data stored in the MCS and how
756 * it maps samples to slices is documented in the PRMs.
757 *
758 * :invariant: :c:member:`isl_surf.samples` > 1
759 */
760 ISL_AUX_USAGE_MCS,
761
762 /** Single-sampled fast-clear-only color compression
763 *
764 * Introduced on Ivy Bridge, this compression scheme compresses
765 * single-sampled color surfaces by storing a bit for each cache line pair
766 * in the main surface in the CCS which indicates that the corresponding
767 * pair of cache lines in the main surface only contains the clear color.
768 * On Skylake, this is increased to two bits per cache line pair with 0x0
769 * meaning resolved and 0x3 meaning clear.
770 *
771 * :invariant: The surface is a color surface
772 * :invariant: :c:member:`isl_surf.samples` == 1
773 */
774 ISL_AUX_USAGE_CCS_D,
775
776 /** Single-sample lossless color compression
777 *
778 * Introduced on Skylake, this compression scheme compresses single-sampled
779 * color surfaces by storing a 2-bit value for each cache line pair in the
780 * main surface which says how the corresponding pair of cache lines in the
781 * main surface are to be interpreted. Valid CCS values include:
782 *
783 * - ``0x0``: Indicates that the corresponding pair of cache lines in the
784 * main surface contain valid color data
785 *
786 * - ``0x1``: Indicates that the corresponding pair of cache lines in the
787 * main surface contain compressed color data. Typically, the
788 * compressed data fits in one of the two cache lines.
789 *
790 * - ``0x3``: Indicates that the corresponding pair of cache lines in the
791 * main surface should be ignored. Those cache lines should be
792 * considered to contain the clear color.
793 *
794 * Starting with Tigerlake, each CCS value is 4 bits per cache line pair in
795 * the main surface.
796 *
797 * :invariant: The surface is a color surface
798 * :invariant: :c:member:`isl_surf.samples` == 1
799 */
800 ISL_AUX_USAGE_CCS_E,
801
802 /** Single-sample lossless color compression with fast clear optimization
803 *
804 * Introduced on Tigerlake, this is identical to ISL_AUX_USAGE_CCS_E except
805 * it also encodes a feature about regular render writes possibly
806 * fast-clearing blocks in the surface. In the Alchemist docs, the name of
807 * the feature is easier to find. In the 3DSTATE_3D_MODE packet, it is
808 * referred to as "Fast Clear Optimization (FCV)".
809 *
810 * :invariant: The surface is a color surface
811 * :invariant: :c:member:`isl_surf.samples` == 1
812 */
813 ISL_AUX_USAGE_FCV_CCS_E,
814
815 /** Media color compression
816 *
817 * Used by the media engine on Tigerlake and above. This compression form
818 * is typically not produced by 3D drivers but they need to be able to
819 * consume it in order to get end-to-end compression when the image comes
820 * from media decode.
821 *
822 * :invariant: The surface is a color surface
823 * :invariant: :c:member:`isl_surf.samples` == 1
824 */
825 ISL_AUX_USAGE_MC,
826
827 /** Combined HiZ+CCS in write-through mode
828 *
829 * In this mode, introduced on Tigerlake, the HiZ and CCS surfaces act as a
830 * single fused compression surface where resolves (but not ambiguates)
831 * operate on both surfaces at the same time. In this mode, the HiZ
832 * surface operates in write-through mode where it is only used for
833 * accelerating depth testing and not for actual compression. The
834 * CCS-compressed surface contains valid data at all times.
835 *
836 * :invariant: The surface is a color surface
837 * :invariant: :c:member:`isl_surf.samples` == 1 for GFX 12, GFX 20 can
838 * be multisampled
839 */
840 ISL_AUX_USAGE_HIZ_CCS_WT,
841
842 /** Combined HiZ+CCS without write-through
843 *
844 * In this mode, introduced on Tigerlake, the HiZ and CCS surfaces act as a
845 * single fused compression surface where resolves (but not ambiguates)
846 * operate on both surfaces at the same time. In this mode, full HiZ
847 * compression is enabled and the CCS-compressed main surface may not
848 * contain valid data. The only way to read the surface outside of the
849 * depth hardware is to do a full resolve which resolves both HiZ and CCS
850 * so the surface is in the pass-through state.
851 *
852 * :invariant: The surface is a depth surface
853 */
854 ISL_AUX_USAGE_HIZ_CCS,
855
856 /** Combined MCS+CCS without write-through
857 *
858 * In this mode, introduced on Tigerlake, we have fused MCS+CCS compression
859 * where the MCS is used for fast-clears and "identical samples"
860 * compression just like on Gfx7-11 but each plane is then CCS compressed.
861 *
862 * :invariant: The surface is a depth surface
863 * :invariant: :c:member:`isl_surf.samples` > 1
864 */
865 ISL_AUX_USAGE_MCS_CCS,
866
867 /** Stencil compression
868 *
869 * Introduced on Tigerlake, this is similar to CCS_E only used to compress
870 * stencil surfaces.
871 *
872 * :invariant: The surface is a stencil surface
873 * :invariant: :c:member:`isl_surf.samples` == 1
874 */
875 ISL_AUX_USAGE_STC_CCS,
876 };
877
878 /**
879 * Enum for keeping track of the state an auxiliary compressed surface.
880 *
881 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
882 * given slice (lod + array layer) can be in one of the seven states described
883 * by this enum. Drawing with or without aux enabled may implicitly cause the
884 * surface to transition between these states. There are also four types of
885 * auxiliary compression operations which cause an explicit transition which
886 * are described by the isl_aux_op enum below.
887 *
888 * Not all operations are valid or useful in all states. The diagram below
889 * contains a complete description of the states and all valid and useful
890 * transitions except clear.
891 *
892 * ::
893 *
894 * Draw w/ Aux
895 * +----------+
896 * | |
897 * | +-------------+ Draw w/ Aux +-------------+
898 * +------>| Compressed |<-------------------| Clear |
899 * | w/ Clear |----->----+ | |
900 * +-------------+ | +-------------+
901 * | /|\ | | |
902 * | | | | |
903 * | | +------<-----+ | Draw w/
904 * | | | | Clear Only
905 * | | Full | | +----------+
906 * Partial | | Resolve | \|/ | |
907 * Resolve | | | +-------------+ |
908 * | | | | Partial |<------+
909 * | | | | Clear |<----------+
910 * | | | +-------------+ |
911 * | | | | |
912 * | | +------>---------+ Full |
913 * | | | Resolve |
914 * Draw w/ aux | | Partial Fast Clear | |
915 * +----------+ | +--------------------------+ | |
916 * | | \|/ | \|/ |
917 * | +-------------+ Full Resolve +-------------+ |
918 * +------>| Compressed |------------------->| Resolved | |
919 * | w/o Clear |<-------------------| | |
920 * +-------------+ Draw w/ Aux +-------------+ |
921 * /|\ | | |
922 * | Draw | | Draw |
923 * | w/ Aux | | w/o Aux |
924 * | Ambiguate | | |
925 * | +--------------------------+ | |
926 * Draw w/o Aux | | | Draw w/o Aux |
927 * +----------+ | | | +----------+ |
928 * | | | \|/ \|/ | | |
929 * | +-------------+ Ambiguate +-------------+ | |
930 * +------>| Pass- |<-------------------| Aux |<------+ |
931 * +------>| through | | Invalid | |
932 * | +-------------+ +-------------+ |
933 * | | | |
934 * +----------+ +-----------------------------------------------------+
935 * Draw w/ Partial Fast Clear
936 * Clear Only
937 *
938 *
939 * While the above general theory applies to all forms of auxiliary
940 * compression on Intel hardware, not all states and operations are available
941 * on all compression types. However, each of the auxiliary states and
942 * operations can be fairly easily mapped onto the above diagram:
943 *
944 * **HiZ:** Hierarchical depth compression is capable of being in any of
945 * the states above. Hardware provides three HiZ operations: "Depth
946 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast Clear",
947 * "Full Resolve", and "Ambiguate" respectively. The hardware provides no
948 * HiZ partial resolve operation so the only way to get into the
949 * "Compressed w/o Clear" state is to render with HiZ when the surface is
950 * in the resolved or pass-through states.
951 *
952 * **MCS:** Multisample compression is technically capable of being in any of
953 * the states above except that most of them aren't useful. Both the render
954 * engine and the sampler support MCS compression and, apart from clear color,
955 * MCS is format-unaware so we leave the surface compressed 100% of the time.
956 * The hardware provides no MCS operations.
957 *
958 * **CCS_D:** Single-sample fast-clears (also called CCS_D in ISL) are one of
959 * the simplest forms of compression since they don't do anything beyond clear
960 * color tracking. They really only support three of the six states: Clear,
961 * Partial Clear, and Pass-through. The only CCS_D operation is "Resolve"
962 * which maps to a full resolve followed by an ambiguate.
963 *
964 * **CCS_E:** Single-sample render target compression (also called CCS_E in
965 * ISL) is capable of being in almost all of the above states. THe only
966 * exception is that it does not have separate resolved and pass- through
967 * states. Instead, the CCS_E full resolve operation does both a resolve and
968 * an ambiguate so it goes directly into the pass-through state. CCS_E also
969 * provides fast clear and partial resolve operations which work as described
970 * above.
971 *
972 * .. note::
973 *
974 * The state machine above isn't quite correct for CCS on TGL. There is a
975 * HW bug (or feature, depending on who you ask) which can cause blocks to
976 * enter the fast-clear state as a side-effect of a regular draw call. This
977 * means that a draw in the resolved or compressed without clear states
978 * takes you to the compressed with clear state, not the compressed without
979 * clear state.
980 */
981 enum isl_aux_state {
982 #ifdef IN_UNIT_TEST
983 ISL_AUX_STATE_ASSERT,
984 #endif
985 /** Clear
986 *
987 * In this state, each block in the auxiliary surface contains a magic
988 * value that indicates that the block is in the clear state. If a block
989 * is in the clear state, its values in the primary surface are ignored
990 * and the color of the samples in the block is taken either the
991 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for depth.
992 * Since neither the primary surface nor the auxiliary surface contains the
993 * clear value, the surface can be cleared to a different color by simply
994 * changing the clear color without modifying either surface.
995 */
996 ISL_AUX_STATE_CLEAR,
997
998 /** Partial Clear
999 *
1000 * In this state, each block in the auxiliary surface contains either the
1001 * magic clear or pass-through value. See Clear and Pass-through for more
1002 * details.
1003 */
1004 ISL_AUX_STATE_PARTIAL_CLEAR,
1005
1006 /** Compressed with clear color
1007 *
1008 * In this state, neither the auxiliary surface nor the primary surface has
1009 * a complete representation of the data. Instead, both surfaces must be
1010 * used together or else rendering corruption may occur. Depending on the
1011 * auxiliary compression format and the data, any given block in the
1012 * primary surface may contain all, some, or none of the data required to
1013 * reconstruct the actual sample values. Blocks may also be in the clear
1014 * state (see Clear) and have their value taken from outside the surface.
1015 */
1016 ISL_AUX_STATE_COMPRESSED_CLEAR,
1017
1018 /** Compressed without clear color
1019 *
1020 * This state is identical to the state above except that no blocks are in
1021 * the clear state. In this state, all of the data required to reconstruct
1022 * the final sample values is contained in the auxiliary and primary
1023 * surface and the clear value is not considered.
1024 */
1025 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
1026
1027 /** Resolved
1028 *
1029 * In this state, the primary surface contains 100% of the data. The
1030 * auxiliary surface is also valid so the surface can be validly used with
1031 * or without aux enabled. The auxiliary surface may, however, contain
1032 * non-trivial data and any update to the primary surface with aux disabled
1033 * will cause the two to get out of sync.
1034 */
1035 ISL_AUX_STATE_RESOLVED,
1036
1037 /** Pass-through
1038 *
1039 * In this state, the primary surface contains 100% of the data and every
1040 * block in the auxiliary surface contains a magic value which indicates
1041 * that the auxiliary surface should be ignored and only the primary
1042 * surface should be considered. In this mode, the primary surface can
1043 * safely be written with ISL_AUX_USAGE_NONE or by something that ignores
1044 * compression such as the blit/copy engine or a CPU map and it will stay
1045 * in the pass-through state. Writing to a surface in pass-through mode
1046 * with aux enabled may cause the auxiliary to be updated to contain
1047 * non-trivial data and it will no longer be in the pass-through state.
1048 * Likely, it will end up compressed, with or without clear color.
1049 */
1050 ISL_AUX_STATE_PASS_THROUGH,
1051
1052 /** Aux Invalid
1053 *
1054 * In this state, the primary surface contains 100% of the data and the
1055 * auxiliary surface is completely bogus. Any attempt to use the auxiliary
1056 * surface is liable to result in rendering corruption. The only thing
1057 * that one can do to re-enable aux once this state is reached is to use an
1058 * ambiguate pass to transition into the pass-through state.
1059 */
1060 ISL_AUX_STATE_AUX_INVALID,
1061 };
1062
1063 /** Enum describing explicit aux transition operations
1064 *
1065 * These operations are used to transition from one isl_aux_state to another.
1066 * Even though a draw does transition the state machine, it's not included in
1067 * this enum as it's something of a special case.
1068 */
1069 enum isl_aux_op {
1070 #ifdef IN_UNIT_TEST
1071 ISL_AUX_OP_ASSERT,
1072 #endif
1073
1074 /** Do nothing */
1075 ISL_AUX_OP_NONE,
1076
1077 /** Fast Clear
1078 *
1079 * This operation writes the magic "clear" value to the auxiliary surface.
1080 * This operation will safely transition any slice of a surface from any
1081 * state to the clear state so long as the entire slice is fast cleared at
1082 * once. A fast clear that only covers part of a slice of a surface is
1083 * called a partial fast clear.
1084 */
1085 ISL_AUX_OP_FAST_CLEAR,
1086
1087 /** Full Resolve
1088 *
1089 * This operation combines the auxiliary surface data with the primary
1090 * surface data and writes the result to the primary. For HiZ, the docs
1091 * call this a depth resolve. For CCS, the hardware full resolve operation
1092 * does both a full resolve and an ambiguate so it actually takes you all
1093 * the way to the pass-through state.
1094 */
1095 ISL_AUX_OP_FULL_RESOLVE,
1096
1097 /** Partial Resolve
1098 *
1099 * This operation considers blocks which are in the "clear" state and
1100 * writes the clear value directly into the primary or auxiliary surface.
1101 * Once this operation completes, the surface is still compressed but no
1102 * longer references the clear color. This operation is only available
1103 * for CCS_E.
1104 */
1105 ISL_AUX_OP_PARTIAL_RESOLVE,
1106
1107 /** Ambiguate
1108 *
1109 * This operation throws away the current auxiliary data and replaces it
1110 * with the magic pass-through value. If an ambiguate operation is
1111 * performed when the primary surface does not contain 100% of the data,
1112 * data will be lost. This operation is only implemented in hardware for
1113 * depth where it is called a HiZ resolve.
1114 */
1115 ISL_AUX_OP_AMBIGUATE,
1116 };
1117
1118 /* TODO(chadv): Explain */
1119 enum isl_array_pitch_span {
1120 ISL_ARRAY_PITCH_SPAN_FULL,
1121 ISL_ARRAY_PITCH_SPAN_COMPACT,
1122 };
1123
1124 /**
1125 * @defgroup Surface Usage
1126 * @{
1127 */
1128 typedef uint64_t isl_surf_usage_flags_t;
1129 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
1130 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
1131 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
1132 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
1133 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
1134 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
1135 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
1136 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 7)
1137 #define ISL_SURF_USAGE_HIZ_BIT (1u << 8)
1138 #define ISL_SURF_USAGE_MCS_BIT (1u << 9)
1139 #define ISL_SURF_USAGE_CCS_BIT (1u << 10)
1140 #define ISL_SURF_USAGE_VERTEX_BUFFER_BIT (1u << 11)
1141 #define ISL_SURF_USAGE_INDEX_BUFFER_BIT (1u << 12)
1142 #define ISL_SURF_USAGE_CONSTANT_BUFFER_BIT (1u << 13)
1143 #define ISL_SURF_USAGE_STAGING_BIT (1u << 14)
1144 #define ISL_SURF_USAGE_CPB_BIT (1u << 15)
1145 #define ISL_SURF_USAGE_PROTECTED_BIT (1u << 16)
1146 #define ISL_SURF_USAGE_VIDEO_DECODE_BIT (1u << 17)
1147 #define ISL_SURF_USAGE_STREAM_OUT_BIT (1u << 18)
1148 #define ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT (1u << 19)
1149 #define ISL_SURF_USAGE_SPARSE_BIT (1u << 20)
1150 #define ISL_SURF_USAGE_NO_AUX_TT_ALIGNMENT_BIT (1u << 21)
1151 #define ISL_SURF_USAGE_BLITTER_DST_BIT (1u << 22)
1152 #define ISL_SURF_USAGE_BLITTER_SRC_BIT (1u << 23)
1153 #define ISL_SURF_USAGE_MULTI_ENGINE_SEQ_BIT (1u << 24)
1154 #define ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT (1u << 25)
1155 /** @} */
1156
1157 /**
1158 * @defgroup Channel Mask
1159 *
1160 * These #define values are chosen to match the values of
1161 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
1162 *
1163 * @{
1164 */
1165 typedef uint8_t isl_channel_mask_t;
1166 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
1167 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
1168 #define ISL_CHANNEL_RED_BIT (1 << 2)
1169 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
1170 /** @} */
1171
1172 /**
1173 * @brief A channel select (also known as texture swizzle) value
1174 */
1175 enum ENUM_PACKED isl_channel_select {
1176 ISL_CHANNEL_SELECT_ZERO = 0,
1177 ISL_CHANNEL_SELECT_ONE = 1,
1178 ISL_CHANNEL_SELECT_RED = 4,
1179 ISL_CHANNEL_SELECT_GREEN = 5,
1180 ISL_CHANNEL_SELECT_BLUE = 6,
1181 ISL_CHANNEL_SELECT_ALPHA = 7,
1182 };
1183
1184 /**
1185 * Identical to VkSampleCountFlagBits.
1186 */
1187 enum isl_sample_count {
1188 ISL_SAMPLE_COUNT_1_BIT = 1u,
1189 ISL_SAMPLE_COUNT_2_BIT = 2u,
1190 ISL_SAMPLE_COUNT_4_BIT = 4u,
1191 ISL_SAMPLE_COUNT_8_BIT = 8u,
1192 ISL_SAMPLE_COUNT_16_BIT = 16u,
1193 };
1194 typedef uint32_t isl_sample_count_mask_t;
1195
1196 /**
1197 * @brief Multisample Format
1198 */
1199 enum isl_msaa_layout {
1200 /**
1201 * @brief Surface is single-sampled.
1202 */
1203 ISL_MSAA_LAYOUT_NONE,
1204
1205 /**
1206 * @brief [SNB+] Interleaved Multisample Format
1207 *
1208 * In this format, multiple samples are interleaved into each cacheline.
1209 * In other words, the sample index is swizzled into the low 6 bits of the
1210 * surface's virtual address space.
1211 *
1212 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
1213 * and its pixel format is 32bpp. Then the first cacheline is arranged
1214 * thus:
1215 *
1216 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
1217 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
1218 *
1219 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
1220 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
1221 *
1222 * The hardware docs refer to this format with multiple terms. In
1223 * Sandybridge, this is the only multisample format; so no term is used.
1224 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
1225 * Multisample Surface). Later hardware docs additionally refer to this
1226 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
1227 * color surfaces).
1228 *
1229 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
1230 * Surface Behavior".
1231 *
1232 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
1233 * Multisampled Surfaces".
1234 */
1235 ISL_MSAA_LAYOUT_INTERLEAVED,
1236
1237 /**
1238 * @brief [IVB+] Array Multisample Format
1239 *
1240 * In this format, the surface's physical layout resembles that of a
1241 * 2D array surface.
1242 *
1243 * Suppose the multisample surface's logical extent is (w, h) and its
1244 * sample count is N. Then surface's physical extent is the same as
1245 * a singlesample 2D surface whose logical extent is (w, h) and array
1246 * length is N. Array slice ``i`` contains the pixel values for sample
1247 * index ``i``.
1248 *
1249 * The Ivybridge docs refer to surfaces in this format as UMS
1250 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
1251 * Surface). The Broadwell docs additionally refer to this format as
1252 * MSFMT_MSS (MSS=Multisample Surface Storage).
1253 *
1254 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
1255 * Multisample Surfaces".
1256 *
1257 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
1258 * Multisample Surfaces".
1259 */
1260 ISL_MSAA_LAYOUT_ARRAY,
1261 };
1262
1263 typedef enum {
1264 ISL_MEMCPY = 0,
1265 ISL_MEMCPY_BGRA8,
1266 ISL_MEMCPY_STREAMING_LOAD,
1267 ISL_MEMCPY_INVALID,
1268 } isl_memcpy_type;
1269
1270 struct isl_surf_fill_state_info;
1271 struct isl_buffer_fill_state_info;
1272 struct isl_depth_stencil_hiz_emit_info;
1273 struct isl_null_fill_state_info;
1274 struct isl_cpb_emit_info;
1275
1276 struct isl_device {
1277 const struct intel_device_info *info;
1278 bool use_separate_stencil;
1279 bool has_bit6_swizzling;
1280
1281 /**
1282 * Describes the layout of a RENDER_SURFACE_STATE structure for the
1283 * current gen.
1284 */
1285 struct {
1286 uint8_t size;
1287 uint8_t align;
1288 uint8_t addr_offset;
1289 uint8_t aux_addr_offset;
1290
1291 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
1292
1293 /* size of the state buffer used to store the clear color + extra
1294 * additional space used by the hardware */
1295 uint8_t clear_color_state_size;
1296 uint8_t clear_color_state_offset;
1297 /* size of the clear color itself - used to copy it to/from a BO */
1298 uint8_t clear_value_size;
1299 uint8_t clear_value_offset;
1300 } ss;
1301
1302 uint64_t max_buffer_size;
1303
1304 /**
1305 * Describes the layout of the depth/stencil/hiz commands as emitted by
1306 * isl_emit_depth_stencil_hiz.
1307 */
1308 struct {
1309 uint8_t size;
1310 uint8_t depth_offset;
1311 uint8_t stencil_offset;
1312 uint8_t hiz_offset;
1313 } ds;
1314
1315 /**
1316 * Describes the layout of the coarse pixel control commands as emitted by
1317 * isl_emit_cpb_control.
1318 */
1319 struct {
1320 uint8_t size;
1321 uint8_t offset;
1322 } cpb;
1323
1324 struct {
1325 uint32_t internal;
1326 uint32_t external;
1327 uint32_t uncached;
1328 uint32_t l1_hdc_l3_llc;
1329 uint32_t blitter_src;
1330 uint32_t blitter_dst;
1331 /* Protected is an additional bit on top of the existing entry index. */
1332 uint32_t protected_mask;
1333 } mocs;
1334
1335 /* Options to configure by the driver: */
1336 bool sampler_route_to_lsc;
1337
1338 /**
1339 * Write buffer length in the upper dword of the
1340 * RENDER_SURFACE_STATE::AuxilliarySurfaceBaseAddress field.
1341 *
1342 * This field is unused for buffer surfaces so we can reuse it store the
1343 * buffer length. This is useful when you want to load a vec4 with (main
1344 * address, size).
1345 */
1346 bool buffer_length_in_aux_addr;
1347
1348 uint64_t dummy_aux_address;
1349
1350 void (*surf_fill_state_s)(const struct isl_device *dev, void *state,
1351 const struct isl_surf_fill_state_info *restrict info);
1352
1353 void (*buffer_fill_state_s)(const struct isl_device *dev, void *state,
1354 const struct isl_buffer_fill_state_info *restrict info);
1355
1356 void (*emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
1357 const struct isl_depth_stencil_hiz_emit_info *restrict info);
1358
1359 void (*null_fill_state_s)(const struct isl_device *dev, void *state,
1360 const struct isl_null_fill_state_info *restrict info);
1361
1362 void (*emit_cpb_control_s)(const struct isl_device *dev, void *batch,
1363 const struct isl_cpb_emit_info *restrict info);
1364 };
1365
1366 struct isl_extent2d {
1367 union { uint32_t w, width; };
1368 union { uint32_t h, height; };
1369 };
1370
1371 struct isl_extent3d {
1372 union { uint32_t w, width; };
1373 union { uint32_t h, height; };
1374 union { uint32_t d, depth; };
1375 };
1376
1377 struct isl_extent4d {
1378 union { uint32_t w, width; };
1379 union { uint32_t h, height; };
1380 union { uint32_t d, depth; };
1381 union { uint32_t a, array_len; };
1382 };
1383
1384 /**
1385 * Describes a single channel of an isl_format
1386 */
1387 struct isl_channel_layout {
1388 /** Channel data encoding */
1389 enum isl_base_type type;
1390 /** Bit at which this channel starts */
1391 uint8_t start_bit;
1392 /** Size in bits */
1393 uint8_t bits;
1394 };
1395
1396 /**
1397 * Describes the layout of an isl_format
1398 *
1399 * Each format has 3D block extent (width, height, depth). The block extent of
1400 * compressed formats is that of the format's compression block. For example,
1401 * the block extent of ``ISL_FORMAT_ETC2_RGB8`` is ``(w=4, h=4, d=1)``. The block
1402 * extent of uncompressed pixel formats, such as ``ISL_FORMAT_R8G8B8A8_UNORM``,
1403 * is ``(w=1, h=1, d=1)``.
1404 */
1405 struct isl_format_layout {
1406 /** Format */
1407 enum isl_format format;
1408
1409 /** Bits per block */
1410 uint16_t bpb;
1411 /** Block width, in pixels */
1412 uint8_t bw;
1413 /** Block height, in pixels */
1414 uint8_t bh;
1415 /** Block depth, in pixels */
1416 uint8_t bd;
1417
1418 /***/
1419 union {
1420 /***/
1421 struct {
1422 /** Red channel */
1423 struct isl_channel_layout r;
1424 /** Green channel */
1425 struct isl_channel_layout g;
1426 /** Blue channel */
1427 struct isl_channel_layout b;
1428 /** Alpha channel */
1429 struct isl_channel_layout a;
1430 /** Luminance channel */
1431 struct isl_channel_layout l;
1432 /** Intensity channel */
1433 struct isl_channel_layout i;
1434 /** Palette channel */
1435 struct isl_channel_layout p;
1436 } channels;
1437 struct isl_channel_layout channels_array[7];
1438 };
1439
1440 /** Set if all channels have the same isl_base_type. Otherwise, ISL_VOID. */
1441 enum isl_base_type uniform_channel_type;
1442
1443 enum isl_colorspace colorspace;
1444 enum isl_txc txc;
1445 };
1446
1447 /***/
1448 struct isl_tile_info {
1449 /** Tiling represented by this isl_tile_info */
1450 enum isl_tiling tiling;
1451
1452 /**
1453 * The size (in bits per block) of a single surface element
1454 *
1455 * For surfaces with power-of-two formats, this is the same as
1456 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1457 * The logical_extent_el field is in terms of elements of this size.
1458 *
1459 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1460 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1461 * of the tiling formats can actually hold an integer number of 96-bit
1462 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1463 * 32-bit element size. It is the responsibility of the caller to
1464 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1465 * the width of a surface in tiles, you would do::
1466 *
1467 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1468 * tile_info.logical_extent_el.width);
1469 */
1470 uint32_t format_bpb;
1471
1472 /**
1473 * The logical size of the tile in units of format_bpb size elements
1474 *
1475 * This field determines how a given surface is cut up into tiles. It is
1476 * used to compute the size of a surface in tiles and can be used to
1477 * determine the location of the tile containing any given surface element.
1478 * The exact value of this field depends heavily on the bits-per-block of
1479 * the format being used.
1480 */
1481 struct isl_extent4d logical_extent_el;
1482
1483 /**
1484 * The maximum number of miplevels that will fit in the miptail.
1485 *
1486 * This does not guarantee that the given number of miplevels will fit in
1487 * the miptail as that is also dependent on the size of the miplevels.
1488 */
1489 uint32_t max_miptail_levels;
1490
1491 /**
1492 * The physical size of the tile in bytes and rows of bytes
1493 *
1494 * This field determines how the tiles of a surface are physically laid
1495 * out in memory. The logical and physical tile extent are frequently the
1496 * same but this is not always the case. For instance, a W-tile (which is
1497 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1498 * its physical size is 128B x 32rows, the same as a Y-tile.
1499 *
1500 * See :c:member:`isl_surf.row_pitch_B`
1501 */
1502 struct isl_extent2d phys_extent_B;
1503 };
1504
1505 /**
1506 * Metadata about a DRM format modifier.
1507 */
1508 struct isl_drm_modifier_info {
1509 uint64_t modifier;
1510
1511 /** Text name of the modifier */
1512 const char *name;
1513
1514 /** ISL tiling implied by this modifier */
1515 enum isl_tiling tiling;
1516
1517 /** Compression types supported by this modifier */
1518 bool supports_render_compression;
1519 bool supports_media_compression;
1520
1521 /** Whether or not this modifier supports clear color */
1522 bool supports_clear_color;
1523 };
1524
1525 /**
1526 * @brief Input to surface initialization
1527 *
1528 * :invariant: width >= 1
1529 * :invariant: height >= 1
1530 * :invariant: depth >= 1
1531 * :invariant: levels >= 1
1532 * :invariant: samples >= 1
1533 * :invariant: array_len >= 1
1534 *
1535 * :invariant: if 1D then height == 1 and depth == 1 and samples == 1
1536 * :invariant: if 2D then depth == 1
1537 * :invariant: if 3D then array_len == 1 and samples == 1
1538 */
1539 struct isl_surf_init_info {
1540 enum isl_surf_dim dim;
1541 enum isl_format format;
1542
1543 uint32_t width;
1544 uint32_t height;
1545 uint32_t depth;
1546 uint32_t levels;
1547 uint32_t array_len;
1548 uint32_t samples;
1549
1550 /** Lower bound for :c:member:`isl_surf.alignment`, in bytes. */
1551 uint32_t min_alignment_B;
1552
1553 /** Lower bound for where to start the miptail */
1554 uint32_t min_miptail_start_level;
1555
1556 /**
1557 * Exact value for :c:member:`isl_surf.row_pitch`. Ignored if zero.
1558 * isl_surf_init() will fail if this is misaligned or out of bounds.
1559 */
1560 uint32_t row_pitch_B;
1561
1562 isl_surf_usage_flags_t usage;
1563
1564 /** Flags that alter how ISL selects isl_surf::tiling. */
1565 isl_tiling_flags_t tiling_flags;
1566 };
1567
1568 /***/
1569 struct isl_surf {
1570 /** Dimensionality of the surface */
1571 enum isl_surf_dim dim;
1572
1573 /**
1574 * Spatial layout of the surface in memory
1575 *
1576 * This is dependent on :c:member:`isl_surf.dim` and hardware generation.
1577 */
1578 enum isl_dim_layout dim_layout;
1579
1580 /** Spatial layout of the samples if isl_surf::samples > 1 */
1581 enum isl_msaa_layout msaa_layout;
1582
1583 /** Memory tiling used by the surface */
1584 enum isl_tiling tiling;
1585
1586 /**
1587 * Base image format of the surface
1588 *
1589 * This need not be the same as the format specified in isl_view::format
1590 * when a surface state is constructed. It must, however, have the same
1591 * number of bits per pixel or else memory calculations will go wrong.
1592 */
1593 enum isl_format format;
1594
1595 /**
1596 * Alignment of the upper-left sample of each subimage, in units of surface
1597 * elements.
1598 */
1599 struct isl_extent3d image_alignment_el;
1600
1601 /**
1602 * Logical extent of the surface's base level, in units of pixels. This is
1603 * identical to the extent defined in isl_surf_init_info.
1604 */
1605 struct isl_extent4d logical_level0_px;
1606
1607 /**
1608 * Physical extent of the surface's base level, in units of physical
1609 * surface samples.
1610 *
1611 * Consider isl_dim_layout as an operator that transforms a logical surface
1612 * layout to a physical surface layout. Then
1613 *
1614 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1615 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1616 */
1617 struct isl_extent4d phys_level0_sa;
1618
1619 /** Number of miplevels in the surface */
1620 uint32_t levels;
1621
1622 /**
1623 * Number of samples in the surface
1624 *
1625 * :invariant: samples >= 1
1626 */
1627 uint32_t samples;
1628
1629 /** Total size of the surface, in bytes. */
1630 uint64_t size_B;
1631
1632 /** Required alignment for the surface's base address. */
1633 uint32_t alignment_B;
1634
1635 /**
1636 * The interpretation of this field depends on the value of
1637 * isl_tile_info::physical_extent_B. In particular, the width of the
1638 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1639 * and the distance in bytes between vertically adjacent tiles in the image
1640 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1641 *
1642 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1643 * this cleanly reduces to being the distance, in bytes, between vertically
1644 * adjacent surface elements.
1645 *
1646 * @see isl_tile_info::phys_extent_B;
1647 */
1648 uint32_t row_pitch_B;
1649
1650 /**
1651 * Pitch between physical array slices, in rows of surface elements.
1652 */
1653 uint32_t array_pitch_el_rows;
1654
1655 enum isl_array_pitch_span array_pitch_span;
1656
1657 /**
1658 * Level at which the miptail starts.
1659 *
1660 * This value is inclusive in the sense that the miptail contains this
1661 * level.
1662 */
1663 uint32_t miptail_start_level;
1664
1665 /** Copy of isl_surf_init_info::usage. */
1666 isl_surf_usage_flags_t usage;
1667 };
1668
1669 struct isl_swizzle {
1670 enum isl_channel_select r:4;
1671 enum isl_channel_select g:4;
1672 enum isl_channel_select b:4;
1673 enum isl_channel_select a:4;
1674 };
1675
1676 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1677 .r = ISL_CHANNEL_SELECT_##R, \
1678 .g = ISL_CHANNEL_SELECT_##G, \
1679 .b = ISL_CHANNEL_SELECT_##B, \
1680 .a = ISL_CHANNEL_SELECT_##A, \
1681 })
1682
1683 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1684
1685 struct isl_view {
1686 /**
1687 * Indicates the usage of the particular view
1688 *
1689 * Normally, this is one bit. However, for a cube map texture, it
1690 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1691 */
1692 isl_surf_usage_flags_t usage;
1693
1694 /**
1695 * The format to use in the view
1696 *
1697 * This may differ from the format of the actual isl_surf but must have
1698 * the same block size.
1699 */
1700 enum isl_format format;
1701
1702 uint32_t base_level;
1703 uint32_t levels;
1704
1705 /**
1706 * Base array layer
1707 *
1708 * For cube maps, both base_array_layer and array_len should be
1709 * specified in terms of 2-D layers and must be a multiple of 6.
1710 *
1711 * 3-D textures are effectively treated as 2-D arrays when used as a
1712 * storage image or render target. If ``usage`` contains
1713 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1714 * base_array_layer and array_len are applied. If the surface is only used
1715 * for texturing, they are ignored.
1716 */
1717 uint32_t base_array_layer;
1718
1719 /**
1720 * Array Length
1721 *
1722 * Indicates the number of array elements starting at Base Array Layer.
1723 */
1724 uint32_t array_len;
1725
1726 /**
1727 * Minimum LOD
1728 *
1729 * Similar to sampler minimum LOD, the computed LOD is clamped to be at
1730 * least min_lod_clamp.
1731 */
1732 float min_lod_clamp;
1733
1734 struct isl_swizzle swizzle;
1735 };
1736
1737 union isl_color_value {
1738 float f32[4];
1739 uint32_t u32[4];
1740 int32_t i32[4];
1741 };
1742
1743 struct isl_surf_fill_state_info {
1744 const struct isl_surf *surf;
1745 const struct isl_view *view;
1746
1747 /**
1748 * The address of the surface in GPU memory.
1749 */
1750 uint64_t address;
1751
1752 /**
1753 * The Memory Object Control state for the filled surface state.
1754 *
1755 * The exact format of this value depends on hardware generation.
1756 */
1757 uint32_t mocs;
1758
1759 /**
1760 * The auxiliary surface or NULL if no auxiliary surface is to be used.
1761 */
1762 const struct isl_surf *aux_surf;
1763 enum isl_aux_usage aux_usage;
1764 uint64_t aux_address;
1765
1766 /**
1767 * The format to use for decoding media compression.
1768 *
1769 * Used together with the surface format.
1770 */
1771 enum isl_format mc_format;
1772
1773 /**
1774 * The clear color for this surface
1775 *
1776 * Valid values depend on hardware generation.
1777 */
1778 union isl_color_value clear_color;
1779
1780 /**
1781 * Send only the clear value address
1782 *
1783 * If set, we only pass the clear address to the GPU and it will fetch it
1784 * from wherever it is.
1785 */
1786 bool use_clear_address;
1787 uint64_t clear_address;
1788
1789 /**
1790 * Surface write disables for gfx4-5
1791 */
1792 isl_channel_mask_t write_disables;
1793
1794 /**
1795 * blend enable for gfx4-5
1796 */
1797 bool blend_enable;
1798
1799 /* Intra-tile offset */
1800 uint16_t x_offset_sa, y_offset_sa;
1801
1802 /**
1803 * Robust image access enabled
1804 *
1805 * This is used to turn off a performance workaround.
1806 */
1807 bool robust_image_access;
1808 };
1809
1810 struct isl_buffer_fill_state_info {
1811 /**
1812 * The address of the surface in GPU memory.
1813 */
1814 uint64_t address;
1815
1816 /**
1817 * The size of the buffer
1818 */
1819 uint64_t size_B;
1820
1821 /**
1822 * The Memory Object Control state for the filled surface state.
1823 *
1824 * The exact format of this value depends on hardware generation.
1825 */
1826 uint32_t mocs;
1827
1828 /**
1829 * The format to use in the surface state
1830 *
1831 * This may differ from the format of the actual isl_surf but have the
1832 * same block size.
1833 */
1834 enum isl_format format;
1835
1836 /**
1837 * The swizzle to use in the surface state
1838 */
1839 struct isl_swizzle swizzle;
1840
1841 uint32_t stride_B;
1842
1843 bool is_scratch;
1844 };
1845
1846 struct isl_depth_stencil_hiz_emit_info {
1847 /**
1848 * The depth surface
1849 */
1850 const struct isl_surf *depth_surf;
1851
1852 /**
1853 * The stencil surface
1854 *
1855 * If separate stencil is not available, this must point to the same
1856 * isl_surf as depth_surf.
1857 */
1858 const struct isl_surf *stencil_surf;
1859
1860 /**
1861 * The view into the depth and stencil surfaces.
1862 *
1863 * This view applies to both surfaces simultaneously.
1864 */
1865 const struct isl_view *view;
1866
1867 /**
1868 * The address of the depth surface in GPU memory
1869 */
1870 uint64_t depth_address;
1871
1872 /**
1873 * The address of the stencil surface in GPU memory
1874 *
1875 * If separate stencil is not available, this must have the same value as
1876 * depth_address.
1877 */
1878 uint64_t stencil_address;
1879
1880 /**
1881 * The Memory Object Control state for depth and stencil buffers
1882 *
1883 * Both depth and stencil will get the same MOCS value. The exact format
1884 * of this value depends on hardware generation.
1885 */
1886 uint32_t mocs;
1887
1888 /**
1889 * The HiZ surface or NULL if HiZ is disabled.
1890 */
1891 const struct isl_surf *hiz_surf;
1892 enum isl_aux_usage hiz_usage;
1893 uint64_t hiz_address;
1894
1895 /**
1896 * The depth clear value
1897 */
1898 float depth_clear_value;
1899
1900 /**
1901 * Track stencil aux usage for Gen >= 12
1902 */
1903 enum isl_aux_usage stencil_aux_usage;
1904 };
1905
1906 struct isl_null_fill_state_info {
1907 struct isl_extent3d size;
1908 uint32_t levels;
1909 uint32_t minimum_array_element;
1910 };
1911
1912 struct isl_cpb_emit_info {
1913 /**
1914 * The coarse pixel shading control surface.
1915 */
1916 const struct isl_surf *surf;
1917
1918 /**
1919 * The view into the control surface.
1920 */
1921 const struct isl_view *view;
1922
1923 /**
1924 * The address of the control surface in GPU memory.
1925 */
1926 uint64_t address;
1927
1928 /**
1929 * The Memory Object Control state for the surface.
1930 */
1931 uint32_t mocs;
1932 };
1933
1934 /*
1935 * Image metadata structure as laid out in the shader parameter
1936 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
1937 * able to use them. That's okay because the padding and any unused
1938 * entries [most of them except when we're doing untyped surface
1939 * access] will be removed by the uniform packing pass.
1940 */
1941 #define ISL_IMAGE_PARAM_OFFSET_OFFSET 0
1942 #define ISL_IMAGE_PARAM_SIZE_OFFSET 4
1943 #define ISL_IMAGE_PARAM_STRIDE_OFFSET 8
1944 #define ISL_IMAGE_PARAM_TILING_OFFSET 12
1945 #define ISL_IMAGE_PARAM_SWIZZLING_OFFSET 16
1946 #define ISL_IMAGE_PARAM_SIZE 20
1947
1948 struct isl_image_param {
1949 /** Offset applied to the X and Y surface coordinates. */
1950 uint32_t offset[2];
1951
1952 /** Surface X, Y and Z dimensions. */
1953 uint32_t size[3];
1954
1955 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
1956 * pixels, vertical slice stride in pixels.
1957 */
1958 uint32_t stride[4];
1959
1960 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
1961 uint32_t tiling[3];
1962
1963 /**
1964 * Right shift to apply for bit 6 address swizzling. Two different
1965 * swizzles can be specified and will be applied one after the other. The
1966 * resulting address will be:
1967 *
1968 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
1969 * (addr >> swizzling[1])))
1970 *
1971 * Use \c 0xff if any of the swizzles is not required.
1972 */
1973 uint32_t swizzling[2];
1974 };
1975
1976 extern const struct isl_format_layout isl_format_layouts[];
1977 extern const char isl_format_names[];
1978 extern const uint16_t isl_format_name_offsets[];
1979
1980 void
1981 isl_device_init(struct isl_device *dev,
1982 const struct intel_device_info *info);
1983
1984 isl_sample_count_mask_t ATTRIBUTE_CONST
1985 isl_device_get_sample_counts(const struct isl_device *dev);
1986
1987 /**
1988 * :returns: The offset of the field within CLEAR_COLOR from which the sampler
1989 * fetches the clear color.
1990 */
1991 uint64_t
1992 isl_get_sampler_clear_field_offset(const struct intel_device_info *devinfo,
1993 enum isl_format format);
1994
1995 /**
1996 * :returns: The isl_format_layout for the given isl_format
1997 */
1998 static inline const struct isl_format_layout * ATTRIBUTE_CONST
isl_format_get_layout(enum isl_format fmt)1999 isl_format_get_layout(enum isl_format fmt)
2000 {
2001 assert(fmt != ISL_FORMAT_UNSUPPORTED);
2002 assert(fmt < ISL_NUM_FORMATS);
2003 return &isl_format_layouts[fmt];
2004 }
2005
2006 bool isl_format_is_valid(enum isl_format);
2007
2008 static inline const char * ATTRIBUTE_CONST
isl_format_get_name(enum isl_format fmt)2009 isl_format_get_name(enum isl_format fmt)
2010 {
2011 assert(fmt != ISL_FORMAT_UNSUPPORTED);
2012 assert(fmt < ISL_NUM_FORMATS);
2013 return isl_format_names + isl_format_name_offsets[fmt];
2014 }
2015
2016 static inline const char * ATTRIBUTE_CONST
isl_format_get_short_name(enum isl_format fmt)2017 isl_format_get_short_name(enum isl_format fmt)
2018 {
2019 return isl_format_get_name(fmt) + 11 /* ISL_FORMAT_ */;
2020 }
2021
2022 /***/
2023 enum isl_format isl_format_for_pipe_format(enum pipe_format pf);
2024
2025 /***/
2026 bool isl_format_supports_rendering(const struct intel_device_info *devinfo,
2027 enum isl_format format);
2028 /***/
2029 bool isl_format_supports_alpha_blending(const struct intel_device_info *devinfo,
2030 enum isl_format format);
2031 /***/
2032 bool isl_format_supports_sampling(const struct intel_device_info *devinfo,
2033 enum isl_format format);
2034 /***/
2035 bool isl_format_supports_filtering(const struct intel_device_info *devinfo,
2036 enum isl_format format);
2037 /***/
2038 bool isl_format_supports_vertex_fetch(const struct intel_device_info *devinfo,
2039 enum isl_format format);
2040 /***/
2041 bool isl_format_supports_typed_writes(const struct intel_device_info *devinfo,
2042 enum isl_format format);
2043 bool isl_format_supports_typed_reads(const struct intel_device_info *devinfo,
2044 enum isl_format format);
2045 bool isl_format_supports_ccs_d(const struct intel_device_info *devinfo,
2046 enum isl_format format);
2047 bool isl_format_supports_ccs_e(const struct intel_device_info *devinfo,
2048 enum isl_format format);
2049 /***/
2050 bool isl_format_supports_multisampling(const struct intel_device_info *devinfo,
2051 enum isl_format format);
2052 bool isl_format_supports_typed_atomics(const struct intel_device_info *devinfo,
2053 enum isl_format fmt);
2054
2055 bool isl_formats_are_ccs_e_compatible(const struct intel_device_info *devinfo,
2056 enum isl_format format1,
2057 enum isl_format format2);
2058 uint8_t isl_format_get_aux_map_encoding(enum isl_format format);
2059
2060 bool isl_formats_have_same_bits_per_channel(enum isl_format format1,
2061 enum isl_format format2);
2062
2063 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2064 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2065 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2066 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2067 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2068 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
2069
2070 static inline bool
isl_format_has_normalized_channel(enum isl_format fmt)2071 isl_format_has_normalized_channel(enum isl_format fmt)
2072 {
2073 return isl_format_has_unorm_channel(fmt) ||
2074 isl_format_has_snorm_channel(fmt);
2075 }
2076
2077 static inline bool
isl_format_has_float_channel(enum isl_format fmt)2078 isl_format_has_float_channel(enum isl_format fmt)
2079 {
2080 return isl_format_has_ufloat_channel(fmt) ||
2081 isl_format_has_sfloat_channel(fmt);
2082 }
2083
2084 static inline bool
isl_format_has_int_channel(enum isl_format fmt)2085 isl_format_has_int_channel(enum isl_format fmt)
2086 {
2087 return isl_format_has_uint_channel(fmt) ||
2088 isl_format_has_sint_channel(fmt);
2089 }
2090
2091 bool isl_format_has_color_component(enum isl_format fmt,
2092 int component) ATTRIBUTE_CONST;
2093
2094 unsigned isl_format_get_num_channels(enum isl_format fmt);
2095
2096 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
2097
2098 static inline bool
isl_format_is_compressed(enum isl_format fmt)2099 isl_format_is_compressed(enum isl_format fmt)
2100 {
2101 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2102
2103 return fmtl->txc != ISL_TXC_NONE;
2104 }
2105
2106 static inline bool
isl_format_has_bc_compression(enum isl_format fmt)2107 isl_format_has_bc_compression(enum isl_format fmt)
2108 {
2109 switch (isl_format_get_layout(fmt)->txc) {
2110 case ISL_TXC_DXT1:
2111 case ISL_TXC_DXT3:
2112 case ISL_TXC_DXT5:
2113 return true;
2114 case ISL_TXC_NONE:
2115 case ISL_TXC_FXT1:
2116 case ISL_TXC_RGTC1:
2117 case ISL_TXC_RGTC2:
2118 case ISL_TXC_BPTC:
2119 case ISL_TXC_ETC1:
2120 case ISL_TXC_ETC2:
2121 case ISL_TXC_ASTC:
2122 return false;
2123
2124 case ISL_TXC_HIZ:
2125 case ISL_TXC_MCS:
2126 case ISL_TXC_CCS:
2127 unreachable("Should not be called on an aux surface");
2128 }
2129
2130 unreachable("bad texture compression mode");
2131 return false;
2132 }
2133
2134 static inline bool
isl_format_is_mcs(enum isl_format fmt)2135 isl_format_is_mcs(enum isl_format fmt)
2136 {
2137 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2138
2139 return fmtl->txc == ISL_TXC_MCS;
2140 }
2141
2142 static inline bool
isl_format_is_hiz(enum isl_format fmt)2143 isl_format_is_hiz(enum isl_format fmt)
2144 {
2145 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2146
2147 return fmtl->txc == ISL_TXC_HIZ;
2148 }
2149
2150 static inline bool
isl_format_is_planar(enum isl_format fmt)2151 isl_format_is_planar(enum isl_format fmt)
2152 {
2153 return fmt == ISL_FORMAT_PLANAR_420_8 ||
2154 fmt == ISL_FORMAT_PLANAR_420_10 ||
2155 fmt == ISL_FORMAT_PLANAR_420_12 ||
2156 fmt == ISL_FORMAT_PLANAR_420_16;
2157 }
2158
2159 static inline bool
isl_format_is_yuv(enum isl_format fmt)2160 isl_format_is_yuv(enum isl_format fmt)
2161 {
2162 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2163
2164 return fmtl->colorspace == ISL_COLORSPACE_YUV;
2165 }
2166
2167 static inline bool
isl_format_block_is_1x1x1(enum isl_format fmt)2168 isl_format_block_is_1x1x1(enum isl_format fmt)
2169 {
2170 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2171
2172 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
2173 }
2174
2175 static inline bool
isl_format_is_srgb(enum isl_format fmt)2176 isl_format_is_srgb(enum isl_format fmt)
2177 {
2178 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
2179 }
2180
2181 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
2182
2183 static inline bool
isl_format_is_rgb(enum isl_format fmt)2184 isl_format_is_rgb(enum isl_format fmt)
2185 {
2186 if (isl_format_is_yuv(fmt))
2187 return false;
2188
2189 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2190
2191 return fmtl->channels.r.bits > 0 &&
2192 fmtl->channels.g.bits > 0 &&
2193 fmtl->channels.b.bits > 0 &&
2194 fmtl->channels.a.bits == 0;
2195 }
2196
2197 static inline bool
isl_format_is_rgbx(enum isl_format fmt)2198 isl_format_is_rgbx(enum isl_format fmt)
2199 {
2200 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2201
2202 return fmtl->channels.r.bits > 0 &&
2203 fmtl->channels.g.bits > 0 &&
2204 fmtl->channels.b.bits > 0 &&
2205 fmtl->channels.a.bits > 0 &&
2206 fmtl->channels.a.type == ISL_VOID;
2207 }
2208
2209 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
2210 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
2211 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
2212
2213 bool isl_format_support_sampler_route_to_lsc(enum isl_format fmt);
2214
2215 union isl_color_value
2216 isl_color_value_swizzle(union isl_color_value src,
2217 struct isl_swizzle swizzle,
2218 bool is_float);
2219
2220 union isl_color_value
2221 isl_color_value_swizzle_inv(union isl_color_value src,
2222 struct isl_swizzle swizzle);
2223
2224 void isl_color_value_pack(const union isl_color_value *value,
2225 enum isl_format format,
2226 uint32_t *data_out);
2227 void isl_color_value_unpack(union isl_color_value *value,
2228 enum isl_format format,
2229 const uint32_t *data_in);
2230
2231 bool isl_is_storage_image_format(const struct intel_device_info *devinfo,
2232 enum isl_format fmt);
2233
2234 enum isl_format
2235 isl_lower_storage_image_format(const struct intel_device_info *devinfo,
2236 enum isl_format fmt);
2237
2238 /* Returns true if this hardware supports typed load/store on a format with
2239 * the same size as the given format.
2240 */
2241 bool
2242 isl_has_matching_typed_storage_image_format(const struct intel_device_info *devinfo,
2243 enum isl_format fmt);
2244
2245 void
2246 isl_tiling_get_info(enum isl_tiling tiling,
2247 enum isl_surf_dim dim,
2248 enum isl_msaa_layout msaa_layout,
2249 uint32_t format_bpb,
2250 uint32_t samples,
2251 struct isl_tile_info *tile_info);
2252
2253 static inline enum isl_tiling
isl_tiling_flag_to_enum(isl_tiling_flags_t flag)2254 isl_tiling_flag_to_enum(isl_tiling_flags_t flag)
2255 {
2256 assert(__builtin_popcount(flag) == 1);
2257 return (enum isl_tiling) (__builtin_ffs(flag) - 1);
2258 }
2259
2260 static inline bool
isl_tiling_is_any_y(enum isl_tiling tiling)2261 isl_tiling_is_any_y(enum isl_tiling tiling)
2262 {
2263 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
2264 }
2265
2266 static inline bool
isl_tiling_is_std_y(enum isl_tiling tiling)2267 isl_tiling_is_std_y(enum isl_tiling tiling)
2268 {
2269 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
2270 }
2271
2272 static inline bool
isl_tiling_is_64(enum isl_tiling tiling)2273 isl_tiling_is_64(enum isl_tiling tiling)
2274 {
2275 return (1u << tiling) & ISL_TILING_STD_64_MASK;
2276 }
2277
2278 uint32_t
2279 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
2280
2281 enum isl_tiling
2282 isl_tiling_from_i915_tiling(uint32_t tiling);
2283
2284
2285 /**
2286 * Return an isl_aux_state to describe an auxiliary surface that is either
2287 * uninitialized or zeroed.
2288 */
2289 enum isl_aux_state
2290 isl_aux_get_initial_state(const struct intel_device_info *devinfo,
2291 enum isl_aux_usage usage,
2292 bool zeroed);
2293
2294 /**
2295 * Return an isl_aux_op needed to enable an access to occur in an
2296 * isl_aux_state suitable for the isl_aux_usage.
2297 *
2298 * .. note::
2299 * If the access will invalidate the main surface, this function should not be
2300 * called and the isl_aux_op of NONE should be used instead. Otherwise, an
2301 * extra (but still lossless) ambiguate may occur.
2302 *
2303 * :invariant: initial_state is possible with an isl_aux_usage compatible with
2304 * the given usage. Two usages are compatible if it's possible to
2305 * switch between them (e.g. CCS_E <-> CCS_D).
2306 * :invariant: fast_clear is false if the aux doesn't support fast clears.
2307 */
2308 enum isl_aux_op
2309 isl_aux_prepare_access(enum isl_aux_state initial_state,
2310 enum isl_aux_usage usage,
2311 bool fast_clear_supported);
2312
2313 /**
2314 * Return the isl_aux_state entered after performing an isl_aux_op.
2315 *
2316 * :invariant: initial_state is possible with the given usage.
2317 * :invariant: op is possible with the given usage.
2318 * :invariant: op must not cause HW to read from an invalid aux.
2319 */
2320 enum isl_aux_state
2321 isl_aux_state_transition_aux_op(enum isl_aux_state initial_state,
2322 enum isl_aux_usage usage,
2323 enum isl_aux_op op);
2324
2325 /**
2326 * Return the isl_aux_state entered after performing a write.
2327 *
2328 * .. note::
2329 *
2330 * full_surface should be true if the write covers the entire slice. Setting
2331 * it to false in this case will still result in a correct (but imprecise)
2332 * aux state.
2333 *
2334 * :invariant: if usage is not ISL_AUX_USAGE_NONE, then initial_state is
2335 * possible with the given usage.
2336 * :invariant: usage can be ISL_AUX_USAGE_NONE iff:
2337 * * the main surface is valid, or
2338 * * the main surface is being invalidated/replaced.
2339 */
2340 enum isl_aux_state
2341 isl_aux_state_transition_write(enum isl_aux_state initial_state,
2342 enum isl_aux_usage usage,
2343 bool full_surface);
2344
2345 /***/
2346 bool
2347 isl_aux_usage_has_fast_clears(enum isl_aux_usage usage);
2348
2349 /***/
2350 bool
2351 isl_aux_usage_has_compression(enum isl_aux_usage usage);
2352
2353 /***/
2354 static inline bool
isl_aux_usage_has_hiz(enum isl_aux_usage usage)2355 isl_aux_usage_has_hiz(enum isl_aux_usage usage)
2356 {
2357 return usage == ISL_AUX_USAGE_HIZ ||
2358 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
2359 usage == ISL_AUX_USAGE_HIZ_CCS;
2360 }
2361
2362 /***/
2363 static inline bool
isl_aux_usage_has_mcs(enum isl_aux_usage usage)2364 isl_aux_usage_has_mcs(enum isl_aux_usage usage)
2365 {
2366 return usage == ISL_AUX_USAGE_MCS ||
2367 usage == ISL_AUX_USAGE_MCS_CCS;
2368 }
2369
2370 /***/
2371 static inline bool
isl_aux_usage_has_ccs(enum isl_aux_usage usage)2372 isl_aux_usage_has_ccs(enum isl_aux_usage usage)
2373 {
2374 return usage == ISL_AUX_USAGE_CCS_D ||
2375 usage == ISL_AUX_USAGE_CCS_E ||
2376 usage == ISL_AUX_USAGE_FCV_CCS_E ||
2377 usage == ISL_AUX_USAGE_MC ||
2378 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
2379 usage == ISL_AUX_USAGE_HIZ_CCS ||
2380 usage == ISL_AUX_USAGE_MCS_CCS ||
2381 usage == ISL_AUX_USAGE_STC_CCS;
2382 }
2383
2384 static inline bool
isl_aux_usage_has_ccs_e(enum isl_aux_usage usage)2385 isl_aux_usage_has_ccs_e(enum isl_aux_usage usage)
2386 {
2387 return usage == ISL_AUX_USAGE_CCS_E ||
2388 usage == ISL_AUX_USAGE_FCV_CCS_E;
2389 }
2390
2391 /***/
2392 static inline bool
isl_aux_state_has_valid_primary(enum isl_aux_state state)2393 isl_aux_state_has_valid_primary(enum isl_aux_state state)
2394 {
2395 return state == ISL_AUX_STATE_RESOLVED ||
2396 state == ISL_AUX_STATE_PASS_THROUGH ||
2397 state == ISL_AUX_STATE_AUX_INVALID;
2398 }
2399
2400 /***/
2401 static inline bool
isl_aux_state_has_valid_aux(enum isl_aux_state state)2402 isl_aux_state_has_valid_aux(enum isl_aux_state state)
2403 {
2404 return state != ISL_AUX_STATE_AUX_INVALID;
2405 }
2406
2407 extern const struct isl_drm_modifier_info isl_drm_modifier_info_list[];
2408
2409 #define isl_drm_modifier_info_for_each(__info) \
2410 for (const struct isl_drm_modifier_info *__info = isl_drm_modifier_info_list; \
2411 __info->modifier != DRM_FORMAT_MOD_INVALID; \
2412 ++__info)
2413
2414 /* According to drm_fourcc.h, the clear color pitch is ignored on MTL but it
2415 * should be 64B aligned for TGL and DG2. There's no need to special-case MTL.
2416 */
2417 #define ISL_DRM_CC_PLANE_PITCH_B 64
2418
2419 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
2420 isl_drm_modifier_get_info(uint64_t modifier);
2421
2422 static inline bool
isl_drm_modifier_has_aux(uint64_t modifier)2423 isl_drm_modifier_has_aux(uint64_t modifier)
2424 {
2425 if (modifier == DRM_FORMAT_MOD_INVALID)
2426 return false;
2427
2428 return isl_drm_modifier_get_info(modifier)->supports_render_compression ||
2429 isl_drm_modifier_get_info(modifier)->supports_media_compression;
2430 }
2431
2432 static inline bool
isl_drm_modifier_needs_display_layout(uint64_t modifier)2433 isl_drm_modifier_needs_display_layout(uint64_t modifier)
2434 {
2435 /* Modifiers supporting compression are specified to be compatible with the
2436 * display engine, even if they won't actually be used for scanout.
2437 */
2438 return isl_drm_modifier_has_aux(modifier);
2439 }
2440
2441 static inline bool
isl_drm_modifier_plane_is_clear_color(uint64_t modifier,uint32_t plane)2442 isl_drm_modifier_plane_is_clear_color(uint64_t modifier, uint32_t plane)
2443 {
2444 if (modifier == DRM_FORMAT_MOD_INVALID)
2445 return false;
2446
2447 ASSERTED const struct isl_drm_modifier_info *mod_info =
2448 isl_drm_modifier_get_info(modifier);
2449 assert(mod_info);
2450
2451 switch (modifier) {
2452 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
2453 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
2454 assert(mod_info->supports_clear_color);
2455 return plane == 2;
2456 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
2457 assert(mod_info->supports_clear_color);
2458 return plane == 1;
2459 default:
2460 assert(!mod_info->supports_clear_color);
2461 return false;
2462 }
2463 }
2464
2465 /** Returns the default isl_aux_state for the given modifier.
2466 *
2467 * If we have a modifier which supports compression, then the auxiliary data
2468 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
2469 * can be in any of the following:
2470 *
2471 * - ISL_AUX_STATE_CLEAR
2472 * - ISL_AUX_STATE_PARTIAL_CLEAR
2473 * - ISL_AUX_STATE_COMPRESSED_CLEAR
2474 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
2475 * - ISL_AUX_STATE_RESOLVED
2476 * - ISL_AUX_STATE_PASS_THROUGH
2477 *
2478 * If the modifier does not support fast-clears, then we are guaranteed
2479 * that the surface is at least partially resolved and the first three not
2480 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
2481 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
2482 * because they are the least common denominator of the set of possible aux
2483 * states and will yield a valid interpretation of the aux data.
2484 *
2485 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
2486 */
2487 static inline enum isl_aux_state
isl_drm_modifier_get_default_aux_state(uint64_t modifier)2488 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
2489 {
2490 const struct isl_drm_modifier_info *mod_info =
2491 isl_drm_modifier_get_info(modifier);
2492
2493 if (!mod_info || !isl_drm_modifier_has_aux(modifier))
2494 return ISL_AUX_STATE_AUX_INVALID;
2495
2496 assert(mod_info->supports_render_compression !=
2497 mod_info->supports_media_compression);
2498 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
2499 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
2500 }
2501
2502 /**
2503 * Return the modifier's score, which indicates the driver's preference for the
2504 * modifier relative to others. A higher score is better. Zero means
2505 * unsupported.
2506 *
2507 * Intended to assist selection of a modifier from an externally provided list,
2508 * such as VkImageDrmFormatModifierListCreateInfoEXT.
2509 */
2510 uint32_t
2511 isl_drm_modifier_get_score(const struct intel_device_info *devinfo,
2512 uint64_t modifier);
2513
2514 /* Return the number of planes used by an image with the given parameters. */
2515 uint32_t
2516 isl_drm_modifier_get_plane_count(const struct intel_device_info *devinfo,
2517 uint64_t modifier,
2518 uint32_t fmt_planes);
2519
2520 struct isl_extent2d ATTRIBUTE_CONST
2521 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
2522
2523 static inline bool
isl_surf_usage_is_display(isl_surf_usage_flags_t usage)2524 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
2525 {
2526 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
2527 }
2528
2529 static inline bool
isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)2530 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
2531 {
2532 return usage & ISL_SURF_USAGE_DEPTH_BIT;
2533 }
2534
2535 static inline bool
isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)2536 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
2537 {
2538 return usage & ISL_SURF_USAGE_STENCIL_BIT;
2539 }
2540
2541 static inline bool
isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)2542 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
2543 {
2544 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2545 (usage & ISL_SURF_USAGE_STENCIL_BIT);
2546 }
2547
2548 static inline bool
isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)2549 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
2550 {
2551 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
2552 }
2553
2554 static inline bool
isl_surf_usage_is_cpb(isl_surf_usage_flags_t usage)2555 isl_surf_usage_is_cpb(isl_surf_usage_flags_t usage)
2556 {
2557 return usage & ISL_SURF_USAGE_CPB_BIT;
2558 }
2559
2560 static inline bool
isl_surf_info_is_z16(const struct isl_surf_init_info * info)2561 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
2562 {
2563 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2564 (info->format == ISL_FORMAT_R16_UNORM);
2565 }
2566
2567 static inline bool
isl_surf_info_is_z32_float(const struct isl_surf_init_info * info)2568 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
2569 {
2570 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2571 (info->format == ISL_FORMAT_R32_FLOAT);
2572 }
2573
2574 static inline struct isl_extent2d
isl_extent2d(uint32_t width,uint32_t height)2575 isl_extent2d(uint32_t width, uint32_t height)
2576 {
2577 struct isl_extent2d e = { { 0 } };
2578
2579 e.width = width;
2580 e.height = height;
2581
2582 return e;
2583 }
2584
2585 static inline struct isl_extent3d
isl_extent3d(uint32_t width,uint32_t height,uint32_t depth)2586 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
2587 {
2588 struct isl_extent3d e = { { 0 } };
2589
2590 e.width = width;
2591 e.height = height;
2592 e.depth = depth;
2593
2594 return e;
2595 }
2596
2597 static inline struct isl_extent4d
isl_extent4d(uint32_t width,uint32_t height,uint32_t depth,uint32_t array_len)2598 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
2599 uint32_t array_len)
2600 {
2601 struct isl_extent4d e = { { 0 } };
2602
2603 e.width = width;
2604 e.height = height;
2605 e.depth = depth;
2606 e.array_len = array_len;
2607
2608 return e;
2609 }
2610
2611 bool isl_color_value_is_zero(union isl_color_value value,
2612 enum isl_format format);
2613
2614 bool isl_color_value_is_zero_one(union isl_color_value value,
2615 enum isl_format format);
2616
2617 static inline bool
isl_swizzle_is_identity(struct isl_swizzle swizzle)2618 isl_swizzle_is_identity(struct isl_swizzle swizzle)
2619 {
2620 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
2621 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
2622 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
2623 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
2624 }
2625
2626 static inline bool
isl_swizzle_is_identity_for_format(enum isl_format format,struct isl_swizzle swizzle)2627 isl_swizzle_is_identity_for_format(enum isl_format format,
2628 struct isl_swizzle swizzle)
2629 {
2630 const struct isl_format_layout *layout = isl_format_get_layout(format);
2631
2632 #define channel_id_or_zero(name, ID) \
2633 (swizzle.name == ISL_CHANNEL_SELECT_##ID || \
2634 layout->channels.name.bits == 0)
2635 return channel_id_or_zero(r, RED) &&
2636 channel_id_or_zero(g, GREEN) &&
2637 channel_id_or_zero(b, BLUE) &&
2638 channel_id_or_zero(a, ALPHA);
2639 #undef channel_id_or_zero
2640 }
2641
2642 bool
2643 isl_swizzle_supports_rendering(const struct intel_device_info *devinfo,
2644 struct isl_swizzle swizzle);
2645
2646 struct isl_swizzle
2647 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
2648 struct isl_swizzle
2649 isl_swizzle_invert(struct isl_swizzle swizzle);
2650
2651 uint32_t isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
2652 bool external);
2653
2654 #define isl_surf_init(dev, surf, ...) \
2655 isl_surf_init_s((dev), (surf), \
2656 &(struct isl_surf_init_info) { __VA_ARGS__ });
2657
2658 bool
2659 isl_surf_init_s(const struct isl_device *dev,
2660 struct isl_surf *surf,
2661 const struct isl_surf_init_info *restrict info);
2662
2663 void
2664 isl_surf_get_tile_info(const struct isl_surf *surf,
2665 struct isl_tile_info *tile_info);
2666
2667 /**
2668 * :param surf: |in| The main surface
2669 * :param hiz_or_mcs_surf: |in| HiZ or MCS surface associated with the main
2670 * surface
2671 * :returns: true if the given surface supports CCS.
2672 */
2673 bool
2674 isl_surf_supports_ccs(const struct isl_device *dev,
2675 const struct isl_surf *surf,
2676 const struct isl_surf *hiz_or_mcs_surf);
2677
2678 /** Constructs a HiZ surface for the given main surface.
2679 *
2680 * :param surf: |in| The main surface
2681 * :param hiz_surf: |out| The HiZ surface to populate on success
2682 * :returns: false if the main surface cannot support HiZ.
2683 */
2684 bool
2685 isl_surf_get_hiz_surf(const struct isl_device *dev,
2686 const struct isl_surf *surf,
2687 struct isl_surf *hiz_surf);
2688
2689 /** Constructs a MCS for the given main surface.
2690 *
2691 * :param surf: |in| The main surface
2692 * :param mcs_surf: |out| The MCS to populate on success
2693 * :returns: false if the main surface cannot support MCS.
2694 */
2695 bool
2696 isl_surf_get_mcs_surf(const struct isl_device *dev,
2697 const struct isl_surf *surf,
2698 struct isl_surf *mcs_surf);
2699
2700 /** Constructs a CCS for the given main surface.
2701 *
2702 * .. note::
2703 *
2704 * Starting with Tigerlake, the CCS is no longer really a surface. It's not
2705 * laid out as an independent surface and isn't referenced by
2706 * RENDER_SURFACE_STATE::"Auxiliary Surface Base Address" like other
2707 * auxiliary compression surfaces. It's a blob of memory that's a 1:256
2708 * scale-down from the main surfaced that's attached side-band via a second
2709 * set of page tables.
2710 *
2711 * :param surf: |in| The main surface
2712 * :param ccs_surf: |out| The CCS to populate on success
2713 * :param row_pitch_B: The row pitch for the CCS in bytes or 0 if
2714 * ISL should calculate the row pitch.
2715 * :returns: false if the main surface cannot support CCS.
2716 */
2717 bool
2718 isl_surf_get_ccs_surf(const struct isl_device *dev,
2719 const struct isl_surf *surf,
2720 struct isl_surf *ccs_surf,
2721 uint32_t row_pitch_B);
2722
2723 /* The value is from Bspec 47709, MCS/CCS Buffers for Render Target(s):
2724 *
2725 * "CCS is a linear buffer created for storing meta-data (AUX data) for
2726 * lossless compression. This buffer related information is mentioned in
2727 * Render Surface State. CCS buffer's size is based on the padded main
2728 * surface (after following Halign and Valign requirements mentioned in the
2729 * Render Surface State). CCS_Buffer_Size = Padded_Main_Surface_Size/256"
2730 */
2731 #define ISL_MAIN_TO_CCS_SIZE_RATIO_XE 256
2732
2733 #define isl_surf_fill_state(dev, state, ...) \
2734 (dev)->surf_fill_state_s(dev, state, \
2735 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
2736
2737 #define isl_surf_fill_state_s(dev, state, info) \
2738 (dev)->surf_fill_state_s(dev, state, info)
2739
2740 #define isl_buffer_fill_state(dev, state, ...) \
2741 (dev)->buffer_fill_state_s(dev, state, \
2742 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
2743
2744 #define isl_buffer_fill_state_s(dev, state, info) \
2745 (dev)->buffer_fill_state_s(dev, state, info);
2746
2747 #define isl_null_fill_state(dev, state, ...) \
2748 (dev)->null_fill_state_s(dev, state, \
2749 &(struct isl_null_fill_state_info) { __VA_ARGS__ });
2750
2751 #define isl_null_fill_state_s(dev, state, info) \
2752 (dev)->null_fill_state_s(dev, state, info);
2753
2754 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
2755 (dev)->emit_depth_stencil_hiz_s(dev, batch, \
2756 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
2757
2758 #define isl_emit_depth_stencil_hiz_s(dev, batch, info) \
2759 (dev)->emit_depth_stencil_hiz_s(dev, batch, info)
2760
2761 #define isl_emit_cpb_control_s(dev, batch, info) \
2762 (dev)->emit_cpb_control_s(dev, batch, info)
2763
2764 void
2765 isl_surf_fill_image_param(const struct isl_device *dev,
2766 struct isl_image_param *param,
2767 const struct isl_surf *surf,
2768 const struct isl_view *view);
2769
2770 void
2771 isl_buffer_fill_image_param(const struct isl_device *dev,
2772 struct isl_image_param *param,
2773 enum isl_format format,
2774 uint64_t size);
2775
2776 /**
2777 * Alignment of the upper-left sample of each subimage, in units of surface
2778 * elements.
2779 */
2780 static inline struct isl_extent3d
isl_surf_get_image_alignment_el(const struct isl_surf * surf)2781 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
2782 {
2783 return surf->image_alignment_el;
2784 }
2785
2786 /**
2787 * Alignment of the upper-left sample of each subimage, in units of surface
2788 * samples.
2789 */
2790 static inline struct isl_extent3d
isl_surf_get_image_alignment_sa(const struct isl_surf * surf)2791 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
2792 {
2793 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2794
2795 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
2796 fmtl->bh * surf->image_alignment_el.h,
2797 fmtl->bd * surf->image_alignment_el.d);
2798 }
2799
2800 /**
2801 * Logical extent of level 0 in units of surface elements.
2802 */
2803 static inline struct isl_extent4d
isl_surf_get_logical_level0_el(const struct isl_surf * surf)2804 isl_surf_get_logical_level0_el(const struct isl_surf *surf)
2805 {
2806 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2807
2808 return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
2809 DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
2810 DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
2811 surf->logical_level0_px.a);
2812 }
2813
2814 /**
2815 * Physical extent of level 0 in units of surface elements.
2816 */
2817 static inline struct isl_extent4d
isl_surf_get_phys_level0_el(const struct isl_surf * surf)2818 isl_surf_get_phys_level0_el(const struct isl_surf *surf)
2819 {
2820 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2821
2822 return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
2823 DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
2824 DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
2825 surf->phys_level0_sa.a);
2826 }
2827
2828 /**
2829 * Pitch between vertically adjacent surface elements, in bytes.
2830 */
2831 static inline uint32_t
isl_surf_get_row_pitch_B(const struct isl_surf * surf)2832 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
2833 {
2834 return surf->row_pitch_B;
2835 }
2836
2837 /**
2838 * Pitch between vertically adjacent surface elements, in units of surface elements.
2839 */
2840 static inline uint32_t
isl_surf_get_row_pitch_el(const struct isl_surf * surf)2841 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
2842 {
2843 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2844
2845 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
2846 return surf->row_pitch_B / (fmtl->bpb / 8);
2847 }
2848
2849 /**
2850 * Pitch between physical array slices, in rows of surface elements.
2851 */
2852 static inline uint32_t
isl_surf_get_array_pitch_el_rows(const struct isl_surf * surf)2853 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
2854 {
2855 return surf->array_pitch_el_rows;
2856 }
2857
2858 /**
2859 * Pitch between physical array slices, in units of surface elements.
2860 */
2861 static inline uint32_t
isl_surf_get_array_pitch_el(const struct isl_surf * surf)2862 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
2863 {
2864 return isl_surf_get_array_pitch_el_rows(surf) *
2865 isl_surf_get_row_pitch_el(surf);
2866 }
2867
2868 /**
2869 * Pitch between physical array slices, in rows of surface samples.
2870 */
2871 static inline uint32_t
isl_surf_get_array_pitch_sa_rows(const struct isl_surf * surf)2872 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
2873 {
2874 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2875 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
2876 }
2877
2878 /**
2879 * Pitch between physical array slices, in bytes.
2880 */
2881 static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf * surf)2882 isl_surf_get_array_pitch(const struct isl_surf *surf)
2883 {
2884 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
2885 }
2886
2887 /**
2888 * Calculate the offset, in units of surface samples, to a subimage in the
2889 * surface.
2890 *
2891 * :invariant: level < surface levels
2892 * :invariant: logical_array_layer < logical array length of surface
2893 * :invariant: logical_z_offset_px < logical depth of surface at level
2894 */
2895 void
2896 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2897 uint32_t level,
2898 uint32_t logical_array_layer,
2899 uint32_t logical_z_offset_px,
2900 uint32_t *x_offset_sa,
2901 uint32_t *y_offset_sa,
2902 uint32_t *z_offset_sa,
2903 uint32_t *array_offset);
2904
2905 /**
2906 * Calculate the offset, in units of surface elements, to a subimage in the
2907 * surface.
2908 *
2909 * :invariant: level < surface levels
2910 * :invariant: logical_array_layer < logical array length of surface
2911 * :invariant: logical_z_offset_px < logical depth of surface at level
2912 */
2913 void
2914 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2915 uint32_t level,
2916 uint32_t logical_array_layer,
2917 uint32_t logical_z_offset_px,
2918 uint32_t *x_offset_el,
2919 uint32_t *y_offset_el,
2920 uint32_t *z_offset_el,
2921 uint32_t *array_offset);
2922
2923 /**
2924 * Calculate the offset, in bytes and intratile surface samples, to a
2925 * subimage in the surface.
2926 *
2927 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2928 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2929 * offsets to samples.
2930 *
2931 * :invariant: level < surface levels
2932 * :invariant: logical_array_layer < logical array length of surface
2933 * :invariant: logical_z_offset_px < logical depth of surface at level
2934 */
2935 void
2936 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2937 uint32_t level,
2938 uint32_t logical_array_layer,
2939 uint32_t logical_z_offset_px,
2940 uint64_t *offset_B,
2941 uint32_t *x_offset_sa,
2942 uint32_t *y_offset_sa);
2943
2944 /**
2945 * Calculate the offset, in bytes and intratile surface elements, to a
2946 * subimage in the surface.
2947 *
2948 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2949 * result to isl_tiling_get_intratile_offset_el.
2950 *
2951 * :invariant: level < surface levels
2952 * :invariant: logical_array_layer < logical array length of surface
2953 * :invariant: logical_z_offset_px < logical depth of surface at level
2954 */
2955 void
2956 isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
2957 uint32_t level,
2958 uint32_t logical_array_layer,
2959 uint32_t logical_z_offset_px,
2960 uint64_t *offset_B,
2961 uint32_t *x_offset_el,
2962 uint32_t *y_offset_el);
2963
2964 /**
2965 * Calculate the range in bytes occupied by a subimage, to the nearest tile.
2966 *
2967 * The range returned will be the smallest memory range in which the give
2968 * subimage fits, rounded to even tiles. Intel images do not usually have a
2969 * direct subimage -> range mapping so the range returned may contain data
2970 * from other sub-images. The returned range is a half-open interval where
2971 * all of the addresses within the subimage are < end_tile_B.
2972 *
2973 * :invariant: level < surface levels
2974 * :invariant: logical_array_layer < logical array length of surface
2975 * :invariant: logical_z_offset_px < logical depth of surface at level
2976 */
2977 void
2978 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
2979 uint32_t level,
2980 uint32_t logical_array_layer,
2981 uint32_t logical_z_offset_px,
2982 uint64_t *start_tile_B,
2983 uint64_t *end_tile_B);
2984
2985 /**
2986 * Create an isl_surf that represents a particular subimage in the surface.
2987 *
2988 * The newly created surface will have a single miplevel and array slice. The
2989 * surface lives at the returned byte and intratile offsets, in samples.
2990 *
2991 * It is safe to call this function with surf == image_surf.
2992 *
2993 * :invariant: level < surface levels
2994 * :invariant: logical_array_layer < logical array length of surface
2995 * :invariant: logical_z_offset_px < logical depth of surface at level
2996 */
2997 void
2998 isl_surf_get_image_surf(const struct isl_device *dev,
2999 const struct isl_surf *surf,
3000 uint32_t level,
3001 uint32_t logical_array_layer,
3002 uint32_t logical_z_offset_px,
3003 struct isl_surf *image_surf,
3004 uint64_t *offset_B,
3005 uint32_t *x_offset_sa,
3006 uint32_t *y_offset_sa);
3007
3008 /**
3009 * Create an isl_surf that is an uncompressed view of a compressed isl_surf
3010 *
3011 * The incoming surface must have a compressed format. The incoming view must
3012 * be a valid view for the given surface with the exception that it's format
3013 * is an umcompressed format with the same bpb as the surface format. The
3014 * incoming view must have isl_view::levels == 1.
3015 *
3016 * When the function returns, the resulting combination of uncompressed_surf
3017 * and uncompressed_view will be a valid view giving an uncompressed view of
3018 * the incoming surface. Depending on tiling, uncompressed_surf may have a
3019 * different isl_surf::dim from surf and uncompressed_view may or may not have
3020 * a zero base_array_layer. For legacy tiling (not Yf or Ys), an intratile
3021 * offset is returned in x_offset_sa and y_offset_sa. For standard Y tilings
3022 * (Yf and Ys), x_offset_sa and y_offset_sa will be set to zero.
3023 *
3024 * It is safe to call this function with surf == uncompressed_surf and
3025 * view == uncompressed_view.
3026 */
3027 bool MUST_CHECK
3028 isl_surf_get_uncompressed_surf(const struct isl_device *dev,
3029 const struct isl_surf *surf,
3030 const struct isl_view *view,
3031 struct isl_surf *uncompressed_surf,
3032 struct isl_view *uncompressed_view,
3033 uint64_t *offset_B,
3034 uint32_t *x_offset_el,
3035 uint32_t *y_offset_el);
3036
3037 /**
3038 * Calculate the intratile offsets to a surface coordinate, in elements.
3039 *
3040 * This function takes a coordinate in global tile space and returns the byte
3041 * offset to the specific tile as well as the offset within that tile to the
3042 * given coordinate in tile space. The returned x/y/z/array offsets are
3043 * guaranteed to lie within the tile.
3044 *
3045 * :param tiling: |in| The tiling of the surface
3046 * :param bpb: |in| The size of the surface format in bits per
3047 * block
3048 * :param array_pitch_el_rows: |in| The array pitch of the surface for flat 2D
3049 * tilings such as ISL_TILING_Y0
3050 * :param total_x_offset_el: |in| The X offset in tile space, in elements
3051 * :param total_y_offset_el: |in| The Y offset in tile space, in elements
3052 * :param total_z_offset_el: |in| The Z offset in tile space, in elements
3053 * :param total_array_offset: |in| The array offset in tile space
3054 * :param tile_offset_B: |out| The returned byte offset to the tile
3055 * :param x_offset_el: |out| The X offset within the tile, in elements
3056 * :param y_offset_el: |out| The Y offset within the tile, in elements
3057 * :param z_offset_el: |out| The Z offset within the tile, in elements
3058 * :param array_offset: |out| The array offset within the tile
3059 */
3060 void
3061 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
3062 enum isl_surf_dim dim,
3063 enum isl_msaa_layout msaa_layout,
3064 uint32_t bpb,
3065 uint32_t samples,
3066 uint32_t row_pitch_B,
3067 uint32_t array_pitch_el_rows,
3068 uint32_t total_x_offset_el,
3069 uint32_t total_y_offset_el,
3070 uint32_t total_z_offset_el,
3071 uint32_t total_array_offset,
3072 uint64_t *tile_offset_B,
3073 uint32_t *x_offset_el,
3074 uint32_t *y_offset_el,
3075 uint32_t *z_offset_el,
3076 uint32_t *array_offset);
3077
3078 /**
3079 * Calculate the intratile offsets to a surface coordinate, in samples.
3080 *
3081 * This function takes a coordinate in global tile space and returns the byte
3082 * offset to the specific tile as well as the offset within that tile to the
3083 * given coordinate in tile space. The returned x/y/z/array offsets are
3084 * guaranteed to lie within the tile.
3085 *
3086 * :param tiling: |in| The tiling of the surface
3087 * :param bpb: |in| The size of the surface format in bits per
3088 * block
3089 * :param array_pitch_el_rows: |in| The array pitch of the surface for flat 2D
3090 * tilings such as ISL_TILING_Y0
3091 * :param total_x_offset_sa: |in| The X offset in tile space, in samples
3092 * :param total_y_offset_sa: |in| The Y offset in tile space, in samples
3093 * :param total_z_offset_sa: |in| The Z offset in tile space, in samples
3094 * :param total_array_offset: |in| The array offset in tile space
3095 * :param tile_offset_B: |out| The returned byte offset to the tile
3096 * :param x_offset_sa: |out| The X offset within the tile, in samples
3097 * :param y_offset_sa: |out| The Y offset within the tile, in samples
3098 * :param z_offset_sa: |out| The Z offset within the tile, in samples
3099 * :param array_offset: |out| The array offset within the tile
3100 */
3101 static inline void
isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,enum isl_surf_dim dim,enum isl_msaa_layout msaa_layout,enum isl_format format,uint32_t samples,uint32_t row_pitch_B,uint32_t array_pitch_el_rows,uint32_t total_x_offset_sa,uint32_t total_y_offset_sa,uint32_t total_z_offset_sa,uint32_t total_array_offset,uint64_t * tile_offset_B,uint32_t * x_offset_sa,uint32_t * y_offset_sa,uint32_t * z_offset_sa,uint32_t * array_offset)3102 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
3103 enum isl_surf_dim dim,
3104 enum isl_msaa_layout msaa_layout,
3105 enum isl_format format,
3106 uint32_t samples,
3107 uint32_t row_pitch_B,
3108 uint32_t array_pitch_el_rows,
3109 uint32_t total_x_offset_sa,
3110 uint32_t total_y_offset_sa,
3111 uint32_t total_z_offset_sa,
3112 uint32_t total_array_offset,
3113 uint64_t *tile_offset_B,
3114 uint32_t *x_offset_sa,
3115 uint32_t *y_offset_sa,
3116 uint32_t *z_offset_sa,
3117 uint32_t *array_offset)
3118 {
3119 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
3120
3121 /* For computing the intratile offsets, we actually want a strange unit
3122 * which is samples for multisampled surfaces but elements for compressed
3123 * surfaces.
3124 */
3125 assert(total_x_offset_sa % fmtl->bw == 0);
3126 assert(total_y_offset_sa % fmtl->bh == 0);
3127 assert(total_z_offset_sa % fmtl->bd == 0);
3128 const uint32_t total_x_offset_el = total_x_offset_sa / fmtl->bw;
3129 const uint32_t total_y_offset_el = total_y_offset_sa / fmtl->bh;
3130 const uint32_t total_z_offset_el = total_z_offset_sa / fmtl->bd;
3131
3132 isl_tiling_get_intratile_offset_el(tiling, dim, msaa_layout, fmtl->bpb,
3133 samples, row_pitch_B,
3134 array_pitch_el_rows,
3135 total_x_offset_el,
3136 total_y_offset_el,
3137 total_z_offset_el,
3138 total_array_offset,
3139 tile_offset_B,
3140 x_offset_sa, y_offset_sa,
3141 z_offset_sa, array_offset);
3142 *x_offset_sa *= fmtl->bw;
3143 *y_offset_sa *= fmtl->bh;
3144 *z_offset_sa *= fmtl->bd;
3145 }
3146
3147 /**
3148 * Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
3149 *
3150 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
3151 * @pre surf->format must be a valid format for depth surfaces
3152 */
3153 uint32_t
3154 isl_surf_get_depth_format(const struct isl_device *dev,
3155 const struct isl_surf *surf);
3156
3157 /**
3158 * Performs a copy from linear to tiled surface
3159 */
3160 void
3161 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
3162 uint32_t yt1, uint32_t yt2,
3163 char *dst, const char *src,
3164 uint32_t dst_pitch, int32_t src_pitch,
3165 bool has_swizzling,
3166 enum isl_tiling tiling,
3167 isl_memcpy_type copy_type);
3168
3169 /**
3170 * Performs a copy from tiled to linear surface
3171 */
3172 void
3173 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
3174 uint32_t yt1, uint32_t yt2,
3175 char *dst, const char *src,
3176 int32_t dst_pitch, uint32_t src_pitch,
3177 bool has_swizzling,
3178 enum isl_tiling tiling,
3179 isl_memcpy_type copy_type);
3180
3181 /**
3182 * Computes the tile_w (in bytes) and tile_h (in rows) of
3183 * different tiling patterns.
3184 */
3185 static inline void
isl_get_tile_dims(enum isl_tiling tiling,uint32_t cpp,uint32_t * tile_w,uint32_t * tile_h)3186 isl_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
3187 uint32_t *tile_w, uint32_t *tile_h)
3188 {
3189 switch (tiling) {
3190 case ISL_TILING_X:
3191 *tile_w = 512;
3192 *tile_h = 8;
3193 break;
3194 case ISL_TILING_Y0:
3195 *tile_w = 128;
3196 *tile_h = 32;
3197 break;
3198 case ISL_TILING_LINEAR:
3199 *tile_w = cpp;
3200 *tile_h = 1;
3201 break;
3202 default:
3203 unreachable("not reached");
3204 }
3205 }
3206
3207 /**
3208 * Computes masks that may be used to select the bits of the X and Y
3209 * coordinates that indicate the offset within a tile. If the BO is untiled,
3210 * the masks are set to 0.
3211 */
3212 static inline void
isl_get_tile_masks(enum isl_tiling tiling,uint32_t cpp,uint32_t * mask_x,uint32_t * mask_y)3213 isl_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
3214 uint32_t *mask_x, uint32_t *mask_y)
3215 {
3216 uint32_t tile_w_bytes, tile_h;
3217
3218 isl_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
3219
3220 *mask_x = tile_w_bytes / cpp - 1;
3221 *mask_y = tile_h - 1;
3222 }
3223
3224 const char *
3225 isl_aux_op_to_name(enum isl_aux_op op);
3226
3227 const char *
3228 isl_tiling_to_name(enum isl_tiling tiling);
3229
3230 const char *
3231 isl_aux_usage_to_name(enum isl_aux_usage usage);
3232
3233 const char *
3234 isl_aux_state_to_name(enum isl_aux_state state);
3235
3236 #ifdef __cplusplus
3237 }
3238 #endif
3239
3240 #endif /* ISL_H */
3241