xref: /aosp_15_r20/external/coreboot/src/drivers/intel/fsp2_0/include/fsp/info_header.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef _FSP2_0_INFO_HEADER_H_
4 #define _FSP2_0_INFO_HEADER_H_
5 
6 #include <types.h>
7 
8 #define FSP_HDR_OFFSET			0x94
9 #define FSP_HDR_SIGNATURE		"FSPH"
10 #define FSP_HDR_ATTRIB_FSPT		1
11 #define FSP_HDR_ATTRIB_FSPM		2
12 #define FSP_HDR_ATTRIB_FSPS		3
13 #define FSP_IMAGE_ID_LENGTH		8
14 
15 struct fsp_header {
16 	uint32_t  signature; //FSPH
17 	uint32_t  header_length;
18 	uint8_t   res1[2];
19 	uint8_t   spec_version;
20 	uint8_t   header_revision;
21 	uint32_t  image_revision;
22 	char      image_id[FSP_IMAGE_ID_LENGTH]; // not zero terminated
23 	uint32_t  image_size;
24 	uint32_t  image_base;
25 	uint16_t  image_attribute;
26 	uint16_t  component_attribute;
27 	uint32_t  cfg_region_offset;
28 	uint32_t  cfg_region_size;
29 	uint32_t  res2;
30 	uint32_t  temp_ram_init_entry_offset; //initial stack
31 	uint32_t  res3;
32 	uint32_t  notify_phase_entry_offset;
33 	uint32_t  fsp_memory_init_entry_offset;
34 	uint32_t  temp_ram_exit_entry_offset;
35 	uint32_t  fsp_silicon_init_entry_offset;
36 	uint32_t  fsp_multi_phase_si_init_entry_offset;
37 	uint16_t  extended_image_revision;
38 	uint16_t  res4;
39 	uint32_t  fsp_multi_phase_mem_init_entry_offset;
40 	uint32_t  res5;
41 }  __packed;
42 
43 
44 enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
45 
46 /*
47  * This is a FSP_INFO_HEADER that came from fsps.bin blob. It contains
48  * both SiliconInit and Notify APIs. When SiliconInit is loaded the
49  * header is saved so that when Notify is called we do not have to start
50  * header parsing again.
51  */
52 extern struct fsp_header fsps_hdr;
53 
54 #endif /* _FSP2_0_INFO_HEADER_H_ */
55