1 /* 2 * Copyright (c) 2021-2022, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __VP_RENDER_COMMON_H__ 23 #define __VP_RENDER_COMMON_H__ 24 25 #include <stdint.h> 26 #include "surface_type.h" 27 28 namespace vp 29 { 30 #define CM_MAX_KERNEL_NAME_SIZE 256 31 #define READ_FIELD_FROM_BUF( dst, type ) \ 32 dst = *((type *) &pBuf[bytePos]); \ 33 bytePos += sizeof(type); 34 35 #define CISA_MAGIC_NUMBER 0x41534943 //"CISA" 36 #define GENX_TGLLP_CISAID 12 37 #define CM_MAX_ARGS_PER_KERNEL 255 // compiler only supports up to 255 arguments 38 #define CM_PAYLOAD_OFFSET 32 // CM Compiler generates offset by 32 bytes. This need to be subtracted from kernel data offset. 39 #define CM_PAYLOAD_OFFSET_LARGE 64 40 #define CM_MAX_THREAD_PAYLOAD_SIZE 2016 // 63 GRF 41 #define CM_KERNEL_BINARY_PADDING_SIZE 128 // Padding after kernel binary to WA page fault issue. 42 #define SURFACE_MASK 0x7 43 44 struct KERNEL_THREAD_SPACE 45 { 46 uint32_t uWidth; 47 uint32_t uHeight; 48 uint32_t uLocalWidth; 49 uint32_t uLocalHeight; 50 }; 51 52 // Need to consistant with compiler 53 enum KRN_ARG_KIND 54 { 55 // compiler-defined kind 56 ARG_KIND_GENERAL = 0x0, 57 ARG_KIND_SAMPLER = 0x1, 58 ARG_KIND_VME_INDEX = 0x6, 59 ARG_KIND_SURFACE = 0x8, //basic surface value 60 // using 3 LSB to classify surface further 61 ARG_KIND_SURFACE_2D = 0x9, 62 ARG_KIND_SURFACE_1D = 0xa, 63 ARG_KIND_SURFACE_SAMPLER8X8_AVS = 0xb, 64 ARG_KIND_SURFACE_SAMPLER = 0xc, 65 ARG_KIND_IMPLICT_LOCALSIZE = 0xe, 66 ARG_KIND_IMPLICT_GROUPSIZE = 0xf, 67 ARG_KIND_IMPLICIT_LOCALID = 0x10, 68 ARG_KIND_GENERAL_DEPVEC = 0x20, 69 ARG_KIND_SURFACE_2D_SCOREBOARD = 0x2A, 70 ARG_KIND_GENERAL_DEPCNT = 0x30, 71 72 //For L0 used only 73 ARG_KIND_INLINE = 0xa00 74 }; 75 76 enum KRN_ARG_ADDRESSMODE 77 { 78 AddressingModeStateful = 0, 79 AddressingModeStateless, 80 AddressingModeBindless, 81 AddressIngModeMax 82 }; 83 84 enum IMPLICIT_ARG_TYPE 85 { 86 ValueType = 0, 87 IndirectDataPtr, 88 ScratchPtr, 89 SamplerStateBasePtr, 90 SurfaceStateBasePtr 91 }; 92 93 struct KRN_ARG 94 { 95 uint32_t uIndex; 96 uint32_t uOffsetInPayload; // offset relative to R0 in payload 97 void* pData; 98 uint32_t uSize; // size of arg in byte 99 KRN_ARG_KIND eArgKind; 100 bool isOutput; 101 KRN_ARG_ADDRESSMODE addressMode; 102 IMPLICIT_ARG_TYPE implicitArgType; 103 }; 104 105 //for L0 use only 106 struct KRN_BTI 107 { 108 uint32_t uIndex; 109 uint32_t uBTI; 110 }; 111 112 //for L0 use only 113 struct KRN_EXECUTE_ENV 114 { 115 uint32_t uBarrierCount; 116 bool bDisableMidThreadPreemption; 117 uint32_t uGrfCount; 118 bool bHasGlobalAtomics; 119 bool bHasNoStatelessWrite; 120 uint32_t uInlineDataPayloadSize; 121 uint32_t uOffsetToSkipPerThreadDataLoad; 122 uint32_t uSimdSize; 123 uint32_t uSubgroupIndependentForwardProgress; 124 uint32_t uEuThreadCount; 125 bool bHasFenceForImageAccess; 126 bool bHasSample; 127 bool bHas4GBBuffers; 128 uint8_t uiWorkGroupWalkOrderDimensions[3]; 129 uint64_t uiPrivateSize; 130 uint32_t uiSlmSize; 131 }; 132 133 using SurfaceIndex = uint32_t; 134 using SamplerIndex = uint32_t; 135 using KernelIndex = uint32_t; // index of current kernel in KERNEL_PARAMS_LIST 136 137 typedef struct _SURFACE_PARAMS 138 { 139 SurfaceType surfType; 140 bool isOutput; 141 bool needVerticalStirde; 142 bool combineChannelY; 143 } SURFACE_PARAMS, *PSURFACE_PARAMS; 144 using KERNEL_ARG_INDEX_SURFACE_MAP = std::map<uint32_t, SURFACE_PARAMS>; 145 146 enum KERNEL_SUBMISSION_MODE 147 { 148 SINGLE_KERNEL_ONLY = 0, 149 MULTI_KERNELS_SINGLE_MEDIA_STATE, 150 }; 151 152 typedef struct _VP_RENDER_CACHE_CNTL 153 { 154 // Input 155 bool bDnDi; 156 bool bLace; 157 bool bCompositing; 158 bool bHdr; 159 160 // Output 161 VPHAL_DNDI_CACHE_CNTL DnDi; 162 VPHAL_LACE_CACHE_CNTL Lace; 163 VPHAL_COMPOSITE_CACHE_CNTL Composite; 164 VPHAL_HDR_CACHE_CNTL Hdr; 165 } VP_RENDER_CACHE_CNTL, *PVP_RENDER_CACHE_CNTL; 166 167 } 168 #endif // !__VP_SFC_COMMON_H__ 169