1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <time.h>
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "util/u_debug.h"
28 #include "util/ralloc.h"
29 #include "util/u_inlines.h"
30 #include "util/format/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "iris_context.h"
33 #include "iris_perf.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "iris_utrace.h"
37 #include "common/intel_sample_positions.h"
38
39 /**
40 * The pipe->set_debug_callback() driver hook.
41 */
42 static void
iris_set_debug_callback(struct pipe_context * ctx,const struct util_debug_callback * cb)43 iris_set_debug_callback(struct pipe_context *ctx,
44 const struct util_debug_callback *cb)
45 {
46 struct iris_context *ice = (struct iris_context *)ctx;
47 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
48
49 util_queue_finish(&screen->shader_compiler_queue);
50
51 if (cb)
52 ice->dbg = *cb;
53 else
54 memset(&ice->dbg, 0, sizeof(ice->dbg));
55 }
56
57 /**
58 * Called from the batch module when it detects a GPU hang.
59 *
60 * In this case, we've lost our GEM context, and can't rely on any existing
61 * state on the GPU. We must mark everything dirty and wipe away any saved
62 * assumptions about the last known state of the GPU.
63 */
64 void
iris_lost_context_state(struct iris_batch * batch)65 iris_lost_context_state(struct iris_batch *batch)
66 {
67 struct iris_context *ice = batch->ice;
68
69 if (batch->name == IRIS_BATCH_RENDER) {
70 batch->screen->vtbl.init_render_context(batch);
71 } else if (batch->name == IRIS_BATCH_COMPUTE) {
72 batch->screen->vtbl.init_compute_context(batch);
73 } else if (batch->name == IRIS_BATCH_BLITTER) {
74 /* No state to set up */
75 } else {
76 unreachable("unhandled batch reset");
77 }
78
79 ice->state.dirty = ~0ull;
80 ice->state.stage_dirty = ~0ull;
81 ice->state.current_hash_scale = 0;
82 memset(&ice->shaders.urb, 0, sizeof(ice->shaders.urb));
83 memset(ice->state.last_block, 0, sizeof(ice->state.last_block));
84 memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
85 ice->state.last_grid_dim = 0;
86 batch->last_binder_address = ~0ull;
87 batch->last_aux_map_state = 0;
88 batch->screen->vtbl.lost_genx_state(ice, batch);
89 }
90
91 static enum pipe_reset_status
iris_get_device_reset_status(struct pipe_context * ctx)92 iris_get_device_reset_status(struct pipe_context *ctx)
93 {
94 struct iris_context *ice = (struct iris_context *)ctx;
95
96 enum pipe_reset_status worst_reset = PIPE_NO_RESET;
97
98 /* Check the reset status of each batch's hardware context, and take the
99 * worst status (if one was guilty, proclaim guilt).
100 */
101 iris_foreach_batch(ice, batch) {
102 enum pipe_reset_status batch_reset =
103 iris_batch_check_for_reset(batch);
104
105 if (batch_reset == PIPE_NO_RESET)
106 continue;
107
108 if (worst_reset == PIPE_NO_RESET) {
109 worst_reset = batch_reset;
110 } else {
111 /* GUILTY < INNOCENT < UNKNOWN */
112 worst_reset = MIN2(worst_reset, batch_reset);
113 }
114 }
115
116 if (worst_reset != PIPE_NO_RESET && ice->reset.reset)
117 ice->reset.reset(ice->reset.data, worst_reset);
118
119 return worst_reset;
120 }
121
122 static void
iris_set_device_reset_callback(struct pipe_context * ctx,const struct pipe_device_reset_callback * cb)123 iris_set_device_reset_callback(struct pipe_context *ctx,
124 const struct pipe_device_reset_callback *cb)
125 {
126 struct iris_context *ice = (struct iris_context *)ctx;
127
128 if (cb)
129 ice->reset = *cb;
130 else
131 memset(&ice->reset, 0, sizeof(ice->reset));
132 }
133
134 static void
iris_get_sample_position(struct pipe_context * ctx,unsigned sample_count,unsigned sample_index,float * out_value)135 iris_get_sample_position(struct pipe_context *ctx,
136 unsigned sample_count,
137 unsigned sample_index,
138 float *out_value)
139 {
140 union {
141 struct {
142 float x[16];
143 float y[16];
144 } a;
145 struct {
146 float _0XOffset, _1XOffset, _2XOffset, _3XOffset,
147 _4XOffset, _5XOffset, _6XOffset, _7XOffset,
148 _8XOffset, _9XOffset, _10XOffset, _11XOffset,
149 _12XOffset, _13XOffset, _14XOffset, _15XOffset;
150 float _0YOffset, _1YOffset, _2YOffset, _3YOffset,
151 _4YOffset, _5YOffset, _6YOffset, _7YOffset,
152 _8YOffset, _9YOffset, _10YOffset, _11YOffset,
153 _12YOffset, _13YOffset, _14YOffset, _15YOffset;
154 } v;
155 } u;
156 switch (sample_count) {
157 case 1: INTEL_SAMPLE_POS_1X(u.v._); break;
158 case 2: INTEL_SAMPLE_POS_2X(u.v._); break;
159 case 4: INTEL_SAMPLE_POS_4X(u.v._); break;
160 case 8: INTEL_SAMPLE_POS_8X(u.v._); break;
161 case 16: INTEL_SAMPLE_POS_16X(u.v._); break;
162 default: unreachable("invalid sample count");
163 }
164
165 out_value[0] = u.a.x[sample_index];
166 out_value[1] = u.a.y[sample_index];
167 }
168
169 static bool
create_dirty_dmabuf_set(struct iris_context * ice)170 create_dirty_dmabuf_set(struct iris_context *ice)
171 {
172 assert(ice->dirty_dmabufs == NULL);
173
174 ice->dirty_dmabufs = _mesa_pointer_set_create(ice);
175 return ice->dirty_dmabufs != NULL;
176 }
177
178 void
iris_mark_dirty_dmabuf(struct iris_context * ice,struct pipe_resource * res)179 iris_mark_dirty_dmabuf(struct iris_context *ice,
180 struct pipe_resource *res)
181 {
182 if (!_mesa_set_search(ice->dirty_dmabufs, res)) {
183 _mesa_set_add(ice->dirty_dmabufs, res);
184 pipe_reference(NULL, &res->reference);
185 }
186 }
187
188 static void
clear_dirty_dmabuf_set(struct iris_context * ice)189 clear_dirty_dmabuf_set(struct iris_context *ice)
190 {
191 set_foreach(ice->dirty_dmabufs, entry) {
192 struct pipe_resource *res = (struct pipe_resource *)entry->key;
193 if (pipe_reference(&res->reference, NULL))
194 res->screen->resource_destroy(res->screen, res);
195 }
196
197 _mesa_set_clear(ice->dirty_dmabufs, NULL);
198 }
199
200 void
iris_flush_dirty_dmabufs(struct iris_context * ice)201 iris_flush_dirty_dmabufs(struct iris_context *ice)
202 {
203 set_foreach(ice->dirty_dmabufs, entry) {
204 struct pipe_resource *res = (struct pipe_resource *)entry->key;
205 ice->ctx.flush_resource(&ice->ctx, res);
206 }
207
208 clear_dirty_dmabuf_set(ice);
209 }
210
211 /**
212 * Destroy a context, freeing any associated memory.
213 */
214 void
iris_destroy_context(struct pipe_context * ctx)215 iris_destroy_context(struct pipe_context *ctx)
216 {
217 struct iris_context *ice = (struct iris_context *)ctx;
218 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
219
220 blorp_finish(&ice->blorp);
221
222 intel_perf_free_context(ice->perf_ctx);
223 if (ctx->stream_uploader)
224 u_upload_destroy(ctx->stream_uploader);
225 if (ctx->const_uploader)
226 u_upload_destroy(ctx->const_uploader);
227
228 clear_dirty_dmabuf_set(ice);
229
230 screen->vtbl.destroy_state(ice);
231
232 for (unsigned i = 0; i < ARRAY_SIZE(ice->shaders.scratch_surfs); i++)
233 pipe_resource_reference(&ice->shaders.scratch_surfs[i].res, NULL);
234
235 for (unsigned i = 0; i < ARRAY_SIZE(ice->shaders.scratch_bos); i++) {
236 for (unsigned j = 0; j < ARRAY_SIZE(ice->shaders.scratch_bos[i]); j++)
237 iris_bo_unreference(ice->shaders.scratch_bos[i][j]);
238 }
239
240 iris_destroy_program_cache(ice);
241 if (screen->measure.config)
242 iris_destroy_ctx_measure(ice);
243
244 u_upload_destroy(ice->state.surface_uploader);
245 u_upload_destroy(ice->state.scratch_surface_uploader);
246 u_upload_destroy(ice->state.dynamic_uploader);
247 u_upload_destroy(ice->query_buffer_uploader);
248
249 iris_destroy_batches(ice);
250 iris_destroy_binder(&ice->state.binder);
251 iris_bo_unreference(ice->draw.generation.ring_bo);
252
253 iris_utrace_fini(ice);
254
255 slab_destroy_child(&ice->transfer_pool);
256 slab_destroy_child(&ice->transfer_pool_unsync);
257
258 ralloc_free(ice);
259 }
260
261 #define genX_call(devinfo, func, ...) \
262 switch ((devinfo)->verx10) { \
263 case 200: \
264 gfx20_##func(__VA_ARGS__); \
265 break; \
266 case 125: \
267 gfx125_##func(__VA_ARGS__); \
268 break; \
269 case 120: \
270 gfx12_##func(__VA_ARGS__); \
271 break; \
272 case 110: \
273 gfx11_##func(__VA_ARGS__); \
274 break; \
275 case 90: \
276 gfx9_##func(__VA_ARGS__); \
277 break; \
278 case 80: \
279 gfx8_##func(__VA_ARGS__); \
280 break; \
281 default: \
282 unreachable("Unknown hardware generation"); \
283 }
284
285 /**
286 * Create a context.
287 *
288 * This is where each context begins.
289 */
290 struct pipe_context *
iris_create_context(struct pipe_screen * pscreen,void * priv,unsigned flags)291 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
292 {
293 struct iris_screen *screen = (struct iris_screen*)pscreen;
294 const struct intel_device_info *devinfo = screen->devinfo;
295 struct iris_context *ice = rzalloc(NULL, struct iris_context);
296
297 if (!ice)
298 return NULL;
299
300 struct pipe_context *ctx = &ice->ctx;
301
302 ctx->screen = pscreen;
303 ctx->priv = priv;
304
305 ctx->stream_uploader = u_upload_create(ctx, 1024 * 1024 * 2,
306 PIPE_BIND_VERTEX_BUFFER |
307 PIPE_BIND_INDEX_BUFFER |
308 PIPE_BIND_CONSTANT_BUFFER,
309 PIPE_USAGE_STREAM, 0);
310 if (!ctx->stream_uploader) {
311 ralloc_free(ice);
312 return NULL;
313 }
314 ctx->const_uploader = u_upload_create(ctx, 1024 * 1024,
315 PIPE_BIND_CONSTANT_BUFFER,
316 PIPE_USAGE_IMMUTABLE,
317 IRIS_RESOURCE_FLAG_DEVICE_MEM);
318 if (!ctx->const_uploader) {
319 u_upload_destroy(ctx->stream_uploader);
320 ralloc_free(ice);
321 return NULL;
322 }
323
324 if (!create_dirty_dmabuf_set(ice)) {
325 ralloc_free(ice);
326 return NULL;
327 }
328
329 ctx->destroy = iris_destroy_context;
330 ctx->set_debug_callback = iris_set_debug_callback;
331 ctx->set_device_reset_callback = iris_set_device_reset_callback;
332 ctx->get_device_reset_status = iris_get_device_reset_status;
333 ctx->get_sample_position = iris_get_sample_position;
334
335 iris_init_context_fence_functions(ctx);
336 iris_init_blit_functions(ctx);
337 iris_init_clear_functions(ctx);
338 iris_init_program_functions(ctx);
339 iris_init_resource_functions(ctx);
340 iris_init_flush_functions(ctx);
341 iris_init_perfquery_functions(ctx);
342
343 iris_init_program_cache(ice);
344 iris_init_binder(ice);
345
346 slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
347 slab_create_child(&ice->transfer_pool_unsync, &screen->transfer_pool);
348
349 ice->state.surface_uploader =
350 u_upload_create(ctx, 64 * 1024, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
351 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
352 IRIS_RESOURCE_FLAG_DEVICE_MEM);
353 ice->state.scratch_surface_uploader =
354 u_upload_create(ctx, 64 * 1024, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
355 IRIS_RESOURCE_FLAG_SCRATCH_MEMZONE |
356 IRIS_RESOURCE_FLAG_DEVICE_MEM);
357 ice->state.dynamic_uploader =
358 u_upload_create(ctx, 64 * 1024, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
359 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE |
360 IRIS_RESOURCE_FLAG_DEVICE_MEM);
361
362 ice->query_buffer_uploader =
363 u_upload_create(ctx, 16 * 1024, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING,
364 0);
365
366 genX_call(devinfo, init_state, ice);
367 genX_call(devinfo, init_blorp, ice);
368 genX_call(devinfo, init_query, ice);
369
370 if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
371 ice->priority = IRIS_CONTEXT_HIGH_PRIORITY;
372 if (flags & PIPE_CONTEXT_LOW_PRIORITY)
373 ice->priority = IRIS_CONTEXT_LOW_PRIORITY;
374 if (flags & PIPE_CONTEXT_PROTECTED)
375 ice->protected = true;
376
377 if (INTEL_DEBUG(DEBUG_BATCH))
378 ice->state.sizes = _mesa_hash_table_u64_create(ice);
379
380 /* Do this before initializing the batches */
381 iris_utrace_init(ice);
382
383 iris_init_batches(ice);
384
385 screen->vtbl.init_render_context(&ice->batches[IRIS_BATCH_RENDER]);
386 screen->vtbl.init_compute_context(&ice->batches[IRIS_BATCH_COMPUTE]);
387 screen->vtbl.init_copy_context(&ice->batches[IRIS_BATCH_BLITTER]);
388
389 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
390 return ctx;
391
392 /* Clover doesn't support u_threaded_context */
393 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
394 return ctx;
395
396 return threaded_context_create(ctx, &screen->transfer_pool,
397 iris_replace_buffer_storage,
398 &(struct threaded_context_options){
399 .unsynchronized_get_device_reset_status = true,
400 },
401 &ice->thrctx);
402 }
403