1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <errno.h>
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/format/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36
37 static bool
iris_is_color_fast_clear_compatible(struct iris_context * ice,enum isl_format format,const union isl_color_value color)38 iris_is_color_fast_clear_compatible(struct iris_context *ice,
39 enum isl_format format,
40 const union isl_color_value color)
41 {
42 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
43 const struct intel_device_info *devinfo = batch->screen->devinfo;
44
45 if (isl_format_has_int_channel(format)) {
46 perf_debug(&ice->dbg, "Integer fast clear not enabled for %s\n",
47 isl_format_get_name(format));
48 return false;
49 }
50
51 for (int i = 0; i < 4; i++) {
52 if (!isl_format_has_color_component(format, i)) {
53 continue;
54 }
55
56 if (devinfo->ver < 9 &&
57 color.f32[i] != 0.0f && color.f32[i] != 1.0f) {
58 return false;
59 }
60 }
61
62 return true;
63 }
64
65 static bool
can_fast_clear_color(struct iris_context * ice,struct pipe_resource * p_res,unsigned level,const struct pipe_box * box,bool render_condition_enabled,enum isl_format render_format,union isl_color_value color)66 can_fast_clear_color(struct iris_context *ice,
67 struct pipe_resource *p_res,
68 unsigned level,
69 const struct pipe_box *box,
70 bool render_condition_enabled,
71 enum isl_format render_format,
72 union isl_color_value color)
73 {
74 struct iris_resource *res = (void *) p_res;
75
76 if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
77 return false;
78
79 if (!isl_aux_usage_has_fast_clears(res->aux.usage))
80 return false;
81
82 /* Check for partial clear */
83 if (box->x > 0 || box->y > 0 ||
84 box->width < u_minify(p_res->width0, level) ||
85 box->height < u_minify(p_res->height0, level)) {
86 return false;
87 }
88
89 /* Avoid conditional fast clears to maintain correct tracking of the aux
90 * state (see iris_resource_finish_write for more info). Note that partial
91 * fast clears (if they existed) would not pose a problem with conditional
92 * rendering.
93 */
94 if (render_condition_enabled &&
95 ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
96 return false;
97 }
98
99 /* Disable sRGB fast-clears for non-0/1 color values. For texturing and
100 * draw calls, HW expects the clear color to be in two different color
101 * spaces after sRGB fast-clears - sRGB in the former and linear in the
102 * latter. By limiting the allowable values to 0/1, both color space
103 * requirements are satisfied.
104 */
105 if (isl_format_is_srgb(render_format) &&
106 !isl_color_value_is_zero_one(color, render_format)) {
107 return false;
108 }
109
110 /* We store clear colors as floats or uints as needed. If there are
111 * texture views in play, the formats will not properly be respected
112 * during resolves because the resolve operations only know about the
113 * resource and not the renderbuffer.
114 */
115 if (!iris_render_formats_color_compatible(render_format, res->surf.format,
116 color, false)) {
117 return false;
118 }
119
120 if (!iris_is_color_fast_clear_compatible(ice, res->surf.format, color))
121 return false;
122
123 /* The RENDER_SURFACE_STATE page for TGL says:
124 *
125 * For an 8 bpp surface with NUM_MULTISAMPLES = 1, Surface Width not
126 * multiple of 64 pixels and more than 1 mip level in the view, Fast Clear
127 * is not supported when AUX_CCS_E is set in this field.
128 *
129 * The granularity of a fast-clear is one CCS element. For an 8 bpp primary
130 * surface, this maps to 32px x 4rows. Due to the surface layout parameters,
131 * if LOD0's width isn't a multiple of 64px, LOD1 and LOD2+ will share CCS
132 * elements. Assuming LOD2 exists, don't fast-clear any level above LOD0
133 * to avoid stomping on other LODs.
134 */
135 if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 &&
136 p_res->width0 % 64) {
137 return false;
138 }
139
140 /* Wa_18020603990 - slow clear surfaces up to 256x256, 32bpp. */
141 const struct intel_device_info *devinfo =
142 ((struct iris_screen *)ice->ctx.screen)->devinfo;
143 if (intel_needs_workaround(devinfo, 18020603990)) {
144 if (isl_format_get_layout(res->surf.format)->bpb <= 32 &&
145 res->surf.logical_level0_px.w <= 256 &&
146 res->surf.logical_level0_px.h <= 256)
147 return false;
148 }
149
150 /* On gfx12.0, CCS fast clears don't seem to cover the correct portion of
151 * the aux buffer when the pitch is not 512B-aligned.
152 */
153 if (devinfo->verx10 == 120 &&
154 res->surf.samples == 1 &&
155 res->surf.row_pitch_B % 512) {
156 perf_debug(&ice->dbg, "Pitch not 512B-aligned. Slow clearing surface.");
157 return false;
158 }
159
160 /* Wa_16021232440: Disable fast clear when height is 16k */
161 if (intel_needs_workaround(devinfo, 16021232440) &&
162 res->surf.logical_level0_px.h == 16 * 1024) {
163 return false;
164 }
165
166 return true;
167 }
168
169 static union isl_color_value
convert_clear_color(enum pipe_format format,const union pipe_color_union * color)170 convert_clear_color(enum pipe_format format,
171 const union pipe_color_union *color)
172 {
173 uint32_t pixel[4];
174 util_format_pack_rgba(format, pixel, color, 1);
175
176 union isl_color_value converted_color;
177 util_format_unpack_rgba(format, &converted_color, pixel, 1);
178
179 /* The converted clear color has channels that are:
180 * - clamped
181 * - quantized
182 * - filled with 0/1 if missing from the format
183 * - swizzled for luminance and intensity formats
184 */
185 return converted_color;
186 }
187
188 static void
fast_clear_color(struct iris_context * ice,struct iris_resource * res,unsigned level,const struct pipe_box * box,union isl_color_value color)189 fast_clear_color(struct iris_context *ice,
190 struct iris_resource *res,
191 unsigned level,
192 const struct pipe_box *box,
193 union isl_color_value color)
194 {
195 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
196 const struct intel_device_info *devinfo = batch->screen->devinfo;
197 struct pipe_resource *p_res = (void *) res;
198
199 bool color_changed = res->aux.clear_color_unknown ||
200 memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0;
201
202 if (color_changed) {
203 /* If we are clearing to a new clear value, we need to resolve fast
204 * clears from other levels/layers first, since we can't have different
205 * levels/layers with different fast clear colors.
206 */
207 for (unsigned res_lvl = 0; res_lvl < res->surf.levels; res_lvl++) {
208 const unsigned level_layers =
209 iris_get_num_logical_layers(res, res_lvl);
210 for (unsigned layer = 0; layer < level_layers; layer++) {
211 if (res_lvl == level &&
212 layer >= box->z &&
213 layer < box->z + box->depth) {
214 /* We're going to clear this layer anyway. Leave it alone. */
215 continue;
216 }
217
218 enum isl_aux_state aux_state =
219 iris_resource_get_aux_state(res, res_lvl, layer);
220
221 if (aux_state != ISL_AUX_STATE_CLEAR &&
222 aux_state != ISL_AUX_STATE_PARTIAL_CLEAR &&
223 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
224 /* This slice doesn't have any fast-cleared bits. */
225 continue;
226 }
227
228 /* If we got here, then the level may have fast-clear bits that use
229 * the old clear value. We need to do a color resolve to get rid
230 * of their use of the clear color before we can change it.
231 * Fortunately, few applications ever change their clear color at
232 * different levels/layers, so this shouldn't happen often.
233 */
234 iris_resource_prepare_access(ice, res,
235 res_lvl, 1, layer, 1,
236 res->aux.usage,
237 false);
238 if (res->aux.clear_color_unknown) {
239 perf_debug(&ice->dbg,
240 "Resolving resource (%p) level %d, layer %d: color changing from "
241 "(unknown) to (%0.2f, %0.2f, %0.2f, %0.2f)\n",
242 res, res_lvl, layer,
243 color.f32[0], color.f32[1], color.f32[2], color.f32[3]);
244 } else {
245 perf_debug(&ice->dbg,
246 "Resolving resource (%p) level %d, layer %d: color changing from "
247 "(%0.2f, %0.2f, %0.2f, %0.2f) to "
248 "(%0.2f, %0.2f, %0.2f, %0.2f)\n",
249 res, res_lvl, layer,
250 res->aux.clear_color.f32[0],
251 res->aux.clear_color.f32[1],
252 res->aux.clear_color.f32[2],
253 res->aux.clear_color.f32[3],
254 color.f32[0], color.f32[1], color.f32[2], color.f32[3]);
255 }
256 }
257 }
258 }
259
260 iris_resource_set_clear_color(ice, res, color);
261
262 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
263 *
264 * "Any transition from any value in {Clear, Render, Resolve} to a
265 * different value in {Clear, Render, Resolve} requires end of pipe
266 * synchronization."
267 *
268 * In other words, fast clear ops are not properly synchronized with
269 * other drawing. We need to use a PIPE_CONTROL to ensure that the
270 * contents of the previous draw hit the render target before we resolve
271 * and again afterwards to ensure that the resolve is complete before we
272 * do any more regular drawing.
273 */
274 iris_emit_end_of_pipe_sync(batch, "fast clear: pre-flush",
275 PIPE_CONTROL_RENDER_TARGET_FLUSH |
276 (devinfo->ver == 12 ? PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
277 PIPE_CONTROL_TILE_CACHE_FLUSH : 0) |
278 (devinfo->verx10 == 120 ? PIPE_CONTROL_DEPTH_STALL : 0) |
279 (devinfo->verx10 == 125 ? PIPE_CONTROL_FLUSH_HDC |
280 PIPE_CONTROL_DATA_CACHE_FLUSH : 0) |
281 PIPE_CONTROL_PSS_STALL_SYNC);
282
283 /* Update the clear color now that previous rendering is complete. */
284 if (color_changed && res->aux.clear_color_bo)
285 iris_resource_update_indirect_color(batch, res);
286
287 /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear is redundant
288 * and can be skipped.
289 */
290 const enum isl_aux_state aux_state =
291 iris_resource_get_aux_state(res, level, box->z);
292 if (box->depth == 1 && aux_state == ISL_AUX_STATE_CLEAR)
293 return;
294
295 iris_batch_sync_region_start(batch);
296
297 struct blorp_batch blorp_batch;
298 blorp_batch_init(&ice->blorp, &blorp_batch, batch, 0);
299
300 struct blorp_surf surf;
301 iris_blorp_surf_for_resource(batch, &surf, p_res, res->aux.usage,
302 level, true);
303
304 blorp_fast_clear(&blorp_batch, &surf, res->surf.format,
305 ISL_SWIZZLE_IDENTITY,
306 level, box->z, box->depth,
307 box->x, box->y, box->x + box->width,
308 box->y + box->height);
309 blorp_batch_finish(&blorp_batch);
310 iris_emit_end_of_pipe_sync(batch,
311 "fast clear: post flush",
312 PIPE_CONTROL_RENDER_TARGET_FLUSH |
313 (devinfo->verx10 == 120 ?
314 PIPE_CONTROL_TILE_CACHE_FLUSH |
315 PIPE_CONTROL_DEPTH_STALL : 0) |
316 PIPE_CONTROL_PSS_STALL_SYNC);
317 iris_batch_sync_region_end(batch);
318
319 iris_resource_set_aux_state(ice, res, level, box->z,
320 box->depth, devinfo->ver < 20 ?
321 ISL_AUX_STATE_CLEAR :
322 ISL_AUX_STATE_COMPRESSED_NO_CLEAR);
323 ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER;
324 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
325 return;
326 }
327
328 static void
clear_color(struct iris_context * ice,struct pipe_resource * p_res,unsigned level,const struct pipe_box * box,bool render_condition_enabled,enum isl_format format,struct isl_swizzle swizzle,union isl_color_value color)329 clear_color(struct iris_context *ice,
330 struct pipe_resource *p_res,
331 unsigned level,
332 const struct pipe_box *box,
333 bool render_condition_enabled,
334 enum isl_format format,
335 struct isl_swizzle swizzle,
336 union isl_color_value color)
337 {
338 struct iris_resource *res = (void *) p_res;
339
340 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
341 const struct intel_device_info *devinfo = batch->screen->devinfo;
342 enum blorp_batch_flags blorp_flags = iris_blorp_flags_for_batch(batch);
343
344 if (render_condition_enabled) {
345 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
346 return;
347
348 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
349 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
350 }
351
352 if (p_res->target == PIPE_BUFFER)
353 util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
354
355 iris_batch_maybe_flush(batch, 1500);
356
357 bool can_fast_clear = can_fast_clear_color(ice, p_res, level, box,
358 render_condition_enabled,
359 format, color);
360 if (can_fast_clear) {
361 fast_clear_color(ice, res, level, box, color);
362 return;
363 }
364
365 enum isl_aux_usage aux_usage =
366 iris_resource_render_aux_usage(ice, res, format, level, false);
367
368 iris_resource_prepare_render(ice, res, format, level, box->z, box->depth,
369 aux_usage);
370 iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_RENDER_WRITE);
371
372 struct blorp_surf surf;
373 iris_blorp_surf_for_resource(batch, &surf, p_res, aux_usage, level, true);
374
375 iris_batch_sync_region_start(batch);
376
377 struct blorp_batch blorp_batch;
378 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
379
380 if (!isl_format_supports_rendering(devinfo, format) &&
381 isl_format_is_rgbx(format))
382 format = isl_format_rgbx_to_rgba(format);
383
384 blorp_clear(&blorp_batch, &surf, format, swizzle,
385 level, box->z, box->depth, box->x, box->y,
386 box->x + box->width, box->y + box->height,
387 color, 0 /* color_write_disable */);
388
389 blorp_batch_finish(&blorp_batch);
390 iris_batch_sync_region_end(batch);
391
392 iris_dirty_for_history(ice, res);
393
394 iris_resource_finish_render(ice, res, level,
395 box->z, box->depth, aux_usage);
396 }
397
398 static bool
can_fast_clear_depth(struct iris_context * ice,struct iris_resource * res,unsigned level,const struct pipe_box * box,bool render_condition_enabled,float depth)399 can_fast_clear_depth(struct iris_context *ice,
400 struct iris_resource *res,
401 unsigned level,
402 const struct pipe_box *box,
403 bool render_condition_enabled,
404 float depth)
405 {
406 struct pipe_resource *p_res = (void *) res;
407 struct pipe_context *ctx = (void *) ice;
408 struct iris_screen *screen = (void *) ctx->screen;
409 const struct intel_device_info *devinfo = screen->devinfo;
410
411 if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
412 return false;
413
414 /* Check for partial clears */
415 if (box->x > 0 || box->y > 0 ||
416 box->width < u_minify(p_res->width0, level) ||
417 box->height < u_minify(p_res->height0, level)) {
418 return false;
419 }
420
421 /* Avoid conditional fast clears to maintain correct tracking of the aux
422 * state (see iris_resource_finish_write for more info). Note that partial
423 * fast clears would not pose a problem with conditional rendering.
424 */
425 if (render_condition_enabled &&
426 ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
427 return false;
428 }
429
430 if (!iris_resource_level_has_hiz(devinfo, res, level))
431 return false;
432
433 /* From the TGL PRM, Vol 9, "Compressed Depth Buffers" (under the
434 * "Texture performant" and "ZCS" columns):
435 *
436 * Update with clear at either 16x8 or 8x4 granularity, based on
437 * fs_clr or otherwise.
438 *
439 * When fast-clearing, hardware behaves in unexpected ways if the clear
440 * rectangle, aligned to 16x8, could cover neighboring LODs. Fortunately,
441 * ISL guarantees that LOD0 will be 8-row aligned and LOD0's height seems
442 * to not matter. Also, few applications ever clear LOD1+. Only allow
443 * fast-clearing upper LODs if no overlap can occur.
444 */
445 if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT && level >= 1 &&
446 (p_res->width0 % 32 != 0 || res->surf.image_alignment_el.h % 8 != 0)) {
447 return false;
448 }
449
450 return true;
451 }
452
453 static void
fast_clear_depth(struct iris_context * ice,struct iris_resource * res,unsigned level,const struct pipe_box * box,float depth)454 fast_clear_depth(struct iris_context *ice,
455 struct iris_resource *res,
456 unsigned level,
457 const struct pipe_box *box,
458 float depth)
459 {
460 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
461 const struct intel_device_info *devinfo = batch->screen->devinfo;
462
463 if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
464 /* From Bspec 47010 (Depth Buffer Clear):
465 *
466 * Since the fast clear cycles to CCS are not cached in TileCache,
467 * any previous depth buffer writes to overlapping pixels must be
468 * flushed out of TileCache before a succeeding Depth Buffer Clear.
469 * This restriction only applies to Depth Buffer with write-thru
470 * enabled, since fast clears to CCS only occur for write-thru mode.
471 *
472 * There may have been a write to this depth buffer. Flush it from the
473 * tile cache just in case.
474 *
475 * Set CS stall bit to guarantee that the fast clear starts the execution
476 * after the tile cache flush completed.
477 */
478 iris_emit_pipe_control_flush(batch, "hiz_ccs_wt: before fast clear",
479 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
480 PIPE_CONTROL_CS_STALL |
481 PIPE_CONTROL_TILE_CACHE_FLUSH);
482 }
483
484 /* If we're clearing to a new clear value, then we need to resolve any clear
485 * flags out of the HiZ buffer into the real depth buffer.
486 */
487 if (res->aux.clear_color_unknown || res->aux.clear_color.f32[0] != depth) {
488 for (unsigned res_level = 0; res_level < res->surf.levels; res_level++) {
489 const unsigned level_layers =
490 iris_get_num_logical_layers(res, res_level);
491 for (unsigned layer = 0; layer < level_layers; layer++) {
492 if (res_level == level &&
493 layer >= box->z &&
494 layer < box->z + box->depth) {
495 /* We're going to clear this layer anyway. Leave it alone. */
496 continue;
497 }
498
499 enum isl_aux_state aux_state =
500 iris_resource_get_aux_state(res, res_level, layer);
501
502 if (aux_state != ISL_AUX_STATE_CLEAR &&
503 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
504 /* This slice doesn't have any fast-cleared bits. */
505 continue;
506 }
507
508 /* If we got here, then the level may have fast-clear bits that
509 * use the old clear value. We need to do a depth resolve to get
510 * rid of their use of the clear value before we can change it.
511 * Fortunately, few applications ever change their depth clear
512 * value so this shouldn't happen often.
513 */
514 iris_hiz_exec(ice, batch, res, res_level, layer, 1,
515 ISL_AUX_OP_FULL_RESOLVE);
516 iris_resource_set_aux_state(ice, res, res_level, layer, 1,
517 ISL_AUX_STATE_RESOLVED);
518 }
519 }
520 const union isl_color_value clear_value = { .f32 = {depth, } };
521 iris_resource_set_clear_color(ice, res, clear_value);
522
523 /* Also set the indirect clear color if it exists. */
524 if (res->aux.clear_color_bo) {
525 uint32_t packed_depth[4] = {};
526 isl_color_value_pack(&clear_value, res->surf.format, packed_depth);
527
528 const uint64_t clear_pixel_offset = res->aux.clear_color_offset +
529 isl_get_sampler_clear_field_offset(devinfo, res->surf.format);
530
531 iris_emit_pipe_control_write(batch, "update fast clear value (Z)",
532 PIPE_CONTROL_WRITE_IMMEDIATE,
533 res->aux.clear_color_bo,
534 clear_pixel_offset, packed_depth[0]);
535
536 /* From the TGL PRMs, Volume 9: Render Engine, State Caching :
537 *
538 * "Any values referenced by pointers within the
539 * RENDER_SURFACE_STATE or SAMPLER_STATE (e.g. Clear Color
540 * Pointer, Border Color or Indirect State Pointer) are considered
541 * to be part of that state and any changes to these referenced
542 * values requires an invalidation of the L1 state cache to ensure
543 * the new values are being used as part of the state."
544 *
545 * Invalidate the state cache as suggested.
546 */
547 iris_emit_pipe_control_flush(batch, "flush fast clear values (z)",
548 PIPE_CONTROL_FLUSH_ENABLE |
549 PIPE_CONTROL_STATE_CACHE_INVALIDATE);
550 }
551 }
552
553 for (unsigned l = 0; l < box->depth; l++) {
554 enum isl_aux_state aux_state =
555 iris_resource_get_aux_state(res, level, box->z + l);
556 if (aux_state != ISL_AUX_STATE_CLEAR) {
557 iris_hiz_exec(ice, batch, res, level,
558 box->z + l, 1, ISL_AUX_OP_FAST_CLEAR);
559 }
560 }
561
562 iris_resource_set_aux_state(ice, res, level, box->z, box->depth,
563 devinfo->ver < 20 ? ISL_AUX_STATE_CLEAR :
564 ISL_AUX_STATE_COMPRESSED_NO_CLEAR);
565 ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER;
566 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
567 }
568
569 static void
clear_depth_stencil(struct iris_context * ice,struct pipe_resource * p_res,unsigned level,const struct pipe_box * box,bool render_condition_enabled,bool clear_depth,bool clear_stencil,float depth,uint8_t stencil)570 clear_depth_stencil(struct iris_context *ice,
571 struct pipe_resource *p_res,
572 unsigned level,
573 const struct pipe_box *box,
574 bool render_condition_enabled,
575 bool clear_depth,
576 bool clear_stencil,
577 float depth,
578 uint8_t stencil)
579 {
580 struct iris_resource *res = (void *) p_res;
581
582 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
583 enum blorp_batch_flags blorp_flags = 0;
584
585 if (render_condition_enabled) {
586 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
587 return;
588
589 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
590 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
591 }
592
593 iris_batch_maybe_flush(batch, 1500);
594
595 struct iris_resource *z_res;
596 struct iris_resource *stencil_res;
597 struct blorp_surf z_surf;
598 struct blorp_surf stencil_surf;
599
600 iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res);
601 if (z_res && clear_depth &&
602 can_fast_clear_depth(ice, z_res, level, box, render_condition_enabled,
603 depth)) {
604 fast_clear_depth(ice, z_res, level, box, depth);
605 iris_dirty_for_history(ice, res);
606 clear_depth = false;
607 z_res = false;
608 }
609
610 /* At this point, we might have fast cleared the depth buffer. So if there's
611 * no stencil clear pending, return early.
612 */
613 if (!(clear_depth || (clear_stencil && stencil_res))) {
614 return;
615 }
616
617 if (clear_depth && z_res) {
618 const enum isl_aux_usage aux_usage =
619 iris_resource_render_aux_usage(ice, z_res, z_res->surf.format, level,
620 false);
621 iris_resource_prepare_render(ice, z_res, z_res->surf.format, level,
622 box->z, box->depth, aux_usage);
623 iris_emit_buffer_barrier_for(batch, z_res->bo, IRIS_DOMAIN_DEPTH_WRITE);
624 iris_blorp_surf_for_resource(batch, &z_surf, &z_res->base.b,
625 aux_usage, level, true);
626 }
627
628 uint8_t stencil_mask = clear_stencil && stencil_res ? 0xff : 0;
629 if (stencil_mask) {
630 iris_resource_prepare_access(ice, stencil_res, level, 1, box->z,
631 box->depth, stencil_res->aux.usage, false);
632 iris_emit_buffer_barrier_for(batch, stencil_res->bo,
633 IRIS_DOMAIN_DEPTH_WRITE);
634 iris_blorp_surf_for_resource(batch, &stencil_surf, &stencil_res->base.b,
635 stencil_res->aux.usage, level, true);
636 }
637
638 iris_batch_sync_region_start(batch);
639
640 struct blorp_batch blorp_batch;
641 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
642
643 blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
644 level, box->z, box->depth,
645 box->x, box->y,
646 box->x + box->width,
647 box->y + box->height,
648 clear_depth && z_res, depth,
649 stencil_mask, stencil);
650
651 blorp_batch_finish(&blorp_batch);
652 iris_batch_sync_region_end(batch);
653
654 iris_dirty_for_history(ice, res);
655
656 if (clear_depth && z_res) {
657 iris_resource_finish_render(ice, z_res, level, box->z, box->depth,
658 z_surf.aux_usage);
659 }
660
661 if (stencil_mask) {
662 iris_resource_finish_write(ice, stencil_res, level, box->z, box->depth,
663 stencil_res->aux.usage);
664 }
665 }
666
667 /**
668 * The pipe->clear() driver hook.
669 *
670 * This clears buffers attached to the current draw framebuffer.
671 */
672 static void
iris_clear(struct pipe_context * ctx,unsigned buffers,const struct pipe_scissor_state * scissor_state,const union pipe_color_union * p_color,double depth,unsigned stencil)673 iris_clear(struct pipe_context *ctx,
674 unsigned buffers,
675 const struct pipe_scissor_state *scissor_state,
676 const union pipe_color_union *p_color,
677 double depth,
678 unsigned stencil)
679 {
680 struct iris_context *ice = (void *) ctx;
681 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
682
683 assert(buffers != 0);
684
685 struct pipe_box box = {
686 .width = cso_fb->width,
687 .height = cso_fb->height,
688 };
689
690 if (scissor_state) {
691 box.x = scissor_state->minx;
692 box.y = scissor_state->miny;
693 box.width = MIN2(box.width, scissor_state->maxx - scissor_state->minx);
694 box.height = MIN2(box.height, scissor_state->maxy - scissor_state->miny);
695 }
696
697 if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
698 struct pipe_surface *psurf = cso_fb->zsbuf;
699
700 box.depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1;
701 box.z = psurf->u.tex.first_layer,
702 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, true,
703 buffers & PIPE_CLEAR_DEPTH,
704 buffers & PIPE_CLEAR_STENCIL,
705 depth, stencil);
706 }
707
708 if (buffers & PIPE_CLEAR_COLOR) {
709 for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
710 if (buffers & (PIPE_CLEAR_COLOR0 << i)) {
711 struct pipe_surface *psurf = cso_fb->cbufs[i];
712 struct iris_surface *isurf = (void *) psurf;
713 box.depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
714 box.z = psurf->u.tex.first_layer,
715
716 clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
717 true, isurf->view.format, isurf->view.swizzle,
718 convert_clear_color(psurf->format, p_color));
719 }
720 }
721 }
722 }
723
724 /**
725 * The pipe->clear_texture() driver hook.
726 *
727 * This clears the given texture resource.
728 */
729 static void
iris_clear_texture(struct pipe_context * ctx,struct pipe_resource * p_res,unsigned level,const struct pipe_box * box,const void * data)730 iris_clear_texture(struct pipe_context *ctx,
731 struct pipe_resource *p_res,
732 unsigned level,
733 const struct pipe_box *box,
734 const void *data)
735 {
736 struct iris_context *ice = (void *) ctx;
737 struct iris_screen *screen = (void *) ctx->screen;
738 const struct intel_device_info *devinfo = screen->devinfo;
739
740 if (util_format_is_depth_or_stencil(p_res->format)) {
741 const struct util_format_unpack_description *unpack =
742 util_format_unpack_description(p_res->format);
743
744 float depth = 0.0;
745 uint8_t stencil = 0;
746
747 if (unpack->unpack_z_float)
748 util_format_unpack_z_float(p_res->format, &depth, data, 1);
749
750 if (unpack->unpack_s_8uint)
751 util_format_unpack_s_8uint(p_res->format, &stencil, data, 1);
752
753 clear_depth_stencil(ice, p_res, level, box, true, true, true,
754 depth, stencil);
755 } else {
756 union isl_color_value color;
757 struct iris_resource *res = (void *) p_res;
758 enum isl_format format = res->surf.format;
759
760 if (!isl_format_supports_rendering(devinfo, format)) {
761 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
762 // XXX: actually just get_copy_format_for_bpb from BLORP
763 // XXX: don't cut and paste this
764 switch (fmtl->bpb) {
765 case 8: format = ISL_FORMAT_R8_UINT; break;
766 case 16: format = ISL_FORMAT_R8G8_UINT; break;
767 case 24: format = ISL_FORMAT_R8G8B8_UINT; break;
768 case 32: format = ISL_FORMAT_R8G8B8A8_UINT; break;
769 case 48: format = ISL_FORMAT_R16G16B16_UINT; break;
770 case 64: format = ISL_FORMAT_R16G16B16A16_UINT; break;
771 case 96: format = ISL_FORMAT_R32G32B32_UINT; break;
772 case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break;
773 default:
774 unreachable("Unknown format bpb");
775 }
776
777 /* No aux surfaces for non-renderable surfaces */
778 assert(res->aux.usage == ISL_AUX_USAGE_NONE);
779 }
780
781 isl_color_value_unpack(&color, format, data);
782
783 clear_color(ice, p_res, level, box, true, format,
784 ISL_SWIZZLE_IDENTITY, color);
785 }
786 }
787
788 /**
789 * The pipe->clear_render_target() driver hook.
790 *
791 * This clears the given render target surface.
792 */
793 static void
iris_clear_render_target(struct pipe_context * ctx,struct pipe_surface * psurf,const union pipe_color_union * p_color,unsigned dst_x,unsigned dst_y,unsigned width,unsigned height,bool render_condition_enabled)794 iris_clear_render_target(struct pipe_context *ctx,
795 struct pipe_surface *psurf,
796 const union pipe_color_union *p_color,
797 unsigned dst_x, unsigned dst_y,
798 unsigned width, unsigned height,
799 bool render_condition_enabled)
800 {
801 struct iris_context *ice = (void *) ctx;
802 struct iris_surface *isurf = (void *) psurf;
803 struct pipe_box box = {
804 .x = dst_x,
805 .y = dst_y,
806 .z = psurf->u.tex.first_layer,
807 .width = width,
808 .height = height,
809 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
810 };
811
812 clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
813 render_condition_enabled,
814 isurf->view.format, isurf->view.swizzle,
815 convert_clear_color(psurf->format, p_color));
816 }
817
818 /**
819 * The pipe->clear_depth_stencil() driver hook.
820 *
821 * This clears the given depth/stencil surface.
822 */
823 static void
iris_clear_depth_stencil(struct pipe_context * ctx,struct pipe_surface * psurf,unsigned flags,double depth,unsigned stencil,unsigned dst_x,unsigned dst_y,unsigned width,unsigned height,bool render_condition_enabled)824 iris_clear_depth_stencil(struct pipe_context *ctx,
825 struct pipe_surface *psurf,
826 unsigned flags,
827 double depth,
828 unsigned stencil,
829 unsigned dst_x, unsigned dst_y,
830 unsigned width, unsigned height,
831 bool render_condition_enabled)
832 {
833 struct iris_context *ice = (void *) ctx;
834 struct pipe_box box = {
835 .x = dst_x,
836 .y = dst_y,
837 .z = psurf->u.tex.first_layer,
838 .width = width,
839 .height = height,
840 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
841 };
842
843 assert(util_format_is_depth_or_stencil(psurf->texture->format));
844
845 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box,
846 render_condition_enabled,
847 flags & PIPE_CLEAR_DEPTH, flags & PIPE_CLEAR_STENCIL,
848 depth, stencil);
849 }
850
851 void
iris_init_clear_functions(struct pipe_context * ctx)852 iris_init_clear_functions(struct pipe_context *ctx)
853 {
854 ctx->clear = iris_clear;
855 ctx->clear_texture = iris_clear_texture;
856 ctx->clear_render_target = iris_clear_render_target;
857 ctx->clear_depth_stencil = iris_clear_depth_stencil;
858 }
859