1 /*
2 * Copyright (c) 2021, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_render_cmdpar.h
24 //! \brief MHW command parameters
25 //! \details
26 //!
27
28 #ifndef __MHW_RENDER_CMDPAR_H__
29 #define __MHW_RENDER_CMDPAR_H__
30
31 #include "mhw_cmdpar.h"
32 #include "mhw_state_heap.h"
33
34 static constexpr uint32_t MHW_RENDER_ENGINE_SSH_SURFACES_PER_BT_MAX = 256;
35 static constexpr uint32_t MHW_RENDER_ENGINE_SAMPLERS_MAX = 16;
36 static constexpr uint32_t MHW_RENDER_ENGINE_SAMPLERS_AVS_MAX = 8;
37 static constexpr uint32_t MHW_RENDER_ENGINE_MEDIA_PALOAD_SIZE_MAX = 512;
38 static constexpr uint32_t MHW_RENDER_ENGINE_URB_SIZE_MAX = 2048;
39 static constexpr uint32_t MHW_RENDER_ENGINE_URB_ENTRIES_MAX = 128;
40 static constexpr uint32_t MHW_RENDER_ENGINE_INTERFACE_DESCRIPTOR_ENTRIES_MAX = 64;
41 static constexpr uint32_t MHW_RENDER_ENGINE_EU_INDEX_MAX = 12;
42 static constexpr uint32_t MHW_RENDER_ENGINE_SIZE_REGISTERS_PER_THREAD = 0x1800;
43 static constexpr uint32_t MHW_MAX_DEPENDENCY_COUNT = 8;
44
45 namespace mhw
46 {
47 namespace render
48 {
49 struct MHW_VFE_SCOREBOARD_DELTA
50 {
51 uint8_t x = 0;
52 uint8_t y = 0;
53 };
54
55 struct MHW_VFE_SCOREBOARD
56 {
57 uint8_t ScoreboardMask = 0;
58 uint8_t ScoreboardColor = 0;
59 bool ScoreboardType = false;
60 bool ScoreboardEnable = false;
61 MHW_VFE_SCOREBOARD_DELTA ScoreboardDelta[MHW_MAX_DEPENDENCY_COUNT] = {};
62 };
63
64 struct MHW_HEAPS_RESOURCE
65 {
66 PMOS_RESOURCE presInstructionBuffer = nullptr;
67 PMHW_INLINE_DATA_PARAMS inlineDataParamsBase = nullptr;
68 uint32_t inlineDataParamSize = 0;
69 };
70
71 enum MHW_VFE_SLICE_DISABLE
72 {
73 MHW_VFE_SLICE_ALL = 0,
74 MHW_VFE_SLICE0_SUBSLICE_ALL,
75 MHW_VFE_SLICE0_SUBSLICE0
76 };
77
78 struct MHW_WALKER_XY
79 {
80 uint16_t x = 0;
81 uint16_t y = 0;
82 };
83
84 enum MHW_WALKER_MODE
85 {
86 MHW_WALKER_MODE_NOT_SET = -1,
87 MHW_WALKER_MODE_DISABLED = 0,
88 MHW_WALKER_MODE_SINGLE = 1, // dual = 0, repel = 1
89 MHW_WALKER_MODE_DUAL = 2, // dual = 1, repel = 0)
90 MHW_WALKER_MODE_TRI = 3, // applies in BDW GT2 which has 1 slice and 3 sampler/VME per slice
91 MHW_WALKER_MODE_QUAD = 4, // applies in HSW GT3 which has 2 slices and 2 sampler/VME per slice
92 MHW_WALKER_MODE_HEX = 6, // applies in BDW GT2 which has 2 slices and 3 sampler/VME per slice
93 MHW_WALKER_MODE_OCT = 8 // may apply in future Gen media architectures
94 };
95
96 enum MHW_EMIT_LOCAL_MODE
97 {
98 MHW_EMIT_LOCAL_NONE = 0,
99 MHW_EMIT_LOCAL_X = 1,
100 MHW_EMIT_LOCAL_XY = 3,
101 MHW_EMIT_LOCAL_XYZ = 7
102 };
103
104 struct MHW_RENDER_ENGINE_CAPS
105 {
106 uint32_t dwMaxUnormSamplers = 0; // Max UNORM Sampler States supported
107 uint32_t dwMaxAVSSamplers = 0; // Max AVS Sampler States supported
108 uint32_t dwMaxBTIndex = 0; // Max Binding Table index per Binding Table
109 uint32_t dwMaxThreads = 0; // Max Threads supported
110 uint32_t dwMaxMediaPayloadSize = 0; // Max Media payload size
111 uint32_t dwMaxURBSize = 0; // Max URB Size
112 uint32_t dwMaxURBEntries = 0; // Max URB Entries
113 uint32_t dwMaxURBEntryAllocationSize = 0; // Max URB Entry Allocation Size
114 uint32_t dwMaxCURBEAllocationSize = 0;
115 uint32_t dwMaxInterfaceDescriptorEntries = 0; // Max Interface Descriptor Entries
116 uint32_t dwMaxSubslice = 0; // Max number of subslice
117 uint32_t dwMaxEUIndex = 0; // Max EU index (sometimes != number of EU)
118 uint32_t dwNumThreadsPerEU = 0; // Num threads per EU
119 uint32_t dwSizeRegistersPerThread = 0; // Size of all registers per thread (for ASM Debug)
120 };
121
122 struct MHW_RENDER_ENGINE_L3_CACHE_SETTINGS
123 {
124 uint32_t dwCntlReg = 0;
125 uint32_t dwCntlReg2 = 0;
126 uint32_t dwCntlReg3 = 0;
127 uint32_t dwSqcReg1 = 0;
128 uint32_t dwSqcReg4 = 0;
129 uint32_t dwLra1Reg = 0;
130 uint32_t dwTcCntlReg = 0;
131 uint32_t dwAllocReg = 0;
132 bool bUpdateDefault = 0;
133 };
134
135 struct MHW_RENDER_ENGINE_L3_CACHE_CONFIG
136 {
137 uint32_t dwL3CacheCntlReg_Register = 0;
138 uint32_t dwL3CacheCntlReg_Setting = 0;
139 uint32_t dwL3CacheCntlReg2_Register = 0;
140 uint32_t dwL3CacheCntlReg2_Setting = 0;
141 uint32_t dwL3CacheCntlReg3_Register = 0;
142 uint32_t dwL3CacheCntlReg3_Setting = 0;
143 uint32_t dwL3CacheSqcReg1_Register = 0;
144 uint32_t dwL3CacheSqcReg1_Setting = 0;
145 uint32_t dwL3CacheSqcReg4_Register = 0;
146 uint32_t dwL3CacheSqcReg4_Setting = 0;
147 uint32_t dwL3LRA1Reg_Register = 0;
148 uint32_t dwL3LRA1Reg_Setting = 0;
149 bool bL3CachingEnabled = false;
150 bool bL3LRA1Reset = false;
151 uint32_t dwRcsL3CacheTcCntlReg_Register = 0;
152 uint32_t dwL3CacheTcCntlReg_Setting = 0;
153 uint32_t dwRcsL3CacheAllocReg_Register = 0;
154 uint32_t dwL3CacheAllocReg_Setting = 0;
155 uint32_t dwCcs0L3CacheTcCntlReg_Register = 0;
156 uint32_t dwCcs0L3CacheAllocReg_Register = 0;
157
158 };
159
160 struct MHW_VFE_PARAMS
161 {
162 uint32_t dwDebugCounterControl = 0; // Debug Counter Control
163 uint32_t dwMaximumNumberofThreads = 0;
164 uint32_t dwNumberofURBEntries = 0;
165 uint32_t dwCURBEAllocationSize = 0;
166 uint32_t dwURBEntryAllocationSize = 0;
167 uint32_t dwPerThreadScratchSpace = 0;
168 uint32_t dwScratchSpaceBasePointer = 0;
169 MHW_VFE_SLICE_DISABLE eVfeSliceDisable = MHW_VFE_SLICE_ALL;
170 MHW_VFE_SCOREBOARD Scoreboard = {};
171 PMHW_KERNEL_STATE pKernelState = nullptr;
172 bool bFusedEuDispatch = 0;
173 uint32_t numOfWalkers = 0;
174 bool enableSingleSliceDispatchCcsMode = 0;
175 // Surface state offset of scratch space buffer.
176 uint32_t scratchStateOffset = 0;
177 };
178
_MHW_PAR_T(MEDIA_OBJECT)179 struct _MHW_PAR_T(MEDIA_OBJECT)
180 {
181 uint32_t dwInterfaceDescriptorOffset = 0;
182 uint32_t dwHalfSliceDestinationSelect = 0;
183 uint32_t dwSliceDestinationSelect = 0;
184 uint32_t dwIndirectLoadLength = 0;
185 uint32_t dwIndirectDataStartAddress = 0;
186 void* pInlineData = nullptr;
187 uint32_t dwInlineDataSize = 0;
188 bool bForceDestination = false;
189 MHW_VFE_SCOREBOARD VfeScoreboard = {};
190 };
191
_MHW_PAR_T(PIPE_MODE_SELECT)192 struct _MHW_PAR_T(PIPE_MODE_SELECT)
193 {
194 uint32_t dwInterfaceDescriptorOffset = 0;
195 uint32_t dwHalfSliceDestinationSelect = 0;
196 uint32_t dwSliceDestinationSelect = 0;
197 uint32_t dwIndirectLoadLength = 0;
198 uint32_t dwIndirectDataStartAddress = 0;
199 void* pInlineData = nullptr;
200 uint32_t dwInlineDataSize = 0;
201 bool bForceDestination = false;
202 MHW_VFE_SCOREBOARD VfeScoreboard = {};
203 };
204
_MHW_PAR_T(PIPELINE_SELECT)205 struct _MHW_PAR_T(PIPELINE_SELECT)
206 {
207 uint32_t pipelineSelection = 0;
208 bool gpGpuPipe = false;
209 };
210
_MHW_PAR_T(STATE_BASE_ADDRESS)211 struct _MHW_PAR_T(STATE_BASE_ADDRESS)
212 {
213 PMOS_RESOURCE presGeneralState = nullptr;
214 uint32_t dwGeneralStateSize = 0;
215 PMOS_RESOURCE presDynamicState = nullptr;
216 uint32_t dwDynamicStateSize = 0;
217 bool bDynamicStateRenderTarget = false;
218 PMOS_RESOURCE presIndirectObjectBuffer = nullptr;
219 uint32_t dwIndirectObjectBufferSize = 0;
220 PMOS_RESOURCE presInstructionBuffer = nullptr;
221 uint32_t dwInstructionBufferSize = 0;
222 uint32_t mocs4InstructionCache = 0;
223 uint32_t mocs4GeneralState = 0;
224 uint32_t mocs4DynamicState = 0;
225 uint32_t mocs4SurfaceState = 0;
226 uint32_t mocs4IndirectObjectBuffer = 0;
227 uint32_t mocs4StatelessDataport = 0;
228 uint32_t l1CacheConfig = 0;
229 bool addressDis = false;
230 };
231
_MHW_PAR_T(MEDIA_VFE_STATE)232 struct _MHW_PAR_T(MEDIA_VFE_STATE)
233 {
234 uint32_t dwDebugCounterControl = 0; // Debug Counter Control
235 uint32_t dwMaximumNumberofThreads = 0;
236 uint32_t dwNumberofURBEntries = 0;
237 uint32_t dwCURBEAllocationSize = 0;
238 uint32_t dwURBEntryAllocationSize = 0;
239 uint32_t dwPerThreadScratchSpace = 0;
240 uint32_t dwScratchSpaceBasePointer = 0;
241 MHW_VFE_SLICE_DISABLE eVfeSliceDisable = MHW_VFE_SLICE_ALL;
242 MHW_VFE_SCOREBOARD Scoreboard = {};
243 PMHW_KERNEL_STATE pKernelState = nullptr;
244 MHW_RENDER_ENGINE_CAPS* pHwCaps = nullptr;
245 };
246
_MHW_PAR_T(MEDIA_CURBE_LOAD)247 struct _MHW_PAR_T(MEDIA_CURBE_LOAD)
248 {
249 PMHW_KERNEL_STATE pKernelState = nullptr;
250 bool bOldInterface = false;
251 uint32_t dwCURBETotalDataLength = 0;
252 uint32_t dwCURBEDataStartAddress = 0;
253 };
254
_MHW_PAR_T(MEDIA_INTERFACE_DESCRIPTOR_LOAD)255 struct _MHW_PAR_T(MEDIA_INTERFACE_DESCRIPTOR_LOAD)
256 {
257 PMHW_KERNEL_STATE pKernelState = nullptr;
258 uint32_t dwNumKernelsLoaded = 0;
259 uint32_t dwIdIdx = 0;
260 uint32_t dwInterfaceDescriptorStartOffset = 0;
261 uint32_t dwInterfaceDescriptorLength = 0;
262 };
263
_MHW_PAR_T(MEDIA_OBJECT_WALKER)264 struct _MHW_PAR_T(MEDIA_OBJECT_WALKER)
265 {
266 uint16_t InterfaceDescriptorOffset = 0;
267 bool CmWalkerEnable = false;
268 uint16_t ColorCountMinusOne = 0;
269 uint16_t UseScoreboard = 0;
270 uint16_t ScoreboardMask = 0;
271 uint8_t MidLoopUnitX = 0;
272 uint8_t MidLoopUnitY = 0;
273 uint8_t MiddleLoopExtraSteps = 0;
274 uint32_t GroupIdLoopSelect = 0;
275 uint32_t InlineDataLength = 0;
276 uint8_t* pInlineData = nullptr ;
277 uint32_t dwLocalLoopExecCount = 0;
278 uint32_t dwGlobalLoopExecCount = 0;
279 MHW_WALKER_MODE WalkerMode = {};
280 MHW_WALKER_XY BlockResolution = {};
281 MHW_WALKER_XY LocalStart = {};
282 MHW_WALKER_XY LocalEnd = {};
283 MHW_WALKER_XY LocalOutLoopStride = {};
284 MHW_WALKER_XY LocalInnerLoopUnit = {};
285 MHW_WALKER_XY GlobalResolution = {};
286 MHW_WALKER_XY GlobalStart = {};
287 MHW_WALKER_XY GlobalOutlerLoopStride = {};
288 MHW_WALKER_XY GlobalInnerLoopUnit = {};
289 bool bAddMediaFlush = false;
290 bool bRequestSingleSlice = false;
291 uint32_t IndirectDataLength = 0;
292 uint32_t IndirectDataStartAddress = 0;
293 };
294
_MHW_PAR_T(GPGPU_WALKER)295 struct _MHW_PAR_T(GPGPU_WALKER)
296 {
297 uint8_t InterfaceDescriptorOffset = 0;
298 bool GpGpuEnable = false;
299 uint32_t ThreadWidth = 0;
300 uint32_t ThreadHeight = 0;
301 uint32_t ThreadDepth = 0;
302 uint32_t GroupWidth = 0;
303 uint32_t GroupHeight = 0;
304 uint32_t GroupDepth = 0;
305 uint32_t GroupStartingX = 0;
306 uint32_t GroupStartingY = 0;
307 uint32_t GroupStartingZ = 0;
308 uint32_t SLMSize = 0;
309 uint32_t IndirectDataLength = 0;
310 uint32_t IndirectDataStartAddress = 0;
311 uint32_t BindingTableID = 0;
312 };
313
_MHW_PAR_T(_3DSTATE_CHROMA_KEY)314 struct _MHW_PAR_T(_3DSTATE_CHROMA_KEY)
315 {
316 uint32_t dwIndex = 0; //!< Chroma Key Index
317 uint32_t dwLow = 0; //!< Chroma Key Low
318 uint32_t dwHigh = 0; //!< Chroma Key High
319 };
320
_MHW_PAR_T(PALETTE_ENTRY)321 struct _MHW_PAR_T(PALETTE_ENTRY)
322 {
323 int32_t iPaletteID = 0; //!< Palette ID
324 int32_t iNumEntries = 0; //!< Palette entries in use
325 void* pPaletteData = nullptr; //!< Palette data
326 };
327
_MHW_PAR_T(STATE_SIP)328 struct _MHW_PAR_T(STATE_SIP)
329 {
330 bool bSipKernel = false;
331 uint32_t dwSipBase = 0;
332 };
333
_MHW_PAR_T(GPGPU_CSR_BASE_ADDRESS)334 struct _MHW_PAR_T(GPGPU_CSR_BASE_ADDRESS)
335 {
336 };
337
_MHW_PAR_T(_3DSTATE_BINDING_TABLE_POOL_ALLOC)338 struct _MHW_PAR_T(_3DSTATE_BINDING_TABLE_POOL_ALLOC)
339 {
340 uint32_t mocs4SurfaceState = 0;
341 };
342
_MHW_PAR_T(CFE_STATE)343 struct _MHW_PAR_T(CFE_STATE)
344 {
345 uint32_t dwDebugCounterControl = 0; // Debug Counter Control
346 uint32_t dwMaximumNumberofThreads = 0;
347 uint32_t dwNumberofURBEntries = 0;
348 uint32_t dwCURBEAllocationSize = 0;
349 uint32_t dwURBEntryAllocationSize = 0;
350 uint32_t dwPerThreadScratchSpace = 0;
351 uint32_t dwScratchSpaceBasePointer = 0;
352 uint32_t ScratchSpaceBuffer = 0;
353 bool FusedEuDispatch = 0;
354 bool NumberOfWalkers = 0;
355 bool SingleSliceDispatchCcsMode = 0;
356 MHW_VFE_SLICE_DISABLE eVfeSliceDisable = MHW_VFE_SLICE_ALL;
357 MHW_VFE_SCOREBOARD Scoreboard = {};
358 PMHW_KERNEL_STATE pKernelState = nullptr;
359 };
360
_MHW_PAR_T(COMPUTE_WALKER)361 struct _MHW_PAR_T(COMPUTE_WALKER)
362 {
363 uint8_t InterfaceDescriptorOffset = 0;
364 bool GpGpuEnable = false;
365 uint32_t ThreadWidth = 0;
366 uint32_t ThreadHeight = 0;
367 uint32_t ThreadDepth = 0;
368 uint32_t GroupWidth = 0;
369 uint32_t GroupHeight = 0;
370 uint32_t GroupDepth = 0;
371 uint32_t GroupStartingX = 0;
372 uint32_t GroupStartingY = 0;
373 uint32_t GroupStartingZ = 0;
374 uint32_t SLMSize = 0;
375 uint32_t IndirectDataLength = 0;
376 uint32_t IndirectDataStartAddress = 0;
377 uint32_t BindingTableID = 0;
378 uint32_t dwMediaIdOffset = 0; //! Offset of the first Media Interface Descriptor (in DSH)
379 uint32_t iMediaId = 0; //! Media Interface Descriptor #
380 uint32_t dwKernelOffset = 0; //! Kernel offset (in ISH)
381 uint32_t dwSamplerOffset = 0; //! Sampler offset (in DSH)
382 uint32_t dwSamplerCount = 0; //! Sample count
383 uint32_t dwBindingTableOffset = 0; //! Binding table offset (in DSH)
384 uint32_t iCurbeOffset = 0; //! Curbe offset (in DSH)
385 uint32_t iCurbeLength = 0; //! Curbe lenght
386 bool bBarrierEnable = false; //! Enable Barrier
387 bool bGlobalBarrierEnable = false; //! Enable Global Barrier (SKL+)
388 uint32_t dwNumberofThreadsInGPGPUGroup = 0; //! Number of threads per group
389 uint32_t dwSharedLocalMemorySize = 0; //! Size of SharedLocalMemory (SLM)
390 int32_t forcePreferredSLMZero = 0; //! force preferredSLM value as 0
391 int32_t iCrsThdConDataRdLn = 0;
392 PMHW_STATE_HEAP pGeneralStateHeap = 0; //! General state heap in use
393 MemoryBlock *memoryBlock = nullptr; //! Memory block associated with the state heap
394 MOS_RESOURCE *postsyncResource = nullptr;
395 uint32_t resourceOffset = 0;
396 bool isEmitInlineParameter = false;
397 uint32_t inlineDataLength = 0;
398 uint8_t *inlineData = nullptr;
399 bool isGenerateLocalId = false;
400 MHW_EMIT_LOCAL_MODE emitLocal = MHW_EMIT_LOCAL_NONE;
401 uint32_t preferredSlmAllocationSize = 0;
402 _MHW_PAR_T(CFE_STATE) cfeState = {};
403 MHW_HEAPS_RESOURCE heapsResource = {};
404
405 };
406
_MHW_PAR_T(STATE_COMPUTE_MODE)407 struct _MHW_PAR_T(STATE_COMPUTE_MODE)
408 {
409 bool enableLargeGrf = false;
410 uint32_t forceEuThreadSchedulingMode = 0;
411 };
412
413 } // namespace render
414 } // namespace mhw
415
416 #endif // __MHW_RENDER_CMDPAR_H__
417