1 /**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 /**
30 * @file
31 *
32 * Abstract graphics pipe state objects.
33 *
34 * Basic notes:
35 * 1. Want compact representations, so we use bitfields.
36 * 2. Put bitfields before other (GLfloat) fields.
37 * 3. enum bitfields need to be at least one bit extra in size so the most
38 * significant bit is zero. MSVC treats enums as signed so if the high
39 * bit is set, the value will be interpreted as a negative number.
40 * That causes trouble in various places.
41 */
42
43
44 #ifndef PIPE_STATE_H
45 #define PIPE_STATE_H
46
47 #include "util/u_memory.h"
48
49 #include "util/compiler.h"
50 #include "p_defines.h"
51 #include "util/format/u_formats.h"
52 #include "util/box.h"
53
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
59 /**
60 * Implementation limits
61 */
62 #define PIPE_MAX_ATTRIBS 32
63 #define PIPE_MAX_CLIP_PLANES 8
64 #define PIPE_MAX_COLOR_BUFS 8
65 #define PIPE_MAX_CONSTANT_BUFFERS 32
66 #define PIPE_MAX_SAMPLERS 32
67 #define PIPE_MAX_SHADER_INPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */
68 #define PIPE_MAX_SHADER_OUTPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */
69 #define PIPE_MAX_SHADER_SAMPLER_VIEWS 128
70 #define PIPE_MAX_SHADER_BUFFERS 32
71 #define PIPE_MAX_SHADER_IMAGES 64
72 #define PIPE_MAX_TEXTURE_LEVELS 16
73 #define PIPE_MAX_SO_BUFFERS 4
74 #define PIPE_MAX_SO_OUTPUTS 128
75 #define PIPE_MAX_VIEWPORTS 16
76 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_COUNT 8
77 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT 2
78 #define PIPE_MAX_WINDOW_RECTANGLES 8
79 #define PIPE_MAX_SAMPLE_LOCATION_GRID_SIZE 4
80
81 #define PIPE_MAX_HW_ATOMIC_BUFFERS 32
82 #define PIPE_MAX_VERTEX_STREAMS 4
83
84 struct pipe_reference
85 {
86 int32_t count; /* atomic */
87 };
88
89
90
91 /**
92 * Primitive (point/line/tri) rasterization info
93 */
94 struct pipe_rasterizer_state
95 {
96 unsigned flatshade:1;
97 unsigned light_twoside:1;
98 unsigned clamp_vertex_color:1;
99 unsigned clamp_fragment_color:1;
100 unsigned front_ccw:1;
101 unsigned cull_face:2; /**< PIPE_FACE_x */
102 unsigned fill_front:2; /**< PIPE_POLYGON_MODE_x */
103 unsigned fill_back:2; /**< PIPE_POLYGON_MODE_x */
104 unsigned offset_point:1;
105 unsigned offset_line:1;
106 unsigned offset_tri:1;
107 unsigned scissor:1;
108 unsigned poly_smooth:1;
109 unsigned poly_stipple_enable:1;
110 unsigned point_smooth:1;
111 unsigned sprite_coord_mode:1; /**< PIPE_SPRITE_COORD_ */
112 unsigned point_quad_rasterization:1; /** points rasterized as quads or points */
113 unsigned point_line_tri_clip:1; /** large points/lines clipped as tris or points/lines */
114 unsigned point_size_per_vertex:1; /**< size computed in vertex shader */
115 unsigned multisample:1; /* XXX maybe more ms state in future */
116 unsigned no_ms_sample_mask_out:1;
117 unsigned force_persample_interp:1;
118 unsigned line_smooth:1;
119 unsigned line_stipple_enable:1;
120 unsigned line_last_pixel:1;
121 unsigned line_rectangular:1; /** lines rasterized as rectangles or parallelograms */
122 unsigned conservative_raster_mode:2; /**< PIPE_CONSERVATIVE_RASTER_x */
123
124 /**
125 * Use the first vertex of a primitive as the provoking vertex for
126 * flat shading.
127 */
128 unsigned flatshade_first:1;
129
130 unsigned half_pixel_center:1;
131 unsigned bottom_edge_rule:1;
132
133 /*
134 * Conservative rasterization subpixel precision bias in bits
135 */
136 unsigned subpixel_precision_x:4;
137 unsigned subpixel_precision_y:4;
138
139 /**
140 * When true, rasterization is disabled and no pixels are written.
141 * This only makes sense with the Stream Out functionality.
142 */
143 unsigned rasterizer_discard:1;
144
145 /**
146 * Exposed by PIPE_CAP_TILE_RASTER_ORDER. When true,
147 * tile_raster_order_increasing_* indicate the order that the rasterizer
148 * should render tiles, to meet the requirements of
149 * GL_MESA_tile_raster_order.
150 */
151 unsigned tile_raster_order_fixed:1;
152 unsigned tile_raster_order_increasing_x:1;
153 unsigned tile_raster_order_increasing_y:1;
154
155 /**
156 * When false, depth clipping is disabled and the depth value will be
157 * clamped later at the per-pixel level before depth testing.
158 * This depends on PIPE_CAP_DEPTH_CLIP_DISABLE.
159 *
160 * If PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE is unsupported, depth_clip_near
161 * is equal to depth_clip_far.
162 */
163 unsigned depth_clip_near:1;
164 unsigned depth_clip_far:1;
165
166 /**
167 * When true, depth clamp is enabled.
168 * If PIPE_CAP_DEPTH_CLAMP_ENABLE is unsupported, this is always the inverse
169 * of depth_clip_far.
170 */
171 unsigned depth_clamp:1;
172
173 /**
174 * When true clip space in the z axis goes from [0..1] (D3D). When false
175 * [-1, 1] (GL).
176 *
177 * NOTE: D3D will always use depth clamping.
178 */
179 unsigned clip_halfz:1;
180
181 /**
182 * When true do not scale offset_units and use same rules for unorm and
183 * float depth buffers (D3D9). When false use GL/D3D1X behaviour.
184 * This depends on PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.
185 */
186 unsigned offset_units_unscaled:1;
187
188 /**
189 * Depth values output from fragment shader may be outside 0..1.
190 * These have to be clamped for use with UNORM buffers.
191 * Vulkan can allow this with an extension,
192 * GL could with NV_depth_buffer_float, but GLES doesn't.
193 */
194 unsigned unclamped_fragment_depth_values:1;
195
196 /**
197 * Enable bits for clipping half-spaces.
198 * This applies to both user clip planes and shader clip distances.
199 * Note that if the bound shader exports any clip distances, these
200 * replace all user clip planes, and clip half-spaces enabled here
201 * but not written by the shader count as disabled.
202 */
203 unsigned clip_plane_enable:PIPE_MAX_CLIP_PLANES;
204
205 unsigned line_stipple_factor:8; /**< [1..256] actually */
206 unsigned line_stipple_pattern:16;
207
208 /**
209 * Replace the given TEXCOORD inputs with point coordinates, max. 8 inputs.
210 * If TEXCOORD (including PCOORD) are unsupported, replace GENERIC inputs
211 * instead. Max. 9 inputs: 8x GENERIC to emulate TEXCOORD, and 1x GENERIC
212 * to emulate PCOORD.
213 */
214 uint16_t sprite_coord_enable; /* 0-7: TEXCOORD/GENERIC, 8: PCOORD */
215
216 float line_width;
217 float point_size; /**< used when no per-vertex size */
218 float offset_units;
219 float offset_scale;
220 float offset_clamp;
221 float conservative_raster_dilate;
222 };
223
224
225 struct pipe_poly_stipple
226 {
227 unsigned stipple[32];
228 };
229
230
231 struct pipe_viewport_state
232 {
233 float scale[3];
234 float translate[3];
235 enum pipe_viewport_swizzle swizzle_x:8;
236 enum pipe_viewport_swizzle swizzle_y:8;
237 enum pipe_viewport_swizzle swizzle_z:8;
238 enum pipe_viewport_swizzle swizzle_w:8;
239 };
240
241
242 struct pipe_scissor_state
243 {
244 unsigned minx:16;
245 unsigned miny:16;
246 unsigned maxx:16;
247 unsigned maxy:16;
248 };
249
250
251 struct pipe_clip_state
252 {
253 float ucp[PIPE_MAX_CLIP_PLANES][4];
254 };
255
256 /**
257 * A single output for vertex transform feedback.
258 */
259 struct pipe_stream_output
260 {
261 unsigned register_index:6; /**< 0 to 63 (OUT index) */
262 unsigned start_component:2; /** 0 to 3 */
263 unsigned num_components:3; /** 1 to 4 */
264 unsigned output_buffer:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
265 unsigned dst_offset:16; /**< offset into the buffer in dwords */
266 unsigned stream:2; /**< 0 to 3 */
267 };
268
269 /**
270 * Stream output for vertex transform feedback.
271 */
272 struct pipe_stream_output_info
273 {
274 unsigned num_outputs;
275 /** stride for an entire vertex for each buffer in dwords */
276 uint16_t stride[PIPE_MAX_SO_BUFFERS];
277
278 /**
279 * Array of stream outputs, in the order they are to be written in.
280 * Selected components are tightly packed into the output buffer.
281 */
282 struct pipe_stream_output output[PIPE_MAX_SO_OUTPUTS];
283 };
284
285 /**
286 * The 'type' parameter identifies whether the shader state contains NIR, TGSI
287 * tokens, etc.
288 *
289 * TODO pipe_compute_state should probably get similar treatment to handle
290 * multiple IR's in a cleaner way..
291 *
292 * NOTE: since it is expected that the consumer will want to perform
293 * additional passes on the nir_shader, the driver takes ownership of
294 * the nir_shader. If gallium frontends need to hang on to the IR (for
295 * example, variant management), it should use nir_shader_clone().
296 */
297 struct pipe_shader_state
298 {
299 enum pipe_shader_ir type;
300 /* TODO move tokens into union. */
301 const struct tgsi_token *tokens;
302 union {
303 void *native;
304 void *nir;
305 } ir;
306 struct pipe_stream_output_info stream_output;
307 };
308
309 static inline void
pipe_shader_state_from_tgsi(struct pipe_shader_state * state,const struct tgsi_token * tokens)310 pipe_shader_state_from_tgsi(struct pipe_shader_state *state,
311 const struct tgsi_token *tokens)
312 {
313 state->type = PIPE_SHADER_IR_TGSI;
314 state->tokens = tokens;
315 memset(&state->stream_output, 0, sizeof(state->stream_output));
316 }
317
318 struct pipe_stencil_state
319 {
320 unsigned enabled:1; /**< stencil[0]: stencil enabled, stencil[1]: two-side enabled */
321 unsigned func:3; /**< PIPE_FUNC_x */
322 unsigned fail_op:3; /**< PIPE_STENCIL_OP_x */
323 unsigned zpass_op:3; /**< PIPE_STENCIL_OP_x */
324 unsigned zfail_op:3; /**< PIPE_STENCIL_OP_x */
325 unsigned valuemask:8;
326 unsigned writemask:8;
327 };
328
329
330 struct pipe_depth_stencil_alpha_state
331 {
332 struct pipe_stencil_state stencil[2]; /**< [0] = front, [1] = back */
333
334 unsigned alpha_enabled:1; /**< alpha test enabled? */
335 unsigned alpha_func:3; /**< PIPE_FUNC_x */
336
337 unsigned depth_enabled:1; /**< depth test enabled? */
338 unsigned depth_writemask:1; /**< allow depth buffer writes? */
339 unsigned depth_func:3; /**< depth test func (PIPE_FUNC_x) */
340 unsigned depth_bounds_test:1; /**< depth bounds test enabled? */
341
342 float alpha_ref_value; /**< reference value */
343 double depth_bounds_min; /**< minimum depth bound */
344 double depth_bounds_max; /**< maximum depth bound */
345 };
346
347
348 struct pipe_rt_blend_state
349 {
350 unsigned blend_enable:1;
351
352 unsigned rgb_func:3; /**< PIPE_BLEND_x */
353 unsigned rgb_src_factor:5; /**< PIPE_BLENDFACTOR_x */
354 unsigned rgb_dst_factor:5; /**< PIPE_BLENDFACTOR_x */
355
356 unsigned alpha_func:3; /**< PIPE_BLEND_x */
357 unsigned alpha_src_factor:5; /**< PIPE_BLENDFACTOR_x */
358 unsigned alpha_dst_factor:5; /**< PIPE_BLENDFACTOR_x */
359
360 unsigned colormask:4; /**< bitmask of PIPE_MASK_R/G/B/A */
361 };
362
363
364 struct pipe_blend_state
365 {
366 unsigned independent_blend_enable:1;
367 unsigned logicop_enable:1;
368 unsigned logicop_func:4; /**< PIPE_LOGICOP_x */
369 unsigned dither:1;
370 unsigned alpha_to_coverage:1;
371 unsigned alpha_to_coverage_dither:1;
372 unsigned alpha_to_one:1;
373 unsigned max_rt:3; /* index of max rt, Ie. # of cbufs minus 1 */
374 unsigned advanced_blend_func:4;
375 unsigned blend_coherent:1;
376 struct pipe_rt_blend_state rt[PIPE_MAX_COLOR_BUFS];
377 };
378
379
380 struct pipe_blend_color
381 {
382 float color[4];
383 };
384
385
386 struct pipe_stencil_ref
387 {
388 uint8_t ref_value[2];
389 };
390
391
392 /**
393 * Note that pipe_surfaces are "texture views for rendering"
394 * and so in the case of ARB_framebuffer_no_attachment there
395 * is no pipe_surface state available such that we may
396 * extract the number of samples and layers.
397 */
398 struct pipe_framebuffer_state
399 {
400 uint16_t width, height;
401 uint16_t layers; /**< Number of layers in a no-attachment framebuffer */
402 uint8_t samples; /**< Number of samples in a no-attachment framebuffer */
403
404 /** multiple color buffers for multiple render targets */
405 uint8_t nr_cbufs;
406 /** used for multiview */
407 uint8_t viewmask;
408 struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS];
409
410 struct pipe_surface *zsbuf; /**< Z/stencil buffer */
411
412 struct pipe_resource *resolve;
413 };
414
415
416 /**
417 * Texture sampler state.
418 */
419 struct pipe_sampler_state
420 {
421 unsigned wrap_s:3; /**< PIPE_TEX_WRAP_x */
422 unsigned wrap_t:3; /**< PIPE_TEX_WRAP_x */
423 unsigned wrap_r:3; /**< PIPE_TEX_WRAP_x */
424 unsigned min_img_filter:1; /**< PIPE_TEX_FILTER_x */
425 unsigned min_mip_filter:2; /**< PIPE_TEX_MIPFILTER_x */
426 unsigned mag_img_filter:1; /**< PIPE_TEX_FILTER_x */
427 unsigned compare_mode:1; /**< PIPE_TEX_COMPARE_x */
428 unsigned compare_func:3; /**< PIPE_FUNC_x */
429 unsigned unnormalized_coords:1; /**< Are coords normalized to [0,1]? */
430 unsigned max_anisotropy:5;
431 unsigned seamless_cube_map:1;
432 unsigned border_color_is_integer:1;
433 unsigned reduction_mode:2; /**< PIPE_TEX_REDUCTION_x */
434 unsigned pad:5; /**< take bits from this for new members */
435 float lod_bias; /**< LOD/lambda bias */
436 float min_lod, max_lod; /**< LOD clamp range, after bias */
437 union pipe_color_union border_color;
438 enum pipe_format border_color_format; /**< only with PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_FREEDRENO, must be last */
439 };
440
441 union pipe_surface_desc {
442 struct {
443 unsigned level;
444 unsigned first_layer:16;
445 unsigned last_layer:16;
446 } tex;
447 struct {
448 unsigned first_element;
449 unsigned last_element;
450 } buf;
451 };
452
453 /**
454 * A view into a texture that can be bound to a color render target /
455 * depth stencil attachment point.
456 */
457 struct pipe_surface
458 {
459 struct pipe_reference reference;
460 enum pipe_format format:16;
461 unsigned writable:1; /**< writable shader resource */
462 struct pipe_resource *texture; /**< resource into which this is a view */
463 struct pipe_context *context; /**< context this surface belongs to */
464
465 /* XXX width/height should be removed */
466 uint16_t width; /**< logical width in pixels */
467 uint16_t height; /**< logical height in pixels */
468
469 /**
470 * Number of samples for the surface. This will be 0 if rendering
471 * should use the resource's nr_samples, or another value if the resource
472 * is bound using FramebufferTexture2DMultisampleEXT.
473 */
474 unsigned nr_samples:8;
475
476 union pipe_surface_desc u;
477 };
478
479
480 /**
481 * A view into a texture that can be bound to a shader stage.
482 */
483 struct pipe_sampler_view
484 {
485 /* Put the refcount on its own cache line to prevent "False sharing". */
486 EXCLUSIVE_CACHELINE(struct pipe_reference reference);
487
488 enum pipe_format format:12; /**< typed PIPE_FORMAT_x */
489 unsigned astc_decode_format:2; /**< intermediate format used for ASTC textures */
490 bool is_tex2d_from_buf:1; /**< true if union is tex2d_from_buf */
491 enum pipe_texture_target target:5; /**< PIPE_TEXTURE_x */
492 unsigned swizzle_r:3; /**< PIPE_SWIZZLE_x for red component */
493 unsigned swizzle_g:3; /**< PIPE_SWIZZLE_x for green component */
494 unsigned swizzle_b:3; /**< PIPE_SWIZZLE_x for blue component */
495 unsigned swizzle_a:3; /**< PIPE_SWIZZLE_x for alpha component */
496 struct pipe_resource *texture; /**< texture into which this is a view */
497 struct pipe_context *context; /**< context this view belongs to */
498 union {
499 struct {
500 unsigned first_layer:16; /**< first layer to use for array textures */
501 unsigned last_layer:16; /**< last layer to use for array textures */
502 unsigned first_level:8; /**< first mipmap level to use */
503 unsigned last_level:8; /**< last mipmap level to use */
504 } tex;
505 struct {
506 unsigned offset; /**< offset in bytes */
507 unsigned size; /**< size of the readable sub-range in bytes */
508 } buf;
509 struct {
510 unsigned offset; /**< offset in pixels */
511 uint16_t row_stride; /**< size of the image row_stride in pixels */
512 uint16_t width; /**< width of image provided by application */
513 uint16_t height; /**< height of image provided by application */
514 } tex2d_from_buf; /**< used in cl extension cl_khr_image2d_from_buffer */
515 } u;
516 };
517
518
519 /**
520 * A description of a buffer or texture image that can be bound to a shader
521 * stage.
522 *
523 * Note that pipe_image_view::access comes from the frontend API, while
524 * shader_access comes from the shader and may contain additional information
525 * (ie. coherent/volatile may be set on shader_access but not on access)
526 */
527 struct pipe_image_view
528 {
529 struct pipe_resource *resource; /**< resource into which this is a view */
530 enum pipe_format format; /**< typed PIPE_FORMAT_x */
531 uint16_t access; /**< PIPE_IMAGE_ACCESS_x */
532 uint16_t shader_access; /**< PIPE_IMAGE_ACCESS_x */
533 union {
534 struct {
535 unsigned first_layer:16; /**< first layer to use for array textures */
536 unsigned last_layer:16; /**< last layer to use for array textures */
537 unsigned level:8; /**< mipmap level to use */
538 bool single_layer_view; /**< single layer view of array */
539 bool is_2d_view_of_3d;
540 } tex;
541 struct {
542 unsigned offset; /**< offset in bytes */
543 unsigned size; /**< size of the accessible sub-range in bytes */
544 } buf;
545 struct {
546 unsigned offset; /**< offset in pixels */
547 uint16_t row_stride; /**< size of the image row_stride in pixels */
548 uint16_t width; /**< width of image provided by application */
549 uint16_t height; /**< height of image provided by application */
550 } tex2d_from_buf; /**< used in cl extension cl_khr_image2d_from_buffer */
551 } u;
552 };
553
554
555 /**
556 * A memory object/resource such as a vertex buffer or texture.
557 */
558 struct pipe_resource
559 {
560 /* Put the refcount on its own cache line to prevent "False sharing". */
561 EXCLUSIVE_CACHELINE(struct pipe_reference reference);
562
563 uint32_t width0; /**< Used by both buffers and textures. */
564 uint16_t height0; /* Textures: The maximum height/depth/array_size is 16k. */
565 uint16_t depth0;
566 uint16_t array_size;
567
568 enum pipe_format format:16; /**< PIPE_FORMAT_x */
569 enum pipe_texture_target target:8; /**< PIPE_TEXTURE_x */
570 uint8_t last_level; /**< Index of last mipmap level present/defined */
571
572 /** Number of samples determining quality, driving rasterizer, shading,
573 * and framebuffer.
574 */
575 uint8_t nr_samples;
576
577 /** Multiple samples within a pixel can have the same value.
578 * nr_storage_samples determines how many slots for different values
579 * there are per pixel. Only color buffers can set this lower than
580 * nr_samples.
581 */
582 uint8_t nr_storage_samples;
583
584 uint8_t nr_sparse_levels; /**< Mipmap levels support partial resident */
585
586 unsigned compression_rate:4; /**< Fixed-rate compresion bitrate if any */
587
588 enum pipe_resource_usage usage:4;
589 uint32_t bind; /**< bitmask of PIPE_BIND_x */
590 uint32_t flags; /**< bitmask of PIPE_RESOURCE_FLAG_x */
591
592 /**
593 * For planar images, ie. YUV EGLImage external, etc, pointer to the
594 * next plane.
595 */
596 struct pipe_resource *next;
597 /* The screen pointer should be last for optimal structure packing.
598 * This pointer cannot be casted directly to a driver's screen. Use
599 * screen::get_driver_pipe_screen instead if it's non-NULL.
600 */
601 struct pipe_screen *screen; /**< screen that this texture belongs to */
602 };
603
604 /**
605 * Opaque object used for separate resource/memory allocations.
606 */
607 struct pipe_memory_allocation;
608
609 /**
610 * Transfer object. For data transfer to/from a resource.
611 */
612 struct pipe_transfer
613 {
614 struct pipe_resource *resource; /**< resource to transfer to/from */
615 enum pipe_map_flags usage:24;
616 unsigned level:8; /**< texture mipmap level */
617 struct pipe_box box; /**< region of the resource to access */
618 unsigned stride; /**< row stride in bytes */
619 uintptr_t layer_stride; /**< image/layer stride in bytes */
620
621 /* Offset into a driver-internal staging buffer to make use of unused
622 * padding in this structure.
623 */
624 unsigned offset;
625 };
626
627
628 /**
629 * A vertex buffer. Typically, all the vertex data/attributes for
630 * drawing something will be in one buffer. But it's also possible, for
631 * example, to put colors in one buffer and texcoords in another.
632 */
633 struct pipe_vertex_buffer
634 {
635 bool is_user_buffer;
636 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */
637
638 union {
639 struct pipe_resource *resource; /**< the actual buffer */
640 const void *user; /**< pointer to a user buffer */
641 } buffer;
642 };
643
644
645 /**
646 * A constant buffer. A subrange of an existing buffer can be set
647 * as a constant buffer.
648 */
649 struct pipe_constant_buffer
650 {
651 struct pipe_resource *buffer; /**< the actual buffer */
652 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */
653 unsigned buffer_size; /**< how much data can be read in shader */
654 const void *user_buffer; /**< pointer to a user buffer if buffer == NULL */
655 };
656
657
658 /**
659 * An untyped shader buffer supporting loads, stores, and atomics.
660 */
661 struct pipe_shader_buffer {
662 struct pipe_resource *buffer; /**< the actual buffer */
663 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */
664 unsigned buffer_size; /**< how much data can be read in shader */
665 };
666
667
668 /**
669 * A stream output target. The structure specifies the range vertices can
670 * be written to.
671 *
672 * In addition to that, the structure should internally maintain the offset
673 * into the buffer, which should be incremented everytime something is written
674 * (appended) to it. The internal offset is buffer_offset + how many bytes
675 * have been written. The internal offset can be stored on the device
676 * and the CPU actually doesn't have to query it.
677 *
678 * Note that the buffer_size variable is actually specifying the available
679 * space in the buffer, not the size of the attached buffer.
680 * In other words in majority of cases buffer_size would simply be
681 * 'buffer->width0 - buffer_offset', so buffer_size refers to the size
682 * of the buffer left, after accounting for buffer offset, for stream output
683 * to write to.
684 *
685 * Use PIPE_QUERY_SO_STATISTICS to know how many primitives have
686 * actually been written.
687 */
688 struct pipe_stream_output_target
689 {
690 struct pipe_reference reference;
691 struct pipe_resource *buffer; /**< the output buffer */
692 struct pipe_context *context; /**< context this SO target belongs to */
693
694 unsigned buffer_offset; /**< offset where data should be written, in bytes */
695 unsigned buffer_size; /**< how much data is allowed to be written */
696 };
697
698
699 /**
700 * Information to describe a vertex attribute (position, color, etc)
701 */
702 struct pipe_vertex_element
703 {
704 /** Offset of this attribute, in bytes, from the start of the vertex */
705 uint16_t src_offset;
706
707 /** Which vertex_buffer (as given to pipe->set_vertex_buffer()) does
708 * this attribute live in?
709 */
710 uint8_t vertex_buffer_index:7;
711
712 /**
713 * Whether this element refers to a dual-slot vertex shader input.
714 * The purpose of this field is to do dual-slot lowering when the CSO is
715 * created instead of during every state change.
716 *
717 * It's lowered by util_lower_uint64_vertex_elements.
718 */
719 bool dual_slot:1;
720
721 /**
722 * This has only 8 bits because all vertex formats should be <= 255.
723 */
724 uint8_t src_format; /* low 8 bits of enum pipe_format. */
725
726 /**< stride to same attrib in next vertex, in bytes */
727 uint32_t src_stride; /* technically only uint16_t, expanded for struct padding */
728
729 /** Instance data rate divisor. 0 means this is per-vertex data,
730 * n means per-instance data used for n consecutive instances (n > 0).
731 */
732 unsigned instance_divisor;
733 };
734
735 /**
736 * Opaque refcounted constant state object encapsulating a vertex buffer,
737 * index buffer, and vertex elements. Used by display lists to bind those
738 * states and pass buffer references quickly.
739 *
740 * The state contains 1 index buffer, 0 or 1 vertex buffer, and 0 or more
741 * vertex elements.
742 *
743 * Constraints on the buffers to get the fastest codepath:
744 * - All buffer contents are considered immutable and read-only after
745 * initialization. This implies the following things.
746 * - No place is required to track whether these buffers are busy.
747 * - All CPU mappings of these buffers can be forced to UNSYNCHRONIZED by
748 * both drivers and common code unconditionally.
749 * - Buffer invalidation can be skipped by both drivers and common code
750 * unconditionally.
751 */
752 struct pipe_vertex_state {
753 struct pipe_reference reference;
754 struct pipe_screen *screen;
755
756 /* The following structure is used as a key for util_vertex_state_cache
757 * to deduplicate identical state objects and thus enable more
758 * opportunities for draw merging.
759 */
760 struct {
761 struct pipe_resource *indexbuf;
762 struct pipe_vertex_buffer vbuffer;
763 unsigned num_elements;
764 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
765 uint32_t full_velem_mask;
766 } input;
767 };
768
769 struct pipe_draw_indirect_info
770 {
771 unsigned offset; /**< must be 4 byte aligned */
772 unsigned stride; /**< must be 4 byte aligned */
773 unsigned draw_count; /**< number of indirect draws */
774 unsigned indirect_draw_count_offset; /**< must be 4 byte aligned */
775
776 /* Indirect draw parameters resource is laid out as follows:
777 *
778 * if using indexed drawing:
779 * struct {
780 * uint32_t count;
781 * uint32_t instance_count;
782 * uint32_t start;
783 * int32_t index_bias;
784 * uint32_t start_instance;
785 * };
786 * otherwise:
787 * struct {
788 * uint32_t count;
789 * uint32_t instance_count;
790 * uint32_t start;
791 * uint32_t start_instance;
792 * };
793 *
794 * If NULL, count_from_stream_output != NULL.
795 */
796 struct pipe_resource *buffer;
797
798 /* Indirect draw count resource: If not NULL, contains a 32-bit value which
799 * is to be used as the real draw_count.
800 */
801 struct pipe_resource *indirect_draw_count;
802
803 /**
804 * Stream output target. If not NULL, it's used to provide the 'count'
805 * parameter based on the number vertices captured by the stream output
806 * stage. (or generally, based on the number of bytes captured)
807 *
808 * Only 'mode', 'start_instance', and 'instance_count' are taken into
809 * account, all the other variables from pipe_draw_info are ignored.
810 *
811 * 'start' is implicitly 0 and 'count' is set as discussed above.
812 * The draw command is non-indexed.
813 *
814 * Note that this only provides the count. The vertex buffers must
815 * be set via set_vertex_buffers manually.
816 */
817 struct pipe_stream_output_target *count_from_stream_output;
818 };
819
820 struct pipe_draw_start_count_bias {
821 unsigned start;
822 unsigned count;
823 int index_bias; /**< a bias to be added to each index */
824 };
825
826 /**
827 * Draw vertex state description. It's translated to pipe_draw_info as follows:
828 * - mode comes from this structure
829 * - index_size is 4
830 * - instance_count is 1
831 * - index.resource comes from pipe_vertex_state
832 * - everything else is 0
833 */
834 struct pipe_draw_vertex_state_info {
835 #if defined(__GNUC__)
836 /* sizeof(mode) == 1 because it's a packed enum. */
837 enum mesa_prim mode; /**< the mode of the primitive */
838 #else
839 /* sizeof(mode) == 1 is required by draw merging in u_threaded_context. */
840 uint8_t mode; /**< the mode of the primitive */
841 #endif
842 bool take_vertex_state_ownership; /**< for skipping reference counting */
843 };
844
845 /**
846 * Information to describe a draw_vbo call.
847 */
848 struct pipe_draw_info
849 {
850 #if defined(__GNUC__)
851 /* sizeof(mode) == 1 because it's a packed enum. */
852 enum mesa_prim mode; /**< the mode of the primitive */
853 #else
854 /* sizeof(mode) == 1 is required by draw merging in u_threaded_context. */
855 uint8_t mode; /**< the mode of the primitive */
856 #endif
857 uint8_t index_size; /**< if 0, the draw is not indexed. */
858 uint8_t view_mask; /**< mask of multiviews for this draw */
859 bool primitive_restart:1;
860 bool has_user_indices:1; /**< if true, use index.user_buffer */
861 bool index_bounds_valid:1; /**< whether min_index and max_index are valid;
862 they're always invalid if index_size == 0 */
863 bool increment_draw_id:1; /**< whether drawid increments for direct draws */
864 bool take_index_buffer_ownership:1; /**< callee inherits caller's refcount
865 (no need to reference indexbuf, but still needs to unreference it) */
866 bool index_bias_varies:1; /**< true if index_bias varies between draws */
867 bool was_line_loop:1; /**< true if mesa_prim was LINE_LOOP before translation */
868 uint8_t _pad:1;
869
870 unsigned start_instance; /**< first instance id */
871 unsigned instance_count; /**< number of instances */
872
873 /**
874 * Primitive restart enable/index (only applies to indexed drawing)
875 */
876 unsigned restart_index;
877
878 /* Pointers must be placed appropriately for optimal structure packing on
879 * 64-bit CPUs.
880 */
881
882 /**
883 * An index buffer. When an index buffer is bound, all indices to vertices
884 * will be looked up from the buffer.
885 *
886 * If has_user_indices, use index.user, else use index.resource.
887 */
888 union {
889 struct pipe_resource *resource; /**< real buffer */
890 const void *user; /**< pointer to a user buffer */
891 } index;
892
893 /* These must be last for better packing in u_threaded_context. */
894 unsigned min_index; /**< the min index */
895 unsigned max_index; /**< the max index */
896 };
897
898
899 /**
900 * Information to describe a blit call.
901 */
902 struct pipe_blit_info
903 {
904 struct {
905 struct pipe_resource *resource;
906 unsigned level;
907 struct pipe_box box; /**< negative width, height only legal for src */
908 /* For pipe_surface-like format casting: */
909 enum pipe_format format; /**< must be supported for sampling (src)
910 or rendering (dst), ZS is always supported */
911 } dst, src;
912
913 unsigned mask; /**< bitmask of PIPE_MASK_R/G/B/A/Z/S */
914 unsigned filter; /**< PIPE_TEX_FILTER_* */
915 uint8_t dst_sample; /**< if non-zero, set sample_mask to (1 << (dst_sample - 1)) */
916 bool sample0_only;
917 bool scissor_enable;
918 struct pipe_scissor_state scissor;
919
920 /* Window rectangles can either be inclusive or exclusive. */
921 bool window_rectangle_include;
922 unsigned num_window_rectangles;
923 struct pipe_scissor_state window_rectangles[PIPE_MAX_WINDOW_RECTANGLES];
924
925 bool render_condition_enable; /**< whether the blit should honor the
926 current render condition */
927 bool alpha_blend; /* dst.rgb = src.rgb * src.a + dst.rgb * (1 - src.a) */
928 };
929
930 /**
931 * Information to describe a launch_grid call.
932 */
933 struct pipe_grid_info
934 {
935 /**
936 * For drivers that use PIPE_SHADER_IR_NATIVE as their prefered IR, this
937 * value will be the index of the kernel in the opencl.kernels metadata
938 * list.
939 */
940 uint32_t pc;
941
942 /**
943 * Will be used to initialize the INPUT resource, and it should point to a
944 * buffer of at least pipe_compute_state::req_input_mem bytes.
945 */
946 const void *input;
947
948 /**
949 * Variable shared memory used by this invocation.
950 *
951 * This comes on top of shader declared shared memory.
952 */
953 uint32_t variable_shared_mem;
954
955 /**
956 * Grid number of dimensions, 1-3, e.g. the work_dim parameter passed to
957 * clEnqueueNDRangeKernel. Note block[] and grid[] must be padded with
958 * 1 for non-used dimensions.
959 */
960 uint work_dim;
961
962 /**
963 * Determine the layout of the working block (in thread units) to be used.
964 */
965 uint block[3];
966
967 /**
968 * last_block allows disabling threads at the farthermost grid boundary.
969 * Full blocks as specified by "block" are launched, but the threads
970 * outside of "last_block" dimensions are disabled.
971 *
972 * If a block touches the grid boundary in the i-th axis, threads with
973 * THREAD_ID[i] >= last_block[i] are disabled.
974 *
975 * If last_block[i] is 0, it has the same behavior as last_block[i] = block[i],
976 * meaning no effect.
977 *
978 * It's equivalent to doing this at the beginning of the compute shader:
979 *
980 * for (i = 0; i < 3; i++) {
981 * if (block_id[i] == grid[i] - 1 &&
982 * last_block[i] && thread_id[i] >= last_block[i])
983 * return;
984 * }
985 */
986 uint last_block[3];
987
988 /**
989 * Determine the layout of the grid (in block units) to be used.
990 */
991 uint grid[3];
992
993 /**
994 * Base offsets to launch grids from
995 */
996 uint grid_base[3];
997
998 /* Indirect compute parameters resource: If not NULL, block sizes are taken
999 * from this buffer instead, which is laid out as follows:
1000 *
1001 * struct {
1002 * uint32_t num_blocks_x;
1003 * uint32_t num_blocks_y;
1004 * uint32_t num_blocks_z;
1005 * };
1006 */
1007 struct pipe_resource *indirect;
1008 unsigned indirect_offset; /**< must be 4 byte aligned */
1009 unsigned indirect_stride;
1010 /* draw related members are for task/mesh shaders */
1011 unsigned draw_count;
1012 unsigned indirect_draw_count_offset;
1013 struct pipe_resource *indirect_draw_count;
1014 };
1015
1016 /**
1017 * Encapsulates all info about a tensor. Only types supported are INT8 and UINT8.
1018 */
1019 struct pipe_tensor {
1020 /**
1021 * Memory-backing for this tensor (use pipe_buffer_*).
1022 */
1023 struct pipe_resource *resource;
1024 /**
1025 * Index of this tensor in the subgraph that contains it.
1026 */
1027 unsigned index;
1028 /**
1029 * Dimensions of this tensor.
1030 */
1031 unsigned dims[4];
1032 /**
1033 * Scale used to quantize this tensor. Only per-tensor quantization is supported.
1034 */
1035 float scale;
1036 /**
1037 * Zero-point used to quantize this tensor.
1038 */
1039 int zero_point;
1040 /**
1041 * Whether the tensor contains data in INT8 or UINT8 format.
1042 */
1043 bool is_signed;
1044 };
1045
1046 /**
1047 * Type of a pipe_ml_operation.
1048 */
1049 enum pipe_ml_operation_type {
1050 PIPE_ML_OPERATION_TYPE_ADD,
1051 PIPE_ML_OPERATION_TYPE_CONVOLUTION,
1052 PIPE_ML_OPERATION_TYPE_POOLING,
1053 };
1054
1055 /**
1056 * Information about a single operation inside a ML subgraph.
1057 */
1058 struct pipe_ml_operation
1059 {
1060 /**
1061 * Type of operation.
1062 */
1063 enum pipe_ml_operation_type type;
1064
1065 /**
1066 * Tensor used as input.
1067 */
1068 struct pipe_tensor *input_tensor;
1069
1070 /**
1071 * Tensor used as output.
1072 */
1073 struct pipe_tensor *output_tensor;
1074
1075 union {
1076 struct {
1077 /**
1078 * For convolutions, tensor containing the weights.
1079 */
1080 struct pipe_tensor *weight_tensor;
1081 /**
1082 * For convolutions, tensor containing the biases.
1083 */
1084 struct pipe_tensor *bias_tensor;
1085
1086 /**
1087 * Stride used to access the input tensor on the x axis.
1088 */
1089 unsigned stride_x;
1090
1091 /**
1092 * Stride used to access the input tensor on the x axis.
1093 */
1094 unsigned stride_y;
1095
1096 /**
1097 * Whether to use padding of type same when accessing the input tensor.
1098 */
1099 bool padding_same;
1100
1101 /**
1102 * Whether this is a pointwise (1x1 kernels) convolution.
1103 */
1104 bool pointwise;
1105
1106 /**
1107 * Whether this is a depthwise convolution.
1108 */
1109 bool depthwise;
1110 } conv;
1111 struct {
1112 /**
1113 * Stride used to access the input tensor on the x axis.
1114 */
1115 unsigned stride_x;
1116
1117 /**
1118 * Stride used to access the input tensor on the x axis.
1119 */
1120 unsigned stride_y;
1121
1122 /**
1123 * Width of the area used for pooling.
1124 */
1125 unsigned filter_width;
1126
1127 /**
1128 * Height of the area used for pooling.
1129 */
1130 unsigned filter_height;
1131
1132 /**
1133 * Whether to use padding of type same when accessing the input tensor.
1134 */
1135 bool padding_same;
1136 } pooling;
1137 struct {
1138 /**
1139 * Additional input tensor, to be added to the other one.
1140 */
1141 struct pipe_tensor *input_tensor;
1142 } add;
1143 };
1144 };
1145
1146 /**
1147 * Subgraph that drivers can subclass to keep the output of the subgraph
1148 * compilation process.
1149 */
1150 struct pipe_ml_subgraph
1151 {
1152 /**
1153 * pipe_context that owns this subgraph.
1154 */
1155 struct pipe_context *context;
1156 };
1157
1158 /**
1159 * Structure used as a header for serialized compute programs.
1160 */
1161 struct pipe_binary_program_header
1162 {
1163 uint32_t num_bytes; /**< Number of bytes in the LLVM bytecode program. */
1164 char blob[];
1165 };
1166
1167 struct pipe_compute_state
1168 {
1169 enum pipe_shader_ir ir_type; /**< IR type contained in prog. */
1170 const void *prog; /**< Compute program to be executed. */
1171 unsigned static_shared_mem; /**< equal to info.shared_size, used for shaders passed as TGSI */
1172 unsigned req_input_mem; /**< Required size of the INPUT resource. */
1173 };
1174
1175 struct pipe_compute_state_object_info
1176 {
1177 /**
1178 * Max number of threads per block supported for the given cso.
1179 */
1180 unsigned max_threads;
1181
1182 /**
1183 * Which multiple should the block size be of for best performance.
1184 *
1185 * E.g. for 8 a block with n * 8 threads would result in optimal utilization
1186 * of the hardware.
1187 */
1188 unsigned preferred_simd_size;
1189
1190 /**
1191 * Bitmask of supported SIMD sizes.
1192 */
1193 unsigned simd_sizes;
1194
1195 /**
1196 * How much private memory does this CSO require per thread (a.k.a. NIR scratch memory).
1197 */
1198 unsigned private_memory;
1199 };
1200
1201 /**
1202 * Structure that contains a callback for device reset messages from the driver
1203 * back to the gallium frontend.
1204 *
1205 * The callback must not be called from driver-created threads.
1206 */
1207 struct pipe_device_reset_callback
1208 {
1209 /**
1210 * Callback for the driver to report when a device reset is detected.
1211 *
1212 * \param data user-supplied data pointer
1213 * \param status PIPE_*_RESET
1214 */
1215 void (*reset)(void *data, enum pipe_reset_status status);
1216
1217 void *data;
1218 };
1219
1220 /**
1221 * Information about memory usage. All sizes are in kilobytes.
1222 */
1223 struct pipe_memory_info
1224 {
1225 unsigned total_device_memory; /**< size of device memory, e.g. VRAM */
1226 unsigned avail_device_memory; /**< free device memory at the moment */
1227 unsigned total_staging_memory; /**< size of staging memory, e.g. GART */
1228 unsigned avail_staging_memory; /**< free staging memory at the moment */
1229 unsigned device_memory_evicted; /**< size of memory evicted (monotonic counter) */
1230 unsigned nr_device_memory_evictions; /**< # of evictions (monotonic counter) */
1231 };
1232
1233 /**
1234 * Structure that contains information about external memory
1235 */
1236 struct pipe_memory_object
1237 {
1238 bool dedicated;
1239 };
1240
1241 #ifdef __cplusplus
1242 }
1243 #endif
1244
1245 #endif
1246