1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 */
6
7 #ifndef __ISYS_IRQ_PRIVATE_H__
8 #define __ISYS_IRQ_PRIVATE_H__
9
10 #include "isys_irq_global.h"
11 #include "isys_irq_local.h"
12
13
14 /* -------------------------------------------------------+
15 | Native command interface (NCI) |
16 + -------------------------------------------------------*/
17
18 /**
19 * @brief Get the isys irq status.
20 * Refer to "isys_irq.h" for details.
21 */
isys_irqc_state_get(const isys_irq_ID_t isys_irqc_id,isys_irqc_state_t * state)22 void isys_irqc_state_get(
23 const isys_irq_ID_t isys_irqc_id,
24 isys_irqc_state_t *state)
25 {
26 state->edge = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_EDGE_REG_IDX);
27 state->mask = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX);
28 state->status = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_STATUS_REG_IDX);
29 state->enable = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX);
30 state->level_no = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_LEVEL_NO_REG_IDX);
31 /*
32 ** Invalid to read/load from write-only register 'clear'
33 ** state->clear = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX);
34 */
35 }
36
37 /**
38 * @brief Dump the isys irq status.
39 * Refer to "isys_irq.h" for details.
40 */
isys_irqc_state_dump(const isys_irq_ID_t isys_irqc_id,const isys_irqc_state_t * state)41 void isys_irqc_state_dump(
42 const isys_irq_ID_t isys_irqc_id,
43 const isys_irqc_state_t *state)
44 {
45 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
46 "isys irq controller id %d\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n",
47 isys_irqc_id,
48 state->status, state->edge, state->mask, state->enable, state->level_no);
49 }
50
51 /* end of NCI */
52
53 /* -------------------------------------------------------+
54 | Device level interface (DLI) |
55 + -------------------------------------------------------*/
56
57 /* Support functions */
isys_irqc_reg_store(const isys_irq_ID_t isys_irqc_id,const unsigned int reg_idx,const hrt_data value)58 void isys_irqc_reg_store(
59 const isys_irq_ID_t isys_irqc_id,
60 const unsigned int reg_idx,
61 const hrt_data value)
62 {
63 unsigned int reg_addr;
64
65 assert(isys_irqc_id < N_ISYS_IRQ_ID);
66 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);
67
68 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
69 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
70 "isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value);
71
72 ia_css_device_store_uint32(reg_addr, value);
73 }
74
isys_irqc_reg_load(const isys_irq_ID_t isys_irqc_id,const unsigned int reg_idx)75 hrt_data isys_irqc_reg_load(
76 const isys_irq_ID_t isys_irqc_id,
77 const unsigned int reg_idx)
78 {
79 unsigned int reg_addr;
80 hrt_data value;
81
82 assert(isys_irqc_id < N_ISYS_IRQ_ID);
83 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);
84
85 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
86 value = ia_css_device_load_uint32(reg_addr);
87 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
88 "isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value);
89
90 return value;
91 }
92
93 /* end of DLI */
94
95
96 #endif /* __ISYS_IRQ_PRIVATE_H__ */
97