1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2024 Intel Corporation
5 */
6 #include "iwl-trans.h"
7 #include "iwl-prph.h"
8 #include "iwl-context-info.h"
9 #include "iwl-context-info-gen3.h"
10 #include "internal.h"
11 #include "fw/dbg.h"
12
13 #define FW_RESET_TIMEOUT (HZ / 5)
14
15 /*
16 * Start up NIC's basic functionality after it has been reset
17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
18 * NOTE: This does not load uCode nor start the embedded processor
19 */
iwl_pcie_gen2_apm_init(struct iwl_trans * trans)20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
21 {
22 int ret = 0;
23
24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
25
26 /*
27 * Use "set_bit" below rather than "write", to preserve any hardware
28 * bits already set by default after reset.
29 */
30
31 /*
32 * Disable L0s without affecting L1;
33 * don't wait for ICH L0s (ICH bug W/A)
34 */
35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
37
38 /* Set FH wait threshold to maximum (HW error during stress W/A) */
39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
40
41 /*
42 * Enable HAP INTA (interrupt from management bus) to
43 * wake device's PCI Express link L1a -> L0s
44 */
45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
46 CSR_HW_IF_CONFIG_REG_HAP_WAKE);
47
48 iwl_pcie_apm_config(trans);
49
50 ret = iwl_finish_nic_init(trans);
51 if (ret)
52 return ret;
53
54 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
55
56 return 0;
57 }
58
iwl_pcie_gen2_apm_stop(struct iwl_trans * trans,bool op_mode_leave)59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
60 {
61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
62
63 if (op_mode_leave) {
64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
65 iwl_pcie_gen2_apm_init(trans);
66
67 /* inform ME that we are leaving */
68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
69 CSR_RESET_LINK_PWR_MGMT_DISABLED);
70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
71 CSR_HW_IF_CONFIG_REG_WAKE_ME |
72 CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
73 mdelay(1);
74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
75 CSR_RESET_LINK_PWR_MGMT_DISABLED);
76 mdelay(5);
77 }
78
79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
80
81 /* Stop device's DMA activity */
82 iwl_pcie_apm_stop_master(trans);
83
84 iwl_trans_sw_reset(trans, false);
85
86 /*
87 * Clear "initialization complete" bit to move adapter from
88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
89 */
90 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
91 iwl_clear_bit(trans, CSR_GP_CNTRL,
92 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
93 else
94 iwl_clear_bit(trans, CSR_GP_CNTRL,
95 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
96 }
97
iwl_trans_pcie_fw_reset_handshake(struct iwl_trans * trans)98 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
99 {
100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 int ret;
102
103 trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
104
105 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
106 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
107 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
108 else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
109 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
110 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
111 else
112 iwl_write32(trans, CSR_DOORBELL_VECTOR,
113 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
114
115 /* wait 200ms */
116 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
117 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
118 FW_RESET_TIMEOUT);
119 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
120 u32 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
121
122 IWL_ERR(trans,
123 "timeout waiting for FW reset ACK (inta_hw=0x%x)\n",
124 inta_hw);
125
126 if (!(inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE)) {
127 struct iwl_fw_error_dump_mode mode = {
128 .type = IWL_ERR_TYPE_RESET_HS_TIMEOUT,
129 .context = IWL_ERR_CONTEXT_FROM_OPMODE,
130 };
131 iwl_op_mode_nic_error(trans->op_mode,
132 IWL_ERR_TYPE_RESET_HS_TIMEOUT);
133 iwl_op_mode_dump_error(trans->op_mode, &mode);
134 }
135 }
136
137 trans_pcie->fw_reset_state = FW_RESET_IDLE;
138 }
139
_iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)140 static void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
141 {
142 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
143
144 lockdep_assert_held(&trans_pcie->mutex);
145
146 if (trans_pcie->is_down)
147 return;
148
149 if (trans->state >= IWL_TRANS_FW_STARTED &&
150 trans_pcie->fw_reset_handshake) {
151 /*
152 * Reset handshake can dump firmware on timeout, but that
153 * should assume that the firmware is already dead.
154 */
155 trans->state = IWL_TRANS_NO_FW;
156 iwl_trans_pcie_fw_reset_handshake(trans);
157 }
158
159 trans_pcie->is_down = true;
160
161 /* tell the device to stop sending interrupts */
162 iwl_disable_interrupts(trans);
163
164 /* device going down, Stop using ICT table */
165 iwl_pcie_disable_ict(trans);
166
167 /*
168 * If a HW restart happens during firmware loading,
169 * then the firmware loading might call this function
170 * and later it might be called again due to the
171 * restart. So don't process again if the device is
172 * already dead.
173 */
174 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
175 IWL_DEBUG_INFO(trans,
176 "DEVICE_ENABLED bit was set and is now cleared\n");
177 iwl_pcie_synchronize_irqs(trans);
178 iwl_pcie_rx_napi_sync(trans);
179 iwl_txq_gen2_tx_free(trans);
180 iwl_pcie_rx_stop(trans);
181 }
182
183 iwl_pcie_ctxt_info_free_paging(trans);
184 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
185 iwl_pcie_ctxt_info_gen3_free(trans, false);
186 else
187 iwl_pcie_ctxt_info_free(trans);
188
189 /* Stop the device, and put it in low power state */
190 iwl_pcie_gen2_apm_stop(trans, false);
191
192 /* re-take ownership to prevent other users from stealing the device */
193 iwl_trans_sw_reset(trans, true);
194
195 /*
196 * Upon stop, the IVAR table gets erased, so msi-x won't
197 * work. This causes a bug in RF-KILL flows, since the interrupt
198 * that enables radio won't fire on the correct irq, and the
199 * driver won't be able to handle the interrupt.
200 * Configure the IVAR table again after reset.
201 */
202 iwl_pcie_conf_msix_hw(trans_pcie);
203
204 /*
205 * Upon stop, the APM issues an interrupt if HW RF kill is set.
206 * This is a bug in certain verions of the hardware.
207 * Certain devices also keep sending HW RF kill interrupt all
208 * the time, unless the interrupt is ACKed even if the interrupt
209 * should be masked. Re-ACK all the interrupts here.
210 */
211 iwl_disable_interrupts(trans);
212
213 /* clear all status bits */
214 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
215 clear_bit(STATUS_INT_ENABLED, &trans->status);
216 clear_bit(STATUS_TPOWER_PMI, &trans->status);
217
218 /*
219 * Even if we stop the HW, we still want the RF kill
220 * interrupt
221 */
222 iwl_enable_rfkill_int(trans);
223 }
224
iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)225 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
226 {
227 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
228 bool was_in_rfkill;
229
230 iwl_op_mode_time_point(trans->op_mode,
231 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
232 NULL);
233
234 mutex_lock(&trans_pcie->mutex);
235 trans_pcie->opmode_down = true;
236 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
237 _iwl_trans_pcie_gen2_stop_device(trans);
238 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
239 mutex_unlock(&trans_pcie->mutex);
240 }
241
iwl_pcie_gen2_nic_init(struct iwl_trans * trans)242 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
243 {
244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
245 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
246 trans->cfg->min_txq_size);
247 int ret;
248
249 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
250 spin_lock_bh(&trans_pcie->irq_lock);
251 ret = iwl_pcie_gen2_apm_init(trans);
252 spin_unlock_bh(&trans_pcie->irq_lock);
253 if (ret)
254 return ret;
255
256 iwl_op_mode_nic_config(trans->op_mode);
257
258 /* Allocate the RX queue, or reset if it is already allocated */
259 if (iwl_pcie_gen2_rx_init(trans))
260 return -ENOMEM;
261
262 /* Allocate or reset and init all Tx and Command queues */
263 if (iwl_txq_gen2_init(trans, trans_pcie->txqs.cmd.q_id, queue_size))
264 return -ENOMEM;
265
266 /* enable shadow regs in HW */
267 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
268 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
269
270 return 0;
271 }
272
iwl_pcie_get_rf_name(struct iwl_trans * trans)273 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
274 {
275 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
276 char *buf = trans_pcie->rf_name;
277 size_t buflen = sizeof(trans_pcie->rf_name);
278 size_t pos;
279 u32 version;
280
281 if (buf[0])
282 return;
283
284 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
285 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
286 pos = scnprintf(buf, buflen, "JF");
287 break;
288 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
289 pos = scnprintf(buf, buflen, "GF");
290 break;
291 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
292 pos = scnprintf(buf, buflen, "GF4");
293 break;
294 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
295 pos = scnprintf(buf, buflen, "HR");
296 break;
297 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
298 pos = scnprintf(buf, buflen, "HR1");
299 break;
300 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
301 pos = scnprintf(buf, buflen, "HRCDB");
302 break;
303 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_FM):
304 pos = scnprintf(buf, buflen, "FM");
305 break;
306 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_WP):
307 if (SILICON_Z_STEP ==
308 CSR_HW_RFID_STEP(trans->hw_rf_id))
309 pos = scnprintf(buf, buflen, "WHTC");
310 else
311 pos = scnprintf(buf, buflen, "WH");
312 break;
313 default:
314 return;
315 }
316
317 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
318 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
319 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
320 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
321 version = iwl_read_prph(trans, CNVI_MBOX_C);
322 switch (version) {
323 case 0x20000:
324 pos += scnprintf(buf + pos, buflen - pos, " B3");
325 break;
326 case 0x120000:
327 pos += scnprintf(buf + pos, buflen - pos, " B5");
328 break;
329 default:
330 pos += scnprintf(buf + pos, buflen - pos,
331 " (0x%x)", version);
332 break;
333 }
334 break;
335 default:
336 break;
337 }
338
339 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
340 trans->hw_rf_id);
341
342 IWL_INFO(trans, "Detected RF %s\n", buf);
343
344 /*
345 * also add a \n for debugfs - need to do it after printing
346 * since our IWL_INFO machinery wants to see a static \n at
347 * the end of the string
348 */
349 pos += scnprintf(buf + pos, buflen - pos, "\n");
350 }
351
iwl_trans_pcie_gen2_fw_alive(struct iwl_trans * trans)352 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans)
353 {
354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
355
356 iwl_pcie_reset_ict(trans);
357
358 /* make sure all queue are not stopped/used */
359 memset(trans_pcie->txqs.queue_stopped, 0,
360 sizeof(trans_pcie->txqs.queue_stopped));
361 memset(trans_pcie->txqs.queue_used, 0,
362 sizeof(trans_pcie->txqs.queue_used));
363
364 /* now that we got alive we can free the fw image & the context info.
365 * paging memory cannot be freed included since FW will still use it
366 */
367 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
368 iwl_pcie_ctxt_info_gen3_free(trans, true);
369 else
370 iwl_pcie_ctxt_info_free(trans);
371
372 /*
373 * Re-enable all the interrupts, including the RF-Kill one, now that
374 * the firmware is alive.
375 */
376 iwl_enable_interrupts(trans);
377 mutex_lock(&trans_pcie->mutex);
378 iwl_pcie_check_hw_rf_kill(trans);
379
380 iwl_pcie_get_rf_name(trans);
381 mutex_unlock(&trans_pcie->mutex);
382 }
383
iwl_pcie_set_ltr(struct iwl_trans * trans)384 static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
385 {
386 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
387 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
388 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
389 u32_encode_bits(250,
390 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
391 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
392 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
393 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
394 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
395
396 /*
397 * To workaround hardware latency issues during the boot process,
398 * initialize the LTR to ~250 usec (see ltr_val above).
399 * The firmware initializes this again later (to a smaller value).
400 */
401 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
402 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
403 !trans->trans_cfg->integrated) {
404 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
405 return true;
406 }
407
408 if (trans->trans_cfg->integrated &&
409 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
410 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
411 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
412 return true;
413 }
414
415 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
416 /* First clear the interrupt, just in case */
417 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
418 MSIX_HW_INT_CAUSES_REG_IML);
419 /* In this case, unfortunately the same ROM bug exists in the
420 * device (not setting LTR correctly), but we don't have control
421 * over the settings from the host due to some hardware security
422 * features. The only workaround we've been able to come up with
423 * so far is to try to keep the CPU and device busy by polling
424 * it and the IML (image loader) completed interrupt.
425 */
426 return false;
427 }
428
429 /* nothing needs to be done on other devices */
430 return true;
431 }
432
iwl_pcie_spin_for_iml(struct iwl_trans * trans)433 static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
434 {
435 /* in practice, this seems to complete in around 20-30ms at most, wait 100 */
436 #define IML_WAIT_TIMEOUT (HZ / 10)
437 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
438 unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;
439 u32 value, loops = 0;
440 bool irq = false;
441
442 if (WARN_ON(!trans_pcie->iml))
443 return;
444
445 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
446 IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
447 value);
448
449 while (time_before(jiffies, end_time)) {
450 if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
451 MSIX_HW_INT_CAUSES_REG_IML) {
452 irq = true;
453 break;
454 }
455 /* Keep the CPU and device busy. */
456 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
457 loops++;
458 }
459
460 IWL_DEBUG_INFO(trans,
461 "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",
462 irq, loops, value);
463
464 /* We don't fail here even if we timed out - maybe we get lucky and the
465 * interrupt comes in later (and we get alive from firmware) and then
466 * we're all happy - but if not we'll fail on alive timeout or get some
467 * other error out.
468 */
469 }
470
iwl_trans_pcie_gen2_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)471 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
472 const struct fw_img *fw, bool run_in_rfkill)
473 {
474 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
475 bool hw_rfkill, keep_ram_busy;
476 int ret;
477
478 /* This may fail if AMT took ownership of the device */
479 if (iwl_pcie_prepare_card_hw(trans)) {
480 IWL_WARN(trans, "Exit HW not ready\n");
481 return -EIO;
482 }
483
484 iwl_enable_rfkill_int(trans);
485
486 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
487
488 /*
489 * We enabled the RF-Kill interrupt and the handler may very
490 * well be running. Disable the interrupts to make sure no other
491 * interrupt can be fired.
492 */
493 iwl_disable_interrupts(trans);
494
495 /* Make sure it finished running */
496 iwl_pcie_synchronize_irqs(trans);
497
498 mutex_lock(&trans_pcie->mutex);
499
500 /* If platform's RF_KILL switch is NOT set to KILL */
501 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
502 if (hw_rfkill && !run_in_rfkill) {
503 ret = -ERFKILL;
504 goto out;
505 }
506
507 /* Someone called stop_device, don't try to start_fw */
508 if (trans_pcie->is_down) {
509 IWL_WARN(trans,
510 "Can't start_fw since the HW hasn't been started\n");
511 ret = -EIO;
512 goto out;
513 }
514
515 /* make sure rfkill handshake bits are cleared */
516 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
517 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
518 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
519
520 /* clear (again), then enable host interrupts */
521 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
522
523 ret = iwl_pcie_gen2_nic_init(trans);
524 if (ret) {
525 IWL_ERR(trans, "Unable to init nic\n");
526 goto out;
527 }
528
529 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
530 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
531 else
532 ret = iwl_pcie_ctxt_info_init(trans, fw);
533 if (ret)
534 goto out;
535
536 keep_ram_busy = !iwl_pcie_set_ltr(trans);
537
538 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
539 IWL_DEBUG_POWER(trans, "function scratch register value is 0x%08x\n",
540 iwl_read32(trans, CSR_FUNC_SCRATCH));
541 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
542 iwl_set_bit(trans, CSR_GP_CNTRL,
543 CSR_GP_CNTRL_REG_FLAG_ROM_START);
544 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
545 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
546 } else {
547 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
548 }
549
550 if (keep_ram_busy)
551 iwl_pcie_spin_for_iml(trans);
552
553 /* re-check RF-Kill state since we may have missed the interrupt */
554 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
555 if (hw_rfkill && !run_in_rfkill)
556 ret = -ERFKILL;
557
558 out:
559 mutex_unlock(&trans_pcie->mutex);
560 return ret;
561 }
562