1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <[email protected]>
5 */
6
7 #include <hyp/switch.h>
8
9 #include <linux/arm-smccc.h>
10 #include <linux/kvm_host.h>
11 #include <linux/types.h>
12 #include <linux/jump_label.h>
13 #include <linux/percpu.h>
14 #include <uapi/linux/psci.h>
15
16 #include <kvm/arm_psci.h>
17
18 #include <asm/barrier.h>
19 #include <asm/cpufeature.h>
20 #include <asm/kprobes.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/kvm_emulate.h>
23 #include <asm/kvm_hyp.h>
24 #include <asm/kvm_mmu.h>
25 #include <asm/fpsimd.h>
26 #include <asm/debug-monitors.h>
27 #include <asm/processor.h>
28 #include <asm/thread_info.h>
29 #include <asm/vectors.h>
30
31 /* VHE specific context */
32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
35
36 /*
37 * HCR_EL2 bits that the NV guest can freely change (no RES0/RES1
38 * semantics, irrespective of the configuration), but that cannot be
39 * applied to the actual HW as things would otherwise break badly.
40 *
41 * - TGE: we want the guest to use EL1, which is incompatible with
42 * this bit being set
43 *
44 * - API/APK: they are already accounted for by vcpu_load(), and can
45 * only take effect across a load/put cycle (such as ERET)
46 */
47 #define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK)
48
__compute_hcr(struct kvm_vcpu * vcpu)49 static u64 __compute_hcr(struct kvm_vcpu *vcpu)
50 {
51 u64 hcr = vcpu->arch.hcr_el2;
52
53 if (!vcpu_has_nv(vcpu))
54 return hcr;
55
56 if (is_hyp_ctxt(vcpu)) {
57 hcr |= HCR_NV | HCR_NV2 | HCR_AT | HCR_TTLB;
58
59 if (!vcpu_el2_e2h_is_set(vcpu))
60 hcr |= HCR_NV1;
61
62 write_sysreg_s(vcpu->arch.ctxt.vncr_array, SYS_VNCR_EL2);
63 }
64
65 return hcr | (__vcpu_sys_reg(vcpu, HCR_EL2) & ~NV_HCR_GUEST_EXCLUDE);
66 }
67
__activate_cptr_traps(struct kvm_vcpu * vcpu)68 static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
69 {
70 u64 cptr;
71
72 /*
73 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
74 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
75 * except for some missing controls, such as TAM.
76 * In this case, CPTR_EL2.TAM has the same position with or without
77 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
78 * shift value for trapping the AMU accesses.
79 */
80 u64 val = CPACR_EL1_TTA | CPTR_EL2_TAM;
81
82 if (guest_owns_fp_regs()) {
83 val |= CPACR_EL1_FPEN;
84 if (vcpu_has_sve(vcpu))
85 val |= CPACR_EL1_ZEN;
86 } else {
87 __activate_traps_fpsimd32(vcpu);
88 }
89
90 if (!vcpu_has_nv(vcpu))
91 goto write;
92
93 /*
94 * The architecture is a bit crap (what a surprise): an EL2 guest
95 * writing to CPTR_EL2 via CPACR_EL1 can't set any of TCPAC or TTA,
96 * as they are RES0 in the guest's view. To work around it, trap the
97 * sucker using the very same bit it can't set...
98 */
99 if (vcpu_el2_e2h_is_set(vcpu) && is_hyp_ctxt(vcpu))
100 val |= CPTR_EL2_TCPAC;
101
102 /*
103 * Layer the guest hypervisor's trap configuration on top of our own if
104 * we're in a nested context.
105 */
106 if (is_hyp_ctxt(vcpu))
107 goto write;
108
109 cptr = vcpu_sanitised_cptr_el2(vcpu);
110
111 /*
112 * Pay attention, there's some interesting detail here.
113 *
114 * The CPTR_EL2.xEN fields are 2 bits wide, although there are only two
115 * meaningful trap states when HCR_EL2.TGE = 0 (running a nested guest):
116 *
117 * - CPTR_EL2.xEN = x0, traps are enabled
118 * - CPTR_EL2.xEN = x1, traps are disabled
119 *
120 * In other words, bit[0] determines if guest accesses trap or not. In
121 * the interest of simplicity, clear the entire field if the guest
122 * hypervisor has traps enabled to dispel any illusion of something more
123 * complicated taking place.
124 */
125 if (!(SYS_FIELD_GET(CPACR_EL1, FPEN, cptr) & BIT(0)))
126 val &= ~CPACR_EL1_FPEN;
127 if (!(SYS_FIELD_GET(CPACR_EL1, ZEN, cptr) & BIT(0)))
128 val &= ~CPACR_EL1_ZEN;
129
130 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S2POE, IMP))
131 val |= cptr & CPACR_EL1_E0POE;
132
133 val |= cptr & CPTR_EL2_TCPAC;
134
135 write:
136 write_sysreg(val, cpacr_el1);
137 }
138
__deactivate_cptr_traps(struct kvm_vcpu * vcpu)139 static void __deactivate_cptr_traps(struct kvm_vcpu *vcpu)
140 {
141 u64 val = CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN;
142
143 if (cpus_have_final_cap(ARM64_SME))
144 val |= CPACR_EL1_SMEN_EL1EN;
145
146 write_sysreg(val, cpacr_el1);
147 }
148
__activate_traps(struct kvm_vcpu * vcpu)149 static void __activate_traps(struct kvm_vcpu *vcpu)
150 {
151 u64 val;
152
153 ___activate_traps(vcpu, __compute_hcr(vcpu));
154
155 if (has_cntpoff()) {
156 struct timer_map map;
157
158 get_timer_map(vcpu, &map);
159
160 /*
161 * We're entrering the guest. Reload the correct
162 * values from memory now that TGE is clear.
163 */
164 if (map.direct_ptimer == vcpu_ptimer(vcpu))
165 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
166 if (map.direct_ptimer == vcpu_hptimer(vcpu))
167 val = __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2);
168
169 if (map.direct_ptimer) {
170 write_sysreg_el0(val, SYS_CNTP_CVAL);
171 isb();
172 }
173 }
174
175 __activate_cptr_traps(vcpu);
176
177 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1);
178 }
179 NOKPROBE_SYMBOL(__activate_traps);
180
__deactivate_traps(struct kvm_vcpu * vcpu)181 static void __deactivate_traps(struct kvm_vcpu *vcpu)
182 {
183 const char *host_vectors = vectors;
184
185 ___deactivate_traps(vcpu);
186
187 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
188
189 if (has_cntpoff()) {
190 struct timer_map map;
191 u64 val, offset;
192
193 get_timer_map(vcpu, &map);
194
195 /*
196 * We're exiting the guest. Save the latest CVAL value
197 * to memory and apply the offset now that TGE is set.
198 */
199 val = read_sysreg_el0(SYS_CNTP_CVAL);
200 if (map.direct_ptimer == vcpu_ptimer(vcpu))
201 __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0) = val;
202 if (map.direct_ptimer == vcpu_hptimer(vcpu))
203 __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2) = val;
204
205 offset = read_sysreg_s(SYS_CNTPOFF_EL2);
206
207 if (map.direct_ptimer && offset) {
208 write_sysreg_el0(val + offset, SYS_CNTP_CVAL);
209 isb();
210 }
211 }
212
213 /*
214 * ARM errata 1165522 and 1530923 require the actual execution of the
215 * above before we can switch to the EL2/EL0 translation regime used by
216 * the host.
217 */
218 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
219
220 __deactivate_cptr_traps(vcpu);
221
222 if (!arm64_kernel_unmapped_at_el0())
223 host_vectors = __this_cpu_read(this_cpu_vector);
224 write_sysreg(host_vectors, vbar_el1);
225 }
226 NOKPROBE_SYMBOL(__deactivate_traps);
227
228 /*
229 * Disable IRQs in __vcpu_{load,put}_{activate,deactivate}_traps() to
230 * prevent a race condition between context switching of PMUSERENR_EL0
231 * in __{activate,deactivate}_traps_common() and IPIs that attempts to
232 * update PMUSERENR_EL0. See also kvm_set_pmuserenr().
233 */
__vcpu_load_activate_traps(struct kvm_vcpu * vcpu)234 static void __vcpu_load_activate_traps(struct kvm_vcpu *vcpu)
235 {
236 unsigned long flags;
237
238 local_irq_save(flags);
239 __activate_traps_common(vcpu);
240 local_irq_restore(flags);
241 }
242
__vcpu_put_deactivate_traps(struct kvm_vcpu * vcpu)243 static void __vcpu_put_deactivate_traps(struct kvm_vcpu *vcpu)
244 {
245 unsigned long flags;
246
247 local_irq_save(flags);
248 __deactivate_traps_common(vcpu);
249 local_irq_restore(flags);
250 }
251
kvm_vcpu_load_vhe(struct kvm_vcpu * vcpu)252 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu)
253 {
254 host_data_ptr(host_ctxt)->__hyp_running_vcpu = vcpu;
255
256 __vcpu_load_switch_sysregs(vcpu);
257 __vcpu_load_activate_traps(vcpu);
258 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch);
259 }
260
kvm_vcpu_put_vhe(struct kvm_vcpu * vcpu)261 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu)
262 {
263 __vcpu_put_deactivate_traps(vcpu);
264 __vcpu_put_switch_sysregs(vcpu);
265
266 host_data_ptr(host_ctxt)->__hyp_running_vcpu = NULL;
267 }
268
compute_emulated_cntx_ctl_el0(struct kvm_vcpu * vcpu,enum vcpu_sysreg reg)269 static u64 compute_emulated_cntx_ctl_el0(struct kvm_vcpu *vcpu,
270 enum vcpu_sysreg reg)
271 {
272 unsigned long ctl;
273 u64 cval, cnt;
274 bool stat;
275
276 switch (reg) {
277 case CNTP_CTL_EL0:
278 cval = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
279 ctl = __vcpu_sys_reg(vcpu, CNTP_CTL_EL0);
280 cnt = compute_counter_value(vcpu_ptimer(vcpu));
281 break;
282 case CNTV_CTL_EL0:
283 cval = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0);
284 ctl = __vcpu_sys_reg(vcpu, CNTV_CTL_EL0);
285 cnt = compute_counter_value(vcpu_vtimer(vcpu));
286 break;
287 default:
288 BUG();
289 }
290
291 stat = cval <= cnt;
292 __assign_bit(__ffs(ARCH_TIMER_CTRL_IT_STAT), &ctl, stat);
293
294 return ctl;
295 }
296
kvm_hyp_handle_timer(struct kvm_vcpu * vcpu,u64 * exit_code)297 static bool kvm_hyp_handle_timer(struct kvm_vcpu *vcpu, u64 *exit_code)
298 {
299 u64 esr, val;
300
301 /*
302 * Having FEAT_ECV allows for a better quality of timer emulation.
303 * However, this comes at a huge cost in terms of traps. Try and
304 * satisfy the reads from guest's hypervisor context without
305 * returning to the kernel if we can.
306 */
307 if (!is_hyp_ctxt(vcpu))
308 return false;
309
310 esr = kvm_vcpu_get_esr(vcpu);
311 if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) != ESR_ELx_SYS64_ISS_DIR_READ)
312 return false;
313
314 switch (esr_sys64_to_sysreg(esr)) {
315 case SYS_CNTP_CTL_EL02:
316 val = compute_emulated_cntx_ctl_el0(vcpu, CNTP_CTL_EL0);
317 break;
318 case SYS_CNTP_CTL_EL0:
319 if (vcpu_el2_e2h_is_set(vcpu))
320 val = read_sysreg_el0(SYS_CNTP_CTL);
321 else
322 val = compute_emulated_cntx_ctl_el0(vcpu, CNTP_CTL_EL0);
323 break;
324 case SYS_CNTP_CVAL_EL02:
325 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
326 break;
327 case SYS_CNTP_CVAL_EL0:
328 if (vcpu_el2_e2h_is_set(vcpu)) {
329 val = read_sysreg_el0(SYS_CNTP_CVAL);
330
331 if (!has_cntpoff())
332 val -= timer_get_offset(vcpu_hptimer(vcpu));
333 } else {
334 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
335 }
336 break;
337 case SYS_CNTPCT_EL0:
338 case SYS_CNTPCTSS_EL0:
339 val = compute_counter_value(vcpu_hptimer(vcpu));
340 break;
341 case SYS_CNTV_CTL_EL02:
342 val = compute_emulated_cntx_ctl_el0(vcpu, CNTV_CTL_EL0);
343 break;
344 case SYS_CNTV_CTL_EL0:
345 if (vcpu_el2_e2h_is_set(vcpu))
346 val = read_sysreg_el0(SYS_CNTV_CTL);
347 else
348 val = compute_emulated_cntx_ctl_el0(vcpu, CNTV_CTL_EL0);
349 break;
350 case SYS_CNTV_CVAL_EL02:
351 val = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0);
352 break;
353 case SYS_CNTV_CVAL_EL0:
354 if (vcpu_el2_e2h_is_set(vcpu))
355 val = read_sysreg_el0(SYS_CNTV_CVAL);
356 else
357 val = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0);
358 break;
359 case SYS_CNTVCT_EL0:
360 case SYS_CNTVCTSS_EL0:
361 val = compute_counter_value(vcpu_hvtimer(vcpu));
362 break;
363 default:
364 return false;
365 }
366
367 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
368 __kvm_skip_instr(vcpu);
369
370 return true;
371 }
372
kvm_hyp_handle_eret(struct kvm_vcpu * vcpu,u64 * exit_code)373 static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code)
374 {
375 u64 esr = kvm_vcpu_get_esr(vcpu);
376 u64 spsr, elr, mode;
377
378 /*
379 * Going through the whole put/load motions is a waste of time
380 * if this is a VHE guest hypervisor returning to its own
381 * userspace, or the hypervisor performing a local exception
382 * return. No need to save/restore registers, no need to
383 * switch S2 MMU. Just do the canonical ERET.
384 *
385 * Unless the trap has to be forwarded further down the line,
386 * of course...
387 */
388 if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV) ||
389 (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_ERET))
390 return false;
391
392 spsr = read_sysreg_el1(SYS_SPSR);
393 mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT);
394
395 switch (mode) {
396 case PSR_MODE_EL0t:
397 if (!(vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)))
398 return false;
399 break;
400 case PSR_MODE_EL2t:
401 mode = PSR_MODE_EL1t;
402 break;
403 case PSR_MODE_EL2h:
404 mode = PSR_MODE_EL1h;
405 break;
406 default:
407 return false;
408 }
409
410 /* If ERETAx fails, take the slow path */
411 if (esr_iss_is_eretax(esr)) {
412 if (!(vcpu_has_ptrauth(vcpu) && kvm_auth_eretax(vcpu, &elr)))
413 return false;
414 } else {
415 elr = read_sysreg_el1(SYS_ELR);
416 }
417
418 spsr = (spsr & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode;
419
420 write_sysreg_el2(spsr, SYS_SPSR);
421 write_sysreg_el2(elr, SYS_ELR);
422
423 return true;
424 }
425
kvm_hyp_handle_tlbi_el2(struct kvm_vcpu * vcpu,u64 * exit_code)426 static bool kvm_hyp_handle_tlbi_el2(struct kvm_vcpu *vcpu, u64 *exit_code)
427 {
428 int ret = -EINVAL;
429 u32 instr;
430 u64 val;
431
432 /*
433 * Ideally, we would never trap on EL2 S1 TLB invalidations using
434 * the EL1 instructions when the guest's HCR_EL2.{E2H,TGE}=={1,1}.
435 * But "thanks" to FEAT_NV2, we don't trap writes to HCR_EL2,
436 * meaning that we can't track changes to the virtual TGE bit. So we
437 * have to leave HCR_EL2.TTLB set on the host. Oopsie...
438 *
439 * Try and handle these invalidation as quickly as possible, without
440 * fully exiting. Note that we don't need to consider any forwarding
441 * here, as having E2H+TGE set is the very definition of being
442 * InHost.
443 *
444 * For the lesser hypervisors out there that have failed to get on
445 * with the VHE program, we can also handle the nVHE style of EL2
446 * invalidation.
447 */
448 if (!(is_hyp_ctxt(vcpu)))
449 return false;
450
451 instr = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
452 val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu));
453
454 if ((kvm_supported_tlbi_s1e1_op(vcpu, instr) &&
455 vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) ||
456 kvm_supported_tlbi_s1e2_op (vcpu, instr))
457 ret = __kvm_tlbi_s1e2(NULL, val, instr);
458
459 if (ret)
460 return false;
461
462 __kvm_skip_instr(vcpu);
463
464 return true;
465 }
466
kvm_hyp_handle_cpacr_el1(struct kvm_vcpu * vcpu,u64 * exit_code)467 static bool kvm_hyp_handle_cpacr_el1(struct kvm_vcpu *vcpu, u64 *exit_code)
468 {
469 u64 esr = kvm_vcpu_get_esr(vcpu);
470 int rt;
471
472 if (!is_hyp_ctxt(vcpu) || esr_sys64_to_sysreg(esr) != SYS_CPACR_EL1)
473 return false;
474
475 rt = kvm_vcpu_sys_get_rt(vcpu);
476
477 if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ) {
478 vcpu_set_reg(vcpu, rt, __vcpu_sys_reg(vcpu, CPTR_EL2));
479 } else {
480 vcpu_write_sys_reg(vcpu, vcpu_get_reg(vcpu, rt), CPTR_EL2);
481 __activate_cptr_traps(vcpu);
482 }
483
484 __kvm_skip_instr(vcpu);
485
486 return true;
487 }
488
kvm_hyp_handle_zcr_el2(struct kvm_vcpu * vcpu,u64 * exit_code)489 static bool kvm_hyp_handle_zcr_el2(struct kvm_vcpu *vcpu, u64 *exit_code)
490 {
491 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
492
493 if (!vcpu_has_nv(vcpu))
494 return false;
495
496 if (sysreg != SYS_ZCR_EL2)
497 return false;
498
499 if (guest_owns_fp_regs())
500 return false;
501
502 /*
503 * ZCR_EL2 traps are handled in the slow path, with the expectation
504 * that the guest's FP context has already been loaded onto the CPU.
505 *
506 * Load the guest's FP context and unconditionally forward to the
507 * slow path for handling (i.e. return false).
508 */
509 kvm_hyp_handle_fpsimd(vcpu, exit_code);
510 return false;
511 }
512
kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu * vcpu,u64 * exit_code)513 static bool kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu *vcpu, u64 *exit_code)
514 {
515 if (kvm_hyp_handle_tlbi_el2(vcpu, exit_code))
516 return true;
517
518 if (kvm_hyp_handle_timer(vcpu, exit_code))
519 return true;
520
521 if (kvm_hyp_handle_cpacr_el1(vcpu, exit_code))
522 return true;
523
524 if (kvm_hyp_handle_zcr_el2(vcpu, exit_code))
525 return true;
526
527 return kvm_hyp_handle_sysreg(vcpu, exit_code);
528 }
529
530 static const exit_handler_fn hyp_exit_handlers[] = {
531 [0 ... ESR_ELx_EC_MAX] = NULL,
532 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
533 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg_vhe,
534 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
535 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
536 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
537 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
538 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low,
539 [ESR_ELx_EC_ERET] = kvm_hyp_handle_eret,
540 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops,
541 };
542
fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code)543 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
544 {
545 synchronize_vcpu_pstate(vcpu, exit_code);
546
547 /*
548 * If we were in HYP context on entry, adjust the PSTATE view
549 * so that the usual helpers work correctly.
550 */
551 if (vcpu_has_nv(vcpu) && (read_sysreg(hcr_el2) & HCR_NV)) {
552 u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT);
553
554 switch (mode) {
555 case PSR_MODE_EL1t:
556 mode = PSR_MODE_EL2t;
557 break;
558 case PSR_MODE_EL1h:
559 mode = PSR_MODE_EL2h;
560 break;
561 }
562
563 *vcpu_cpsr(vcpu) &= ~(PSR_MODE_MASK | PSR_MODE32_BIT);
564 *vcpu_cpsr(vcpu) |= mode;
565 }
566
567 return __fixup_guest_exit(vcpu, exit_code, hyp_exit_handlers);
568 }
569
570 /* Switch to the guest for VHE systems running in EL2 */
__kvm_vcpu_run_vhe(struct kvm_vcpu * vcpu)571 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
572 {
573 struct kvm_cpu_context *host_ctxt;
574 struct kvm_cpu_context *guest_ctxt;
575 u64 exit_code;
576
577 host_ctxt = host_data_ptr(host_ctxt);
578 guest_ctxt = &vcpu->arch.ctxt;
579
580 sysreg_save_host_state_vhe(host_ctxt);
581
582 fpsimd_lazy_switch_to_guest(vcpu);
583
584 /*
585 * Note that ARM erratum 1165522 requires us to configure both stage 1
586 * and stage 2 translation for the guest context before we clear
587 * HCR_EL2.TGE. The stage 1 and stage 2 guest context has already been
588 * loaded on the CPU in kvm_vcpu_load_vhe().
589 */
590 __activate_traps(vcpu);
591
592 __kvm_adjust_pc(vcpu);
593
594 sysreg_restore_guest_state_vhe(guest_ctxt);
595 __debug_switch_to_guest(vcpu);
596
597 do {
598 /* Jump in the fire! */
599 exit_code = __guest_enter(vcpu);
600
601 /* And we're baaack! */
602 } while (fixup_guest_exit(vcpu, &exit_code));
603
604 sysreg_save_guest_state_vhe(guest_ctxt);
605
606 __deactivate_traps(vcpu);
607
608 fpsimd_lazy_switch_to_host(vcpu);
609
610 sysreg_restore_host_state_vhe(host_ctxt);
611
612 if (guest_owns_fp_regs())
613 __fpsimd_save_fpexc32(vcpu);
614
615 __debug_switch_to_host(vcpu);
616
617 return exit_code;
618 }
619 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
620
__kvm_vcpu_run(struct kvm_vcpu * vcpu)621 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
622 {
623 int ret;
624
625 local_daif_mask();
626
627 /*
628 * Having IRQs masked via PMR when entering the guest means the GIC
629 * will not signal the CPU of interrupts of lower priority, and the
630 * only way to get out will be via guest exceptions.
631 * Naturally, we want to avoid this.
632 *
633 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
634 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
635 */
636 pmr_sync();
637
638 ret = __kvm_vcpu_run_vhe(vcpu);
639
640 /*
641 * local_daif_restore() takes care to properly restore PSTATE.DAIF
642 * and the GIC PMR if the host is using IRQ priorities.
643 */
644 local_daif_restore(DAIF_PROCCTX_NOIRQ);
645
646 /*
647 * When we exit from the guest we change a number of CPU configuration
648 * parameters, such as traps. We rely on the isb() in kvm_call_hyp*()
649 * to make sure these changes take effect before running the host or
650 * additional guests.
651 */
652 return ret;
653 }
654
__hyp_call_panic(u64 spsr,u64 elr,u64 par)655 static void __noreturn __hyp_call_panic(u64 spsr, u64 elr, u64 par)
656 {
657 struct kvm_cpu_context *host_ctxt;
658 struct kvm_vcpu *vcpu;
659
660 host_ctxt = host_data_ptr(host_ctxt);
661 vcpu = host_ctxt->__hyp_running_vcpu;
662
663 __deactivate_traps(vcpu);
664 sysreg_restore_host_state_vhe(host_ctxt);
665
666 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n",
667 spsr, elr,
668 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR),
669 read_sysreg(hpfar_el2), par, vcpu);
670 }
671 NOKPROBE_SYMBOL(__hyp_call_panic);
672
hyp_panic(void)673 void __noreturn hyp_panic(void)
674 {
675 u64 spsr = read_sysreg_el2(SYS_SPSR);
676 u64 elr = read_sysreg_el2(SYS_ELR);
677 u64 par = read_sysreg_par();
678
679 __hyp_call_panic(spsr, elr, par);
680 }
681
kvm_unexpected_el2_exception(void)682 asmlinkage void kvm_unexpected_el2_exception(void)
683 {
684 __kvm_unexpected_el2_exception();
685 }
686