1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_GENOA_POC_DATA_FABRIC_H 4 #define AMD_GENOA_POC_DATA_FABRIC_H 5 6 #include <amdblocks/data_fabric_defs.h> 7 #include <types.h> 8 9 #define DF_VGA_EN DF_REG_ID(0, 0xc08) 10 11 union df_vga_en { 12 struct { 13 uint32_t ve : 1; /* [ 0.. 0] */ 14 uint32_t np : 1; /* [ 1.. 1] */ 15 uint32_t cpu_dis : 1; /* [ 2.. 2] */ 16 uint32_t : 1; /* [ 3.. 3] */ 17 uint32_t dst_fabric_id : 12; /* [ 4..15] */ 18 uint32_t : 16; /* [16..31] */ 19 }; 20 uint32_t raw; 21 }; 22 23 #define DF_PCI_CFG_BASE0 DF_REG_ID(0, 0xc80) 24 #define DF_PCI_CFG_LIMIT0 DF_REG_ID(0, 0xc84) 25 26 #define DF_PCI_CFG_MAP_COUNT 8 27 28 #define DF_PCI_CFG_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) 29 #define DF_PCI_CFG_BASE(reg) (DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg)) 30 #define DF_PCI_CFG_LIMIT(reg) (DF_PCI_CFG_LIMIT0 + DF_PCI_CFG_REG_OFFSET(reg)) 31 32 union df_pci_cfg_base { 33 struct { 34 uint32_t re : 1; /* [ 0.. 0] */ 35 uint32_t we : 1; /* [ 1.. 1] */ 36 uint32_t : 6; /* [ 2.. 7] */ 37 uint32_t segment_num : 8; /* [ 8..15] */ 38 uint32_t bus_num_base : 8; /* [16..23] */ 39 uint32_t : 8; /* [24..31] */ 40 }; 41 uint32_t raw; 42 }; 43 44 union df_pci_cfg_limit { 45 struct { 46 uint32_t dst_fabric_id : 12; /* [ 0..11] */ 47 uint32_t : 4; /* [12..15] */ 48 uint32_t bus_num_limit : 8; /* [16..23] */ 49 uint32_t : 8; /* [24..31] */ 50 }; 51 uint32_t raw; 52 }; 53 54 #define DF_IO_BASE0 DF_REG_ID(0, 0xd00) 55 #define DF_IO_LIMIT0 DF_REG_ID(0, 0xd04) 56 57 #define DF_IO_REG_COUNT 8 58 59 #define DF_IO_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t)) 60 #define DF_IO_BASE(reg) (DF_IO_BASE0 + DF_IO_REG_OFFSET(reg)) 61 #define DF_IO_LIMIT(reg) (DF_IO_LIMIT0 + DF_IO_REG_OFFSET(reg)) 62 63 union df_io_base { 64 struct { 65 uint32_t re : 1; /* [ 0.. 0] */ 66 uint32_t we : 1; /* [ 1.. 1] */ 67 uint32_t : 3; /* [ 2.. 4] */ 68 uint32_t ie : 1; /* [ 5.. 5] */ 69 uint32_t : 10; /* [ 6..15] */ 70 uint32_t io_base : 13; /* [16..28] */ 71 uint32_t : 3; /* [29..31] */ 72 }; 73 uint32_t raw; 74 }; 75 76 union df_io_limit { 77 struct { 78 uint32_t dst_fabric_id : 12; /* [ 0..11] */ 79 uint32_t : 4; /* [12..15] */ 80 uint32_t io_limit : 13; /* [16..28] */ 81 uint32_t : 3; /* [29..31] */ 82 }; 83 uint32_t raw; 84 }; 85 86 #define DF_IO_ADDR_SHIFT 12 87 88 #define DF_MMIO_BASE0 DF_REG_ID(0, 0xd80) 89 #define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xd84) 90 #define DF_MMIO_SHIFT 16 91 #define DF_MMIO_CTRL0 DF_REG_ID(0, 0xd88) 92 #define DF_MMIO_ADDR_EXT0 DF_REG_ID(0, 0xd8c) 93 #define DF_MMIO_EXT_ADDR_SHIFT 48 94 95 #define DF_MMIO_REG_SET_SIZE 4 96 #define DF_MMIO_REG_SET_COUNT 16 97 98 union df_mmio_control { 99 struct { 100 uint32_t re : 1; /* [ 0.. 0] */ 101 uint32_t we : 1; /* [ 1.. 1] */ 102 uint32_t : 1; /* [ 2.. 2] */ 103 uint32_t np : 1; /* [ 3.. 3] */ 104 uint32_t : 12; /* [ 4..15] */ 105 uint32_t dst_fabric_id : 12; /* [16..27] */ 106 uint32_t : 4; /* [28..31] */ 107 }; 108 uint32_t raw; 109 }; 110 111 union df_mmio_addr_ext { 112 struct { 113 uint32_t base_ext : 8; /* [ 0.. 7] */ 114 uint32_t : 8; /* [ 8..15] */ 115 uint32_t limit_ext : 8; /* [16..23] */ 116 uint32_t : 8; /* [24..31] */ 117 }; 118 uint32_t raw; 119 }; 120 121 #define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) 122 #define DF_FICAD_LO DF_REG_ID(4, 0xB8) 123 #define DF_FICAD_HI DF_REG_ID(4, 0xBC) 124 125 union df_ficaa { 126 struct { 127 uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ 128 uint32_t reg_num : 10; /* [10.. 1] */ 129 uint32_t func_num : 3; /* [13..11] */ 130 uint32_t b64_en : 1; /* [14..14] */ 131 uint32_t : 1; /* [15..15] */ 132 uint32_t inst_id : 8; /* [23..16] */ 133 uint32_t : 8; /* [31..24] */ 134 }; 135 uint32_t raw; 136 }; 137 138 #endif /* AMD_GENOA_POC_DATA_FABRIC_H */ 139