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Searched defs:logicPhyRegMap (Results 1 – 3 of 3) sorted by relevance

/XiangShan/src/main/scala/xiangshan/backend/
H A DVecExcpDataMergeModule.scala502 val logicPhyRegMap = Vec(RabCommitWidth, ValidIO(new RegWriteFromRab)) constant
H A DCtrlBlock.scala953 val logicPhyRegMap = Vec(RabCommitWidth, ValidIO(new RegWriteFromRab)) constant
/XiangShan/src/main/scala/xiangshan/backend/rob/
H A DRob.scala112 val logicPhyRegMap = Vec(RabCommitWidth, ValidIO(new RegWriteFromRab)) constant