1 /* 2 * Copyright (c) 2017-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_kernel_hme_g12.h 24 //! \brief Hme kernel MDF RT based implementation for Gen12 platform 25 //! 26 #ifndef __CODECHAL_KERNEL_HME_MDF_G12_H__ 27 #define __CODECHAL_KERNEL_HME_MDF_G12_H__ 28 #include "codechal_kernel_hme.h" 29 30 #define MAX_HME_BWD_REF 4 31 #define MAX_HME_FWD_REF 8 32 33 class CodechalKernelHmeMdfG12 : public CodechalKernelHme 34 { 35 public: 36 37 // Redfine the curbe with the binding table Infices 38 class Curbe 39 { 40 public: Curbe()41 Curbe() 42 { 43 MOS_SecureMemcpy(&m_data, sizeof(m_data), &m_initCurbe, sizeof(m_initCurbe)); 44 } 45 struct CurbeData 46 { 47 // DW0 48 union 49 { 50 struct 51 { 52 uint32_t SkipModeEn : MOS_BITFIELD_BIT(0); 53 uint32_t AdaptiveEn : MOS_BITFIELD_BIT(1); 54 uint32_t BiMixDis : MOS_BITFIELD_BIT(2); 55 uint32_t reserved3 : MOS_BITFIELD_RANGE(3, 4); 56 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT(5); 57 uint32_t reserved6 : MOS_BITFIELD_BIT(6); 58 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT(7); 59 uint32_t reserved8 : MOS_BITFIELD_RANGE(8, 23); 60 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE(24, 31); 61 }; 62 uint32_t Value; 63 } DW0; 64 // DW1 65 union 66 { 67 struct 68 { 69 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE(0, 5); 70 uint32_t reserved6 : MOS_BITFIELD_RANGE(6, 15); 71 uint32_t BiWeight : MOS_BITFIELD_RANGE(16, 21); 72 uint32_t reserved22 : MOS_BITFIELD_RANGE(22, 27); 73 uint32_t UniMixDisable : MOS_BITFIELD_BIT(28); 74 uint32_t reserved29 : MOS_BITFIELD_RANGE(29, 31); 75 }; 76 uint32_t Value; 77 } DW1; 78 // DW2 79 union 80 { 81 struct 82 { 83 uint32_t MaxLenSP : MOS_BITFIELD_RANGE(0, 7); 84 uint32_t MaxNumSU : MOS_BITFIELD_RANGE(8, 15); 85 uint32_t reserved16 : MOS_BITFIELD_RANGE(16, 31); 86 }; 87 uint32_t Value; 88 } DW2; 89 // DW3 90 union 91 { 92 struct 93 { 94 uint32_t SrcSize : MOS_BITFIELD_RANGE(0, 1); 95 uint32_t reserved2 : MOS_BITFIELD_RANGE(2, 3); 96 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE(4, 5); 97 uint32_t SrcAccess : MOS_BITFIELD_BIT(6); 98 uint32_t RefAccess : MOS_BITFIELD_BIT(7); 99 uint32_t SearchCtrl : MOS_BITFIELD_RANGE(8, 10); 100 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT(11); 101 uint32_t SubPelMode : MOS_BITFIELD_RANGE(12, 13); 102 uint32_t SkipType : MOS_BITFIELD_BIT(14); 103 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT(15); 104 uint32_t InterChromaMode : MOS_BITFIELD_BIT(16); 105 uint32_t FTEnable : MOS_BITFIELD_BIT(17); 106 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT(18); 107 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT(19); 108 uint32_t InterSAD : MOS_BITFIELD_RANGE(20, 21); 109 uint32_t IntraSAD : MOS_BITFIELD_RANGE(22, 23); 110 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE(24, 30); 111 uint32_t reserved31 : MOS_BITFIELD_BIT(31); 112 }; 113 uint32_t Value; 114 } DW3; 115 // DW4 116 union 117 { 118 struct 119 { 120 uint32_t reserved0 : MOS_BITFIELD_RANGE(0, 7); 121 uint32_t PictureHeightMinus1 : MOS_BITFIELD_RANGE(8, 15); 122 uint32_t PictureWidth : MOS_BITFIELD_RANGE(16, 23); 123 uint32_t reserved24 : MOS_BITFIELD_RANGE(24, 31); 124 }; 125 uint32_t Value; 126 } DW4; 127 // DW5 128 union 129 { 130 struct 131 { 132 uint32_t SumMVThreshold : MOS_BITFIELD_RANGE(0, 7); 133 uint32_t QpPrimeY : MOS_BITFIELD_RANGE(8, 15); 134 uint32_t RefWidth : MOS_BITFIELD_RANGE(16, 23); 135 uint32_t RefHeight : MOS_BITFIELD_RANGE(24, 31); 136 }; 137 uint32_t Value; 138 } DW5; 139 // DW6 140 union 141 { 142 struct 143 { 144 uint32_t reserved0 : MOS_BITFIELD_BIT(0); 145 uint32_t InputStreamInEn : MOS_BITFIELD_BIT(1); 146 uint32_t LCUSize : MOS_BITFIELD_BIT(2); 147 uint32_t WriteDistortions : MOS_BITFIELD_BIT(3); 148 uint32_t UseMvFromPrevStep : MOS_BITFIELD_BIT(4); 149 uint32_t BRCEnable : MOS_BITFIELD_BIT(5); 150 uint32_t reserved5 : MOS_BITFIELD_RANGE(6, 7); 151 uint32_t SuperCombineDist : MOS_BITFIELD_RANGE(8, 15); 152 uint32_t MaxVmvR : MOS_BITFIELD_RANGE(16, 31); 153 }; 154 uint32_t Value; 155 } DW6; 156 // DW7 157 union 158 { 159 struct 160 { 161 uint32_t reserved0 : MOS_BITFIELD_RANGE(0, 15); 162 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE(16, 17); 163 uint32_t BilinearEnable : MOS_BITFIELD_BIT(18); 164 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT(19); 165 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT(20); 166 uint32_t AConlyHAAR : MOS_BITFIELD_BIT(21); 167 uint32_t RefIDCostMode : MOS_BITFIELD_BIT(22); 168 uint32_t reserved23 : MOS_BITFIELD_BIT(23); 169 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE(24, 31); 170 }; 171 uint32_t Value; 172 } DW7; 173 // DW8 174 union 175 { 176 struct 177 { 178 uint32_t Mode0Cost : MOS_BITFIELD_RANGE(0, 7); 179 uint32_t Mode1Cost : MOS_BITFIELD_RANGE(8, 15); 180 uint32_t Mode2Cost : MOS_BITFIELD_RANGE(16, 23); 181 uint32_t Mode3Cost : MOS_BITFIELD_RANGE(24, 31); 182 }; 183 uint32_t Value; 184 } DW8; 185 // DW9 186 union 187 { 188 struct 189 { 190 uint32_t Mode4Cost : MOS_BITFIELD_RANGE(0, 7); 191 uint32_t Mode5Cost : MOS_BITFIELD_RANGE(8, 15); 192 uint32_t Mode6Cost : MOS_BITFIELD_RANGE(16, 23); 193 uint32_t Mode7Cost : MOS_BITFIELD_RANGE(24, 31); 194 }; 195 uint32_t Value; 196 } DW9; 197 // DW10 198 union 199 { 200 struct 201 { 202 uint32_t Mode8Cost : MOS_BITFIELD_RANGE(0, 7); 203 uint32_t Mode9Cost : MOS_BITFIELD_RANGE(8, 15); 204 uint32_t RefIDCost : MOS_BITFIELD_RANGE(16, 23); 205 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE(24, 31); 206 }; 207 uint32_t Value; 208 } DW10; 209 // DW11 210 union 211 { 212 struct 213 { 214 uint32_t MV0Cost : MOS_BITFIELD_RANGE(0, 7); 215 uint32_t MV1Cost : MOS_BITFIELD_RANGE(8, 15); 216 uint32_t MV2Cost : MOS_BITFIELD_RANGE(16, 23); 217 uint32_t MV3Cost : MOS_BITFIELD_RANGE(24, 31); 218 }; 219 uint32_t Value; 220 } DW11; 221 // DW12 222 union 223 { 224 struct 225 { 226 uint32_t MV4Cost : MOS_BITFIELD_RANGE(0, 7); 227 uint32_t MV5Cost : MOS_BITFIELD_RANGE(8, 15); 228 uint32_t MV6Cost : MOS_BITFIELD_RANGE(16, 23); 229 uint32_t MV7Cost : MOS_BITFIELD_RANGE(24, 31); 230 }; 231 uint32_t Value; 232 } DW12; 233 // DW13 234 union 235 { 236 struct 237 { 238 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE(0, 7); 239 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE(8, 15); 240 uint32_t RefStreaminCost : MOS_BITFIELD_RANGE(16, 23); 241 uint32_t ROIEnable : MOS_BITFIELD_RANGE(24, 26); 242 uint32_t reserved27 : MOS_BITFIELD_RANGE(27, 31); 243 }; 244 uint32_t Value; 245 } DW13; 246 // DW14 247 union 248 { 249 struct 250 { 251 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT(0); 252 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT(1); 253 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT(2); 254 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT(3); 255 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT(4); 256 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT(5); 257 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT(6); 258 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT(7); 259 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT(8); 260 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT(9); 261 uint32_t reserved10 : MOS_BITFIELD_RANGE(10, 31); 262 }; 263 uint32_t Value; 264 } DW14; 265 // DW15 266 union 267 { 268 struct 269 { 270 uint32_t PrevMvReadPosFactor : MOS_BITFIELD_RANGE(0, 7); 271 uint32_t MvShiftFactor : MOS_BITFIELD_RANGE(8, 15); 272 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 31); 273 }; 274 uint32_t Value; 275 } DW15; 276 277 struct 278 { 279 // DW16 280 union 281 { 282 struct 283 { 284 SearchPathDelta SPDelta_0; 285 SearchPathDelta SPDelta_1; 286 SearchPathDelta SPDelta_2; 287 SearchPathDelta SPDelta_3; 288 }; 289 uint32_t Value; 290 } DW16; 291 // DW17 292 union 293 { 294 struct 295 { 296 SearchPathDelta SPDelta_4; 297 SearchPathDelta SPDelta_5; 298 SearchPathDelta SPDelta_6; 299 SearchPathDelta SPDelta_7; 300 }; 301 uint32_t Value; 302 } DW17; 303 // DW18 304 union 305 { 306 struct 307 { 308 SearchPathDelta SPDelta_8; 309 SearchPathDelta SPDelta_9; 310 SearchPathDelta SPDelta_10; 311 SearchPathDelta SPDelta_11; 312 }; 313 uint32_t Value; 314 } DW18; 315 // DW19 316 union 317 { 318 struct 319 { 320 SearchPathDelta SPDelta_12; 321 SearchPathDelta SPDelta_13; 322 SearchPathDelta SPDelta_14; 323 SearchPathDelta SPDelta_15; 324 }; 325 uint32_t Value; 326 } DW19; 327 // DW20 328 union 329 { 330 struct 331 { 332 SearchPathDelta SPDelta_16; 333 SearchPathDelta SPDelta_17; 334 SearchPathDelta SPDelta_18; 335 SearchPathDelta SPDelta_19; 336 }; 337 uint32_t Value; 338 } DW20; 339 // DW21 340 union 341 { 342 struct 343 { 344 SearchPathDelta SPDelta_20; 345 SearchPathDelta SPDelta_21; 346 SearchPathDelta SPDelta_22; 347 SearchPathDelta SPDelta_23; 348 }; 349 uint32_t Value; 350 } DW21; 351 // DW22 352 union 353 { 354 struct 355 { 356 SearchPathDelta SPDelta_24; 357 SearchPathDelta SPDelta_25; 358 SearchPathDelta SPDelta_26; 359 SearchPathDelta SPDelta_27; 360 }; 361 uint32_t Value; 362 } DW22; 363 // DW23 364 union 365 { 366 struct 367 { 368 SearchPathDelta SPDelta_28; 369 SearchPathDelta SPDelta_29; 370 SearchPathDelta SPDelta_30; 371 SearchPathDelta SPDelta_31; 372 }; 373 uint32_t Value; 374 } DW23; 375 // DW24 376 union 377 { 378 struct 379 { 380 SearchPathDelta SPDelta_32; 381 SearchPathDelta SPDelta_33; 382 SearchPathDelta SPDelta_34; 383 SearchPathDelta SPDelta_35; 384 }; 385 uint32_t Value; 386 } DW24; 387 // DW25 388 union 389 { 390 struct 391 { 392 SearchPathDelta SPDelta_36; 393 SearchPathDelta SPDelta_37; 394 SearchPathDelta SPDelta_38; 395 SearchPathDelta SPDelta_39; 396 }; 397 uint32_t Value; 398 } DW25; 399 // DW26 400 union 401 { 402 struct 403 { 404 SearchPathDelta SPDelta_40; 405 SearchPathDelta SPDelta_41; 406 SearchPathDelta SPDelta_42; 407 SearchPathDelta SPDelta_43; 408 }; 409 uint32_t Value; 410 } DW26; 411 // DW27 412 union 413 { 414 struct 415 { 416 SearchPathDelta SPDelta_44; 417 SearchPathDelta SPDelta_45; 418 SearchPathDelta SPDelta_46; 419 SearchPathDelta SPDelta_47; 420 }; 421 uint32_t Value; 422 } DW27; 423 // DW28 424 union 425 { 426 struct 427 { 428 SearchPathDelta SPDelta_48; 429 SearchPathDelta SPDelta_49; 430 SearchPathDelta SPDelta_50; 431 SearchPathDelta SPDelta_51; 432 }; 433 uint32_t Value; 434 } DW28; 435 // DW29 436 union 437 { 438 struct 439 { 440 SearchPathDelta SPDelta_52; 441 SearchPathDelta SPDelta_53; 442 SearchPathDelta SPDelta_54; 443 SearchPathDelta SPDelta_55; 444 }; 445 uint32_t Value; 446 } DW29; 447 } SpDelta; 448 449 // DW30 450 union 451 { 452 struct 453 { 454 uint32_t ActualMBWidth : MOS_BITFIELD_RANGE(0, 15); 455 uint32_t ActualMBHeight : MOS_BITFIELD_RANGE(16, 31); 456 }; 457 uint32_t Value; 458 } DW30; 459 // DW31 460 union 461 { 462 struct 463 { 464 uint32_t RoiCtrl : MOS_BITFIELD_RANGE(0, 7); 465 uint32_t MaxTuSize : MOS_BITFIELD_RANGE(8, 9); 466 uint32_t MaxCuSize : MOS_BITFIELD_RANGE(10, 11); 467 uint32_t NumImePredictors : MOS_BITFIELD_RANGE(12, 15); 468 uint32_t Reserved : MOS_BITFIELD_RANGE(16, 23); 469 uint32_t PuTypeCtrl : MOS_BITFIELD_RANGE(24, 31); 470 }; 471 uint32_t Value; 472 } DW31; 473 // DW32 474 union 475 { 476 struct 477 { 478 uint32_t ForceMvx0 : MOS_BITFIELD_RANGE(0, 15); 479 uint32_t ForceMvy0 : MOS_BITFIELD_RANGE(16, 31); 480 }; 481 uint32_t Value; 482 } DW32; 483 // DW33 484 union 485 { 486 struct 487 { 488 uint32_t ForceMvx1 : MOS_BITFIELD_RANGE(0, 15); 489 uint32_t ForceMvy1 : MOS_BITFIELD_RANGE(16, 31); 490 }; 491 uint32_t Value; 492 } DW33; 493 // DW34 494 union 495 { 496 struct 497 { 498 uint32_t ForceMvx2 : MOS_BITFIELD_RANGE(0, 15); 499 uint32_t ForceMvy2 : MOS_BITFIELD_RANGE(16, 31); 500 }; 501 uint32_t Value; 502 } DW34; 503 // DW35 504 union 505 { 506 struct 507 { 508 uint32_t ForceMvx3 : MOS_BITFIELD_RANGE(0, 15); 509 uint32_t ForceMvy3 : MOS_BITFIELD_RANGE(16, 31); 510 }; 511 uint32_t Value; 512 } DW35; 513 // DW36 514 union 515 { 516 struct 517 { 518 uint32_t ForceRefIdx0 : MOS_BITFIELD_RANGE(0, 3); 519 uint32_t ForceRefIdx1 : MOS_BITFIELD_RANGE(4, 7); 520 uint32_t ForceRefIdx2 : MOS_BITFIELD_RANGE(8, 11); 521 uint32_t ForceRefIdx3 : MOS_BITFIELD_RANGE(12, 15); 522 uint32_t NumMergeCandCu8x8 : MOS_BITFIELD_RANGE(16, 19); 523 uint32_t NumMergeCandCu16x16 : MOS_BITFIELD_RANGE(20, 23); 524 uint32_t NumMergeCandCu32x32 : MOS_BITFIELD_RANGE(24, 27); 525 uint32_t NumMergeCandCu64x64 : MOS_BITFIELD_RANGE(28, 31); 526 }; 527 uint32_t Value; 528 } DW36; 529 // DW37 530 union 531 { 532 struct 533 { 534 uint32_t SegID : MOS_BITFIELD_RANGE(0, 15); 535 uint32_t QpEnable : MOS_BITFIELD_RANGE(16, 19); 536 uint32_t SegIDEnable : MOS_BITFIELD_BIT(20); 537 uint32_t Reserved : MOS_BITFIELD_RANGE(21, 22); 538 uint32_t ForceRefIdEnable : MOS_BITFIELD_BIT(23); 539 uint32_t Reserved1 : MOS_BITFIELD_RANGE(24, 31); 540 }; 541 uint32_t Value; 542 } DW37; 543 // DW38 544 union 545 { 546 struct 547 { 548 uint32_t ForceQp0 : MOS_BITFIELD_RANGE(0, 7); 549 uint32_t ForceQp1 : MOS_BITFIELD_RANGE(8, 15); 550 uint32_t ForceQp2 : MOS_BITFIELD_RANGE(16, 23); 551 uint32_t ForceQp3 : MOS_BITFIELD_RANGE(24, 31); 552 }; 553 uint32_t Value; 554 } DW38; 555 // DW39 556 union 557 { 558 struct 559 { 560 uint32_t Reserved; 561 }; 562 uint32_t Value; 563 } DW39; 564 } m_data; 565 static const uint32_t m_curbeSize = sizeof(CurbeData); 566 static const uint32_t m_initCurbe[40]; 567 }; 568 // clang-format on 569 570 protected: 571 572 CmThreadSpace *m_threadSpace4x = nullptr; 573 CmThreadSpace *m_threadSpace16x = nullptr; 574 CmThreadSpace *m_threadSpace32x = nullptr; 575 CmProgram *m_cmProgramME = nullptr; 576 577 CmKernel *m_cmKrnME4x = nullptr; 578 CmKernel *m_cmKrnME16x = nullptr; 579 CmKernel *m_cmKrnME32x = nullptr; 580 581 CmKernel *m_cmKrnME4xP = nullptr; 582 CmKernel *m_cmKrnME32xP = nullptr; 583 CmKernel *m_cmKrnME16xP = nullptr; 584 585 CmKernel *m_cmKrnME4xB = nullptr; 586 CmKernel *m_cmKrnME16xB = nullptr; 587 CmKernel *m_cmKrnME32xB = nullptr; 588 589 typedef struct _HME_YUV_SurfaceInfo 590 { _HME_YUV_SurfaceInfo_HME_YUV_SurfaceInfo591 _HME_YUV_SurfaceInfo() 592 { 593 for (uint8_t i = 0; i < MAX_HME_BWD_REF; i++) 594 BwdReference[i] = nullptr; 595 596 for (uint8_t i = 0; i < MAX_HME_FWD_REF; i++) 597 FwdReference[i] = nullptr; 598 } 599 CmSurface2D *SrcSurface = nullptr; 600 CmSurface2D *FwdReference[MAX_HME_FWD_REF]; 601 SurfaceIndex *VMEFwdIdx = nullptr; 602 CmSurface2D *BwdReference[MAX_HME_BWD_REF]; 603 SurfaceIndex *VMEBwdIdx = nullptr; 604 }HmeYUVInfo; 605 606 HmeYUVInfo m_HME4xYUVInfo; 607 HmeYUVInfo m_HME16xYUVInfo; 608 HmeYUVInfo m_HME32xYUVInfo; 609 610 CmSurface2D *m_HME4xDistortionSurface = nullptr; 611 CmSurface2D *m_HME4xMVSurface = nullptr; 612 CmSurface2D *m_HME16xMVSurface = nullptr; 613 CmSurface2D *m_HME32xMVSurface = nullptr; 614 CmBuffer *m_VdencStreamInBuffer = nullptr; 615 CmBuffer *m_SumMvandDistortionBuffer = nullptr; 616 617 public: 618 //! 619 //! \brief Constructor 620 //! 621 //! \param [in] me4xDistBufferSupported 622 //! flag to support 4x Distortion buffer 623 //! 624 CodechalKernelHmeMdfG12( 625 CodechalEncoderState *encoder, 626 bool me4xDistBufferSupported = true); 627 628 //! 629 //! \brief Destructor 630 //! 631 ~CodechalKernelHmeMdfG12(); 632 633 MOS_STATUS AllocateResources()override; 634 635 //! 636 //! \brief Retrieve HME surfaces to send to Enc 637 //! 638 //! 639 CmSurface2D* GetCmSurface(uint32_t surfaceId)override; 640 641 //! 642 //! \brief Execute HME kernel 643 //! 644 //! \param [in] curbeParam 645 //! Reference to CurbeParam 646 //! \param [in] surfaceParam 647 //! Reference to SurfaceParams 648 //! \param [in] hmeLevel 649 //! current Hme level to run the kernel 650 //! 651 // 652 //! \return MOS_STATUS 653 //! MOS_STATUS_SUCCESS if success 654 //! 655 MOS_STATUS Execute(CurbeParam &curbeParam, SurfaceParams &surfaceParam, HmeLevel hmeLevel)override; 656 657 //! 658 //! \brief Release the MDF RT Reources 659 //! 660 MOS_STATUS ReleaseResources()override; 661 662 protected: GetCurbeSize()663 uint32_t GetCurbeSize() override { return Curbe::m_curbeSize; } 664 //! 665 //! \brief Set the Curbe parameters such that it can be passed as kernel argument 666 //! 667 MOS_STATUS SetMECurbe(Curbe& curbe); 668 669 virtual MOS_STATUS SetupSurfaces(); 670 671 virtual MOS_STATUS InitKernelState(void *kernelIsa, uint32_t kernelIsaSize); 672 673 virtual MOS_STATUS SetupKernelArgs(CmKernel *cmKrn); 674 675 MOS_STATUS DestroyYUVSurfaces(HmeYUVInfo& YUVInfo); 676 677 }; 678 679 #endif /* __CODECHAL_KERNEL_HME_G12_H__ */ 680