1 /* 2 * Copyright (c) 2017-2020, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_encode_csc_ds.h 24 //! \brief Defines base class for CSC and Downscaling 25 //! 26 27 #ifndef __CODECHAL_ENCODE_CSC_DS_H__ 28 #define __CODECHAL_ENCODE_CSC_DS_H__ 29 30 #include "codechal.h" 31 #include "codechal_hw.h" 32 #include "codechal_encode_sfc.h" 33 #include "codechal_utilities.h" 34 #include "mos_context_next.h" 35 36 //! 37 //! \enum DsStage 38 //! \brief Ds stage 39 //! 40 enum DsStage 41 { 42 dsDisabled = 0, 43 dsStage2x = 1, 44 dsStage4x = 2, 45 dsStage16x = 3, 46 dsStage2x4x = 4, 47 dsStage32x = 5, 48 // below used by HEVC Gen10 DsConv kernel 49 dsConvUnknown = 0, 50 ds2xFromOrig = 1, 51 ds4xFromOrig = 2, 52 ds2x4xFromOrig = 3, 53 ds16xFromOrig = 4, 54 convFromOrig = 8, 55 convDs2xFromOrig = 9, 56 convDs4xFromOrig = 10, 57 convDs2x4xFromOrig = 11, 58 }; 59 60 //! 61 //! \class ScalingBindingTable 62 //! \brief Scaling binding table 63 //! 64 struct ScalingBindingTable 65 { 66 uint32_t dwScalingFrameSrcY; 67 uint32_t dwScalingFrameDstY; 68 uint32_t dwScalingFieldTopSrcY; 69 uint32_t dwScalingFieldBotSrcY; 70 uint32_t dwScalingFieldTopDstY; 71 uint32_t dwScalingFieldBotDstY; 72 uint32_t dwScalingFrameFlatnessChkDst; 73 uint32_t dwScalingFieldFlatnessChkTopDst; 74 uint32_t dwScalingFieldFlatnessChkBotDst; 75 uint32_t dwScalingFrameMbVprocStatsDst; 76 uint32_t dwScalingFieldMbVprocStatsTopDst; 77 uint32_t dwScalingFieldMbVprocStatsBotDst; 78 uint32_t dwBindingTableStartOffset; 79 uint32_t dwNumBindingTableEntries; 80 }; 81 82 //! 83 //! \class CodechalEncodeCscDs 84 //! \details CSC and Downscaling base class 85 //! Entry point to create CSC Downscaling class instance 86 //! This class defines the base class for CSC and Downscaling feature, it includes 87 //! common member fields, functions, interfaces etc shared by all Gens. 88 //! 89 class CodechalEncodeCscDs 90 { 91 public: 92 //!< \cond SKIP_DOXYGEN 93 //! 94 //! \brief Curbe params for CSC kernel 95 //! 96 struct CurbeParams 97 { 98 PMHW_KERNEL_STATE pKernelState = nullptr; 99 uint32_t dwInputPictureWidth = 0; 100 uint32_t dwInputPictureHeight = 0; 101 bool b16xScalingInUse = false; 102 bool b32xScalingInUse = false; 103 bool bFieldPicture = false; 104 bool bCscOrCopyOnly = false; 105 bool bFlatnessCheckEnabled = false; 106 bool bMBVarianceOutputEnabled = false; 107 bool bMBPixelAverageOutputEnabled = false; 108 bool bBlock8x8StatisticsEnabled = false; 109 ENCODE_INPUT_COLORSPACE inputColorSpace = ECOLORSPACE_P709; 110 DsStage downscaleStage = dsDisabled; 111 uint8_t ucEncBitDepthLuma = 8; 112 uint8_t ucEncBitDepthChroma = 8; 113 bool bConvertFlag = false; 114 bool bHevcEncHistorySum = false; 115 bool bUseLCU32 = false; 116 }; 117 118 //! 119 //! \brief Kernel params for CSC kernel 120 //! 121 struct KernelParams 122 { 123 DsStage stageDsConversion = dsDisabled; 124 bool b16xScalingInUse = false; 125 bool b32xScalingInUse = false; 126 bool cscOrCopyOnly = false; 127 bool bLastTaskInPhaseCSC = false; 128 bool bLastTaskInPhase4xDS = false; 129 bool bLastTaskInPhase16xDS = false; 130 bool bLastTaskInPhase32xDS = false; 131 bool bRawInputProvided = false; 132 bool bStatsInputProvided = false; 133 bool bScalingforRef = false; 134 MOS_SURFACE sInputRawSurface = {}; // for FEI to pass in raw surface 135 MOS_RESOURCE sInputStatsBuffer = {}; 136 MOS_RESOURCE sInputStatsBotFieldBuffer = {}; 137 CODEC_PICTURE inputPicture = {}; 138 ENCODE_INPUT_COLORSPACE inputColorSpace = ECOLORSPACE_P709; 139 PMOS_SURFACE psFormatConversionOnlyInputSurface = nullptr; 140 PMOS_SURFACE psFormatConvertedSurface = nullptr; 141 void* hevcExtParams = nullptr; 142 }; 143 144 //! 145 //! \brief 4xDS kernel Curbe data 146 //! 147 struct Ds4xKernelCurbeData 148 { Ds4xKernelCurbeDataDs4xKernelCurbeData149 Ds4xKernelCurbeData() 150 { 151 DW0 = 0; 152 DW1 = ds4xSrcYPlane; 153 DW2 = ds4xDstYPlane; 154 DW3_InputYBTIBottomField = 155 DW4_OutputYBTIBottomField = 156 DW5_FlatnessThreshold = 157 DW6 = 158 DW7_Reserved = 0; 159 DW8 = ds4xDstFlatness; 160 DW9_FlatnessOutputBTIBottomField = 0; 161 DW10 = ds4xDstMbVProc; 162 DW11_MBVProcStatsBTIBottomField = 0; 163 } 164 165 // uint32_t 0 - GRF R1.0 166 union 167 { 168 struct 169 { 170 uint32_t DW0_InputPictureWidth : MOS_BITFIELD_RANGE(0, 15); 171 uint32_t DW0_InputPictureHeight : MOS_BITFIELD_RANGE(16, 31); 172 }; 173 uint32_t DW0; 174 }; 175 176 // DW1 177 union 178 { 179 struct 180 { 181 uint32_t DW1_InputYBTIFrame; 182 }; 183 struct 184 { 185 uint32_t DW1_InputYBTITopField; 186 }; 187 uint32_t DW1; 188 }; 189 190 // DW2 191 union 192 { 193 struct 194 { 195 uint32_t DW2_OutputYBTIFrame; 196 }; 197 struct 198 { 199 uint32_t DW2_OutputYBTITopField; 200 }; 201 uint32_t DW2; 202 }; 203 204 // DW3 205 uint32_t DW3_InputYBTIBottomField; 206 207 // DW4 208 uint32_t DW4_OutputYBTIBottomField; 209 210 // DW5 211 uint32_t DW5_FlatnessThreshold; 212 213 // DW6 214 union 215 { 216 struct 217 { 218 uint32_t DW6_EnableMBFlatnessCheck : MOS_BITFIELD_BIT(0); 219 uint32_t DW6_EnableMBVarianceOutput : MOS_BITFIELD_BIT(1); 220 uint32_t DW6_EnableMBPixelAverageOutput : MOS_BITFIELD_BIT(2); 221 uint32_t DW6_EnableBlock8x8StatisticsOutput : MOS_BITFIELD_BIT(3); 222 uint32_t : MOS_BITFIELD_RANGE(4, 31); 223 }; 224 uint32_t DW6; 225 }; 226 227 // DW7 228 uint32_t DW7_Reserved; 229 230 // DW8 231 union 232 { 233 struct 234 { 235 uint32_t DW8_FlatnessOutputBTIFrame; 236 }; 237 struct 238 { 239 uint32_t DW8_FlatnessOutputBTITopField; 240 }; 241 uint32_t DW8; 242 }; 243 244 // DW9 245 uint32_t DW9_FlatnessOutputBTIBottomField; 246 247 // DW10 248 union 249 { 250 struct 251 { 252 uint32_t DW10_MBVProcStatsBTIFrame; 253 }; 254 struct 255 { 256 uint32_t DW10_MBVProcStatsBTITopField; 257 }; 258 uint32_t DW10; 259 }; 260 261 // DW11 262 uint32_t DW11_MBVProcStatsBTIBottomField; 263 }; 264 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(Ds4xKernelCurbeData)) == 12); 265 266 //! 267 //! \brief 2xDS kernel Curbe data 268 //! 269 struct Ds2xKernelCurbeData 270 { Ds2xKernelCurbeDataDs2xKernelCurbeData271 Ds2xKernelCurbeData() 272 { 273 DW0 = 274 DW1_Reserved = 275 DW2_Reserved = 276 DW3_Reserved = 277 DW4_Reserved = 278 DW5_Reserved = 279 DW6_Reserved = 280 DW7_Reserved = 0; 281 DW8 = ds2xSrcYPlane; 282 DW9 = ds2xDstYPlane; 283 DW10_InputYBTIBottomField = 284 DW11_OutputYBTIBottomField = 0; 285 } 286 287 // uint32_t 0 - GRF R1.0 288 union 289 { 290 struct 291 { 292 uint32_t DW0_InputPictureWidth : MOS_BITFIELD_RANGE(0, 15); 293 uint32_t DW0_InputPictureHeight : MOS_BITFIELD_RANGE(16, 31); 294 }; 295 uint32_t DW0; 296 }; 297 298 // DW1 299 uint32_t DW1_Reserved; 300 301 // DW2 302 uint32_t DW2_Reserved; 303 304 // DW3 305 uint32_t DW3_Reserved; 306 307 // DW4 308 uint32_t DW4_Reserved; 309 310 // DW5 311 uint32_t DW5_Reserved; 312 313 // DW6 314 uint32_t DW6_Reserved; 315 316 // DW7 317 uint32_t DW7_Reserved; 318 319 // DW8 320 union 321 { 322 struct 323 { 324 uint32_t DW8_InputYBTIFrame : MOS_BITFIELD_RANGE(0, 31); 325 }; 326 struct 327 { 328 uint32_t DW8_InputYBTITopField : MOS_BITFIELD_RANGE(0, 31); 329 }; 330 uint32_t DW8; 331 }; 332 333 // DW9 334 union 335 { 336 struct 337 { 338 uint32_t DW9_OutputYBTIFrame : MOS_BITFIELD_RANGE(0, 31); 339 }; 340 struct 341 { 342 uint32_t DW9_OutputYBTITopField : MOS_BITFIELD_RANGE(0, 31); 343 }; 344 uint32_t DW9; 345 }; 346 347 // DW10 348 uint32_t DW10_InputYBTIBottomField; 349 350 // DW11 351 uint32_t DW11_OutputYBTIBottomField; 352 }; 353 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(Ds2xKernelCurbeData)) == 12); 354 IsEnabled()355 uint8_t IsEnabled() const { return m_cscDsConvEnable; } GetRawSurfWidth()356 uint32_t GetRawSurfWidth() const { return m_cscRawSurfWidth; } GetRawSurfHeight()357 uint32_t GetRawSurfHeight() const { return m_cscRawSurfHeight; } RequireCsc()358 bool RequireCsc() const { return m_cscFlag != 0; } RequireCopyOnly()359 bool RequireCopyOnly() const { return m_cscFlag == 1; } // m_cscRequireCopy bit only UseSfc()360 bool UseSfc() const { return m_cscUsingSfc != 0; } IsSfcEnabled()361 bool IsSfcEnabled() const { return m_cscEnableSfc != 0; } IsMediaCopyEnabled()362 bool IsMediaCopyEnabled() const { return m_cscEnableMediaCopy != 0; } RenderConsumesCscSurface()363 bool RenderConsumesCscSurface() const { return m_cscRequireCopy || m_cscRequireColor || m_cscRequireConvTo8bPlanar; } VdboxConsumesCscSurface()364 bool VdboxConsumesCscSurface() const { return m_cscRequireCopy || m_cscRequireColor || m_cscRequireMmc; } 365 // 0 for native HW support; 1 for CSC kernel; 2 for VEBOX CscMethod()366 uint8_t CscMethod() const { return (m_cscRequireColor ? (m_cscUsingSfc ? 2 : 1) : 0); } 367 DisableCsc()368 void DisableCsc() { m_cscDsConvEnable = 0; } EnableCopy()369 void EnableCopy() { m_cscEnableCopy = 1; } DisableCopy()370 void DisableCopy() { m_cscEnableCopy = 0; } EnableMediaCopy()371 void EnableMediaCopy() { m_cscEnableMediaCopy = 1; } EnableColor()372 void EnableColor() { m_cscEnableColor = 1; } EnableMmc()373 void EnableMmc() { m_cscEnableMmc = 1; } EnableSfc()374 void EnableSfc() { m_cscEnableSfc = 1; } DisableSfc()375 void DisableSfc() { m_cscEnableSfc = 0; } ResetCscFlag()376 void ResetCscFlag() { m_cscFlag = 0; } 377 //! \endcond 378 379 //! 380 //! \brief Copy constructor 381 //! 382 CodechalEncodeCscDs(const CodechalEncodeCscDs&) = delete; 383 384 //! 385 //! \brief Copy assignment operator 386 //! 387 CodechalEncodeCscDs& operator=(const CodechalEncodeCscDs&) = delete; 388 389 //! 390 //! \brief Destructor 391 //! 392 virtual ~CodechalEncodeCscDs(); 393 394 //! 395 //! \brief Get CSC kernel BT count 396 //! 397 //! \return Number of BTI 398 //! 399 virtual uint8_t GetBTCount() const; 400 401 //! 402 //! \brief Get CSC surface allocation width/height/format 403 //! 404 //! \return MOS_STATUS 405 //! MOS_STATUS_SUCCESS if success, else fail reason 406 //! 407 void GetCscAllocation(uint32_t &width, uint32_t &height, MOS_FORMAT &format); 408 409 //! 410 //! \brief Initialize the class 411 //! 412 //! \return MOS_STATUS 413 //! MOS_STATUS_SUCCESS if success, else fail reason 414 //! 415 MOS_STATUS Initialize(); 416 417 //! 418 //! \brief Check if need to do CSC/DS/Conversion 419 //! 420 //! \return MOS_STATUS 421 //! MOS_STATUS_SUCCESS if success, else fail reason 422 //! 423 MOS_STATUS CheckCondition(); 424 425 //! 426 //! \brief Check if recon surface's alignment meet HW requirement 427 //! 428 //! \return MOS_STATUS 429 //! MOS_STATUS_SUCCESS if success, else fail reason 430 //! 431 MOS_STATUS CheckReconSurfaceAlignment(PMOS_SURFACE surface); 432 433 //! 434 //! \brief Check if raw surface's alignment meet HW requirement 435 //! 436 //! \return MOS_STATUS 437 //! MOS_STATUS_SUCCESS if success, else fail reason 438 //! 439 MOS_STATUS CheckRawSurfaceAlignment(PMOS_SURFACE surface); 440 441 //! 442 //! \brief Set HCP recon surface alignment 443 //! 444 //! \return MOS_STATUS 445 //! MOS_STATUS_SUCCESS if success, else fail reason 446 //! 447 void SetHcpReconAlignment(uint8_t alignment); 448 449 //! 450 //! \brief On-demand sync for the CSC output surface before use 451 //! 452 //! \return MOS_STATUS 453 //! MOS_STATUS_SUCCESS if success, else fail reason 454 //! 455 MOS_STATUS WaitCscSurface(MOS_GPU_CONTEXT gpuContext, bool readOnly); 456 457 //! 458 //! \brief Encode kernel functions 459 //! 460 //! \return MOS_STATUS 461 //! MOS_STATUS_SUCCESS if success, else fail reason 462 //! 463 MOS_STATUS KernelFunctions(KernelParams* params); 464 465 MOS_STATUS SetHevcCscFlagAndRawColor(); 466 467 //! 468 //! \brief CSC using SFC 469 //! 470 //! \return MOS_STATUS 471 //! MOS_STATUS_SUCCESS if success, else fail reason 472 //! 473 virtual MOS_STATUS CscUsingSfc(ENCODE_INPUT_COLORSPACE colorSpace); 474 475 //! 476 //! \brief CSC kernel function 477 //! 478 //! \return MOS_STATUS 479 //! MOS_STATUS_SUCCESS if success, else fail reason 480 //! 481 virtual MOS_STATUS CscKernel(KernelParams* params); 482 483 //! 484 //! \brief DS kernel function 485 //! 486 //! \return MOS_STATUS 487 //! MOS_STATUS_SUCCESS if success, else fail reason 488 //! 489 virtual MOS_STATUS DsKernel(KernelParams* params); 490 491 //! 492 //! \brief Raw surface Media Copy function 493 //! 494 //! \return MOS_STATUS 495 //! MOS_STATUS_SUCCESS if success, else fail reason 496 //! 497 MOS_STATUS RawSurfaceMediaCopy(MOS_FORMAT format); 498 499 //! 500 //! \brief Surface Need Extra Copy 501 //! 502 //! \return MOS_STATUS 503 //! MOS_STATUS_SUCCESS if success, else fail reason 504 //! SurfaceNeedsExtraCopy()505 virtual MOS_STATUS SurfaceNeedsExtraCopy() 506 { 507 return MOS_STATUS_SUCCESS; 508 } 509 510 protected: 511 //! 512 //! \brief CSC kernel supported color format 513 //! 514 enum CscColor 515 { 516 cscColorNv12TileY = 0, // NV12 Tile-Y 517 cscColorP010 = 1, // P010 518 cscColorP210 = 2, // P210 (not supported yet) 519 cscColorYUY2 = 3, // YUY2 520 cscColorY210 = 4, // Y210 521 cscColorARGB = 5, // ARGB 522 cscColorNv12Linear = 6, // NV12 linear 523 cscColorAYUV = 7, // AYUV 524 cscColorARGB10 = 8, // ARGB10 525 cscColorY410 = 9, // Y410 526 cscColorABGR = 10, // ABGR 527 cscColorABGR10 = 11, // ABGR10 528 cscColorEnumNumber = 12 529 }; 530 531 //! 532 //! \brief CSC kernel Curbe data 533 //! 534 struct CscKernelCurbeData 535 { CscKernelCurbeDataCscKernelCurbeData536 CscKernelCurbeData() 537 { 538 DW0 = 0; 539 DW1_SrcNV12SurfYIndex = cscSrcYPlane; 540 DW2_DstYSurfIndex = cscDstDsYPlane; 541 DW3_FlatDstSurfIndex = cscDstFlatOrMbStats; 542 DW4_CopyDstNV12SurfIndex = cscDstCopyYPlane; 543 DW5 = 0; 544 DW6_FlatnessThreshold = 0; 545 DW7 = 0; 546 DW8_SrcNV12SurfUVIndex = cscSrcUVPlane; 547 } 548 549 union 550 { 551 struct 552 { 553 // uint32_t 0 - GRF R1.0 554 uint32_t DW0_InputPictureWidth : MOS_BITFIELD_RANGE(0, 15); 555 uint32_t DW0_InputPictureHeight : MOS_BITFIELD_RANGE(16, 31); 556 }; 557 uint32_t DW0; 558 }; 559 560 // DW1: Surface index source linear NV12 Y Plane 561 uint32_t DW1_SrcNV12SurfYIndex; 562 563 // DW2: Surface index downscale destination Planar Y 564 uint32_t DW2_DstYSurfIndex; 565 566 // DW3: Surface index flatness destination 567 uint32_t DW3_FlatDstSurfIndex; 568 569 // DW4: Surface index copy destination NV12 570 uint32_t DW4_CopyDstNV12SurfIndex; 571 572 union 573 { 574 struct 575 { 576 // dw5: operation mode 577 uint32_t DW5_CscDsCopyOpCode : MOS_BITFIELD_RANGE(0, 7); 578 uint32_t DW5_InputColorFormat : MOS_BITFIELD_RANGE(8, 15); 579 uint32_t DW5_Reserved : MOS_BITFIELD_RANGE(16, 31); 580 }; 581 uint32_t DW5; 582 }; 583 584 // DW6: MBFlatnessThreshold 585 uint32_t DW6_FlatnessThreshold; 586 587 union 588 { 589 struct 590 { 591 // dw7: EnableMBFlatnessCheck 592 uint32_t DW7_EnableMBFlatnessCheck : MOS_BITFIELD_BIT(0); 593 uint32_t DW7_Reserved : MOS_BITFIELD_RANGE(1, 31); 594 }; 595 uint32_t DW7; 596 }; 597 598 // DW8: Surface index source linear NV12 UV Plane 599 uint32_t DW8_SrcNV12SurfUVIndex; 600 }; 601 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CscKernelCurbeData)) == 9); 602 603 //! 604 //! \brief Surface params for CSC kernel 605 //! 606 struct SurfaceParamsCsc 607 { 608 bool bFlatnessCheckEnabled = false; 609 bool bMBVProcStatsEnabled = false; 610 bool bScalingInUses16UnormSurfFmt = false; 611 bool bScalingInUses32UnormSurfFmt = false; 612 PMOS_SURFACE psInputSurface = nullptr; 613 PMOS_SURFACE psOutput4xDsSurface = nullptr; 614 PMOS_SURFACE psOutput2xDsSurface = nullptr; 615 PMOS_SURFACE psOutputCopiedSurface = nullptr; 616 PMOS_SURFACE psFlatnessCheckSurface = nullptr; 617 PMOS_RESOURCE presMBVProcStatsBuffer = nullptr; 618 void* hevcExtParams = nullptr; 619 }; 620 621 //! 622 //! \brief Surface params for DS kernel 623 //! 624 struct SurfaceParamsDS 625 { 626 PMOS_SURFACE psInputSurface = nullptr; 627 uint32_t dwInputFrameWidth = 0; 628 uint32_t dwInputFrameHeight = 0; 629 uint32_t dwInputBottomFieldOffset = 0; 630 PMOS_SURFACE psOutputSurface = nullptr; 631 uint32_t dwOutputFrameWidth = 0; 632 uint32_t dwOutputFrameHeight = 0; 633 uint32_t dwOutputBottomFieldOffset = 0; 634 bool bScalingOutUses16UnormSurfFmt = false; 635 bool bScalingOutUses32UnormSurfFmt = false; 636 bool bFlatnessCheckEnabled = false; 637 PMOS_SURFACE psFlatnessCheckSurface = nullptr; 638 uint32_t dwFlatnessCheckBottomFieldOffset = 0; 639 bool bMBVProcStatsEnabled = false; 640 PMOS_RESOURCE presMBVProcStatsBuffer = nullptr; 641 PMOS_RESOURCE presMBVProcStatsBotFieldBuffer = nullptr; 642 uint32_t dwMBVProcStatsBottomFieldOffset = 0; 643 bool bCurrPicIsFrame = false; 644 bool bPreEncInUse = false; 645 bool bEnable8x8Statistics = false; 646 }; 647 648 //! 649 //! \brief Constructor 650 //! 651 CodechalEncodeCscDs(CodechalEncoderState* encoder); 652 653 //! 654 //! \brief Allocate CSC surface or pick an existing one from the pool 655 //! 656 //! \return MOS_STATUS 657 //! MOS_STATUS_SUCCESS if success, else fail reason 658 //! 659 virtual MOS_STATUS AllocateSurfaceCsc(); 660 661 //! 662 //! \brief Allocate Copy surface or pick an existing one from the pool 663 //! 664 //! \return MOS_STATUS 665 //! MOS_STATUS_SUCCESS if success, else fail reason 666 //! 667 virtual MOS_STATUS AllocateSurfaceCopy(MOS_FORMAT); 668 669 //! 670 //! \brief Initialize DS kernel state 671 //! 672 //! \return MOS_STATUS 673 //! MOS_STATUS_SUCCESS if success, else fail reason 674 //! 675 virtual MOS_STATUS InitKernelStateDS(); 676 677 //! 678 //! \brief Set SurfaceParamsDS for DS kernel 679 //! 680 //! \param params 681 //! KernelParams pointer from caller 682 //! 683 //! \return MOS_STATUS 684 //! MOS_STATUS_SUCCESS if success, else fail reason 685 //! 686 MOS_STATUS SetSurfaceParamsDS(KernelParams* params); 687 688 //! 689 //! \brief Setup Curbe for DS kernel 690 //! 691 //! \return MOS_STATUS 692 //! MOS_STATUS_SUCCESS if success, else fail reason 693 //! 694 virtual MOS_STATUS SetCurbeDS4x(); 695 696 //! 697 //! \brief Set-up surface sent to ENC/PAK 698 //! 699 //! \return MOS_STATUS 700 //! MOS_STATUS_SUCCESS if success, else fail reason 701 //! 702 MOS_STATUS SetSurfacesToEncPak(); 703 704 //! 705 //! \brief Check alignment copy 706 //! 707 //! \param surface 708 //! Pointer to MOS_SURFACE 709 //! 710 //! \return MOS_STATUS 711 //! MOS_STATUS_SUCCESS if success, else fail reason 712 //! 713 virtual MOS_STATUS CheckRawSurfaceAlignment(MOS_SURFACE surface); 714 715 716 CodechalEncoderState* m_encoder = nullptr; //!< Pointer to ENCODER base class 717 MOS_INTERFACE* m_osInterface = nullptr; //!< OS interface 718 CodechalHwInterface* m_hwInterface = nullptr; //!< HW interface 719 CodechalDebugInterface* m_debugInterface = nullptr; //!< Debug interface 720 MhwMiInterface* m_miInterface = nullptr; //!< Common Mi Interface 721 MhwRenderInterface* m_renderInterface = nullptr; //!< Render engine interface 722 XMHW_STATE_HEAP_INTERFACE* m_stateHeapInterface = nullptr; //!< State heap class interface 723 CodecHalEncodeSfc* m_sfcState = nullptr; //!< SFC interface 724 MHW_KERNEL_STATE* m_cscKernelState = nullptr; //!< CSC kernel state 725 MHW_KERNEL_STATE* m_dsKernelState = nullptr; //!< DS kernel state 726 MediaCopyBaseState* m_mediaCopyBaseState = nullptr; //!< Media copy state 727 728 union 729 { 730 struct 731 { 732 uint8_t m_cscRequireCopy : 1; //!< bit 0 = 1: raw surface is non-aligned, requires copy 733 uint8_t m_cscRequireColor : 1; //!< bit 1 = 1: raw surface is not NV12 Tile-Y, requires CSC 734 uint8_t m_cscRequireMmc : 1; //!< bit 2 = 1: raw surface is MMC compressed, requires decompression 735 uint8_t m_cscRequireConvTo8bPlanar : 1; //!< bit 3 = 1: raw surface requires 10/8-bit conversion 736 uint8_t m_cscUsingSfc : 1; //!< bit 4 = 1: use SFC to do CSC, only applies to RGB 737 uint8_t reserved1 : 3; 738 }; 739 uint8_t m_cscFlag; //!< the actual CSC/Copy operation to be performed for raw surface 740 }; 741 742 uint8_t m_rawSurfAlignment = 4; //!< Raw surface alignment 743 uint8_t m_mfxReconSurfAlignment = 16; //!< Recon surface alignment for MFX engine 744 uint8_t m_hcpReconSurfAlignment = 8; //!< Recon surface alignment for HCP engine 745 uint32_t m_cscRawSurfWidth = 0; //!< Raw surface allocation width 746 uint32_t m_cscRawSurfHeight = 0; //!< Raw surface allocation height 747 uint32_t m_walkerResolutionX = 0; //!< Media walker resolution X 748 uint32_t m_walkerResolutionY = 0; //!< Media walker resolution Y 749 uint32_t m_cscCurbeLength = 0; //!< CSC kernel Curbe length 750 uint32_t m_cscKernelUID = 0; //!< CSC kernel UID 751 uint32_t m_dsBTCount[2] = { 0 }; //!< DS kernel BTI count 752 uint32_t m_dsCurbeLength[2] = { 0 }; //!< DS kernel Curbe length 753 uint32_t m_dsInlineDataLength = 0; //!< DS kernel inline data length 754 uint32_t m_dsBTISrcY = ds4xSrcYPlane; //!< DS kernel BTI: source Y 755 uint32_t m_dsBTIDstY = ds4xDstYPlane; //!< DS kernel BTI: destination Y 756 uint32_t m_dsBTISrcYTopField = ds4xSrcYPlaneTopField; //!< DS kernel BTI: source Y top filed 757 uint32_t m_dsBTIDstYTopField = ds4xDstYPlaneTopField; //!< DS kernel BTI: destination Y top filed 758 uint32_t m_dsBTISrcYBtmField = ds4xSrcYPlaneBtmField; //!< DS kernel BTI: source Y bottom filed 759 uint32_t m_dsBTIDstYBtmField = ds4xDstYPlaneBtmField; //!< DS kernel BTI: destination Y bottom filed 760 uint32_t m_dsBTIDstFlatness = ds4xDstFlatness; //!< DS kernel BTI: destination flatness 761 uint32_t m_dsBTIDstFlatnessTopField = ds4xDstFlatnessTopField; //!< DS kernel BTI: destination flatness top field 762 uint32_t m_dsBTIDstFlatnessBtmField = ds4xDstFlatnessBtmField; //!< DS kernel BTI: destination flatness bottom field 763 uint32_t m_dsBTIDstMbVProc = ds4xDstMbVProc; //!< DS kernel BTI: destination MbStats 764 uint32_t m_dsBTIDstMbVProcTopField = ds4xDstMbVProcTopField; //!< DS kernel BTI: destination MbStats top filed 765 uint32_t m_dsBTIDstMbVProcBtmField = ds4xDstMbVProcBtmField; //!< DS kernel BTI: destination MbStats bottom filed 766 uint32_t m_combinedKernelSize = 0; //!< Combined kernel size 767 uint8_t* m_kernelBase = nullptr; //!< kernel binary base address 768 uint8_t* m_dsKernelBase = nullptr; //!< kernel binary base address for DS kernel 769 CscColor m_colorRawSurface = cscColorNv12TileY; //!< Raw surface color format 770 CurbeParams m_curbeParams; //!< Curbe param (shared by CSC and DS kernel) 771 SurfaceParamsCsc m_surfaceParamsCsc; //!< CSC surface param 772 SurfaceParamsDS m_surfaceParamsDS; //!< DS surface param 773 774 //! 775 //! Reference to data members in Encoder class 776 //! 777 bool& m_useRawForRef; 778 bool& m_useCommonKernel; 779 bool& m_useHwScoreboard; 780 bool& m_renderContextUsesNullHw; 781 bool& m_groupIdSelectSupported; 782 bool& m_16xMeSupported; 783 bool& m_32xMeSupported; 784 bool& m_scalingEnabled; 785 bool& m_2xScalingEnabled; 786 bool& m_firstField; 787 bool& m_fieldScalingOutputInterleaved; 788 bool& m_flatnessCheckEnabled; 789 bool& m_mbStatsEnabled; 790 bool& m_mbStatsSupported; 791 bool& m_singleTaskPhaseSupported; 792 bool& m_firstTaskInPhase; 793 bool& m_lastTaskInPhase; 794 bool& m_pollingSyncEnabled; 795 uint8_t& m_groupId; 796 uint8_t& m_outputChromaFormat; 797 uint32_t& m_standard; 798 uint32_t& m_mode; 799 uint32_t& m_downscaledWidth4x; 800 uint32_t& m_downscaledHeight4x; 801 uint32_t& m_downscaledWidth16x; 802 uint32_t& m_downscaledHeight16x; 803 uint32_t& m_downscaledWidth32x; 804 uint32_t& m_downscaledHeight32x; 805 uint32_t& m_scaledBottomFieldOffset; 806 uint32_t& m_scaled16xBottomFieldOffset; 807 uint32_t& m_scaled32xBottomFieldOffset; 808 uint32_t& m_mbVProcStatsBottomFieldOffset; 809 uint32_t& m_mbStatsBottomFieldOffset; 810 uint32_t& m_flatnessCheckBottomFieldOffset; 811 uint32_t& m_verticalLineStride; 812 uint32_t& m_maxBtCount; 813 uint32_t& m_vmeStatesSize; 814 uint32_t& m_storeData; 815 uint32_t& m_syncMarkerOffset; 816 uint32_t & m_syncMarkerValue; 817 MOS_GPU_CONTEXT& m_renderContext; 818 MHW_WALKER_MODE& m_walkerMode; 819 CODEC_REF_LIST*& m_currRefList; 820 MOS_RESOURCE& m_resMbStatsBuffer; 821 MOS_SURFACE*& m_rawSurfaceToEnc; 822 MOS_SURFACE*& m_rawSurfaceToPak; 823 824 //! 825 //! \brief CSC kernel binding table 826 //! 827 enum CscKernelBTI 828 { 829 cscSrcYPlane = 0, 830 cscSrcUVPlane = 1, 831 cscDstDsYPlane = 2, 832 cscDstDsUVPlane = 3, 833 cscDstFlatOrMbStats = 4, 834 cscDstCopyYPlane = 5, 835 cscDstCopyUVPlane = 6, 836 cscNumSurfaces = 7 837 }; 838 839 //! 840 //! \brief CSC kernel header struct 841 //! 842 struct CscKernelHeader 843 { 844 int kernelCount = 0; 845 CODECHAL_KERNEL_HEADER header = {}; 846 }; 847 848 //! 849 //! \brief 4xDS kernel binding table 850 //! 851 enum Ds4xKernelBTI 852 { 853 ds4xSrcYPlane = 0, 854 ds4xDstYPlane = 1, 855 ds4xSrcYPlaneTopField = 0, 856 ds4xDstYPlaneTopField = 1, 857 ds4xSrcYPlaneBtmField = 2, 858 ds4xDstYPlaneBtmField = 3, 859 ds4xDstFlatness = 4, 860 ds4xDstFlatnessTopField = 4, 861 ds4xDstFlatnessBtmField = 5, 862 ds4xDstMbVProc = 6, 863 ds4xDstMbVProcTopField = 6, 864 ds4xDstMbVProcBtmField = 7, 865 ds4xNumSurfaces = 8 866 }; 867 868 //! 869 //! \brief 2xDS kernel binding table 870 //! 871 enum Ds2xKernelBTI 872 { 873 ds2xSrcYPlane = 0, 874 ds2xDstYPlane = 1, 875 ds2xSrcYPlaneTopField = 0, 876 ds2xDstYPlaneTopField = 1, 877 ds2xSrcYPlaneBtmField = 2, 878 ds2xDstYPlaneBtmField = 3, 879 ds2xNumSurfaces = 4 880 }; 881 882 //! 883 //! \brief DS kernel Curbe data 884 struct DsKernelInlineData 885 { DsKernelInlineDataDsKernelInlineData886 DsKernelInlineData() 887 { 888 DW04_VideoXScalingStep = 889 DW05_VideoStepDelta = 0.0; 890 DW00 = 891 DW01 = 892 DW02 = 893 DW03 = 894 DW06 = 895 DW07_GroupIDNumber = 896 DW08 = 897 DW09 = 898 DW10 = 899 DW11 = 900 DW12 = 901 DW13_Reserved = 902 DW14_Reserved = 903 DW15_Reserved = 0; 904 } 905 906 // uint32_t 0 - GRF R7.0 907 union 908 { 909 // All 910 struct 911 { 912 uint32_t DestinationBlockHorizontalOrigin : 16; 913 uint32_t DestinationBlockVerticalOrigin : 16; 914 }; 915 // Block Copy 916 struct 917 { 918 uint32_t BlockHeight : 16; 919 uint32_t BufferOffset : 16; 920 }; 921 // FMD Summation 922 struct 923 { 924 uint32_t StartRowOffset; 925 }; 926 uint32_t DW00; 927 }; 928 929 // uint32_t 1 - GRF R7.1 930 union 931 { 932 // Composite 933 struct 934 { 935 uint32_t HorizontalBlockCompositeMaskLayer0 : 16; 936 uint32_t VerticalBlockCompositeMaskLayer0 : 16; 937 }; 938 // FMD Summation 939 struct 940 { 941 uint32_t TotalRows; 942 }; 943 uint32_t DW01; 944 }; 945 946 // uint32_t 2 - GRF R7.2 947 union 948 { 949 // Composite 950 struct 951 { 952 uint32_t HorizontalBlockCompositeMaskLayer1 : 16; 953 uint32_t VerticalBlockCompositeMaskLayer1 : 16; 954 }; 955 // FMD Summation 956 struct 957 { 958 uint32_t StartColumnOffset; 959 }; 960 uint32_t DW02; 961 }; 962 963 // uint32_t 3 - GRF R7.3 964 union 965 { 966 // Composite 967 struct 968 { 969 uint32_t HorizontalBlockCompositeMaskLayer2 : 16; 970 uint32_t VerticalBlockCompositeMaskLayer2 : 16; 971 }; 972 // FMD Summation 973 struct 974 { 975 uint32_t TotalColumns; 976 }; 977 uint32_t DW03; 978 }; 979 980 // uint32_t 4 - GRF R7.4 981 // Sampler Load 982 float DW04_VideoXScalingStep; 983 984 // uint32_t 5 - GRF R7.5 985 // NLAS 986 float DW05_VideoStepDelta; 987 988 // uint32_t 6 - GRF R7.6 989 union 990 { 991 // AVScaling 992 struct 993 { 994 uint32_t VerticalBlockNumber : 17; 995 uint32_t AreaOfInterest : 1; 996 uint32_t : 14; 997 }; 998 uint32_t DW06; 999 }; 1000 1001 // uint32_t 7 - GRF R7.7 1002 // AVScaling 1003 uint32_t DW07_GroupIDNumber; 1004 1005 // uint32_t 8 - GRF R8.0 1006 union 1007 { 1008 // Composite 1009 struct 1010 { 1011 uint32_t HorizontalBlockCompositeMaskLayer3 : 16; 1012 uint32_t VerticalBlockCompositeMaskLayer3 : 16; 1013 }; 1014 uint32_t DW08; 1015 }; 1016 1017 // uint32_t 9 - GRF R8.1 1018 union 1019 { 1020 // Composite 1021 struct 1022 { 1023 uint32_t HorizontalBlockCompositeMaskLayer4 : 16; 1024 uint32_t VerticalBlockCompositeMaskLayer4 : 16; 1025 }; 1026 uint32_t DW09; 1027 }; 1028 1029 // uint32_t 10 - GRF R8.2 1030 union 1031 { 1032 // Composite 1033 struct 1034 { 1035 uint32_t HorizontalBlockCompositeMaskLayer5 : 16; 1036 uint32_t VerticalBlockCompositeMaskLayer5 : 16; 1037 }; 1038 uint32_t DW10; 1039 }; 1040 1041 // uint32_t 11 - GRF R8.3 1042 union 1043 { 1044 // Composite 1045 struct 1046 { 1047 uint32_t HorizontalBlockCompositeMaskLayer6 : 16; 1048 uint32_t VerticalBlockCompositeMaskLayer6 : 16; 1049 }; 1050 uint32_t DW11; 1051 }; 1052 1053 // uint32_t 12 - GRF R8.4 1054 union 1055 { 1056 // Composite 1057 struct 1058 { 1059 uint32_t HorizontalBlockCompositeMaskLayer7 : 16; 1060 uint32_t VerticalBlockCompositeMaskLayer7 : 16; 1061 }; 1062 uint32_t DW12; 1063 }; 1064 1065 // uint32_t 13 - GRF R8.5 1066 uint32_t DW13_Reserved; 1067 1068 // uint32_t 14 - GRF R8.6 1069 uint32_t DW14_Reserved; 1070 1071 // uint32_t 15 - GRF R8.7 1072 uint32_t DW15_Reserved; 1073 }; 1074 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(DsKernelInlineData)) == 16); 1075 1076 //! 1077 //! \brief Check raw surface color format 1078 //! 1079 //! \return MOS_STATUS 1080 //! MOS_STATUS_SUCCESS if success, else fail reason 1081 //! 1082 virtual MOS_STATUS CheckRawColorFormat(MOS_FORMAT format, MOS_TILE_TYPE tileType); 1083 1084 //! 1085 //! \brief Initialize SFC state 1086 //! 1087 //! \return MOS_STATUS 1088 //! MOS_STATUS_SUCCESS if success, else fail reason 1089 //! 1090 virtual MOS_STATUS InitSfcState(); 1091 1092 //! 1093 //! \brief Setup SFC params 1094 //! 1095 //! \return MOS_STATUS 1096 //! MOS_STATUS_SUCCESS if success, else fail reason 1097 //! 1098 MOS_STATUS SetParamsSfc(CODECHAL_ENCODE_SFC_PARAMS* sfcParams); 1099 1100 //! 1101 //! \brief Initialize CSC kernel state 1102 //! 1103 //! \return MOS_STATUS 1104 //! MOS_STATUS_SUCCESS if success, else fail reason 1105 //! 1106 virtual MOS_STATUS InitKernelStateCsc(); 1107 1108 //! 1109 //! \brief Setup Gen-specific kernel params 1110 //! 1111 //! \return MOS_STATUS 1112 //! MOS_STATUS_SUCCESS if success, else fail reason 1113 //! 1114 virtual MOS_STATUS SetKernelParamsCsc(KernelParams* params); 1115 1116 //! 1117 //! \brief Setup Curbe 1118 //! 1119 //! \return MOS_STATUS 1120 //! MOS_STATUS_SUCCESS if success, else fail reason 1121 //! 1122 virtual MOS_STATUS SetCurbeCsc(); 1123 1124 //! 1125 //! \brief Send surface for CSC kernel 1126 //! 1127 //! \return MOS_STATUS 1128 //! MOS_STATUS_SUCCESS if success, else fail reason 1129 //! 1130 virtual MOS_STATUS SendSurfaceCsc(PMOS_COMMAND_BUFFER cmdBuffer); 1131 1132 //! 1133 //! \brief Setup Curbe for DS kernel 1134 //! 1135 //! \return MOS_STATUS 1136 //! MOS_STATUS_SUCCESS if success, else fail reason 1137 //! 1138 virtual MOS_STATUS SetCurbeDS2x(); 1139 1140 //! 1141 //! \brief Send surface for DS kernel 1142 //! 1143 //! \return MOS_STATUS 1144 //! MOS_STATUS_SUCCESS if success, else fail reason 1145 //! 1146 MOS_STATUS SendSurfaceDS(PMOS_COMMAND_BUFFER cmdBuffer); 1147 1148 //! 1149 //! \brief Set walker command 1150 //! 1151 //! \return MOS_STATUS 1152 //! MOS_STATUS_SUCCESS if success, else fail reason 1153 //! SetWalkerCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_KERNEL_STATE * kernelState)1154 virtual MOS_STATUS SetWalkerCmd( 1155 MOS_COMMAND_BUFFER *cmdBuffer, 1156 MHW_KERNEL_STATE *kernelState) 1157 { 1158 return MOS_STATUS_SUCCESS; 1159 } 1160 1161 union 1162 { 1163 struct 1164 { 1165 uint8_t m_cscEnableCopy : 1; //!< bit 0 = 1: Ds+Copy kernel is enabled to copy non-aligned raw surface 1166 uint8_t m_cscEnableColor : 1; //!< bit 1 = 1: Ds+Copy kernel is enabled to perform CSC 1167 uint8_t m_cscEnableMmc : 1; //!< bit 2 = 1: Ds+Copy kernel is enabled to decompress MMC raw surface 1168 uint8_t m_cscEnableSfc : 1; //!< bit 3 = 1: VEBOX is enabled to perform ARGB CSC 1169 uint8_t m_cscEnableMediaCopy : 1; //!< bit 4 = 1: Media Copy is enabled to copy non-aligned raw surface 1170 uint8_t reserved : 3; 1171 }; 1172 uint8_t m_cscDsConvEnable; 1173 }; 1174 1175 uint32_t m_threadTraverseSizeX = 5; //!< target traverse thread space size in width 1176 uint32_t m_threadTraverseSizeY = 2; //!< target traverse thread space size in height 1177 }; 1178 1179 #endif // __CODECHAL_ENCODE_CSC_DS_H__ 1180