1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_encode_hevc_base.h 24 //! \brief Defines base class for HEVC encoder. 25 //! 26 27 #ifndef __CODECHAL_ENCODE_HEVC_BASE_H__ 28 #define __CODECHAL_ENCODE_HEVC_BASE_H__ 29 30 #include "codechal_encoder_base.h" 31 32 #if USE_CODECHAL_DEBUG_TOOL 33 #include "codechal_debug_encode_par.h" 34 #endif 35 36 //*------------------------------------------------------------------------------ 37 //* Codec Definitions 38 //*------------------------------------------------------------------------------ 39 #define CODECHAL_HEVC_MAX_SPS_NUM 16 40 #define CODECHAL_HEVC_MAX_PPS_NUM 64 41 #define CODECHAL_VDENC_HEVC_MAX_SLICE_NUM 70 42 43 #define CODECHAL_HEVC_MAX_LCU_SIZE_G9 32 44 #define CODECHAL_HEVC_MIN_LCU_SIZE 16 45 #define CODECHAL_HEVC_MIN_CU_SIZE 8 46 #define CODECHAL_HEVC_MIN_TILE_SIZE 128 47 #define CODECHAL_HEVC_FRAME_BRC_BLOCK_SIZE 32 48 #define CODECHAL_HEVC_LCU_BRC_BLOCK_SIZE 128 49 50 #define CODECHAL_ENCODE_HEVC_NUM_MAX_VME_L0_REF_G9 3 51 #define CODECHAL_ENCODE_HEVC_NUM_MAX_VME_L1_REF_G9 1 52 53 #define CODECHAL_ENCODE_HEVC_NUM_MAX_VME_L0_REF_G10 4 54 #define CODECHAL_ENCODE_HEVC_NUM_MAX_VME_L1_REF_G10 4 55 56 #define CODECHAL_ENCODE_HEVC_MAX_NUM_WEIGHTED_PRED_L0 1 57 #define CODECHAL_ENCODE_HEVC_MAX_NUM_WEIGHTED_PRED_L1 1 58 59 #define CODECHAL_HEVC_MAX_NUM_HCP_PIPE 8 60 #define CODECHAL_HEVC_MAX_NUM_BRC_PASSES 4 // It doesn't include the 5th PAK pass for the BRC panic mode 61 62 #define ENCODE_HEVC_4K_PIC_WIDTH 3840 63 #define ENCODE_HEVC_4K_PIC_HEIGHT 2160 64 65 #define ENCODE_HEVC_5K_PIC_WIDTH 5120 66 #define ENCODE_HEVC_5K_PIC_HEIGHT 2880 67 68 #define ENCODE_HEVC_8K_PIC_WIDTH 7680 69 #define ENCODE_HEVC_8K_PIC_HEIGHT 4320 70 71 #define ENCODE_HEVC_16K_PIC_WIDTH 16384 72 #define ENCODE_HEVC_16K_PIC_HEIGHT 4096 73 74 // Max supported resolution for HEVC encode is 4K X 2K 75 #define ENCODE_HEVC_MAX_4K_PIC_WIDTH 4096 76 #define ENCODE_HEVC_MAX_4K_PIC_HEIGHT 2176 77 78 #define ENCODE_HEVC_MAX_8K_PIC_WIDTH 8192 79 #define ENCODE_HEVC_MAX_8K_PIC_HEIGHT 8192 80 81 #define ENCODE_HEVC_MAX_16K_PIC_WIDTH 16384 82 #define ENCODE_HEVC_MAX_16K_PIC_HEIGHT 16384 83 84 #define ENCODE_HEVC_MIN_DSS_PIC_WIDTH 480 85 #define ENCODE_HEVC_MIN_DSS_PIC_HEIGHT 320 86 87 // HEVC has only 3 target usage modes 88 #define CODECHAL_ENCODE_HEVC_TARGET_USAGE_MODE_PERFORMANCE 0 89 #define CODECHAL_ENCODE_HEVC_TARGET_USAGE_MODE_NORMAL 1 90 #define CODECHAL_ENCODE_HEVC_TARGET_USAGE_MODE_QUALITY 2 91 92 #define HEVC_BRC_CONSTANT_SURFACE_WIDTH_G9 (64) 93 #define HEVC_BRC_CONSTANT_SURFACE_HEIGHT_G9 (53) 94 #define HEVC_BRC_HISTORY_BUFFER_SIZE_G9 (576) 95 #define HEVC_BRC_HISTORY_BUFFER_SIZE_G10 (832) 96 #define HEVC_BRC_HISTORY_BUFFER_SIZE_G12 (1088) 97 #define HEVC_BRC_CONSTANT_SURFACE_HEIGHT_G10 (35) 98 99 #define CODECHAL_HEVC_NUM_PAK_SLICE_BATCH_BUFFERS (3) 100 #define HEVC_CONCURRENT_SURFACE_HEIGHT (32) 101 #define HEVC_BRC_SKIP_VAL_TABLE_SIZE (128) 102 #define HEVC_BRC_LAMBDA_TABLE_SIZE (1024) 103 #define HEVC_BRC_MVMODE_TABLE_SIZE (1664) 104 #define CODECHAL_INIT_DSH_SIZE_HEVC_ENC (MHW_PAGE_SIZE * 2) 105 #define HEVC_START_CODE_NAL_OFFSET (2) 106 #define HEVC_PAK_STATISTICS_SSE_OFFSET (32) 107 108 #define CODECHAL_ENCODE_HEVC_MAX_SLICE_QP 51 109 110 #define CODECHAL_ENCODE_HEVC_MIN_ICQ_QUALITYFACTOR 1 111 #define CODECHAL_ENCODE_HEVC_MAX_ICQ_QUALITYFACTOR 51 112 113 #define CODECHAL_ENCODE_HEVC_NUM_SYNC_TAGS 36 114 115 #define CODECHAL_ENCODE_HEVC_DEFAULT_AVBR_ACCURACY 30 116 #define CODECHAL_ENCODE_HEVC_DEFAULT_AVBR_CONVERGENCE 150 117 118 // Hevc always uses maxMvLen corresponding to AVC level 51. Refer GetMaxMvLen from AVC. 119 #define CODECHAL_ENCODE_HEVC_MAX_MV_LEN_AVC_LEVEL_51 511 120 121 #define CODECHAL_ENCODE_HEVC_GET_SIZE_IN_LCU(var, lcu_size) \ 122 ((var + (lcu_size - 1)) / lcu_size) 123 124 #define CODECHAL_HEVC_PAK_STREAMOUT_SIZE 0x500000 //size is accounted for 4Kx4K with all 8x8 CU,based on streamout0 and streamout1 requirements 125 //(4096*4096)/64 *16 (streamout0) + 1MB(streamout 1). there is scope to reduce streamout1 size. Need to check with HW team. 126 // 8K is just an estimation 127 #define CODECHAL_HEVC_BRC_QP_ADJUST_SIZE 576 128 129 #define CODECHAL_ENCODE_HEVC_NUM_MAX_VDENC_L0_REF_G10 3 // multiref, hevc vdenc 130 #define CODECHAL_ENCODE_HEVC_NUM_MAX_VDENC_L1_REF_G10 3 // multiref, hevc vdenc 131 132 #define CODECHAL_VDENC_HEVC_BRC_DEBUG_BUF_SIZE 0x1000 // 0x1000 = 4096 133 #define CODECHAL_VDENC_HEVC_BRC_HUC_STATUS_ERROR_MASK (1<<30) 134 #define CODECHAL_VDENC_HEVC_BRC_HUC_STATUS_ARITHMETIC_OVERFLOW_ERROR_MASK (1<<29) 135 #define CODECHAL_VDENC_HEVC_BRC_HUC_STATUS_MEMORY_ACCESS_ERROR_MASK (1<<28) 136 #define CODECHAL_VDENC_HEVC_BRC_HUC_STATUS_HISTORY_BUFFER_ERROR_MASK (1<<27) 137 #define CODECHAL_VDENC_HEVC_BRC_HUC_STATUS_DMEM_ERROR_MASK (1<<26) 138 139 #define CODECHAL_VDENC_HEVC_BRC_PAK_STATS_BUF_SIZE 464 // 116 DWORDs HEVC Frame Statistics 140 141 const char QPcTable[22] = { 29, 30, 31, 32, 32, 33, 34, 34, 35, 35, 36, 36, 37, 37, 37, 38, 38, 38, 39, 39, 39, 39 }; 142 143 const unsigned char g_cInit_HEVC_BRC_QP_ADJUST[CODECHAL_HEVC_BRC_QP_ADJUST_SIZE] = { 144 0x01, 0x02, 0x03, 0x05, 0x06, 0x01, 0x01, 0x02, 0x03, 0x05, 0x00, 0x00, 0x01, 0x02, 0x03, 0xff, 145 0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xfe, 0xfe, 0xff, 0x00, 0x01, 0xfd, 0xfd, 146 0xff, 0xff, 0x00, 0xfb, 0xfd, 0xfe, 0xff, 0xff, 0xfa, 0xfb, 0xfd, 0xfe, 0xff, 0x00, 0x04, 0x1e, 147 0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 148 149 0x01, 0x02, 0x03, 0x05, 0x06, 0x01, 0x01, 0x02, 0x03, 0x05, 0x00, 0x01, 0x01, 0x02, 0x03, 0xff, 150 0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0x00, 0x01, 0xfe, 0xff, 151 0xff, 0xff, 0x00, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0xfb, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x04, 0x1e, 152 0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x04, 0x05, 0x06, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 153 154 0x01, 0x01, 0x02, 0x04, 0x05, 0x01, 0x01, 0x01, 0x02, 0x04, 0x00, 0x00, 0x01, 0x01, 0x02, 0xff, 155 0x00, 0x00, 0x01, 0x01, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0x01, 0xfe, 0xff, 156 0xff, 0xff, 0x00, 0xfd, 0xfe, 0xff, 0xff, 0x00, 0xfb, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x02, 0x14, 157 0x28, 0x46, 0x82, 0xa0, 0xc8, 0xff, 0x04, 0x04, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 158 159 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 160 0x03, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x03, 0xff, 0xff, 0x00, 0x00, 0x00, 161 0x01, 0x02, 0x02, 0x02, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0xfe, 0xff, 0xff, 162 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 163 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0xfe, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 164 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 166 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 167 168 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 169 0x03, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x03, 0xff, 0xff, 0x00, 0x00, 0x00, 170 0x01, 0x02, 0x02, 0x02, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0xfe, 0xff, 0xff, 171 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 172 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0xfe, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 173 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 174 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 176 177 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 178 0x03, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x03, 0xff, 0xff, 0x00, 0x00, 0x00, 179 0x01, 0x02, 0x02, 0x02, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0xfe, 0xff, 0xff, 180 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 181 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0xfe, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 182 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 185 }; 186 187 const uint16_t SLCSZ_THRDELTAI_U16[52] = 188 { //assuming Mb lag = 8 189 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[0-9] 190 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[10-19] 191 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[20-29] 192 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[30-39] 193 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[40-49] 194 100, 100 //[50-51] 195 }; 196 197 const uint16_t SLCSZ_THRDELTAP_U16[52] = 198 { //assuming Mb lag = 6 199 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[0-9] 200 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[10-19] 201 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[20-29] 202 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[30-39] 203 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[40-49] 204 100, 100 //[50-51] 205 }; 206 207 enum 208 { 209 // 2x down-scaling kernel 210 CODECHAL_HEVC_SCALING_FRAME_BEGIN = 0, 211 CODECHAL_HEVC_SCALING_FRAME_SRC_Y = CODECHAL_HEVC_SCALING_FRAME_BEGIN + 0, 212 CODECHAL_HEVC_SCALING_FRAME_DST_Y = CODECHAL_HEVC_SCALING_FRAME_BEGIN + 1, 213 CODECHAL_HEVC_SCALING_FRAME_END = CODECHAL_HEVC_SCALING_FRAME_BEGIN + 2, 214 215 // 32x32 PU mode decision kernel 216 CODECHAL_HEVC_32x32_PU_BEGIN = CODECHAL_HEVC_SCALING_FRAME_END, 217 CODECHAL_HEVC_32x32_PU_OUTPUT = CODECHAL_HEVC_32x32_PU_BEGIN + 0, 218 CODECHAL_HEVC_32x32_PU_SRC_Y = CODECHAL_HEVC_32x32_PU_BEGIN + 1, 219 CODECHAL_HEVC_32x32_PU_SRC_UV = CODECHAL_HEVC_32x32_PU_BEGIN + 2, 220 CODECHAL_HEVC_32x32_PU_SRC_Y2x = CODECHAL_HEVC_32x32_PU_BEGIN + 3, 221 CODECHAL_HEVC_32x32_PU_SLICE_MAP = CODECHAL_HEVC_32x32_PU_BEGIN + 4, 222 CODECHAL_HEVC_32x32_PU_SRC_Y2x_VME = CODECHAL_HEVC_32x32_PU_BEGIN + 5, 223 CODECHAL_HEVC_32x32_PU_BRC_Input = CODECHAL_HEVC_32x32_PU_BEGIN + 6, 224 CODECHAL_HEVC_32x32_PU_LCU_QP = CODECHAL_HEVC_32x32_PU_BEGIN + 7, 225 CODECHAL_HEVC_32x32_PU_BRC_DATA = CODECHAL_HEVC_32x32_PU_BEGIN + 8, 226 CODECHAL_HEVC_32x32_PU_STATS_DATA = CODECHAL_HEVC_32x32_PU_BEGIN + 9, 227 CODECHAL_HEVC_32x32_PU_DEBUG = CODECHAL_HEVC_32x32_PU_BEGIN + 10, 228 CODECHAL_HEVC_32x32_PU_END = CODECHAL_HEVC_32x32_PU_BEGIN + 11, 229 230 // 16x16 SAD computation kernel 231 CODECHAL_HEVC_16x16_PU_SAD_BEGIN = CODECHAL_HEVC_32x32_PU_END, 232 CODECHAL_HEVC_16x16_PU_SAD_SRC_Y = CODECHAL_HEVC_16x16_PU_SAD_BEGIN + 0, 233 CODECHAL_HEVC_16x16_PU_SAD_SRC_UV = CODECHAL_HEVC_16x16_PU_SAD_BEGIN + 1, 234 CODECHAL_HEVC_16x16_PU_SAD_OUTPUT = CODECHAL_HEVC_16x16_PU_SAD_BEGIN + 2, 235 CODECHAL_HEVC_16x16_PU_SAD_32x32_MD_DATA = CODECHAL_HEVC_16x16_PU_SAD_BEGIN + 3, 236 CODECHAL_HEVC_16x16_PU_SLICE_MAP = CODECHAL_HEVC_16x16_PU_SAD_BEGIN + 4, 237 CODECHAL_HEVC_16x16_PU_Simplest_Intra = CODECHAL_HEVC_16x16_PU_SAD_BEGIN + 5, 238 CODECHAL_HEVC_16x16_PU_SAD_DEBUG = CODECHAL_HEVC_16x16_PU_SAD_BEGIN + 6, 239 CODECHAL_HEVC_16x16_PU_SAD_END = CODECHAL_HEVC_16x16_PU_SAD_BEGIN + 7, 240 241 // 16x16 PU mode decision kernel 242 CODECHAL_HEVC_16x16_PU_MD_BEGIN = CODECHAL_HEVC_16x16_PU_SAD_END, 243 CODECHAL_HEVC_16x16_PU_MD_SRC_Y = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 0, 244 CODECHAL_HEVC_16x16_PU_MD_SRC_UV = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 1, 245 CODECHAL_HEVC_16x16_PU_MD_16x16_SAD_DATA = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 2, 246 CODECHAL_HEVC_16x16_PU_MD_PAK_OBJ = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 3, 247 CODECHAL_HEVC_16x16_PU_MD_32x32_MD_DATA = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 4, 248 CODECHAL_HEVC_16x16_PU_MD_VME_8x8_MD_DATA = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 5, 249 CODECHAL_HEVC_16x16_PU_MD_SLICE_MAP = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 6, 250 CODECHAL_HEVC_16x16_PU_MD_VME_SRC = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 7, 251 CODECHAL_HEVC_16x16_PU_MD_BRC_Input = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 8, 252 CODECHAL_HEVC_16x16_PU_MD_Simplest_Intra = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 9, 253 CODECHAL_HEVC_16x16_PU_MD_LCU_QP = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 10, 254 CODECHAL_HEVC_16x16_PU_MD_BRC_Data = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 11, 255 CODECHAL_HEVC_16x16_PU_MD_DEBUG = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 12, 256 CODECHAL_HEVC_16x16_PU_MD_END = CODECHAL_HEVC_16x16_PU_MD_BEGIN + 13, 257 258 // 8x8 PU kernel 259 CODECHAL_HEVC_8x8_PU_BEGIN = CODECHAL_HEVC_16x16_PU_MD_END, 260 CODECHAL_HEVC_8x8_PU_SRC_Y = CODECHAL_HEVC_8x8_PU_BEGIN + 0, 261 CODECHAL_HEVC_8x8_PU_SRC_UV = CODECHAL_HEVC_8x8_PU_BEGIN + 1, 262 CODECHAL_HEVC_8x8_PU_SLICE_MAP = CODECHAL_HEVC_8x8_PU_BEGIN + 2, 263 CODECHAL_HEVC_8x8_PU_VME_8x8_MODE = CODECHAL_HEVC_8x8_PU_BEGIN + 3, 264 CODECHAL_HEVC_8x8_PU_INTRA_MODE = CODECHAL_HEVC_8x8_PU_BEGIN + 4, 265 CODECHAL_HEVC_8x8_PU_BRC_Input = CODECHAL_HEVC_8x8_PU_BEGIN + 5, 266 CODECHAL_HEVC_8x8_PU_Simplest_Intra = CODECHAL_HEVC_8x8_PU_BEGIN + 6, 267 CODECHAL_HEVC_8x8_PU_LCU_QP = CODECHAL_HEVC_8x8_PU_BEGIN + 7, 268 CODECHAL_HEVC_8x8_PU_BRC_Data = CODECHAL_HEVC_8x8_PU_BEGIN + 8, 269 CODECHAL_HEVC_8x8_PU_DEBUG = CODECHAL_HEVC_8x8_PU_BEGIN + 9, 270 CODECHAL_HEVC_8x8_PU_END = CODECHAL_HEVC_8x8_PU_BEGIN + 10, 271 272 // 8x8 PU FMODE kernel 273 CODECHAL_HEVC_8x8_PU_FMODE_BEGIN = CODECHAL_HEVC_8x8_PU_END, 274 CODECHAL_HEVC_8x8_PU_FMODE_PAK_OBJECT = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 0, 275 CODECHAL_HEVC_8x8_PU_FMODE_VME_8x8_MODE = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 1, 276 CODECHAL_HEVC_8x8_PU_FMODE_INTRA_MODE = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 2, 277 CODECHAL_HEVC_8x8_PU_FMODE_PAK_COMMAND = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 3, 278 CODECHAL_HEVC_8x8_PU_FMODE_SLICE_MAP = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 4, 279 CODECHAL_HEVC_8x8_PU_FMODE_INTRADIST = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 5, 280 CODECHAL_HEVC_8x8_PU_FMODE_BRC_Input = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 6, 281 CODECHAL_HEVC_8x8_PU_FMODE_Simplest_Intra = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 7, 282 CODECHAL_HEVC_8x8_PU_FMODE_LCU_QP = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 8, 283 CODECHAL_HEVC_8x8_PU_FMODE_BRC_Data = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 9, 284 CODECHAL_HEVC_8x8_PU_FMODE_HAAR_DIST16x16 = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 10, 285 CODECHAL_HEVC_8x8_PU_FMODE_STATS_DATA = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 11, 286 CODECHAL_HEVC_8x8_PU_FMODE_FRAME_STATS_DATA = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 12, 287 CODECHAL_HEVC_8x8_PU_FMODE_DEBUG = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 13, 288 CODECHAL_HEVC_8x8_PU_FMODE_END = CODECHAL_HEVC_8x8_PU_FMODE_BEGIN + 14, 289 290 // B 32x32 PU intra check kernel 291 CODECHAL_HEVC_B_32x32_PU_BEGIN = CODECHAL_HEVC_8x8_PU_FMODE_END, 292 CODECHAL_HEVC_B_32x32_PU_OUTPUT = CODECHAL_HEVC_B_32x32_PU_BEGIN + 0, 293 CODECHAL_HEVC_B_32x32_PU_SRC_Y = CODECHAL_HEVC_B_32x32_PU_BEGIN + 1, 294 CODECHAL_HEVC_B_32x32_PU_SRC_UV = CODECHAL_HEVC_B_32x32_PU_BEGIN + 2, 295 CODECHAL_HEVC_B_32x32_PU_SRC_Y2x = CODECHAL_HEVC_B_32x32_PU_BEGIN + 3, 296 CODECHAL_HEVC_B_32x32_PU_SLICE_MAP = CODECHAL_HEVC_B_32x32_PU_BEGIN + 4, 297 CODECHAL_HEVC_B_32x32_PU_SRC_Y2x_VME = CODECHAL_HEVC_B_32x32_PU_BEGIN + 5, 298 CODECHAL_HEVC_B_32x32_PU_Simplest_Intra = CODECHAL_HEVC_B_32x32_PU_BEGIN + 6, 299 CODECHAL_HEVC_B_32x32_PU_HME_MVP = CODECHAL_HEVC_B_32x32_PU_BEGIN + 7, 300 CODECHAL_HEVC_B_32x32_PU_HME_DIST = CODECHAL_HEVC_B_32x32_PU_BEGIN + 8, 301 CODECHAL_HEVC_B_32x32_PU_LCU_SKIP = CODECHAL_HEVC_B_32x32_PU_BEGIN + 9, 302 CODECHAL_HEVC_B_32x32_PU_DEBUG = CODECHAL_HEVC_B_32x32_PU_BEGIN + 10, 303 CODECHAL_HEVC_B_32x32_PU_END = CODECHAL_HEVC_B_32x32_PU_BEGIN + 11, 304 305 // B MB ENC kernel 306 CODECHAL_HEVC_B_MBENC_BEGIN = CODECHAL_HEVC_B_32x32_PU_END, 307 CODECHAL_HEVC_B_MBENC_CU_RECORD = CODECHAL_HEVC_B_MBENC_BEGIN + 0, 308 CODECHAL_HEVC_B_MBENC_PAK_CMD = CODECHAL_HEVC_B_MBENC_BEGIN + 1, 309 CODECHAL_HEVC_B_MBENC_SRC_Y = CODECHAL_HEVC_B_MBENC_BEGIN + 2, 310 CODECHAL_HEVC_B_MBENC_SRC_UV = CODECHAL_HEVC_B_MBENC_BEGIN + 3, 311 CODECHAL_HEVC_B_MBENC_INTRA_DIST = CODECHAL_HEVC_B_MBENC_BEGIN + 4, 312 CODECHAL_HEVC_B_MBENC_MIN_DIST = CODECHAL_HEVC_B_MBENC_BEGIN + 5, 313 CODECHAL_HEVC_B_MBENC_HME_MVP = CODECHAL_HEVC_B_MBENC_BEGIN + 6, 314 CODECHAL_HEVC_B_MBENC_HME_DIST = CODECHAL_HEVC_B_MBENC_BEGIN + 7, 315 CODECHAL_HEVC_B_MBENC_SLICE_MAP = CODECHAL_HEVC_B_MBENC_BEGIN + 8, 316 CODECHAL_HEVC_B_MBENC_VME_UNISIC_DATA = CODECHAL_HEVC_B_MBENC_BEGIN + 9, 317 CODECHAL_HEVC_B_MBENC_Simplest_Intra = CODECHAL_HEVC_B_MBENC_BEGIN + 10, 318 CODECHAL_HEVC_B_MBENC_REF_COLLOC = CODECHAL_HEVC_B_MBENC_BEGIN + 11, 319 CODECHAL_HEVC_B_MBENC_Reserved = CODECHAL_HEVC_B_MBENC_BEGIN + 12, 320 CODECHAL_HEVC_B_MBENC_BRC_Input = CODECHAL_HEVC_B_MBENC_BEGIN + 13, 321 CODECHAL_HEVC_B_MBENC_LCU_QP = CODECHAL_HEVC_B_MBENC_BEGIN + 14, 322 CODECHAL_HEVC_B_MBENC_BRC_DATA = CODECHAL_HEVC_B_MBENC_BEGIN + 15, 323 // 324 CODECHAL_HEVC_B_MBENC_VME_CURRENT = CODECHAL_HEVC_B_MBENC_BEGIN + 16, 325 CODECHAL_HEVC_B_MBENC_VME_FORWARD_0 = CODECHAL_HEVC_B_MBENC_BEGIN + 17, 326 CODECHAL_HEVC_B_MBENC_VME_BACKWARD_0 = CODECHAL_HEVC_B_MBENC_BEGIN + 18, 327 CODECHAL_HEVC_B_MBENC_VME_FORWARD_1 = CODECHAL_HEVC_B_MBENC_BEGIN + 19, 328 CODECHAL_HEVC_B_MBENC_VME_BACKWARD_1 = CODECHAL_HEVC_B_MBENC_BEGIN + 20, 329 CODECHAL_HEVC_B_MBENC_VME_FORWARD_2 = CODECHAL_HEVC_B_MBENC_BEGIN + 21, 330 CODECHAL_HEVC_B_MBENC_VME_BACKWARD_2 = CODECHAL_HEVC_B_MBENC_BEGIN + 22, 331 CODECHAL_HEVC_B_MBENC_VME_FORWARD_3 = CODECHAL_HEVC_B_MBENC_BEGIN + 23, 332 CODECHAL_HEVC_B_MBENC_VME_BACKWARD_3 = CODECHAL_HEVC_B_MBENC_BEGIN + 24, 333 CODECHAL_HEVC_B_MBENC_VME_FORWARD_4 = CODECHAL_HEVC_B_MBENC_BEGIN + 25, 334 CODECHAL_HEVC_B_MBENC_VME_BACKWARD_4 = CODECHAL_HEVC_B_MBENC_BEGIN + 26, 335 CODECHAL_HEVC_B_MBENC_VME_FORWARD_5 = CODECHAL_HEVC_B_MBENC_BEGIN + 27, 336 CODECHAL_HEVC_B_MBENC_VME_BACKWARD_5 = CODECHAL_HEVC_B_MBENC_BEGIN + 28, 337 CODECHAL_HEVC_B_MBENC_VME_FORWARD_6 = CODECHAL_HEVC_B_MBENC_BEGIN + 29, 338 CODECHAL_HEVC_B_MBENC_VME_BACKWARD_6 = CODECHAL_HEVC_B_MBENC_BEGIN + 30, 339 CODECHAL_HEVC_B_MBENC_VME_FORWARD_7 = CODECHAL_HEVC_B_MBENC_BEGIN + 31, 340 CODECHAL_HEVC_B_MBENC_VME_BACKWARD_7 = CODECHAL_HEVC_B_MBENC_BEGIN + 32, 341 // 342 CODECHAL_HEVC_B_MBENC_VME_MUL_CURRENT = CODECHAL_HEVC_B_MBENC_BEGIN + 33, 343 CODECHAL_HEVC_B_MBENC_VME_MUL_BACKWARD_0 = CODECHAL_HEVC_B_MBENC_BEGIN + 34, 344 CODECHAL_HEVC_B_MBENC_VME_MUL_NOUSE_0 = CODECHAL_HEVC_B_MBENC_BEGIN + 35, 345 CODECHAL_HEVC_B_MBENC_VME_MUL_BACKWARD_1 = CODECHAL_HEVC_B_MBENC_BEGIN + 36, 346 CODECHAL_HEVC_B_MBENC_VME_MUL_NOUSE_1 = CODECHAL_HEVC_B_MBENC_BEGIN + 37, 347 CODECHAL_HEVC_B_MBENC_VME_MUL_BACKWARD_2 = CODECHAL_HEVC_B_MBENC_BEGIN + 38, 348 CODECHAL_HEVC_B_MBENC_VME_MUL_NOUSE_2 = CODECHAL_HEVC_B_MBENC_BEGIN + 39, 349 CODECHAL_HEVC_B_MBENC_VME_MUL_BACKWARD_3 = CODECHAL_HEVC_B_MBENC_BEGIN + 40, 350 CODECHAL_HEVC_B_MBENC_VME_MUL_NOUSE_3 = CODECHAL_HEVC_B_MBENC_BEGIN + 41, 351 // 352 CODECHAL_HEVC_B_MBENC_CONCURRENT_THD_MAP = CODECHAL_HEVC_B_MBENC_BEGIN + 42, 353 CODECHAL_HEVC_B_MBENC_MV_IDX = CODECHAL_HEVC_B_MBENC_BEGIN + 43, 354 CODECHAL_HEVC_B_MBENC_MVP_IDX = CODECHAL_HEVC_B_MBENC_BEGIN + 44, 355 CODECHAL_HEVC_B_MBENC_HAAR_DIST16x16 = CODECHAL_HEVC_B_MBENC_BEGIN + 45, 356 CODECHAL_HEVC_B_MBENC_STATS_DATA = CODECHAL_HEVC_B_MBENC_BEGIN + 46, 357 CODECHAL_HEVC_B_MBENC_FRAME_STATS_DATA = CODECHAL_HEVC_B_MBENC_BEGIN + 47, 358 CODECHAL_HEVC_B_MBENC_DEBUG = CODECHAL_HEVC_B_MBENC_BEGIN + 48, 359 // 360 CODECHAL_HEVC_B_MBENC_END = CODECHAL_HEVC_B_MBENC_BEGIN + 49, 361 362 //Coarse Intra distortion 363 CODECHAL_HEVC_COARSE_INTRA_BEGIN = CODECHAL_HEVC_B_MBENC_END, 364 CODECHAL_HEVC_COARSE_INTRA_Y4 = CODECHAL_HEVC_COARSE_INTRA_BEGIN + 0, 365 CODECHAL_HEVC_COARSE_INTRA_DISTORTION = CODECHAL_HEVC_COARSE_INTRA_BEGIN + 1, 366 CODECHAL_HEVC_COARSE_INTRA_VME_Y4 = CODECHAL_HEVC_COARSE_INTRA_BEGIN + 2, 367 CODECHAL_HEVC_COARSE_INTRA_END = CODECHAL_HEVC_COARSE_INTRA_BEGIN + 3, 368 369 // HEVC B PAK kernel 370 CODECHAL_HEVC_B_PAK_BEGIN = CODECHAL_HEVC_COARSE_INTRA_END, 371 CODECHAL_HEVC_B_PAK_CU_RECORD = CODECHAL_HEVC_B_PAK_BEGIN + 0, 372 CODECHAL_HEVC_B_PAK_PAK_OBJ = CODECHAL_HEVC_B_PAK_BEGIN + 1, 373 CODECHAL_HEVC_B_PAK_SLICE_MAP = CODECHAL_HEVC_B_PAK_BEGIN + 2, 374 CODECHAL_HEVC_B_PAK_BRC_INPUT = CODECHAL_HEVC_B_PAK_BEGIN + 3, 375 CODECHAL_HEVC_B_PAK_LCU_QP = CODECHAL_HEVC_B_PAK_BEGIN + 4, 376 CODECHAL_HEVC_B_PAK_BRC_DATA = CODECHAL_HEVC_B_PAK_BEGIN + 5, 377 CODECHAL_HEVC_B_PAK_MB_DATA = CODECHAL_HEVC_B_PAK_BEGIN + 6, 378 CODECHAL_HEVC_B_PAK_MVP_DATA = CODECHAL_HEVC_B_PAK_BEGIN + 7, 379 CODECHAL_HEVC_B_PAK_WA_PAK_DATA = CODECHAL_HEVC_B_PAK_BEGIN + 8, 380 CODECHAL_HEVC_B_PAK_WA_PAK_OBJ = CODECHAL_HEVC_B_PAK_BEGIN + 9, 381 CODECHAL_HEVC_B_PAK_DEBUG = CODECHAL_HEVC_B_PAK_BEGIN + 10, 382 CODECHAL_HEVC_B_PAK_END = CODECHAL_HEVC_B_PAK_BEGIN + 11, 383 384 //HEVC FORMAT CONVERSION AND DOWNSCALING KERNEL 385 CODECHAL_HEVC_DS_COMBINED_BEGIN = CODECHAL_HEVC_B_PAK_END, 386 CODECHAL_HEVC_DS_COMBINED_10BIT_Y = CODECHAL_HEVC_DS_COMBINED_BEGIN + 0, 387 CODECHAL_HEVC_DS_COMBINED_10BIT_UV = CODECHAL_HEVC_DS_COMBINED_BEGIN + 1, 388 CODECHAL_HEVC_DS_COMBINED_8BIT_Y = CODECHAL_HEVC_DS_COMBINED_BEGIN + 2, 389 CODECHAL_HEVC_DS_COMBINED_8BIT_UV = CODECHAL_HEVC_DS_COMBINED_BEGIN + 3, 390 CODECHAL_HEVC_DS_COMBINED_4xDOWNSCALE = CODECHAL_HEVC_DS_COMBINED_BEGIN + 4, 391 CODECHAL_HEVC_DS_COMBINED_MB_STATS = CODECHAL_HEVC_DS_COMBINED_BEGIN + 5, 392 CODECHAL_HEVC_DS_COMBINED_2xDOWNSCALE = CODECHAL_HEVC_DS_COMBINED_BEGIN + 6, 393 CODECHAL_HEVC_DS_COMBINED_END = CODECHAL_HEVC_DS_COMBINED_BEGIN + 7, 394 395 //BRC Init/Reset 396 CODECHAL_HEVC_BRC_INIT_RESET_BEGIN = CODECHAL_HEVC_DS_COMBINED_END, 397 CODECHAL_HEVC_BRC_INIT_RESET_HISTORY = CODECHAL_HEVC_BRC_INIT_RESET_BEGIN + 0, 398 CODECHAL_HEVC_BRC_INIT_RESET_DISTORTION = CODECHAL_HEVC_BRC_INIT_RESET_BEGIN + 1, 399 CODECHAL_HEVC_BRC_INIT_RESET_END = CODECHAL_HEVC_BRC_INIT_RESET_BEGIN + 2, 400 401 //BRC Update (frame based) 402 CODECHAL_HEVC_BRC_UPDATE_BEGIN = CODECHAL_HEVC_BRC_INIT_RESET_END, 403 CODECHAL_HEVC_BRC_UPDATE_HISTORY = CODECHAL_HEVC_BRC_UPDATE_BEGIN + 0, 404 CODECHAL_HEVC_BRC_UPDATE_PREV_PAK = CODECHAL_HEVC_BRC_UPDATE_BEGIN + 1, 405 CODECHAL_HEVC_BRC_UPDATE_PIC_STATE_R = CODECHAL_HEVC_BRC_UPDATE_BEGIN + 2, 406 CODECHAL_HEVC_BRC_UPDATE_PIC_STATE_W = CODECHAL_HEVC_BRC_UPDATE_BEGIN + 3, 407 CODECHAL_HEVC_BRC_UPDATE_ENC_OUTPUT = CODECHAL_HEVC_BRC_UPDATE_BEGIN + 4, 408 CODECHAL_HEVC_BRC_UPDATE_DISTORTION = CODECHAL_HEVC_BRC_UPDATE_BEGIN + 5, 409 CODECHAL_HEVC_BRC_UPDATE_BRCDATA = CODECHAL_HEVC_BRC_UPDATE_BEGIN + 6, 410 CODECHAL_HEVC_BRC_UPDATE_END = CODECHAL_HEVC_BRC_UPDATE_BEGIN + 7, 411 412 //BRC Update (LCU-based) 413 CODECHAL_HEVC_BRC_LCU_UPDATE_BEGIN = CODECHAL_HEVC_BRC_UPDATE_END, 414 CODECHAL_HEVC_BRC_LCU_UPDATE_HISTORY = CODECHAL_HEVC_BRC_LCU_UPDATE_BEGIN + 0, 415 CODECHAL_HEVC_BRC_LCU_UPDATE_HME_DISTORTION = CODECHAL_HEVC_BRC_LCU_UPDATE_BEGIN + 1, 416 CODECHAL_HEVC_BRC_LCU_UPDATE_INTRA_DISTORTION = CODECHAL_HEVC_BRC_LCU_UPDATE_BEGIN + 2, 417 CODECHAL_HEVC_BRC_LCU_UPDATE_HME_MVP = CODECHAL_HEVC_BRC_LCU_UPDATE_BEGIN + 3, 418 CODECHAL_HEVC_BRC_LCU_UPDATE_LCU_QP = CODECHAL_HEVC_BRC_LCU_UPDATE_BEGIN + 4, 419 CODECHAL_HEVC_BRC_LCU_UPDATE_ROI = CODECHAL_HEVC_BRC_LCU_UPDATE_BEGIN + 5, 420 CODECHAL_HEVC_BRC_LCU_UPDATE_END = CODECHAL_HEVC_BRC_LCU_UPDATE_BEGIN + 6, 421 422 // P MB ENC kernel 423 CODECHAL_HEVC_P_MBENC_BEGIN = CODECHAL_HEVC_BRC_LCU_UPDATE_END, 424 CODECHAL_HEVC_P_MBENC_CU_RECORD = CODECHAL_HEVC_P_MBENC_BEGIN + 0, 425 CODECHAL_HEVC_P_MBENC_PAK_CMD = CODECHAL_HEVC_P_MBENC_BEGIN + 1, 426 CODECHAL_HEVC_P_MBENC_SRC_Y = CODECHAL_HEVC_P_MBENC_BEGIN + 2, 427 CODECHAL_HEVC_P_MBENC_SRC_UV = CODECHAL_HEVC_P_MBENC_BEGIN + 3, 428 CODECHAL_HEVC_P_MBENC_INTRA_DIST = CODECHAL_HEVC_P_MBENC_BEGIN + 4, 429 CODECHAL_HEVC_P_MBENC_MIN_DIST = CODECHAL_HEVC_P_MBENC_BEGIN + 5, 430 CODECHAL_HEVC_P_MBENC_HME_MVP = CODECHAL_HEVC_P_MBENC_BEGIN + 6, 431 CODECHAL_HEVC_P_MBENC_HME_DIST = CODECHAL_HEVC_P_MBENC_BEGIN + 7, 432 CODECHAL_HEVC_P_MBENC_SLICE_MAP = CODECHAL_HEVC_P_MBENC_BEGIN + 8, 433 CODECHAL_HEVC_P_MBENC_VME_UNISIC_DATA = CODECHAL_HEVC_P_MBENC_BEGIN + 9, 434 CODECHAL_HEVC_P_MBENC_Simplest_Intra = CODECHAL_HEVC_P_MBENC_BEGIN + 10, 435 CODECHAL_HEVC_P_MBENC_REF_COLLOC = CODECHAL_HEVC_P_MBENC_BEGIN + 11, 436 CODECHAL_HEVC_P_MBENC_Reserved = CODECHAL_HEVC_P_MBENC_BEGIN + 12, 437 CODECHAL_HEVC_P_MBENC_BRC_Input = CODECHAL_HEVC_P_MBENC_BEGIN + 13, 438 CODECHAL_HEVC_P_MBENC_LCU_QP = CODECHAL_HEVC_P_MBENC_BEGIN + 14, 439 CODECHAL_HEVC_P_MBENC_BRC_DATA = CODECHAL_HEVC_P_MBENC_BEGIN + 15, 440 // 441 CODECHAL_HEVC_P_MBENC_VME_CURRENT = CODECHAL_HEVC_P_MBENC_BEGIN + 16, 442 CODECHAL_HEVC_P_MBENC_VME_FORWARD_0 = CODECHAL_HEVC_P_MBENC_BEGIN + 17, 443 CODECHAL_HEVC_P_MBENC_VME_FORWARD_1 = CODECHAL_HEVC_P_MBENC_BEGIN + 19, 444 CODECHAL_HEVC_P_MBENC_VME_FORWARD_2 = CODECHAL_HEVC_P_MBENC_BEGIN + 21, 445 CODECHAL_HEVC_P_MBENC_VME_FORWARD_3 = CODECHAL_HEVC_P_MBENC_BEGIN + 23, 446 CODECHAL_HEVC_P_MBENC_VME_FORWARD_4 = CODECHAL_HEVC_P_MBENC_BEGIN + 25, 447 CODECHAL_HEVC_P_MBENC_VME_FORWARD_5 = CODECHAL_HEVC_P_MBENC_BEGIN + 27, 448 CODECHAL_HEVC_P_MBENC_VME_FORWARD_6 = CODECHAL_HEVC_P_MBENC_BEGIN + 29, 449 CODECHAL_HEVC_P_MBENC_VME_FORWARD_7 = CODECHAL_HEVC_P_MBENC_BEGIN + 31, 450 451 // 452 CODECHAL_HEVC_P_MBENC_CONCURRENT_THD_MAP = CODECHAL_HEVC_P_MBENC_BEGIN + 33, 453 CODECHAL_HEVC_P_MBENC_MV_IDX = CODECHAL_HEVC_P_MBENC_BEGIN + 34, 454 CODECHAL_HEVC_P_MBENC_MVP_IDX = CODECHAL_HEVC_P_MBENC_BEGIN + 35, 455 CODECHAL_HEVC_P_MBENC_DEBUG = CODECHAL_HEVC_P_MBENC_BEGIN + 36, 456 // 457 CODECHAL_HEVC_P_MBENC_END = CODECHAL_HEVC_P_MBENC_BEGIN + 37, 458 459 CODECHAL_HEVC_NUM_SURFACES = CODECHAL_HEVC_P_MBENC_END 460 }; 461 462 enum 463 { 464 // 2x down-scaling kernel 465 CODECHAL_HEVC_FEI_SCALING_FRAME_BEGIN = 0, 466 CODECHAL_HEVC_FEI_SCALING_FRAME_SRC_Y = CODECHAL_HEVC_FEI_SCALING_FRAME_BEGIN + 0, 467 CODECHAL_HEVC_FEI_SCALING_FRAME_DST_Y = CODECHAL_HEVC_FEI_SCALING_FRAME_BEGIN + 1, 468 CODECHAL_HEVC_FEI_SCALING_FRAME_END = CODECHAL_HEVC_FEI_SCALING_FRAME_BEGIN + 2, 469 470 // 32x32 PU mode decision kernel 471 CODECHAL_HEVC_FEI_32x32_PU_BEGIN = CODECHAL_HEVC_FEI_SCALING_FRAME_END, 472 CODECHAL_HEVC_FEI_32x32_PU_OUTPUT = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 0, 473 CODECHAL_HEVC_FEI_32x32_PU_SRC_Y = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 1, 474 CODECHAL_HEVC_FEI_32x32_PU_SRC_UV = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 2, 475 CODECHAL_HEVC_FEI_32x32_PU_SRC_Y2x = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 3, 476 CODECHAL_HEVC_FEI_32x32_PU_SLICE_MAP = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 4, 477 CODECHAL_HEVC_FEI_32x32_PU_SRC_Y2x_VME = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 5, 478 CODECHAL_HEVC_FEI_32x32_PU_BRC_Input = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 6, 479 CODECHAL_HEVC_FEI_32x32_PU_LCU_QP = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 7, 480 CODECHAL_HEVC_FEI_32x32_PU_BRC_DATA = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 8, 481 CODECHAL_HEVC_FEI_32x32_PU_STATS_DATA = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 9, 482 CODECHAL_HEVC_FEI_32x32_PU_DEBUG = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 10, 483 CODECHAL_HEVC_FEI_32x32_PU_END = CODECHAL_HEVC_FEI_32x32_PU_BEGIN + 11, 484 485 // 16x16 SAD computation kernel 486 CODECHAL_HEVC_FEI_16x16_PU_SAD_BEGIN = CODECHAL_HEVC_FEI_32x32_PU_END, 487 CODECHAL_HEVC_FEI_16x16_PU_SAD_SRC_Y = CODECHAL_HEVC_FEI_16x16_PU_SAD_BEGIN + 0, 488 CODECHAL_HEVC_FEI_16x16_PU_SAD_SRC_UV = CODECHAL_HEVC_FEI_16x16_PU_SAD_BEGIN + 1, 489 CODECHAL_HEVC_FEI_16x16_PU_SAD_OUTPUT = CODECHAL_HEVC_FEI_16x16_PU_SAD_BEGIN + 2, 490 CODECHAL_HEVC_FEI_16x16_PU_SAD_32x32_MD_DATA = CODECHAL_HEVC_FEI_16x16_PU_SAD_BEGIN + 3, 491 CODECHAL_HEVC_FEI_16x16_PU_SLICE_MAP = CODECHAL_HEVC_FEI_16x16_PU_SAD_BEGIN + 4, 492 CODECHAL_HEVC_FEI_16x16_PU_Simplest_Intra = CODECHAL_HEVC_FEI_16x16_PU_SAD_BEGIN + 5, 493 CODECHAL_HEVC_FEI_16x16_PU_SAD_DEBUG = CODECHAL_HEVC_FEI_16x16_PU_SAD_BEGIN + 6, 494 CODECHAL_HEVC_FEI_16x16_PU_SAD_END = CODECHAL_HEVC_FEI_16x16_PU_SAD_BEGIN + 7, 495 496 // 16x16 PU mode decision kernel 497 CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN = CODECHAL_HEVC_FEI_16x16_PU_SAD_END, 498 CODECHAL_HEVC_FEI_16x16_PU_MD_SRC_Y = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 0, 499 CODECHAL_HEVC_FEI_16x16_PU_MD_SRC_UV = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 1, 500 CODECHAL_HEVC_FEI_16x16_PU_MD_16x16_SAD_DATA = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 2, 501 CODECHAL_HEVC_FEI_16x16_PU_MD_PAK_OBJ = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 3, 502 CODECHAL_HEVC_FEI_16x16_PU_MD_32x32_MD_DATA = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 4, 503 CODECHAL_HEVC_FEI_16x16_PU_MD_VME_8x8_MD_DATA = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 5, 504 CODECHAL_HEVC_FEI_16x16_PU_MD_SLICE_MAP = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 6, 505 CODECHAL_HEVC_FEI_16x16_PU_MD_VME_SRC = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 7, 506 CODECHAL_HEVC_FEI_16x16_PU_MD_BRC_Input = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 8, 507 CODECHAL_HEVC_FEI_16x16_PU_MD_Simplest_Intra = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 9, 508 CODECHAL_HEVC_FEI_16x16_PU_MD_LCU_QP = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 10, 509 CODECHAL_HEVC_FEI_16x16_PU_MD_BRC_Data = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 11, 510 CODECHAL_HEVC_FEI_16x16_PU_MD_DEBUG = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 12, 511 CODECHAL_HEVC_FEI_16x16_PU_MD_END = CODECHAL_HEVC_FEI_16x16_PU_MD_BEGIN + 13, 512 513 // 8x8 PU kernel 514 CODECHAL_HEVC_FEI_8x8_PU_BEGIN = CODECHAL_HEVC_FEI_16x16_PU_MD_END, 515 CODECHAL_HEVC_FEI_8x8_PU_SRC_Y = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 0, 516 CODECHAL_HEVC_FEI_8x8_PU_SRC_UV = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 1, 517 CODECHAL_HEVC_FEI_8x8_PU_SLICE_MAP = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 2, 518 CODECHAL_HEVC_FEI_8x8_PU_VME_8x8_MODE = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 3, 519 CODECHAL_HEVC_FEI_8x8_PU_INTRA_MODE = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 4, 520 CODECHAL_HEVC_FEI_8x8_PU_BRC_Input = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 5, 521 CODECHAL_HEVC_FEI_8x8_PU_Simplest_Intra = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 6, 522 CODECHAL_HEVC_FEI_8x8_PU_LCU_QP = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 7, 523 CODECHAL_HEVC_FEI_8x8_PU_BRC_Data = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 8, 524 CODECHAL_HEVC_FEI_8x8_PU_DEBUG = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 9, 525 CODECHAL_HEVC_FEI_8x8_PU_END = CODECHAL_HEVC_FEI_8x8_PU_BEGIN + 10, 526 527 // 8x8 PU FMODE kernel 528 CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN = CODECHAL_HEVC_FEI_8x8_PU_END, 529 CODECHAL_HEVC_FEI_8x8_PU_FMODE_PAK_OBJECT = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 0, 530 CODECHAL_HEVC_FEI_8x8_PU_FMODE_VME_8x8_MODE = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 1, 531 CODECHAL_HEVC_FEI_8x8_PU_FMODE_INTRA_MODE = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 2, 532 CODECHAL_HEVC_FEI_8x8_PU_FMODE_PAK_COMMAND = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 3, 533 CODECHAL_HEVC_FEI_8x8_PU_FMODE_SLICE_MAP = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 4, 534 CODECHAL_HEVC_FEI_8x8_PU_FMODE_INTRADIST = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 5, 535 CODECHAL_HEVC_FEI_8x8_PU_FMODE_BRC_Input = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 6, 536 CODECHAL_HEVC_FEI_8x8_PU_FMODE_Simplest_Intra = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 7, 537 CODECHAL_HEVC_FEI_8x8_PU_FMODE_LCU_QP = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 8, 538 CODECHAL_HEVC_FEI_8x8_PU_FMODE_BRC_Data = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 9, 539 CODECHAL_HEVC_FEI_8x8_PU_FMODE_HAAR16x16 = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 10, 540 CODECHAL_HEVC_FEI_8x8_PU_FMODE_STATS_DATA = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 11, 541 CODECHAL_HEVC_FEI_8X8_PU_FMODE_FRAME_STATS_DATA = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 12, 542 CODECHAL_HEVC_FEI_8X8_PU_FMODE_CTB_DISTORTION = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 13, 543 CODECHAL_HEVC_FEI_8x8_PU_FMODE_DEBUG = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 14, 544 CODECHAL_HEVC_FEI_8x8_PU_FMODE_END = CODECHAL_HEVC_FEI_8x8_PU_FMODE_BEGIN + 15, 545 546 // B 32x32 PU intra check kernel 547 CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN = CODECHAL_HEVC_FEI_8x8_PU_FMODE_END, 548 CODECHAL_HEVC_FEI_B_32x32_PU_OUTPUT = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 0, 549 CODECHAL_HEVC_FEI_B_32x32_PU_SRC_Y = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 1, 550 CODECHAL_HEVC_FEI_B_32x32_PU_SRC_UV = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 2, 551 CODECHAL_HEVC_FEI_B_32x32_PU_SRC_Y2x = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 3, 552 CODECHAL_HEVC_FEI_B_32x32_PU_SLICE_MAP = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 4, 553 CODECHAL_HEVC_FEI_B_32x32_PU_SRC_Y2x_VME = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 5, 554 CODECHAL_HEVC_FEI_B_32x32_PU_Simplest_Intra = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 6, 555 CODECHAL_HEVC_FEI_B_32x32_PU_HME_MVP = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 7, 556 CODECHAL_HEVC_FEI_B_32x32_PU_HME_DIST = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 8, 557 CODECHAL_HEVC_FEI_B_32x32_PU_LCU_SKIP = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 9, 558 CODECHAL_HEVC_FEI_B_32x32_PU_DEBUG = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 10, 559 CODECHAL_HEVC_FEI_B_32x32_PU_END = CODECHAL_HEVC_FEI_B_32x32_PU_BEGIN + 11, 560 561 // B MB ENC kernel 562 CODECHAL_HEVC_FEI_B_MBENC_BEGIN = CODECHAL_HEVC_FEI_B_32x32_PU_END, 563 CODECHAL_HEVC_FEI_B_MBENC_CU_RECORD = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 0, 564 CODECHAL_HEVC_FEI_B_MBENC_PAK_CMD = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 1, 565 CODECHAL_HEVC_FEI_B_MBENC_SRC_Y = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 2, 566 CODECHAL_HEVC_FEI_B_MBENC_SRC_UV = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 3, 567 CODECHAL_HEVC_FEI_B_MBENC_INTRA_DIST = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 4, 568 CODECHAL_HEVC_FEI_B_MBENC_MIN_DIST = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 5, 569 CODECHAL_HEVC_FEI_B_MBENC_HME_MVP = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 6, 570 CODECHAL_HEVC_FEI_B_MBENC_HME_DIST = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 7, 571 CODECHAL_HEVC_FEI_B_MBENC_SLICE_MAP = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 8, 572 CODECHAL_HEVC_FEI_B_MBENC_VME_UNISIC_DATA = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 9, 573 CODECHAL_HEVC_FEI_B_MBENC_Simplest_Intra = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 10, 574 CODECHAL_HEVC_FEI_B_MBENC_REF_COLLOC = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 11, 575 CODECHAL_HEVC_FEI_B_MBENC_Reserved = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 12, 576 CODECHAL_HEVC_FEI_B_MBENC_BRC_Input = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 13, 577 CODECHAL_HEVC_FEI_B_MBENC_LCU_QP = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 14, 578 CODECHAL_HEVC_FEI_B_MBENC_BRC_DATA = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 15, 579 // 580 CODECHAL_HEVC_FEI_B_MBENC_VME_CURRENT = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 16, 581 CODECHAL_HEVC_FEI_B_MBENC_VME_FORWARD_0 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 17, 582 CODECHAL_HEVC_FEI_B_MBENC_VME_BACKWARD_0 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 18, 583 CODECHAL_HEVC_FEI_B_MBENC_VME_FORWARD_1 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 19, 584 CODECHAL_HEVC_FEI_B_MBENC_VME_BACKWARD_1 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 20, 585 CODECHAL_HEVC_FEI_B_MBENC_VME_FORWARD_2 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 21, 586 CODECHAL_HEVC_FEI_B_MBENC_VME_BACKWARD_2 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 22, 587 CODECHAL_HEVC_FEI_B_MBENC_VME_FORWARD_3 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 23, 588 CODECHAL_HEVC_FEI_B_MBENC_VME_BACKWARD_3 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 24, 589 CODECHAL_HEVC_FEI_B_MBENC_VME_FORWARD_4 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 25, 590 CODECHAL_HEVC_FEI_B_MBENC_VME_BACKWARD_4 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 26, 591 CODECHAL_HEVC_FEI_B_MBENC_VME_FORWARD_5 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 27, 592 CODECHAL_HEVC_FEI_B_MBENC_VME_BACKWARD_5 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 28, 593 CODECHAL_HEVC_FEI_B_MBENC_VME_FORWARD_6 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 29, 594 CODECHAL_HEVC_FEI_B_MBENC_VME_BACKWARD_6 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 30, 595 CODECHAL_HEVC_FEI_B_MBENC_VME_FORWARD_7 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 31, 596 CODECHAL_HEVC_FEI_B_MBENC_VME_BACKWARD_7 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 32, 597 // 598 CODECHAL_HEVC_FEI_B_MBENC_VME_MUL_CURRENT = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 33, 599 CODECHAL_HEVC_FEI_B_MBENC_VME_MUL_BACKWARD_0 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 34, 600 CODECHAL_HEVC_FEI_B_MBENC_VME_MUL_NOUSE_0 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 35, 601 CODECHAL_HEVC_FEI_B_MBENC_VME_MUL_BACKWARD_1 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 36, 602 CODECHAL_HEVC_FEI_B_MBENC_VME_MUL_NOUSE_1 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 37, 603 CODECHAL_HEVC_FEI_B_MBENC_VME_MUL_BACKWARD_2 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 38, 604 CODECHAL_HEVC_FEI_B_MBENC_VME_MUL_NOUSE_2 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 39, 605 CODECHAL_HEVC_FEI_B_MBENC_VME_MUL_BACKWARD_3 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 40, 606 CODECHAL_HEVC_FEI_B_MBENC_VME_MUL_NOUSE_3 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 41, 607 // 608 CODECHAL_HEVC_FEI_B_MBENC_CONCURRENT_THD_MAP = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 42, 609 CODECHAL_HEVC_FEI_B_MBENC_MV_IDX = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 43, 610 CODECHAL_HEVC_FEI_B_MBENC_MVP_IDX = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 44, 611 CODECHAL_HEVC_FEI_B_MBENC_HAAR_DIST16x16 = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 45, 612 CODECHAL_HEVC_FEI_B_MBENC_STATS_DATA = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 46, 613 CODECHAL_HEVC_FEI_B_MBENC_FRAME_STATS_DATA = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 47, 614 // 615 CODECHAL_HEVC_FEI_B_MBENC_EXTERNAL_MVP = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 48, 616 CODECHAL_HEVC_FEI_B_MBENC_PER_CTB_CTRL = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 49, 617 CODECHAL_HEVC_FEI_B_MBENC_CTB_DISTORTION = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 50, 618 CODECHAL_HEVC_FEI_B_MBENC_DEBUG = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 51, 619 // 620 CODECHAL_HEVC_FEI_B_MBENC_END = CODECHAL_HEVC_FEI_B_MBENC_BEGIN + 52, 621 622 // HEVC B PAK kernel 623 CODECHAL_HEVC_FEI_B_PAK_BEGIN = CODECHAL_HEVC_FEI_B_MBENC_END, 624 CODECHAL_HEVC_FEI_B_PAK_CU_RECORD = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 0, 625 CODECHAL_HEVC_FEI_B_PAK_PAK_OBJ = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 1, 626 CODECHAL_HEVC_FEI_B_PAK_SLICE_MAP = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 2, 627 CODECHAL_HEVC_FEI_B_PAK_BRC_INPUT = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 3, 628 CODECHAL_HEVC_FEI_B_PAK_LCU_QP = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 4, 629 CODECHAL_HEVC_FEI_B_PAK_BRC_DATA = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 5, 630 CODECHAL_HEVC_FEI_B_PAK_MB_DATA = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 6, 631 CODECHAL_HEVC_FEI_B_PAK_MVP_DATA = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 7, 632 CODECHAL_HEVC_FEI_B_PAK_WA_PAK_DATA = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 8, 633 CODECHAL_HEVC_FEI_B_PAK_WA_PAK_OBJ = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 9, 634 CODECHAL_HEVC_FEI_B_PAK_DEBUG = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 10, 635 CODECHAL_HEVC_FEI_B_PAK_END = CODECHAL_HEVC_FEI_B_PAK_BEGIN + 11, 636 637 //HEVC FORMAT CONVERSION AND DOWNSCALING KERNEL 638 CODECHAL_HEVC_FEI_DS_COMBINED_BEGIN = CODECHAL_HEVC_FEI_B_PAK_END, 639 CODECHAL_HEVC_FEI_DS_COMBINED_10BIT_Y = CODECHAL_HEVC_FEI_DS_COMBINED_BEGIN + 0, 640 CODECHAL_HEVC_FEI_DS_COMBINED_10BIT_UV = CODECHAL_HEVC_FEI_DS_COMBINED_BEGIN + 1, 641 CODECHAL_HEVC_FEI_DS_COMBINED_8BIT_Y = CODECHAL_HEVC_FEI_DS_COMBINED_BEGIN + 2, 642 CODECHAL_HEVC_FEI_DS_COMBINED_8BIT_UV = CODECHAL_HEVC_FEI_DS_COMBINED_BEGIN + 3, 643 CODECHAL_HEVC_FEI_DS_COMBINED_4xDOWNSCALE = CODECHAL_HEVC_FEI_DS_COMBINED_BEGIN + 4, 644 CODECHAL_HEVC_FEI_DS_COMBINED_MB_STATS = CODECHAL_HEVC_FEI_DS_COMBINED_BEGIN + 5, 645 CODECHAL_HEVC_FEI_DS_COMBINED_2xDOWNSCALE = CODECHAL_HEVC_FEI_DS_COMBINED_BEGIN + 6, 646 CODECHAL_HEVC_FEI_DS_COMBINED_END = CODECHAL_HEVC_FEI_DS_COMBINED_BEGIN + 7, 647 648 // P MB ENC kernel 649 CODECHAL_HEVC_FEI_P_MBENC_BEGIN = CODECHAL_HEVC_FEI_DS_COMBINED_END, 650 CODECHAL_HEVC_FEI_P_MBENC_CU_RECORD = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 0, 651 CODECHAL_HEVC_FEI_P_MBENC_PAK_CMD = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 1, 652 CODECHAL_HEVC_FEI_P_MBENC_SRC_Y = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 2, 653 CODECHAL_HEVC_FEI_P_MBENC_SRC_UV = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 3, 654 CODECHAL_HEVC_FEI_P_MBENC_INTRA_DIST = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 4, 655 CODECHAL_HEVC_FEI_P_MBENC_MIN_DIST = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 5, 656 CODECHAL_HEVC_FEI_P_MBENC_HME_MVP = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 6, 657 CODECHAL_HEVC_FEI_P_MBENC_HME_DIST = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 7, 658 CODECHAL_HEVC_FEI_P_MBENC_SLICE_MAP = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 8, 659 CODECHAL_HEVC_FEI_P_MBENC_VME_UNISIC_DATA = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 9, 660 CODECHAL_HEVC_FEI_P_MBENC_Simplest_Intra = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 10, 661 CODECHAL_HEVC_FEI_P_MBENC_REF_COLLOC = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 11, 662 CODECHAL_HEVC_FEI_P_MBENC_Reserved = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 12, 663 CODECHAL_HEVC_FEI_P_MBENC_BRC_Input = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 13, 664 CODECHAL_HEVC_FEI_P_MBENC_LCU_QP = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 14, 665 CODECHAL_HEVC_FEI_P_MBENC_BRC_DATA = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 15, 666 // 667 CODECHAL_HEVC_FEI_P_MBENC_VME_CURRENT = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 16, 668 CODECHAL_HEVC_FEI_P_MBENC_VME_FORWARD_0 = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 17, 669 CODECHAL_HEVC_FEI_P_MBENC_VME_FORWARD_1 = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 19, 670 CODECHAL_HEVC_FEI_P_MBENC_VME_FORWARD_2 = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 21, 671 CODECHAL_HEVC_FEI_P_MBENC_VME_FORWARD_3 = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 23, 672 CODECHAL_HEVC_FEI_P_MBENC_VME_FORWARD_4 = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 25, 673 CODECHAL_HEVC_FEI_P_MBENC_VME_FORWARD_5 = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 27, 674 CODECHAL_HEVC_FEI_P_MBENC_VME_FORWARD_6 = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 29, 675 CODECHAL_HEVC_FEI_P_MBENC_VME_FORWARD_7 = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 31, 676 // 677 CODECHAL_HEVC_FEI_P_MBENC_CONCURRENT_THD_MAP = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 33, 678 CODECHAL_HEVC_FEI_P_MBENC_MV_IDX = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 34, 679 CODECHAL_HEVC_FEI_P_MBENC_MVP_IDX = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 35, 680 CODECHAL_HEVC_FEI_P_MBENC_DEBUG = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 36, 681 // 682 CODECHAL_HEVC_FEI_P_MBENC_END = CODECHAL_HEVC_FEI_P_MBENC_BEGIN + 37, 683 684 CODECHAL_HEVC_FEI_NUM_SURFACES = CODECHAL_HEVC_FEI_P_MBENC_END 685 }; 686 687 //! 688 //! \enum HEVC_ME_DIST_TYPE 689 //! \brief HEVC me dist type 690 //! 691 enum HEVC_ME_DIST_TYPE 692 { 693 HEVC_ME_DIST_TYPE_INTRA = 0, 694 HEVC_ME_DIST_TYPE_INTRA_BRC_DIST, 695 HEVC_ME_DIST_TYPE_INTER_BRC_DIST 696 }; 697 698 //! 699 //! \enum CODECHAL_ENCODE_HEVC_MULTIPRED 700 //! \brief Codechal encode HEVC multipred 701 //! 702 enum CODECHAL_ENCODE_HEVC_MULTIPRED 703 { 704 CODECHAL_ENCODE_HEVC_MULTIPRED_ENABLE = 0x01, 705 CODECHAL_ENCODE_HEVC_MULTIPRED_DISABLE = 0x80 706 } ; 707 708 //! 709 //! \struct CODECHAL_ENCODE_HEVC_SLICE_MAP 710 //! \brief Codechal encode HEVC slice map 711 //! 712 struct CODECHAL_ENCODE_HEVC_SLICE_MAP 713 { 714 uint8_t ucSliceID; 715 uint8_t Reserved[3]; 716 }; 717 using PCODECHAL_ENCODE_HEVC_SLICE_MAP = CODECHAL_ENCODE_HEVC_SLICE_MAP*; 718 719 //! 720 //! \struct CODECHAL_ENCODE_HEVC_WALKING_CONTROL_REGION 721 //! \brief Codechal encode HEVC walking control region 722 //! 723 struct CODECHAL_ENCODE_HEVC_WALKING_CONTROL_REGION 724 { 725 uint16_t Reserve0[2]; 726 uint16_t StartYCurrentSlice; 727 uint16_t StartYNextSlice; 728 uint16_t Xoffset; 729 uint16_t Reserve1[2]; 730 uint16_t Yoffset; 731 uint32_t Reserve2[4]; 732 uint32_t alignment[8]; 733 }; 734 using PCODECHAL_ENCODE_HEVC_WALKING_CONTROL_REGION = CODECHAL_ENCODE_HEVC_WALKING_CONTROL_REGION*; 735 736 //! 737 //! \struct CODECHAL_ENCODE_HEVC_REFFRAME_SYNC_OBJ 738 //! \brief Codechal encode HEVC reference frame sync object 739 //! 740 struct CODECHAL_ENCODE_HEVC_REFFRAME_SYNC_OBJ 741 { 742 uint32_t uiSemaphoreObjCount = 0; 743 MOS_RESOURCE resSyncObject = {}; 744 bool bInUsed = false; 745 CODECHAL_ENCODE_BUFFER resSemaphoreMem = {}; 746 }; 747 using PCODECHAL_ENCODE_HEVC_REFFRAME_SYNC_OBJ = CODECHAL_ENCODE_HEVC_REFFRAME_SYNC_OBJ*; 748 749 C_ASSERT((sizeof(CODECHAL_ENCODE_HEVC_WALKING_CONTROL_REGION)) == 64); 750 751 //! 752 //! \struct CODECHAL_ENCODE_HEVC_WALKINGPATTERN_PARAM 753 //! \brief Codechal encode HEVC walking pattern parameter 754 //! 755 struct CODECHAL_ENCODE_HEVC_WALKINGPATTERN_PARAM 756 { 757 // Media Walker setting 758 MHW_WALKER_PARAMS MediaWalker; 759 MHW_VFE_SCOREBOARD ScoreBoard; 760 761 int Offset_Y; 762 int Offset_Delta; 763 uint32_t dwNumRegion; 764 uint32_t dwMaxHeightInRegion; 765 uint32_t dwNumUnitsInRegion; 766 }; 767 using PCODECHAL_ENCODE_HEVC_WALKINGPATTERN_PARAM = CODECHAL_ENCODE_HEVC_WALKINGPATTERN_PARAM*; 768 769 //! 770 //! \struct CODECHAL_ENCODE_HEVC_PAK_STATS_BUFFER 771 //! \brief Codechal encode HEVC PAK States buffer 772 //! 773 struct CODECHAL_ENCODE_HEVC_PAK_STATS_BUFFER 774 { 775 uint32_t HCP_BITSTREAM_BYTECOUNT_FRAME; 776 uint32_t HCP_BITSTREAM_BYTECOUNT_FRAME_NOHEADER; 777 uint32_t HCP_IMAGE_STATUS_CONTROL; 778 uint32_t Reserved0; 779 uint32_t HCP_IMAGE_STATUS_CONTROL_FOR_LAST_PASS; 780 uint32_t Reserved1[3]; 781 }; 782 783 //! 784 //! \enum CODECHAL_HEVC_MBENC_KRNIDX 785 //! \brief Codechal HEVC MBENC KRNIDX 786 //! 787 enum CODECHAL_HEVC_MBENC_KRNIDX 788 { 789 CODECHAL_HEVC_MBENC_2xSCALING = 0, 790 CODECHAL_HEVC_MBENC_32x32MD, 791 CODECHAL_HEVC_MBENC_16x16SAD, 792 CODECHAL_HEVC_MBENC_16x16MD, 793 CODECHAL_HEVC_MBENC_8x8PU, 794 CODECHAL_HEVC_MBENC_8x8FMODE, 795 CODECHAL_HEVC_MBENC_32x32INTRACHECK, 796 CODECHAL_HEVC_MBENC_BENC, 797 CODECHAL_HEVC_MBENC_BPAK, 798 CODECHAL_HEVC_MBENC_ADV, 799 CODECHAL_HEVC_MBENC_NUM, 800 CODECHAL_HEVC_MBENC_DS_COMBINED = CODECHAL_HEVC_MBENC_NUM, //this will be added for 10 bit for KBL 801 CODECHAL_HEVC_MBENC_NUM_KBL, 802 CODECHAL_HEVC_MBENC_PENC = CODECHAL_HEVC_MBENC_NUM_KBL, 803 CODECHAL_HEVC_MBENC_ADV_P, 804 CODECHAL_HEVC_MBENC_NUM_BXT_SKL //Only BXT and SKL support HEVC P frame 805 }; 806 807 //! 808 //! \enum CODECHAL_HEVC_FEI_MBENC_KRNIDX 809 //! \brief Codechal HEVC FEI MBENC KRNIDX 810 //! 811 enum CODECHAL_HEVC_FEI_MBENC_KRNIDX 812 { 813 CODECHAL_HEVC_FEI_MBENC_BENC = CODECHAL_HEVC_MBENC_BENC, 814 CODECHAL_HEVC_FEI_MBENC_BPAK, 815 CODECHAL_HEVC_FEI_MBENC_NUM, 816 CODECHAL_HEVC_FEI_MBENC_DS_COMBINED = CODECHAL_HEVC_FEI_MBENC_NUM, //this will be added for 10 bit for KBL 817 CODECHAL_HEVC_FEI_MBENC_NUM_KBL, 818 CODECHAL_HEVC_FEI_MBENC_PENC = CODECHAL_HEVC_FEI_MBENC_NUM_KBL, 819 CODECHAL_HEVC_FEI_MBENC_NUM_BXT_SKL //Only BXT and SKL support HEVC P frame 820 } ; 821 822 //! 823 //! \enum CODECHAL_HEVC_BRC_KRNIDX 824 //! \brief Codechal HEVC BRC KRNIDX 825 //! 826 enum CODECHAL_HEVC_BRC_KRNIDX 827 { 828 CODECHAL_HEVC_BRC_COARSE_INTRA = 0, 829 CODECHAL_HEVC_BRC_INIT, 830 CODECHAL_HEVC_BRC_RESET, 831 CODECHAL_HEVC_BRC_FRAME_UPDATE, 832 CODECHAL_HEVC_BRC_LCU_UPDATE, 833 CODECHAL_HEVC_BRC_NUM 834 }; 835 836 //! \class CodechalEncodeHevcBase 837 //! \brief HEVC encoder base class 838 //! \details This class defines the base class for HEVC encoder, it includes 839 //! common member fields, functions, interfaces etc shared by both dual-pipe and VDEnc for all Gens. 840 //! 841 //! To create a HEVC encoder instance, client needs to call CodechalEncodeHevcBase::CreateHevcState() 842 //! 843 class CodechalEncodeHevcBase : public CodechalEncoderState 844 { 845 public: 846 static constexpr uint32_t MAX_LCU_SIZE = 64; //!< Max LCU size 64 847 static constexpr uint32_t QP_NUM = 52; //!< Number of QP values 848 849 static const uint8_t TransformSkipCoeffsTable[4][2][2][2][2]; //!< Transform skip related coeff table 850 static const uint16_t TransformSkipLambdaTable[QP_NUM]; //!< Transform skip related lambda table 851 852 static const uint8_t CC_BYPASS = 0x0; //!< MFX Video Copy Mode 853 static const uint8_t CC_LIST_MODE = 0x1; //!< MFX Video CP Copy Mode 854 855 //! HEVC encoder slice type enum 856 enum 857 { 858 CODECHAL_ENCODE_HEVC_B_SLICE = 0, 859 CODECHAL_ENCODE_HEVC_P_SLICE = 1, 860 CODECHAL_ENCODE_HEVC_I_SLICE = 2, 861 CODECHAL_ENCODE_HEVC_NUM_SLICE_TYPES = 3 862 }; 863 864 // Parameters passed from application 865 PCODEC_HEVC_ENCODE_PICTURE_PARAMS m_hevcPicParams = nullptr; //!< Pointer to picture parameter 866 PCODEC_HEVC_ENCODE_SEQUENCE_PARAMS m_hevcSeqParams = nullptr; //!< Pointer to sequence parameter 867 PCODEC_HEVC_ENCODE_SLICE_PARAMS m_hevcSliceParams = nullptr; //!< Pointer to slice parameter 868 CodecEncodeHevcFeiPicParams * m_hevcFeiPicParams = nullptr; //!< Pointer to FEI picture parameter 869 PCODECHAL_HEVC_IQ_MATRIX_PARAMS m_hevcIqMatrixParams = nullptr; //!< Pointer to IQ matrix parameter 870 871 uint32_t m_widthAlignedMaxLcu = 0; //!< Picture width aligned in max LCU size 872 uint32_t m_heightAlignedMaxLcu = 0; //!< Picture height aligned in max LCU size 873 874 // PAK resources 875 MOS_RESOURCE m_resDeblockingFilterRowStoreScratchBuffer; //!< Deblocking filter row store scratch data buffer 876 MOS_RESOURCE m_resDeblockingFilterTileRowStoreScratchBuffer; //!< Deblocking filter tile row store Scratch data buffer 877 MOS_RESOURCE m_resDeblockingFilterColumnRowStoreScratchBuffer; //!< Deblocking filter column row Store scratch data buffer 878 MOS_RESOURCE m_resMetadataLineBuffer; //!< Metadata line data buffer 879 MOS_RESOURCE m_resMetadataTileLineBuffer; //!< Metadata tile line data buffer 880 MOS_RESOURCE m_resMetadataTileColumnBuffer; //!< Metadata tile column data buffer 881 MOS_RESOURCE m_resSaoLineBuffer; //!< SAO line data buffer 882 MOS_RESOURCE m_resSaoTileLineBuffer; //!< SAO tile line data buffer 883 MOS_RESOURCE m_resSaoTileColumnBuffer; //!< SAO tile column data buffer 884 MOS_RESOURCE m_resLcuBaseAddressBuffer; //!< LCU base address buffer 885 MOS_RESOURCE m_resLcuIldbStreamOutBuffer; //!< LCU ILDB streamout buffer 886 MOS_RESOURCE m_resSaoStreamOutBuffer; //!< SAO streamout buffer 887 MOS_RESOURCE m_resFrameStatStreamOutBuffer; //!< Frame statistics streamout buffer 888 MOS_RESOURCE m_resSseSrcPixelRowStoreBuffer; //!< SSE src pixel row store buffer 889 MHW_BATCH_BUFFER m_batchBufferForPakSlices[CODECHAL_HEVC_NUM_PAK_SLICE_BATCH_BUFFERS]; //!< Batch buffer for pak slice commands 890 uint32_t m_currPakSliceIdx = 0; //!< Current pak slice index 891 bool m_useBatchBufferForPakSlices = false; //!< Flag to indicate if batch buffer is used for PAK slice level commands 892 uint32_t m_batchBufferForPakSlicesStartOffset = 0; //!< Pak slice command start offset within batch buffer 893 894 uint32_t m_defaultPictureStatesSize = 0; //!< Picture state command size 895 uint32_t m_defaultPicturePatchListSize = 0; //!< Picture state patch list size 896 uint32_t m_defaultSliceStatesSize = 0; //!< Slice state command size 897 uint32_t m_defaultSlicePatchListSize = 0; //!< Slice state patch list size 898 899 unsigned char m_uc2NdSaoPass = 0; //!< Second SAO pass number 900 bool m_b2NdSaoPassNeeded = false; //!< Second SAO pass enable flag 901 902 CODECHAL_ENCODE_HEVC_REFFRAME_SYNC_OBJ m_refSync[CODEC_NUM_TRACKED_BUFFERS]; //!< Reference frame sync object 903 PCODECHAL_ENCODE_HEVC_REFFRAME_SYNC_OBJ m_currRefSync = nullptr; //!< Pointer to current frame sync object 904 unsigned char m_lastMbCodeIndex = 0; //!< Used in the non-parallel BRC to check if the previous PAK is ready 905 unsigned char m_currMinus2MbCodeIndex = 0; //!< Used in the parallel BRC to check if the (N-2)th PAK is ready, where N is the frame number 906 907 int8_t m_refIdxMapping[CODEC_MAX_NUM_REF_FRAME_HEVC]; //!< Reference frame index mapping 908 bool m_lowDelay = false; //!< Low delay flag 909 bool m_sameRefList = false; //!< Flag to specify if ref list L0 and L1 are same 910 bool m_isMaxLcu64 = false; //!< Flag to specify if max LCU size is 64 911 uint32_t m_sizeOfMvTemporalBuffer = 0; //!< MV temporal buffer size 912 bool m_encode4KSequence = false; //!< Flag to specify if input sequence is 4k size 913 bool m_encode16KSequence = false; //!< Flag to specify if input sequence is 16k size 914 bool m_hevcRdoqEnabled = false; //!< RDOQ enable flag 915 uint32_t m_rdoqIntraTuThreshold = 0; //!< RDOQ intra threshold 916 bool m_hevcIFrameRdoqEnabled = true; //!< Control intra frame RDOQ enable/disable 917 #if (_DEBUG || _RELEASE_INTERNAL) 918 bool m_rdoqIntraTuOverride = false; //!< Override RDOQ intra TU or not 919 bool m_rdoqIntraTuDisableOverride = false; //!< Override RDOQ intra TU disable 920 uint16_t m_rdoqIntraTuThresholdOverride = 0; //!< Override RDOQ intra TU threshold 921 #endif 922 bool m_is10BitHevc = false; //!< 10bit encoding flag 923 unsigned char m_chromaFormat = HCP_CHROMA_FORMAT_YUV420; //!< Chroma format(420, 422 etc) 924 unsigned char m_bitDepth = 8; //!< Bit depth 925 uint32_t m_maxNumSlicesSupported = CODECHAL_HEVC_MAX_NUM_SLICES_LVL_5; //!< Maximal number of slices supported 926 uint32_t m_sizeOfSseSrcPixelRowStoreBufferPerLcu = 0; //!< Size of SSE row store buffer per LCU 927 uint32_t m_sizeOfHcpPakFrameStats = 0; //!> Size of HEVC PAK frame statistics 928 uint8_t m_roundingInter = 4; // the value is from prototype 929 uint8_t m_roundingIntra = 10; // the value is from prototype 930 931 bool m_currUsedRefPic[CODEC_MAX_NUM_REF_FRAME_HEVC]; //!< Reference picture usage array 932 CODEC_PIC_ID m_picIdx[CODEC_MAX_NUM_REF_FRAME_HEVC]; //!< Reference picture index array 933 PCODEC_REF_LIST m_refList[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC]; //!< Pointer to reference pictures 934 PCODECHAL_NAL_UNIT_PARAMS *m_nalUnitParams = nullptr; //!< Pointer to NAL unit parameters 935 bool m_enable26WalkingPattern = false; //!< 26 walking pattern enable flag 936 937 // ME 938 bool m_hmeEnabled = false; //!< HME enable flag 939 bool m_b16XMeEnabled = false; //!< 16xME enable flag 940 bool m_b32XMeEnabled = false; //!< 32xME enable flag 941 MOS_SURFACE m_s4XMeMvDataBuffer; //!< 4xME mv data buffer 942 MOS_SURFACE m_s16XMeMvDataBuffer; //!< 16xME mv data buffer 943 MOS_SURFACE m_s32XMeMvDataBuffer; //!< 32xME mv data buffer 944 MOS_SURFACE m_s4XMeDistortionBuffer; //!< 4xME distortion buffer 945 bool m_brcDistortionBufferSupported = false; //!< Brc distorion supported flag 946 bool m_b4XMeDistortionBufferSupported = false; //!< 4xME distorion supported flag 947 uint8_t * m_bmeMethodTable = nullptr; //!< Pointer for ME method table based on TargetUsage 948 uint8_t * m_meMethodTable = nullptr; //!< Pointer for ME method table based on TargetUsage 949 950 // BRC 951 uint16_t m_usAvbrAccuracy = 0; //!< AVBR accuracy 952 uint16_t m_usAvbrConvergence = 0; //!< AVBR convergence 953 double m_dBrcInitCurrentTargetBufFullInBits = 0.0; //!< Initial value of target buffer fullness in bits 954 double m_dBrcInitResetInputBitsPerFrame = 0.0; //!< Input bits per frame 955 uint32_t m_brcInitResetBufSizeInBits = 0; //!< Target buffer size in bits 956 uint32_t m_hevcBrcPakStatisticsSize = 0; //!< BRC PAK statistics size 957 bool m_brcEnabled = false; //!< BRC enable flag 958 bool m_lcuBrcEnabled = false; //!< LCU BRC enable flag 959 bool m_brcInit = true; //!< BRC init flag 960 bool m_brcReset = false; //!< BRC reset flag 961 bool m_brcRoiEnabled = false; //!< BRC Roi flag 962 bool m_roiValueInDeltaQp = true; //!< ROI Value in deltaQP or priority flag 963 964 CODECHAL_ENCODE_BUFFER m_resPakcuLevelStreamoutData; //!< PAK LCU level stream out data buffer 965 966 // Mb Qp Data 967 bool m_mbQpDataEnabled = false; //!< Mb Qp Data Enable Flag. 968 MOS_SURFACE m_mbQpDataSurface; //!< Pointer to MOS_SURFACE of Mb Qp data surface, provided by DDI. 969 970 protected: 971 //! 972 //! \brief Constructor 973 //! 974 CodechalEncodeHevcBase(CodechalHwInterface* hwInterface, 975 CodechalDebugInterface* debugInterface, 976 PCODECHAL_STANDARD_INFO standardInfo); 977 978 uint8_t* m_kernelBinary = nullptr; //!< Pointer to the kernel binary 979 uint32_t m_combinedKernelSize = 0; //!< Combined kernel binary size 980 PMHW_VDBOX_HEVC_SLICE_STATE m_sliceStateParams = nullptr; //!< Slice state parameters 981 PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS m_pipeModeSelectParams = nullptr; //!< Pipe mode select parameters 982 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS m_pipeBufAddrParams = nullptr; //!< Pipe buffer addr parameters 983 984 public: 985 //! 986 //! \brief Destructor 987 //! ~CodechalEncodeHevcBase()988 virtual ~CodechalEncodeHevcBase() {}; 989 990 //! 991 //! \brief Help function to check if the rate control method is BRC 992 //! 993 //! \param [in] rc 994 //! Rate control method 995 //! 996 //! \return True if using BRC , else return false 997 //! IsRateControlBrc(uint8_t rc)998 bool IsRateControlBrc(uint8_t rc) 999 { 1000 return (rc == RATECONTROL_CBR) || 1001 (rc == RATECONTROL_VBR) || 1002 (rc == RATECONTROL_AVBR) || 1003 (rc == RATECONTROL_VCM) || 1004 (rc == RATECONTROL_ICQ) || 1005 (rc == RATECONTROL_QVBR); 1006 } 1007 1008 //! 1009 //! \brief Help function to calculate the slice QP 1010 //! 1011 //! \return Slice QP value 1012 //! CalSliceQp()1013 int CalSliceQp() 1014 { 1015 CODECHAL_ENCODE_ASSERT(m_hevcSliceParams); 1016 CODECHAL_ENCODE_ASSERT(m_hevcPicParams); 1017 1018 int qp = m_hevcSliceParams->slice_qp_delta + m_hevcPicParams->QpY; 1019 CODECHAL_ENCODE_ASSERT(qp >= 0 && qp < QP_NUM); 1020 return qp; 1021 } 1022 1023 //! 1024 //! \brief Help function to get current PAK pass 1025 //! 1026 //! \return Current PAK pass 1027 //! GetCurrentPass()1028 virtual int GetCurrentPass() 1029 { 1030 return m_currPass; 1031 } 1032 1033 //! 1034 //! \brief Help function to check if current PAK pass is first pass 1035 //! 1036 //! \return True if current PAK pass is first pass, otherwise return false 1037 //! IsFirstPass()1038 virtual bool IsFirstPass() 1039 { 1040 return GetCurrentPass() == 0 ? true : false; 1041 } 1042 1043 //! 1044 //! \brief Help function to check if current PAK pass is last pass 1045 //! 1046 //! \return True if current PAK pass is last pass, otherwise return false 1047 //! IsLastPass()1048 virtual bool IsLastPass() 1049 { 1050 return GetCurrentPass() == m_numPasses ? true : false; 1051 } 1052 1053 //! 1054 //! \brief Help function to check if legacy command buffer is used 1055 //! 1056 //! \return True if using legacy command buffer, otherwise return false 1057 //! UseRenderCommandBuffer()1058 bool UseRenderCommandBuffer() 1059 { 1060 return (m_osInterface->pfnGetGpuContext(m_osInterface) == m_renderContext); 1061 } 1062 1063 //! 1064 //! \brief Help function to retrieve a command buffer 1065 //! 1066 //! \param [in, out] cmdBuffer 1067 //! Pointer to command buffer 1068 //! 1069 //! \return MOS_STATUS 1070 //! MOS_STATUS_SUCCESS if success, else fail reason 1071 //! 1072 virtual MOS_STATUS GetCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 1073 1074 //! 1075 //! \brief Help function to return a command buffer 1076 //! 1077 //! \param [in] cmdBuffer 1078 //! Pointer to command buffer 1079 //! 1080 //! \return MOS_STATUS 1081 //! MOS_STATUS_SUCCESS if success, else fail reason 1082 //! 1083 virtual MOS_STATUS ReturnCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 1084 1085 //! 1086 //! \brief Help function to submit a command buffer 1087 //! 1088 //! \param [in] cmdBuffer 1089 //! Pointer to command buffer 1090 //! \param [in] nullRendering 1091 //! Null rendering flag 1092 //! 1093 //! \return MOS_STATUS 1094 //! MOS_STATUS_SUCCESS if success, else fail reason 1095 //! 1096 virtual MOS_STATUS SubmitCommandBuffer( 1097 PMOS_COMMAND_BUFFER cmdBuffer, 1098 bool bNullRendering); 1099 1100 //! 1101 //! \brief Help function to verify command buffer size 1102 //! 1103 //! \return MOS_STATUS 1104 //! MOS_STATUS_SUCCESS if success, else fail reason 1105 //! 1106 virtual MOS_STATUS VerifyCommandBufferSize(); 1107 1108 //! 1109 //! \brief Help function to send prolog with frame tracking information 1110 //! 1111 //! \param [in] cmdBuffer 1112 //! Pointer to command buffer 1113 //! \param [in] frameTrackingRequested 1114 //! True if frame tracking info is needed, false otherwise 1115 //! 1116 //! \return MOS_STATUS 1117 //! MOS_STATUS_SUCCESS if success, else fail reason 1118 //! 1119 virtual MOS_STATUS SendPrologWithFrameTracking( 1120 PMOS_COMMAND_BUFFER cmdBuffer, 1121 bool frameTrackingRequested, 1122 MHW_MI_MMIOREGISTERS *mmioRegister = nullptr); 1123 1124 //! 1125 //! \brief Wait for dependent VDBOX to get ready 1126 //! 1127 //! \param [in] cmdBuffer 1128 //! Pointer to command buffer 1129 //! 1130 //! \return MOS_STATUS 1131 //! MOS_STATUS_SUCCESS if success, else fail reason 1132 //! 1133 MOS_STATUS WaitForVDBOX(PMOS_COMMAND_BUFFER cmdBuffer); 1134 1135 //! 1136 //! \brief Add MI_SEMAPHORE_WAIT command in command buffer 1137 //! 1138 //! \param [in] semaphoreMem 1139 //! Pointer to semaphore resource 1140 //! \param [in] cmdBuffer 1141 //! Pointer to command buffer 1142 //! \param [in] semValue 1143 //! Value to wait on semaphore memory 1144 //! 1145 //! \return MOS_STATUS 1146 //! MOS_STATUS_SUCCESS if success, else fail reason 1147 //! 1148 MOS_STATUS SendHWWaitCommand( 1149 PMOS_RESOURCE semaphoreMem, 1150 PMOS_COMMAND_BUFFER cmdBuffer, 1151 uint32_t semValue); 1152 1153 //! 1154 //! \brief Send MI atomic command 1155 //! 1156 //! \param [in] semaMem 1157 //! Pointer to semaphore resource 1158 //! \param [in] ImmData 1159 //! immediate data for atomic operation 1160 //! \param [in] opCode 1161 //! enum value of MHW_COMMON_MI_ATOMIC_OPCODE 1162 //! \param [in] cmdBuffer 1163 //! Pointer to command buffer 1164 //! 1165 //! \return MOS_STATUS 1166 //! MOS_STATUS_SUCCESS if success, else fail reason 1167 //! 1168 MOS_STATUS SendMIAtomicCmd( 1169 PMOS_RESOURCE semaMem, 1170 uint32_t ImmData, 1171 MHW_COMMON_MI_ATOMIC_OPCODE opCode, 1172 PMOS_COMMAND_BUFFER cmdBuffer); 1173 1174 //! 1175 //! \brief Store data to semaphore memory 1176 //! 1177 //! \param [in] semaphoreMem 1178 //! Pointer to semaphore resource 1179 //! \param [in] cmdBuffer 1180 //! Pointer to command buffer 1181 //! \param [in] value 1182 //! Value to store in semaphore memory 1183 //! 1184 //! \return MOS_STATUS 1185 //! MOS_STATUS_SUCCESS if success, else fail reason 1186 //! 1187 MOS_STATUS SetSemaphoreMem( 1188 PMOS_RESOURCE semaphoreMem, 1189 PMOS_COMMAND_BUFFER cmdBuffer, 1190 uint32_t value); 1191 1192 //! 1193 //! \brief Allocate resources for encoder instance 1194 //! \details It is invoked when initializing encoder instance and it would call #AllocateEncResources(), #AllocateBrcResources(), 1195 //! #AllocatePakResources() and #InitSurfaceInfoTable() 1196 //! 1197 //! \return MOS_STATUS 1198 //! MOS_STATUS_SUCCESS if success, else fail reason 1199 //! 1200 MOS_STATUS AllocateResources(); 1201 1202 //! 1203 //! \brief Free encoder resources 1204 //! \details It is invoked when destorying encoder instance and it would call #FreeEncResources(), #FreeBrcResources() 1205 //! and #FreePakResources() 1206 //! 1207 //! \return void 1208 //! 1209 void FreeResources(); 1210 1211 //! 1212 //! \brief Help function to allocate a 1D buffer 1213 //! 1214 //! \param [in,out] buffer 1215 //! Pointer to allocated buffer 1216 //! \param [in] size 1217 //! Buffer size 1218 //! \param [in] name 1219 //! Buffer name 1220 //! 1221 //! \return MOS_STATUS 1222 //! MOS_STATUS_SUCCESS if success, else fail reason 1223 //! 1224 MOS_STATUS AllocateBuffer( 1225 PCODECHAL_ENCODE_BUFFER buffer, 1226 uint32_t size, 1227 const char* name, 1228 int32_t dwMemType = 0); 1229 1230 //! 1231 //! \brief Help function to allocate a generic 2D surface 1232 //! 1233 //! \param [in,out] surface 1234 //! Pointer to allocated surface 1235 //! \param [in] width 1236 //! Surface width 1237 //! \param [in] height 1238 //! Surface height 1239 //! \param [in] name 1240 //! Surface name 1241 //! \param [in] tileType 1242 //! Tile type 1243 //! 1244 //! \return MOS_STATUS 1245 //! MOS_STATUS_SUCCESS if success, else fail reason 1246 //! 1247 MOS_STATUS AllocateBuffer2D( 1248 PMOS_SURFACE surface, 1249 uint32_t width, 1250 uint32_t height, 1251 const char* name, 1252 MOS_TILE_TYPE tileType = MOS_TILE_LINEAR, 1253 int32_t dwMemType = 0); 1254 1255 //! 1256 //! \brief Help function to allocate a NV12 TILE_Y surface 1257 //! 1258 //! \param [in,out] surface 1259 //! Pointer to allocated surface 1260 //! \param [in] width 1261 //! Surface width 1262 //! \param [in] height 1263 //! Surface height 1264 //! \param [in] name 1265 //! Surface name 1266 //! 1267 //! \return MOS_STATUS 1268 //! MOS_STATUS_SUCCESS if success, else fail reason 1269 //! 1270 MOS_STATUS AllocateSurface( 1271 PMOS_SURFACE surface, 1272 uint32_t width, 1273 uint32_t height, 1274 const char* name, 1275 int32_t dwMemType = 0); 1276 1277 //! 1278 //! \brief Help function to allocate PAK slice level batch buffers 1279 //! 1280 //! \param [in] numSlices 1281 //! Number of slices 1282 //! \param [in] numPakPasses 1283 //! Number of PAK passes 1284 //! 1285 //! \return MOS_STATUS 1286 //! MOS_STATUS_SUCCESS if success, else fail reason 1287 //! 1288 MOS_STATUS AllocateBatchBufferForPakSlices( 1289 uint32_t numSlices, 1290 unsigned char numPakPasses); 1291 1292 //! \brief Calculates the PSNR values for luma/ chroma 1293 //! 1294 //! \param [in, out] encodeStatus 1295 //! Pointer to encoder status 1296 //! \param [in, out] encodeStatusReport 1297 //! Pointer to encoder status report 1298 //! 1299 //! \return MOS_STATUS 1300 //! MOS_STATUS_SUCCESS if success, else fail reason 1301 //! 1302 MOS_STATUS CalculatePSNR( 1303 EncodeStatus *encodeStatus, 1304 EncodeStatusReport *encodeStatusReport); 1305 1306 //! \brief Copy sum square error for luma/ chroma channel from 1307 //! frame statistics report into encodeStatus buffer 1308 //! 1309 //! \param [in, out] cmdBuffer 1310 //! Pointer to command buffer 1311 //! 1312 //! \return MOS_STATUS 1313 //! MOS_STATUS_SUCCESS if success, else fail reason 1314 //! 1315 virtual MOS_STATUS ReadSseStatistics(PMOS_COMMAND_BUFFER cmdBuffer); 1316 1317 //! 1318 //! \brief Help function to release PAK slice level batch buffers 1319 //! 1320 //! \param [in] index 1321 //! Index of batch buffer to be released 1322 //! 1323 //! \return MOS_STATUS 1324 //! MOS_STATUS_SUCCESS if success, else fail reason 1325 //! 1326 MOS_STATUS ReleaseBatchBufferForPakSlices(uint32_t index); 1327 1328 //! 1329 //! \brief Help function to get the MaxMBPS for speicifc level Id 1330 //! 1331 //! \param [in] levelIdc 1332 //! HEVC level Id 1333 //! \param [in] maxMBPS 1334 //! Max MBPS 1335 //! \param [in] maxBytePerPic 1336 //! Max byte per picture 1337 //! 1338 //! \return MaxMBPS(max number of MB per second) for input level Id 1339 //! 1340 MOS_STATUS GetMaxMBPS(uint32_t levelIdc, uint32_t* maxMBPS, uint64_t* maxBytePerPic); 1341 1342 //! 1343 //! \brief Help function to calcuate max frame size corresponding to the input profile/level 1344 //! 1345 //! \return Max frame size in bytes 1346 //! 1347 uint32_t GetProfileLevelMaxFrameSize(); 1348 1349 //! 1350 //! \brief Help function to create a flat scaling list (when scaling list is not passed in sequence parameter) 1351 //! 1352 //! \return void 1353 //! 1354 void CreateFlatScalingList(); 1355 1356 //! 1357 //! \brief Help function to create a default scaling list (when scaling list data is not presented in picture parameter) 1358 //! 1359 //! \return void 1360 //! 1361 void CreateDefaultScalingList(); 1362 1363 //! 1364 //! \brief Validate low delay mode for B frame 1365 //! 1366 //! \param [in] slcParams 1367 //! Pointer to slice parameter 1368 //! 1369 //! \return MOS_STATUS 1370 //! MOS_STATUS_SUCCESS if success, else fail reason 1371 //! 1372 MOS_STATUS ValidateLowDelayBFrame(PCODEC_HEVC_ENCODE_SLICE_PARAMS slcParams); 1373 1374 //! 1375 //! \brief Validate if reference list L0 and L1 are same 1376 //! 1377 //! \param [in] slcParams 1378 //! Pointer to slice parameter 1379 //! 1380 //! \return MOS_STATUS 1381 //! MOS_STATUS_SUCCESS if success, else fail reason 1382 //! 1383 MOS_STATUS ValidateSameRefInL0L1(PCODEC_HEVC_ENCODE_SLICE_PARAMS slcParams); 1384 1385 //! 1386 //! \brief Verify slice SAO state 1387 //! 1388 //! \return MOS_STATUS 1389 //! MOS_STATUS_SUCCESS if success, else fail reason 1390 //! 1391 MOS_STATUS VerifySliceSAOState(); 1392 1393 //! 1394 //! \brief Update recon surface to Variant format for 422 10-bit 1395 //! 1396 //! \return MOS_STATUS 1397 //! MOS_STATUS_SUCCESS if success, else fail reason 1398 //! 1399 MOS_STATUS UpdateYUY2SurfaceInfo( 1400 PMOS_SURFACE surface, 1401 bool is10Bit); 1402 1403 //! 1404 //! \brief Check if the color format of the surface is supported 1405 //! 1406 //! \details If the color format is not supported, and the Codec/Gen supports color space conversion feature 1407 // then Csc+Ds+Conversion kernel will be called to convert raw surface to supported color format 1408 //! 1409 //! \param [in] surface 1410 //! pointer to surface 1411 //! 1412 //! \return bool 1413 //! true if the color format is supported, false otherwise 1414 //! CheckSupportedFormat(PMOS_SURFACE surface)1415 virtual bool CheckSupportedFormat(PMOS_SURFACE surface) { return true; } 1416 1417 //! 1418 //! \brief Initialize encoder instance with the provided settings 1419 //! \details When derived class overwrite this function to do its own initialization, 1420 // it should call #CodechalEncodeHevcBase::Initialize() first 1421 // to do common initializations 1422 //! 1423 //! \param [in] settings 1424 //! Encoder settings 1425 //! 1426 //! \return MOS_STATUS 1427 //! MOS_STATUS_SUCCESS if success, else fail reason 1428 //! 1429 virtual MOS_STATUS Initialize(CodechalSetting * settings); 1430 1431 //! 1432 //! \brief Initialize surface info 1433 //! 1434 //! \return MOS_STATUS 1435 //! MOS_STATUS_SUCCESS if success, else fail reason 1436 //! InitSurfaceInfoTable()1437 virtual MOS_STATUS InitSurfaceInfoTable() 1438 { 1439 return MOS_STATUS_SUCCESS; 1440 } 1441 1442 //! 1443 //! \brief Setup/configure encoder based on sequence parameter set 1444 //! \details It is invoked when the encoder receives a new sequence parameter set and it would 1445 //! set up and configure the encoder state that used for the sequence 1446 //! 1447 //! \return MOS_STATUS 1448 //! MOS_STATUS_SUCCESS if success, else fail reason 1449 //! 1450 virtual MOS_STATUS SetSequenceStructs(); 1451 1452 //! 1453 //! \brief Setup/configure encoder based on picture parameter set 1454 //! \details It is invoked for every picture and it would set up and configure the 1455 // encoder state that used for current picture 1456 //! 1457 //! \return MOS_STATUS 1458 //! MOS_STATUS_SUCCESS if success, else fail reason 1459 //! 1460 virtual MOS_STATUS SetPictureStructs(); 1461 1462 //! 1463 //! \brief Calculate maximum bitsize allowed for LCU 1464 //! \details Calculate LCU max coding size according to log2_max_coding_block_size_minus3 1465 //! 1466 //! \return MOS_STATUS 1467 //! MOS_STATUS_SUCCESS if success, else fail reason 1468 //! 1469 virtual MOS_STATUS CalcLCUMaxCodingSize(); 1470 1471 //! 1472 //! \brief Setup/configure encoder based on slice parameter set 1473 //! \details It is invoked for every picture and and it would set up and configure the 1474 // encoder state that used for current picture and slices 1475 //! 1476 //! \return MOS_STATUS 1477 //! MOS_STATUS_SUCCESS if success, else fail reason 1478 //! 1479 virtual MOS_STATUS SetSliceStructs(); 1480 1481 //! 1482 //! \brief Calculate transform skip parameters 1483 //! 1484 //! \param [in, out] params 1485 //! Transform skip parameters 1486 //! 1487 //! \return void 1488 //! 1489 virtual void CalcTransformSkipParameters(MHW_VDBOX_ENCODE_HEVC_TRANSFORM_SKIP_PARAMS& params); 1490 1491 //! 1492 //! \brief Retreive image status information 1493 //! 1494 //! \param [in] cmdBuffer 1495 //! Pointer to command buffer 1496 //! 1497 //! \return MOS_STATUS 1498 //! MOS_STATUS_SUCCESS if success, else fail reason 1499 //! 1500 virtual MOS_STATUS ReadImageStatus(PMOS_COMMAND_BUFFER cmdBuffer); 1501 1502 //! 1503 //! \brief Retreive HCP status 1504 //! 1505 //! \param [in] cmdBuffer 1506 //! Pointer to command buffer 1507 //! 1508 //! \return MOS_STATUS 1509 //! MOS_STATUS_SUCCESS if success, else fail reason 1510 //! 1511 virtual MOS_STATUS ReadHcpStatus(PMOS_COMMAND_BUFFER cmdBuffer); 1512 1513 //! 1514 //! \brief Retreive BRC Pak statistics 1515 //! 1516 //! \param [in] cmdBuffer 1517 //! Pointer to command buffer 1518 //! \param [in] params 1519 //! BRC pak statistics parameters 1520 //! 1521 //! \return MOS_STATUS 1522 //! MOS_STATUS_SUCCESS if success, else fail reason 1523 //! 1524 virtual MOS_STATUS ReadBrcPakStatistics( 1525 PMOS_COMMAND_BUFFER cmdBuffer, 1526 EncodeReadBrcPakStatsParams* params); 1527 1528 //! 1529 //! \brief Get encoder status report 1530 //! 1531 //! \param [in, out] encodeStatus 1532 //! Pointer to encoder status 1533 //! \param [in, out] encodeStatusReport 1534 //! Pointer to encoder status report 1535 //! 1536 //! \return MOS_STATUS 1537 //! MOS_STATUS_SUCCESS if success, else fail reason 1538 //! 1539 virtual MOS_STATUS GetStatusReport( 1540 EncodeStatus *encodeStatus, 1541 EncodeStatusReport *encodeStatusReport); 1542 1543 //! 1544 //! \brief User Feature key report 1545 //! 1546 //! \return MOS_STATUS 1547 //! MOS_STATUS_SUCCESS if success, else fail reason 1548 //! 1549 virtual MOS_STATUS UserFeatureKeyReport(); 1550 1551 //! 1552 //! \brief Initialize encoder at picture level 1553 //! 1554 //! \param [in] params 1555 //! Picture encoding parameters 1556 //! 1557 //! \return MOS_STATUS 1558 //! MOS_STATUS_SUCCESS if success, else fail reason 1559 //! 1560 virtual MOS_STATUS InitializePicture(const EncoderParams& params); 1561 1562 //! 1563 //! \brief Perform platform capability check 1564 //! 1565 //! \return MOS_STATUS 1566 //! MOS_STATUS_SUCCESS if success, else fail reason 1567 //! PlatformCapabilityCheck()1568 virtual MOS_STATUS PlatformCapabilityCheck() 1569 { 1570 return MOS_STATUS_SUCCESS; 1571 } 1572 1573 //! 1574 //! \brief Set batch buffer for PAK slices 1575 //! 1576 //! \return MOS_STATUS 1577 //! MOS_STATUS_SUCCESS if success, else fail reason 1578 //! 1579 virtual MOS_STATUS SetBatchBufferForPakSlices(); 1580 1581 // HCP/PAK functions 1582 1583 //! 1584 //! \brief Set HCP_PIPE_MODE_SELECT parameters 1585 //! 1586 //! \param [in, out] pipeModeSelectParams 1587 //! HCP_PIPE_MODE_SELECT parameters 1588 //! 1589 //! \return void 1590 //! 1591 virtual void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams); 1592 1593 //! 1594 //! \brief Set HCP_SURFACE_PARAMS for source picture 1595 //! 1596 //! \param [in, out] srcSurfaceParams 1597 //! HCP_SURFACE_PARAMS for source picture 1598 //! 1599 //! \return void 1600 //! 1601 virtual void SetHcpSrcSurfaceParams(MHW_VDBOX_SURFACE_PARAMS& srcSurfaceParams); 1602 1603 //! 1604 //! \brief Set HCP_SURFACE_PARAMS for recon picture 1605 //! 1606 //! \param [in, out] reconSurfaceParams 1607 //! HCP_SURFACE_PARAMS for recon picture 1608 //! 1609 //! \return void 1610 //! 1611 virtual void SetHcpReconSurfaceParams(MHW_VDBOX_SURFACE_PARAMS &reconSurfaceParams); 1612 1613 //! 1614 //! \brief Set HCP_SURFACE_PARAMS for reference picture 1615 //! 1616 //! \param [in, out] refSurfaceParams 1617 //! HCP_SURFACE_PARAMS for reference picture 1618 //! 1619 //! \return void 1620 //! 1621 virtual void SetHcpRefSurfaceParams(MHW_VDBOX_SURFACE_PARAMS &refSurfaceParams); 1622 1623 //! 1624 //! \brief Set HCP_PIPE_BUF_ADDR parameters 1625 //! 1626 //! \param [in, out] pipeBufAddrParams 1627 //! HCP_PIPE_BUF_ADDR parameters 1628 //! 1629 //! \return void 1630 //! 1631 virtual void SetHcpPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams); 1632 1633 //! 1634 //! \brief Set HCP_IND_OBJ_BASE_ADDR parameters 1635 //! 1636 //! \param [in, out] indObjBaseAddrParams 1637 //! HCP_IND_OBJ_BASE_ADDR parameters 1638 //! 1639 //! \return void 1640 //! 1641 virtual void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams); 1642 1643 //! 1644 //! \brief Set HCP_QM_STATE and HCP_FQM_STATE parameters 1645 //! 1646 //! \param [in, out] fqmParams 1647 //! HCP_FQM_STATE parameters 1648 //! \param [in, out] qmParams 1649 //! HCP_QM_STATE parameters 1650 //! 1651 //! \return MOS_STATUS 1652 //! MOS_STATUS_SUCCESS if success, else fail reason 1653 //! 1654 virtual void SetHcpQmStateParams(MHW_VDBOX_QM_PARAMS& fqmParams, MHW_VDBOX_QM_PARAMS& qmParams); 1655 1656 //! 1657 //! \brief Set HCP_PIC_STATE parameters 1658 //! 1659 //! \param [in, out] picStateParams 1660 //! HCP_PIC_STATE parameters 1661 //! 1662 //! \return void 1663 //! 1664 virtual void SetHcpPicStateParams(MHW_VDBOX_HEVC_PIC_STATE& picStateParams); 1665 1666 //! 1667 //! \brief Set HCP_SLICE_STATE parameters shared by all slices 1668 //! 1669 //! \param [in, out] sliceStateParams 1670 //! HCP_SLICE_STATE parameters 1671 //! 1672 //! \return void 1673 //! 1674 virtual void SetHcpSliceStateCommonParams(MHW_VDBOX_HEVC_SLICE_STATE& sliceStateParams); 1675 1676 //! 1677 //! \brief Create HCP_SLICE_STATE parameters shared by all slices 1678 //! 1679 //! \return void 1680 //! 1681 virtual void CreateMhwParams(); 1682 1683 //! 1684 //! \brief Set HCP_SLICE_STATE parameters that are different at slice level 1685 //! 1686 //! \param [in, out] sliceStateParams 1687 //! HCP_SLICE_STATE parameters 1688 //! \param [in] slcData 1689 //! Pointer to CODEC_ENCODE_SLCDATA 1690 //! \param [in] currSlcIdx 1691 //! Current slice index 1692 //! 1693 //! \return void 1694 //! 1695 virtual void SetHcpSliceStateParams( 1696 MHW_VDBOX_HEVC_SLICE_STATE& sliceStateParams, 1697 PCODEC_ENCODER_SLCDATA slcData, 1698 uint32_t currSlcIdx); 1699 1700 //! 1701 //! \brief Add HCP_REF_IDX command to command buffer or batch buffer 1702 //! 1703 //! \param [in, out] cmdBuffer 1704 //! Pointer to the command buffer 1705 //! \param [in, out] batchBuffer 1706 //! Pointer to the batch buffer 1707 //! \param [in] params 1708 //! Pointer to MHW_VDBOX_HEVC_SLICE_STATE parameters 1709 //! 1710 //! \return MOS_STATUS 1711 //! MOS_STATUS_SUCCESS if success, else fail reason 1712 //! 1713 virtual MOS_STATUS AddHcpRefIdxCmd( 1714 PMOS_COMMAND_BUFFER cmdBuffer, 1715 PMHW_BATCH_BUFFER batchBuffer, 1716 PMHW_VDBOX_HEVC_SLICE_STATE params); 1717 1718 //! 1719 //! \brief Add HCP_PAK_INSERT_OBJECT commands for NALUs to command buffer or batch buffer 1720 //! \details This function would add multiple HCP_PAK_INSERT_OBJECT, one of each NALU 1721 //! 1722 //! \param [in, out] cmdBuffer 1723 //! Pointer to the command buffer 1724 //! \param [in, out] batchBuffer 1725 //! Pointer to the batch buffer 1726 //! \param [in] params 1727 //! Pointer to MHW_VDBOX_HEVC_SLICE_STATE parameters 1728 //! 1729 //! \return MOS_STATUS 1730 //! MOS_STATUS_SUCCESS if success, else fail reason 1731 //! 1732 virtual MOS_STATUS AddHcpPakInsertNALUs( 1733 PMOS_COMMAND_BUFFER cmdBuffer, 1734 PMHW_BATCH_BUFFER batchBuffer, 1735 PMHW_VDBOX_HEVC_SLICE_STATE params); 1736 1737 //! 1738 //! \brief Add HCP_PAK_INSERT_OBJECT commands for slice header to command buffer or batch buffer 1739 //! 1740 //! \param [in, out] cmdBuffer 1741 //! Pointer to the command buffer 1742 //! \param [in, out] batchBuffer 1743 //! Pointer to the batch buffer 1744 //! \param [in] params 1745 //! Pointer to MHW_VDBOX_HEVC_SLICE_STATE parameters 1746 //! 1747 //! \return MOS_STATUS 1748 //! MOS_STATUS_SUCCESS if success, else fail reason 1749 //! 1750 virtual MOS_STATUS AddHcpPakInsertSliceHeader( 1751 PMOS_COMMAND_BUFFER cmdBuffer, 1752 PMHW_BATCH_BUFFER batchBuffer, 1753 PMHW_VDBOX_HEVC_SLICE_STATE params); 1754 1755 //! \brief Initialize kernel state 1756 //! 1757 //! \return MOS_STATUS 1758 //! MOS_STATUS_SUCCESS if success, else fail reason 1759 //! 1760 virtual MOS_STATUS InitKernelState() = 0; 1761 1762 //! 1763 //! \brief Get max binding table count required 1764 //! 1765 //! \return Value of max binding table count 1766 //! 1767 virtual uint32_t GetMaxBtCount() = 0; 1768 1769 //! 1770 //! \brief Allocate resources for PAK 1771 //! 1772 //! \return MOS_STATUS 1773 //! MOS_STATUS_SUCCESS if success, else fail reason 1774 //! 1775 virtual MOS_STATUS AllocatePakResources(); 1776 1777 //! 1778 //! \brief Free PAK resources 1779 //! 1780 //! \return MOS_STATUS 1781 //! MOS_STATUS_SUCCESS if success, else fail reason 1782 //! 1783 virtual MOS_STATUS FreePakResources(); 1784 1785 //! 1786 //! \brief Allocate resources for ENC 1787 //! 1788 //! \return MOS_STATUS 1789 //! MOS_STATUS_SUCCESS if success, else fail reason 1790 //! 1791 virtual MOS_STATUS AllocateEncResources() = 0; 1792 1793 //! 1794 //! \brief Free ENC resources 1795 //! 1796 //! \return MOS_STATUS 1797 //! MOS_STATUS_SUCCESS if success, else fail reason 1798 //! 1799 virtual MOS_STATUS FreeEncResources() = 0; 1800 1801 //! 1802 //! \brief Allocate BRC resources 1803 //! 1804 //! \return MOS_STATUS 1805 //! MOS_STATUS_SUCCESS if success, else fail reason 1806 //! 1807 virtual MOS_STATUS AllocateBrcResources() = 0; 1808 1809 //! 1810 //! \brief Free BRC resources 1811 //! 1812 //! \return MOS_STATUS 1813 //! MOS_STATUS_SUCCESS if success, else fail reason 1814 //! 1815 virtual MOS_STATUS FreeBrcResources() = 0; 1816 1817 //! 1818 //! \brief Calculate down scaled dimensions 1819 //! 1820 //! \return MOS_STATUS 1821 //! MOS_STATUS_SUCCESS if success, else fail reason 1822 //! 1823 virtual MOS_STATUS CalcScaledDimensions() = 0; 1824 1825 //! 1826 //! \brief Validate ref frame data 1827 //! 1828 //! \param [in] slcParams 1829 //! Slice parameters 1830 //! 1831 //! \return MOS_STATUS 1832 //! MOS_STATUS_SUCCESS if success, else fail reason 1833 //! 1834 virtual MOS_STATUS ValidateRefFrameData(PCODEC_HEVC_ENCODE_SLICE_PARAMS slcParams) = 0; 1835 1836 //! 1837 //! \brief Encode kernel functions 1838 //! 1839 //! \return MOS_STATUS 1840 //! MOS_STATUS_SUCCESS if success, else fail reason 1841 //! 1842 virtual MOS_STATUS EncodeKernelFunctions() = 0; 1843 1844 //! 1845 //! \brief Execute kernel functions 1846 //! 1847 //! \return MOS_STATUS 1848 //! MOS_STATUS_SUCCESS if success, else fail reason 1849 //! 1850 MOS_STATUS ExecuteKernelFunctions(); 1851 1852 //! 1853 //! \brief Encode command at picture level 1854 //! 1855 //! \return MOS_STATUS 1856 //! MOS_STATUS_SUCCESS if success, else fail reason 1857 //! 1858 virtual MOS_STATUS ExecutePictureLevel() = 0; 1859 1860 //! 1861 //! \brief Encode command at slice level 1862 //! 1863 //! \return MOS_STATUS 1864 //! MOS_STATUS_SUCCESS if success, else fail reason 1865 //! 1866 virtual MOS_STATUS ExecuteSliceLevel() = 0; 1867 1868 //! 1869 //! \brief Calculate picture state command size 1870 //! 1871 //! \return MOS_STATUS 1872 //! MOS_STATUS_SUCCESS if success, else fail reason 1873 //! 1874 virtual MOS_STATUS CalculatePictureStateCommandSize(); 1875 1876 //! 1877 //! \brief Calculate picture state command size 1878 //! 1879 //! \param [in, out] cmdBuffer 1880 //! Pointer to the command buffer 1881 //! 1882 //! \return MOS_STATUS 1883 //! MOS_STATUS_SUCCESS if success, else fail reason 1884 //! 1885 virtual MOS_STATUS AddHcpPipeBufAddrCmd( 1886 PMOS_COMMAND_BUFFER cmdBuffer); 1887 1888 //! 1889 //! \brief Initialize MMC state 1890 //! 1891 //! \return MOS_STATUS 1892 //! MOS_STATUS_SUCCESS if success 1893 //! 1894 virtual MOS_STATUS InitMmcState(); 1895 1896 //! 1897 //! \brief Compute Temporal Different 1898 //! 1899 //! \return short 1900 //! return the current picordercnt difference 1901 //! 1902 short ComputeTemporalDifferent( 1903 CODEC_PICTURE refPic); 1904 1905 //! 1906 //! \brief Init surface codec params 1D 1907 //! 1908 //! \return MOS_STATUS 1909 //! MOS_STATUS_SUCCESS if success 1910 //! 1911 MOS_STATUS InitSurfaceCodecParams1D( 1912 CODECHAL_SURFACE_CODEC_PARAMS* p, 1913 PMOS_RESOURCE buffer, 1914 uint32_t size, 1915 uint32_t offset, 1916 uint32_t cacheabilityControl, 1917 uint32_t bindingTableOffset, 1918 bool isWritable); 1919 1920 //! 1921 //! \brief Init surface codec params 2D 1922 //! 1923 //! \return MOS_STATUS 1924 //! MOS_STATUS_SUCCESS if success 1925 //! 1926 MOS_STATUS InitSurfaceCodecParams2D( 1927 CODECHAL_SURFACE_CODEC_PARAMS* p, 1928 PMOS_SURFACE surface, 1929 uint32_t cacheabilityControl, 1930 uint32_t bindingTableOffset, 1931 uint32_t verticalLineStride, 1932 bool isWritable); 1933 1934 //! 1935 //! \brief Update the slice count according to the slice shutdown policy 1936 //! UpdateSSDSliceCount()1937 virtual void UpdateSSDSliceCount() { return; }; 1938 1939 void MotionEstimationDisableCheck(); 1940 1941 //! 1942 //! \brief Allocate 4x ME resources 1943 //! 1944 //! \param [in] param 1945 //! Pointer to parameters 1946 //! 1947 //! \return MOS_STATUS 1948 //! MOS_STATUS_SUCCESS if success, else fail reason 1949 //! 1950 MOS_STATUS AllocateResources4xME( 1951 HmeParams* param); 1952 1953 //! 1954 //! \brief Allocate 16x ME resources 1955 //! 1956 //! \param [in] param 1957 //! Pointer to parameters 1958 //! 1959 //! \return MOS_STATUS 1960 //! MOS_STATUS_SUCCESS if success, else fail reason 1961 //! 1962 MOS_STATUS AllocateResources16xME( 1963 HmeParams* param); 1964 1965 //! 1966 //! \brief Allocate 32x ME resources 1967 //! 1968 //! \param [in] param 1969 //! Pointer to parameters 1970 //! 1971 //! \return MOS_STATUS 1972 //! MOS_STATUS_SUCCESS if success, else fail reason 1973 //! 1974 MOS_STATUS AllocateResources32xME( 1975 HmeParams* param); 1976 1977 //! 1978 //! \brief Destroy ME resources 1979 //! 1980 //! \param [in] param 1981 //! Pointer to parameters 1982 //! 1983 //! \return MOS_STATUS 1984 //! MOS_STATUS_SUCCESS if success, else fail reason 1985 //! 1986 MOS_STATUS DestroyMEResources( 1987 HmeParams* param); 1988 1989 #if USE_CODECHAL_DEBUG_TOOL 1990 MOS_STATUS DumpSeqParams( 1991 PCODEC_HEVC_ENCODE_SEQUENCE_PARAMS seqParams); 1992 1993 MOS_STATUS DumpPicParams( 1994 PCODEC_HEVC_ENCODE_PICTURE_PARAMS picParams); 1995 1996 MOS_STATUS DumpFeiPicParams( 1997 CodecEncodeHevcFeiPicParams *feiPicParams); 1998 1999 MOS_STATUS DumpSliceParams( 2000 PCODEC_HEVC_ENCODE_SLICE_PARAMS sliceParams, 2001 PCODEC_HEVC_ENCODE_PICTURE_PARAMS picParams); 2002 2003 MOS_STATUS DumpMbEncPakOutput(PCODEC_REF_LIST currRefList, CodechalDebugInterface* debugInterface); 2004 2005 MOS_STATUS DumpFrameStatsBuffer(CodechalDebugInterface* debugInterface); 2006 2007 #endif 2008 }; 2009 2010 #endif // __CODECHAL_ENCODE_HEVC_BASE_H__ 2011