1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_encode_hevc_g9.h 24 //! \brief HEVC dual-pipe encoder for GEN9 platform. 25 //! 26 27 #ifndef __CODECHAL_ENCODE_HEVC_G9_H__ 28 #define __CODECHAL_ENCODE_HEVC_G9_H__ 29 30 #include "codechal_encode_hevc.h" 31 32 enum CODECHAL_ENCODE_BINDING_TABLE_OFFSET_ME_CM_G9 33 { 34 CODECHAL_ENCODE_ME_MV_DATA_SURFACE_CM_G9 = 0, 35 CODECHAL_ENCODE_16xME_MV_DATA_SURFACE_CM_G9 = 1, 36 CODECHAL_ENCODE_32xME_MV_DATA_SURFACE_CM_G9 = 1, 37 CODECHAL_ENCODE_ME_DISTORTION_SURFACE_CM_G9 = 2, 38 CODECHAL_ENCODE_ME_BRC_DISTORTION_CM_G9 = 3, 39 CODECHAL_ENCODE_ME_RESERVED0_CM_G9 = 4, 40 CODECHAL_ENCODE_ME_CURR_FOR_FWD_REF_CM_G9 = 5, 41 CODECHAL_ENCODE_ME_FWD_REF_IDX0_CM_G9 = 6, 42 CODECHAL_ENCODE_ME_RESERVED1_CM_G9 = 7, 43 CODECHAL_ENCODE_ME_FWD_REF_IDX1_CM_G9 = 8, 44 CODECHAL_ENCODE_ME_RESERVED2_CM_G9 = 9, 45 CODECHAL_ENCODE_ME_FWD_REF_IDX2_CM_G9 = 10, 46 CODECHAL_ENCODE_ME_RESERVED3_CM_G9 = 11, 47 CODECHAL_ENCODE_ME_FWD_REF_IDX3_CM_G9 = 12, 48 CODECHAL_ENCODE_ME_RESERVED4_CM_G9 = 13, 49 CODECHAL_ENCODE_ME_FWD_REF_IDX4_CM_G9 = 14, 50 CODECHAL_ENCODE_ME_RESERVED5_CM_G9 = 15, 51 CODECHAL_ENCODE_ME_FWD_REF_IDX5_CM_G9 = 16, 52 CODECHAL_ENCODE_ME_RESERVED6_CM_G9 = 17, 53 CODECHAL_ENCODE_ME_FWD_REF_IDX6_CM_G9 = 18, 54 CODECHAL_ENCODE_ME_RESERVED7_CM_G9 = 19, 55 CODECHAL_ENCODE_ME_FWD_REF_IDX7_CM_G9 = 20, 56 CODECHAL_ENCODE_ME_RESERVED8_CM_G9 = 21, 57 CODECHAL_ENCODE_ME_CURR_FOR_BWD_REF_CM_G9 = 22, 58 CODECHAL_ENCODE_ME_BWD_REF_IDX0_CM_G9 = 23, 59 CODECHAL_ENCODE_ME_RESERVED9_CM_G9 = 24, 60 CODECHAL_ENCODE_ME_BWD_REF_IDX1_CM_G9 = 25, 61 CODECHAL_ENCODE_ME_VDENC_STREAMIN_CM_G9 = 26, 62 CODECHAL_ENCODE_ME_NUM_SURFACES_CM_G9 = 27 63 }; 64 65 //! Intra transform type 66 enum 67 { 68 INTRA_TRANSFORM_REGULAR = 0, 69 INTRA_TRANSFORM_RESERVED = 1, 70 INTRA_TRANSFORM_HAAR = 2, 71 INTRA_TRANSFORM_HADAMARD = 3 72 }; 73 74 // Downscaling 2x kernels for Ultra HME 75 struct MEDIA_OBJECT_DOWNSCALING_2X_STATIC_DATA_G9 76 { 77 union { 78 struct { 79 uint32_t PicWidth : MOS_BITFIELD_RANGE(0, 15); 80 uint32_t PicHeight : MOS_BITFIELD_RANGE(16, 31); 81 }; 82 uint32_t Value; 83 } DW0; 84 85 union { 86 struct { 87 uint32_t Reserved; 88 }; 89 uint32_t Value; 90 } DW1; 91 92 union { 93 struct { 94 uint32_t Reserved; 95 }; 96 uint32_t Value; 97 } DW2; 98 99 union { 100 struct { 101 uint32_t Reserved; 102 }; 103 uint32_t Value; 104 } DW3; 105 106 union { 107 struct { 108 uint32_t Reserved; 109 }; 110 uint32_t Value; 111 } DW4; 112 113 union { 114 struct { 115 uint32_t Reserved; 116 }; 117 uint32_t Value; 118 } DW5; 119 120 union { 121 struct { 122 uint32_t Reserved; 123 }; 124 uint32_t Value; 125 } DW6; 126 127 union { 128 struct { 129 uint32_t Reserved; 130 }; 131 uint32_t Value; 132 } DW7; 133 134 union { 135 struct { 136 uint32_t BTI_Src_Y; 137 }; 138 uint32_t Value; 139 } DW8; 140 141 union { 142 struct { 143 uint32_t BTI_Dst_Y; 144 }; 145 uint32_t Value; 146 } DW9; 147 }; 148 149 //! HEVC encoder intra 32x32 PU mode decision kernel curbe for GEN9 150 struct CODECHAL_ENC_HEVC_I_32x32_PU_MODE_DECISION_CURBE_G9 151 { 152 union { 153 struct { 154 uint32_t FrameWidth : MOS_BITFIELD_RANGE(0, 15); 155 uint32_t FrameHeight : MOS_BITFIELD_RANGE(16, 31); 156 }; 157 uint32_t Value; 158 } DW0; 159 160 union { 161 struct { 162 uint32_t SliceType : MOS_BITFIELD_RANGE(0, 1); 163 uint32_t PuType : MOS_BITFIELD_RANGE(2, 3); 164 uint32_t EnableStatsDataDump : MOS_BITFIELD_BIT(4); 165 uint32_t LCUType : MOS_BITFIELD_BIT(5); 166 uint32_t Res_6_15 : MOS_BITFIELD_RANGE(6, 15); 167 uint32_t SliceQP : MOS_BITFIELD_RANGE(16, 23); 168 uint32_t BRCEnable : MOS_BITFIELD_BIT(24); 169 uint32_t LCUBRCEnable : MOS_BITFIELD_BIT(25); 170 uint32_t ROIEnable : MOS_BITFIELD_BIT(26); 171 uint32_t FASTSurveillanceFlag : MOS_BITFIELD_BIT(27); 172 uint32_t Res_28 : MOS_BITFIELD_BIT(28); 173 uint32_t EnableFlexibleParam : MOS_BITFIELD_BIT(29); 174 uint32_t EnableQualityImprovement : MOS_BITFIELD_BIT(30); 175 uint32_t EnableDebugDump : MOS_BITFIELD_BIT(31); 176 }; 177 uint32_t Value; 178 } DW1; 179 180 union { 181 struct { 182 uint32_t Lambda; 183 }; 184 uint32_t Value; 185 } DW2; 186 187 union { 188 struct { 189 uint32_t ModeCost32x32; 190 }; 191 uint32_t Value; 192 } DW3; 193 194 union { 195 struct { 196 uint32_t EarlyExit; 197 }; 198 uint32_t Value; 199 } DW4; 200 201 union { 202 struct { 203 uint32_t Reserved; 204 }; 205 uint32_t Value; 206 } DW5; 207 208 union { 209 struct { 210 uint32_t Reserved; 211 }; 212 uint32_t Value; 213 } DW6; 214 215 union { 216 struct { 217 uint32_t Reserved; 218 }; 219 uint32_t Value; 220 } DW7; 221 222 union { 223 struct { 224 uint32_t BTI_32x32PU_Output; 225 }; 226 uint32_t Value; 227 } DW8; 228 229 union { 230 struct { 231 uint32_t BTI_Src_Y; 232 }; 233 uint32_t Value; 234 } DW9; 235 236 union { 237 struct { 238 uint32_t BTI_Src_Y2x; 239 }; 240 uint32_t Value; 241 } DW10; 242 243 union { 244 struct { 245 uint32_t BTI_Slice_Map; 246 }; 247 uint32_t Value; 248 } DW11; 249 250 union { 251 struct { 252 uint32_t BTI_Src_Y2x_VME; 253 }; 254 uint32_t Value; 255 } DW12; 256 257 union { 258 struct { 259 uint32_t BTI_Brc_Input; 260 }; 261 uint32_t Value; 262 } DW13; 263 264 union { 265 struct { 266 uint32_t BTI_LCU_Qp_Surface; 267 }; 268 uint32_t Value; 269 } DW14; 270 271 union { 272 struct { 273 uint32_t BTI_Brc_Data; 274 }; 275 uint32_t Value; 276 } DW15; 277 278 union { 279 struct { 280 uint32_t BTI_Stats_Data; 281 }; 282 uint32_t Value; 283 } DW16; 284 285 union { 286 struct { 287 uint32_t BTI_Kernel_Debug; 288 }; 289 uint32_t Value; 290 } DW17; 291 }; 292 293 using PCODECHAL_ENC_HEVC_I_32x32_PU_MODE_DECISION_CURBE_G9 = struct CODECHAL_ENC_HEVC_I_32x32_PU_MODE_DECISION_CURBE_G9*; 294 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_ENC_HEVC_I_32x32_PU_MODE_DECISION_CURBE_G9)) == 18); 295 296 //! HEVC encoder intra 16x16 SAD kernel curbe for GEN9 297 struct CODECHAL_ENC_HEVC_I_16x16_SAD_CURBE_G9 298 { 299 union { 300 struct { 301 uint32_t FrameWidth : MOS_BITFIELD_RANGE(0, 15); 302 uint32_t FrameHeight : MOS_BITFIELD_RANGE(16, 31); 303 }; 304 uint32_t Value; 305 } DW0; 306 307 union { 308 struct { 309 uint32_t Log2MaxCUSize : MOS_BITFIELD_RANGE(0, 7); 310 uint32_t Log2MinCUSize : MOS_BITFIELD_RANGE(8, 15); 311 uint32_t Log2MinTUSize : MOS_BITFIELD_RANGE(16, 23); 312 uint32_t EnableIntraEarlyExit : MOS_BITFIELD_BIT(24); 313 uint32_t Res_25_31 : MOS_BITFIELD_RANGE(25, 31); 314 }; 315 uint32_t Value; 316 } DW1; 317 318 union { 319 struct { 320 uint32_t SliceType : MOS_BITFIELD_RANGE(0, 1); 321 uint32_t SimFlagForInter : MOS_BITFIELD_BIT(2); 322 uint32_t FASTSurveillanceFlag : MOS_BITFIELD_BIT(3); 323 uint32_t Res_4_31 : MOS_BITFIELD_RANGE(4, 31); 324 }; 325 uint32_t Value; 326 } DW2; 327 328 union { 329 struct { 330 uint32_t Reserved; 331 }; 332 uint32_t Value; 333 } DW3; 334 335 union { 336 struct { 337 uint32_t Reserved; 338 }; 339 uint32_t Value; 340 } DW4; 341 342 union { 343 struct { 344 uint32_t Reserved; 345 }; 346 uint32_t Value; 347 } DW5; 348 349 union { 350 struct { 351 uint32_t Reserved; 352 }; 353 uint32_t Value; 354 } DW6; 355 356 union { 357 struct { 358 uint32_t Reserved; 359 }; 360 uint32_t Value; 361 } DW7; 362 363 union { 364 struct { 365 uint32_t BTI_Src_Y; 366 }; 367 uint32_t Value; 368 } DW8; 369 370 union { 371 struct { 372 uint32_t BTI_Sad_16x16_PU_Output; 373 }; 374 uint32_t Value; 375 } DW9; 376 377 union { 378 struct { 379 uint32_t BTI_32x32_Pu_ModeDecision; 380 }; 381 uint32_t Value; 382 } DW10; 383 384 union { 385 struct { 386 uint32_t BTI_Slice_Map; 387 }; 388 uint32_t Value; 389 } DW11; 390 391 union { 392 struct { 393 uint32_t BTI_Simplest_Intra; 394 }; 395 uint32_t Value; 396 } DW12; 397 398 union { 399 struct { 400 uint32_t BTI_Debug; 401 }; 402 uint32_t Value; 403 } DW13; 404 }; 405 406 using PCODECHAL_ENC_HEVC_I_16x16_SAD_CURBE_G9 = struct CODECHAL_ENC_HEVC_I_16x16_SAD_CURBE_G9*; 407 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_ENC_HEVC_I_16x16_SAD_CURBE_G9)) == 14); 408 409 //! HEVC encoder intra 16x16 PU mode decision kernel curbe for GEN9 410 struct CODECHAL_ENC_HEVC_I_16x16_PU_MODEDECISION_CURBE_G9 411 { 412 union { 413 struct { 414 uint32_t FrameWidth : MOS_BITFIELD_RANGE(0, 15); 415 uint32_t FrameHeight : MOS_BITFIELD_RANGE(16, 31); 416 }; 417 uint32_t Value; 418 } DW0; 419 420 union { 421 struct { 422 uint32_t Log2MaxCUSize : MOS_BITFIELD_RANGE(0, 7); 423 uint32_t Log2MinCUSize : MOS_BITFIELD_RANGE(8, 15); 424 uint32_t Log2MinTUSize : MOS_BITFIELD_RANGE(16, 23); 425 uint32_t SliceQp : MOS_BITFIELD_RANGE(24, 31); 426 }; 427 uint32_t Value; 428 } DW1; 429 430 union { 431 struct { 432 uint32_t FixedPoint_Lambda_PredMode; 433 }; 434 uint32_t Value; 435 } DW2; 436 437 union { 438 struct { 439 uint32_t LambdaScalingFactor : MOS_BITFIELD_RANGE(0, 7); 440 uint32_t SliceType : MOS_BITFIELD_RANGE(8, 9); 441 uint32_t Reserved_10_15 : MOS_BITFIELD_RANGE(10, 15); 442 uint32_t IntraRefreshEn : MOS_BITFIELD_RANGE(16, 17); 443 uint32_t EnableRollingIntra : MOS_BITFIELD_BIT(18); 444 uint32_t HalfUpdateMixedLCU : MOS_BITFIELD_BIT(19); 445 uint32_t Reserved_20_23 : MOS_BITFIELD_RANGE(20, 23); 446 uint32_t EnableIntraEarlyExit : MOS_BITFIELD_BIT(24); 447 uint32_t BRCEnable : MOS_BITFIELD_BIT(25); 448 uint32_t LCUBRCEnable : MOS_BITFIELD_BIT(26); 449 uint32_t ROIEnable : MOS_BITFIELD_BIT(27); 450 uint32_t FASTSurveillanceFlag : MOS_BITFIELD_BIT(28); 451 uint32_t EnableQualityImprovement : MOS_BITFIELD_BIT(29); 452 uint32_t EnableFlexibleParam : MOS_BITFIELD_BIT(30); 453 uint32_t Reserved_31 : MOS_BITFIELD_BIT(31); 454 }; 455 uint32_t Value; 456 } DW3; 457 458 union { 459 struct { 460 uint32_t PenaltyForIntra8x8NonDCPredMode : MOS_BITFIELD_RANGE(0, 7); 461 uint32_t IntraComputeType : MOS_BITFIELD_RANGE(8, 15); 462 uint32_t AVCIntra8x8Mask : MOS_BITFIELD_RANGE(16, 23); 463 uint32_t IntraSadAdjust : MOS_BITFIELD_RANGE(24, 31); 464 }; 465 uint32_t Value; 466 } DW4; 467 468 union { 469 struct { 470 uint32_t FixedPoint_Lambda_CU_Mode_for_Cost_Calculation; 471 }; 472 uint32_t Value; 473 } DW5; 474 475 union { 476 struct { 477 uint32_t ScreenContentFlag : MOS_BITFIELD_BIT(0); 478 uint32_t Reserved : MOS_BITFIELD_RANGE(1, 31); 479 }; 480 uint32_t Value; 481 } DW6; 482 483 union { 484 struct { 485 uint32_t ModeCostIntraNonPred : MOS_BITFIELD_RANGE(0, 7); 486 uint32_t ModeCostIntra16x16 : MOS_BITFIELD_RANGE(8, 15); 487 uint32_t ModeCostIntra8x8 : MOS_BITFIELD_RANGE(16, 23); 488 uint32_t ModeCostIntra4x4 : MOS_BITFIELD_RANGE(24, 31); 489 }; 490 uint32_t Value; 491 } DW7; 492 493 union { 494 struct { 495 uint32_t FixedPoint_Lambda_CU_Mode_for_Luma; 496 }; 497 uint32_t Value; 498 } DW8; 499 500 union { 501 struct { 502 uint32_t IntraRefreshMBNum : MOS_BITFIELD_RANGE(0, 15); 503 uint32_t IntraRefreshUnitInMB : MOS_BITFIELD_RANGE(16, 23); 504 uint32_t IntraRefreshQPDelta : MOS_BITFIELD_RANGE(24, 31); 505 }; 506 uint32_t Value; 507 } DW9; 508 509 union { 510 struct { 511 uint32_t HaarTransformMode : MOS_BITFIELD_RANGE(0, 1); 512 uint32_t SimplifiedFlagForInter : MOS_BITFIELD_BIT(2); 513 uint32_t Reserved : MOS_BITFIELD_RANGE(3, 31); 514 }; 515 uint32_t Value; 516 } DW10; 517 518 union { 519 struct { 520 uint32_t Reserved; 521 }; 522 uint32_t Value; 523 } DW11; 524 525 union { 526 struct { 527 uint32_t Reserved; 528 }; 529 uint32_t Value; 530 } DW12; 531 532 union { 533 struct { 534 uint32_t Reserved; 535 }; 536 uint32_t Value; 537 } DW13; 538 539 union { 540 struct { 541 uint32_t Reserved; 542 }; 543 uint32_t Value; 544 } DW14; 545 546 union { 547 struct { 548 uint32_t Reserved; 549 }; 550 uint32_t Value; 551 } DW15; 552 553 union { 554 struct { 555 uint32_t BTI_Src_Y; 556 }; 557 uint32_t Value; 558 } DW16; 559 560 union { 561 struct { 562 uint32_t BTI_Sad_16x16_PU; 563 }; 564 uint32_t Value; 565 } DW17; 566 567 union { 568 struct { 569 uint32_t BTI_PAK_Object; 570 }; 571 uint32_t Value; 572 } DW18; 573 574 union { 575 struct { 576 uint32_t BTI_SAD_32x32_PU_mode; 577 }; 578 uint32_t Value; 579 } DW19; 580 581 union { 582 struct { 583 uint32_t BTI_VME_Mode_8x8; 584 }; 585 uint32_t Value; 586 } DW20; 587 588 union { 589 struct { 590 uint32_t BTI_Slice_Map; 591 }; 592 uint32_t Value; 593 } DW21; 594 595 union { 596 struct { 597 uint32_t BTI_VME_Src; 598 }; 599 uint32_t Value; 600 } DW22; 601 602 union { 603 struct { 604 uint32_t BTI_BRC_Input; 605 }; 606 uint32_t Value; 607 } DW23; 608 609 union { 610 struct { 611 uint32_t BTI_Simplest_Intra; 612 }; 613 uint32_t Value; 614 } DW24; 615 616 union { 617 struct { 618 uint32_t BTI_LCU_Qp_Surface; 619 }; 620 uint32_t Value; 621 } DW25; 622 623 union { 624 struct { 625 uint32_t BTI_BRC_Data; 626 }; 627 uint32_t Value; 628 } DW26; 629 630 union { 631 struct { 632 uint32_t BTI_Debug; 633 }; 634 uint32_t Value; 635 } DW27; 636 }; 637 638 using PCODECHAL_ENC_HEVC_I_16x16_PU_MODEDECISION_CURBE_G9 = struct CODECHAL_ENC_HEVC_I_16x16_PU_MODEDECISION_CURBE_G9*; 639 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_ENC_HEVC_I_16x16_PU_MODEDECISION_CURBE_G9)) == 28); 640 641 //! HEVC encoder intra 8x8 PU kernel curbe for GEN9 642 struct CODECHAL_ENC_HEVC_I_8x8_PU_CURBE_G9 643 { 644 union { 645 struct { 646 uint32_t FrameWidth : MOS_BITFIELD_RANGE(0, 15); 647 uint32_t FrameHeight : MOS_BITFIELD_RANGE(16, 31); 648 }; 649 uint32_t Value; 650 } DW0; 651 652 union { 653 struct { 654 uint32_t SliceType : MOS_BITFIELD_RANGE(0, 1); 655 uint32_t PuType : MOS_BITFIELD_RANGE(2, 3); 656 uint32_t DcFilterFlag : MOS_BITFIELD_BIT(4); 657 uint32_t AngleRefineFlag : MOS_BITFIELD_BIT(5); 658 uint32_t LCUType : MOS_BITFIELD_BIT(6); 659 uint32_t ScreenContentFlag : MOS_BITFIELD_BIT(7); 660 uint32_t IntraRefreshEn : MOS_BITFIELD_RANGE(8, 9); 661 uint32_t EnableRollingIntra : MOS_BITFIELD_BIT(10); 662 uint32_t HalfUpdateMixedLCU : MOS_BITFIELD_BIT(11); 663 uint32_t Reserved_12_15 : MOS_BITFIELD_RANGE(12, 15); 664 uint32_t QPValue : MOS_BITFIELD_RANGE(16, 23); 665 uint32_t EnableIntraEarlyExit : MOS_BITFIELD_BIT(24); 666 uint32_t BRCEnable : MOS_BITFIELD_BIT(25); 667 uint32_t LCUBRCEnable : MOS_BITFIELD_BIT(26); 668 uint32_t ROIEnable : MOS_BITFIELD_BIT(27); 669 uint32_t FASTSurveillanceFlag : MOS_BITFIELD_BIT(28); 670 uint32_t EnableFlexibleParam : MOS_BITFIELD_BIT(29); 671 uint32_t EnableQualityImprovement : MOS_BITFIELD_BIT(30); 672 uint32_t EnableDebugDump : MOS_BITFIELD_BIT(31); 673 }; 674 uint32_t Value; 675 } DW1; 676 677 union { 678 struct { 679 uint32_t LumaLambda; 680 }; 681 uint32_t Value; 682 } DW2; 683 684 union { 685 struct { 686 uint32_t ChromaLambda; 687 }; 688 uint32_t Value; 689 } DW3; 690 691 union { 692 struct { 693 uint32_t HaarTransformFlag : MOS_BITFIELD_RANGE(0, 1); 694 uint32_t SimplifiedFlagForInter : MOS_BITFIELD_BIT(2); 695 uint32_t Reserved : MOS_BITFIELD_RANGE(3, 31); 696 }; 697 uint32_t Value; 698 } DW4; 699 700 union { 701 struct { 702 uint32_t IntraRefreshMBNum : MOS_BITFIELD_RANGE(0, 15); 703 uint32_t IntraRefreshUnitInMB : MOS_BITFIELD_RANGE(16, 23); 704 uint32_t IntraRefreshQPDelta : MOS_BITFIELD_RANGE(24, 31); 705 }; 706 uint32_t Value; 707 } DW5; 708 709 union { 710 struct { 711 uint32_t Reserved; 712 }; 713 uint32_t Value; 714 } DW6; 715 716 union { 717 struct { 718 uint32_t Reserved; 719 }; 720 uint32_t Value; 721 } DW7; 722 723 union { 724 struct { 725 uint32_t BTI_Src_Y; 726 }; 727 uint32_t Value; 728 } DW8; 729 730 union { 731 struct { 732 uint32_t BTI_Slice_Map; 733 }; 734 uint32_t Value; 735 } DW9; 736 737 union { 738 struct { 739 uint32_t BTI_VME_8x8_Mode; 740 }; 741 uint32_t Value; 742 } DW10; 743 744 union { 745 struct { 746 uint32_t BTI_Intra_Mode; 747 }; 748 uint32_t Value; 749 } DW11; 750 751 union { 752 struct { 753 uint32_t BTI_BRC_Input; 754 }; 755 uint32_t Value; 756 } DW12; 757 758 union { 759 struct { 760 uint32_t BTI_Simplest_Intra; 761 }; 762 uint32_t Value; 763 } DW13; 764 765 union { 766 struct { 767 uint32_t BTI_LCU_Qp_Surface; 768 }; 769 uint32_t Value; 770 } DW14; 771 772 union { 773 struct { 774 uint32_t BTI_BRC_Data; 775 }; 776 uint32_t Value; 777 } DW15; 778 779 union { 780 struct { 781 uint32_t BTI_Debug; 782 }; 783 uint32_t Value; 784 } DW16; 785 }; 786 787 using PCODECHAL_ENC_HEVC_I_8x8_PU_CURBE_G9 = struct CODECHAL_ENC_HEVC_I_8x8_PU_CURBE_G9*; 788 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_ENC_HEVC_I_8x8_PU_CURBE_G9)) == 17); 789 790 //! HEVC encoder intra 8x8 PU final mode decision kernel curbe for GEN9 791 struct CODECHAL_ENC_HEVC_I_8x8_PU_FMODE_CURBE_G9 792 { 793 union { 794 struct { 795 uint32_t FrameWidth : MOS_BITFIELD_RANGE(0, 15); 796 uint32_t FrameHeight : MOS_BITFIELD_RANGE(16, 31); 797 }; 798 uint32_t Value; 799 } DW0; 800 801 union { 802 struct { 803 uint32_t SliceType : MOS_BITFIELD_RANGE(0, 1); 804 uint32_t PuType : MOS_BITFIELD_RANGE(2, 3); 805 uint32_t PakReordingFlag : MOS_BITFIELD_BIT(4); 806 uint32_t ReservedMBZ : MOS_BITFIELD_BIT(5); 807 uint32_t LCUType : MOS_BITFIELD_BIT(6); 808 uint32_t ScreenContentFlag : MOS_BITFIELD_BIT(7); 809 uint32_t IntraRefreshEn : MOS_BITFIELD_RANGE(8, 9); 810 uint32_t EnableRollingIntra : MOS_BITFIELD_BIT(10); 811 uint32_t HalfUpdateMixedLCU : MOS_BITFIELD_BIT(11); 812 uint32_t Reserved_12_23 : MOS_BITFIELD_RANGE(12, 23); 813 uint32_t EnableIntraEarlyExit : MOS_BITFIELD_BIT(24); 814 uint32_t BRCEnable : MOS_BITFIELD_BIT(25); 815 uint32_t LCUBRCEnable : MOS_BITFIELD_BIT(26); 816 uint32_t ROIEnable : MOS_BITFIELD_BIT(27); 817 uint32_t FASTSurveillanceFlag : MOS_BITFIELD_BIT(28); 818 uint32_t EnableFlexibleParam : MOS_BITFIELD_BIT(29); 819 uint32_t EnableQualityImprovement : MOS_BITFIELD_BIT(30); 820 uint32_t EnableDebugDump : MOS_BITFIELD_BIT(31); 821 }; 822 uint32_t Value; 823 } DW1; 824 825 union { 826 struct { 827 uint32_t LambdaForLuma; 828 }; 829 uint32_t Value; 830 } DW2; 831 832 union { 833 struct { 834 uint32_t LambdaForDistCalculation; 835 }; 836 uint32_t Value; 837 } DW3; 838 839 union { 840 struct { 841 uint32_t ModeCostFor8x8PU_TU8; 842 }; 843 uint32_t Value; 844 } DW4; 845 846 union { 847 struct { 848 uint32_t ModeCostFor8x8PU_TU4; 849 }; 850 uint32_t Value; 851 } DW5; 852 853 union { 854 struct { 855 uint32_t SATD16x16PuThreshold : MOS_BITFIELD_RANGE(0, 15); 856 uint32_t BiasFactorToward8x8 : MOS_BITFIELD_RANGE(16, 31); 857 }; 858 uint32_t Value; 859 } DW6; 860 861 union { 862 struct { 863 uint32_t Qp : MOS_BITFIELD_RANGE(0, 15); 864 uint32_t QpForInter : MOS_BITFIELD_RANGE(16, 31); 865 }; 866 uint32_t Value; 867 } DW7; 868 869 union { 870 struct { 871 uint32_t SimplifiedFlagForInter : MOS_BITFIELD_BIT(0); 872 uint32_t EnableStatsDataDump : MOS_BITFIELD_BIT(1); 873 uint32_t Reserved_2_7 : MOS_BITFIELD_RANGE(2, 7); 874 uint32_t KBLControlFlag : MOS_BITFIELD_BIT(8); 875 uint32_t Reserved_9_31 : MOS_BITFIELD_RANGE(9, 31); 876 }; 877 uint32_t Value; 878 } DW8; 879 880 union { 881 struct { 882 uint32_t IntraRefreshMBNum : MOS_BITFIELD_RANGE(0, 15); 883 uint32_t IntraRefreshUnitInMB : MOS_BITFIELD_RANGE(16, 23); 884 uint32_t IntraRefreshQPDelta : MOS_BITFIELD_RANGE(24, 31); 885 }; 886 uint32_t Value; 887 } DW9; 888 889 union { 890 struct { 891 uint32_t Reserved; 892 }; 893 uint32_t Value; 894 } DW10; 895 896 union { 897 struct { 898 uint32_t Reserved; 899 }; 900 uint32_t Value; 901 } DW11; 902 903 union { 904 struct { 905 uint32_t Reserved; 906 }; 907 uint32_t Value; 908 } DW12; 909 910 union { 911 struct { 912 uint32_t Reserved; 913 }; 914 uint32_t Value; 915 } DW13; 916 917 union { 918 struct { 919 uint32_t Reserved; 920 }; 921 uint32_t Value; 922 } DW14; 923 924 union { 925 struct { 926 uint32_t Reserved; 927 }; 928 uint32_t Value; 929 } DW15; 930 931 union { 932 struct { 933 uint32_t BTI_PAK_Object; 934 }; 935 uint32_t Value; 936 } DW16; 937 938 union { 939 struct { 940 uint32_t BTI_VME_8x8_Mode; 941 }; 942 uint32_t Value; 943 } DW17; 944 945 union { 946 struct { 947 uint32_t BTI_Intra_Mode; 948 }; 949 uint32_t Value; 950 } DW18; 951 952 union { 953 struct { 954 uint32_t BTI_PAK_Command; 955 }; 956 uint32_t Value; 957 } DW19; 958 959 union { 960 struct { 961 uint32_t BTI_Slice_Map; 962 }; 963 uint32_t Value; 964 } DW20; 965 966 union { 967 struct { 968 uint32_t BTI_IntraDist; 969 }; 970 uint32_t Value; 971 } DW21; 972 973 union { 974 struct { 975 uint32_t BTI_BRC_Input; 976 }; 977 uint32_t Value; 978 } DW22; 979 980 union { 981 struct { 982 uint32_t BTI_Simplest_Intra; 983 }; 984 uint32_t Value; 985 } DW23; 986 987 union { 988 struct { 989 uint32_t BTI_LCU_Qp_Surface; 990 }; 991 uint32_t Value; 992 } DW24; 993 994 union { 995 struct { 996 uint32_t BTI_BRC_Data; 997 }; 998 uint32_t Value; 999 } DW25; 1000 1001 union { 1002 struct { 1003 uint32_t BTI_Haar_Dist16x16; 1004 }; 1005 uint32_t Value; 1006 } DW26; 1007 1008 union { 1009 struct { 1010 uint32_t BTI_Stats_Data; 1011 }; 1012 uint32_t Value; 1013 } DW27; 1014 1015 union { 1016 struct { 1017 uint32_t BTI_Frame_Stats_Data; 1018 }; 1019 uint32_t Value; 1020 } DW28; 1021 1022 union { 1023 struct { 1024 uint32_t BTI_Debug; 1025 }; 1026 uint32_t Value; 1027 } DW29; 1028 }; 1029 1030 using PCODECHAL_ENC_HEVC_I_8x8_PU_FMODE_CURBE_G9 = struct CODECHAL_ENC_HEVC_I_8x8_PU_FMODE_CURBE_G9*; 1031 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_ENC_HEVC_I_8x8_PU_FMODE_CURBE_G9)) == 30); 1032 1033 //! HEVC encoder B 32x32 PU intra check kernel curbe for GEN9 1034 struct CODECHAL_ENC_HEVC_B_32x32_PU_INTRA_CHECK_CURBE_G9 1035 { 1036 union { 1037 struct { 1038 uint32_t FrameWidth : MOS_BITFIELD_RANGE(0, 15); 1039 uint32_t FrameHeight : MOS_BITFIELD_RANGE(16, 31); 1040 }; 1041 uint32_t Value; 1042 } DW0; 1043 1044 union { 1045 struct { 1046 uint32_t SliceType : MOS_BITFIELD_RANGE(0, 1); 1047 uint32_t Reserved : MOS_BITFIELD_RANGE(2, 7); 1048 uint32_t Log2MinTUSize : MOS_BITFIELD_RANGE(8, 15); 1049 uint32_t Flags : MOS_BITFIELD_RANGE(16, 23); 1050 uint32_t EnableIntraEarlyExit : MOS_BITFIELD_BIT(24); 1051 uint32_t HMEEnable : MOS_BITFIELD_BIT(25); 1052 uint32_t FASTSurveillanceFlag : MOS_BITFIELD_BIT(26); 1053 uint32_t Res_27_30 : MOS_BITFIELD_RANGE(27, 30); 1054 uint32_t EnableDebugDump : MOS_BITFIELD_BIT(31); 1055 }; 1056 uint32_t Value; 1057 } DW1; 1058 1059 union { 1060 struct { 1061 uint32_t QpValue : MOS_BITFIELD_RANGE(0, 15); 1062 uint32_t QpMultiplier : MOS_BITFIELD_RANGE(16, 31); 1063 }; 1064 uint32_t Value; 1065 } DW2; 1066 1067 union { 1068 struct { 1069 uint32_t Reserved; 1070 }; 1071 uint32_t Value; 1072 } DW3; 1073 1074 union { 1075 struct { 1076 uint32_t Reserved; 1077 }; 1078 uint32_t Value; 1079 } DW4; 1080 1081 union { 1082 struct { 1083 uint32_t Reserved; 1084 }; 1085 uint32_t Value; 1086 } DW5; 1087 1088 union { 1089 struct { 1090 uint32_t Reserved; 1091 }; 1092 uint32_t Value; 1093 } DW6; 1094 1095 union { 1096 struct { 1097 uint32_t Reserved; 1098 }; 1099 uint32_t Value; 1100 } DW7; 1101 1102 union { 1103 struct { 1104 uint32_t BTI_Per32x32PuIntraCheck; 1105 }; 1106 uint32_t Value; 1107 } DW8; 1108 1109 union { 1110 struct { 1111 uint32_t BTI_Src_Y; 1112 }; 1113 uint32_t Value; 1114 } DW9; 1115 1116 union { 1117 struct { 1118 uint32_t BTI_Src_Y2X; 1119 }; 1120 uint32_t Value; 1121 } DW10; 1122 1123 union { 1124 struct { 1125 uint32_t BTI_Slice_Map; 1126 }; 1127 uint32_t Value; 1128 } DW11; 1129 1130 union { 1131 struct { 1132 uint32_t BTI_VME_Y2X; 1133 }; 1134 uint32_t Value; 1135 } DW12; 1136 1137 union { 1138 struct { 1139 uint32_t BTI_Simplest_Intra; // output only 1140 }; 1141 uint32_t Value; 1142 } DW13; 1143 1144 union { 1145 struct { 1146 uint32_t BTI_HME_MVPred; 1147 }; 1148 uint32_t Value; 1149 } DW14; 1150 1151 union { 1152 struct { 1153 uint32_t BTI_HME_Dist; 1154 }; 1155 uint32_t Value; 1156 } DW15; 1157 1158 union { 1159 struct { 1160 uint32_t BTI_LCU_Skip; 1161 }; 1162 uint32_t Value; 1163 } DW16; 1164 1165 union { 1166 struct { 1167 uint32_t BTI_Debug; 1168 }; 1169 uint32_t Value; 1170 } DW17; 1171 }; 1172 1173 using PCODECHAL_ENC_HEVC_B_32x32_PU_INTRA_CHECK_CURBE_G9 = struct CODECHAL_ENC_HEVC_B_32x32_PU_INTRA_CHECK_CURBE_G9; 1174 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_ENC_HEVC_B_32x32_PU_INTRA_CHECK_CURBE_G9)) == 18); 1175 1176 //! HEVC encoder B Pak kernel curbe for GEN9 1177 struct CODECHAL_ENC_HEVC_B_PAK_CURBE_G9 1178 { 1179 union 1180 { 1181 struct 1182 { 1183 uint32_t FrameWidth : MOS_BITFIELD_RANGE(0, 15); 1184 uint32_t FrameHeight : MOS_BITFIELD_RANGE(16, 31); 1185 }; 1186 struct 1187 { 1188 uint32_t Value; 1189 }; 1190 } DW0; 1191 1192 union 1193 { 1194 struct 1195 { 1196 uint32_t Qp : MOS_BITFIELD_RANGE(0, 7); 1197 uint32_t Res_8_15 : MOS_BITFIELD_RANGE(8, 15); 1198 uint32_t MaxVmvR : MOS_BITFIELD_RANGE(16, 31); 1199 }; 1200 struct 1201 { 1202 uint32_t Value; 1203 }; 1204 } DW1; 1205 1206 union 1207 { 1208 struct 1209 { 1210 uint32_t SliceType : MOS_BITFIELD_RANGE(0, 1); 1211 uint32_t EnableEmptyCURecordsDump : MOS_BITFIELD_BIT(2); 1212 uint32_t Res_3_7 : MOS_BITFIELD_RANGE(3, 7); 1213 uint32_t SimplestIntraEnable : MOS_BITFIELD_BIT(8); 1214 uint32_t BrcEnable : MOS_BITFIELD_BIT(9); 1215 uint32_t LcuBrcEnable : MOS_BITFIELD_BIT(10); 1216 uint32_t ROIEnable : MOS_BITFIELD_BIT(11); 1217 uint32_t FASTSurveillanceFlag : MOS_BITFIELD_BIT(12); 1218 uint32_t EnableRollingIntra : MOS_BITFIELD_BIT(13); 1219 uint32_t Res_14 : MOS_BITFIELD_BIT(14); 1220 uint32_t EnableQualityImprovement : MOS_BITFIELD_BIT(15); 1221 uint32_t KBLControlFlag : MOS_BITFIELD_BIT(16); 1222 uint32_t Res_17_30 : MOS_BITFIELD_RANGE(17, 30); 1223 uint32_t ScreenContent : MOS_BITFIELD_BIT(31); 1224 }; 1225 struct 1226 { 1227 uint32_t Value; 1228 }; 1229 } DW2; 1230 1231 union 1232 { 1233 struct 1234 { 1235 uint32_t IntraRefreshMBNum : MOS_BITFIELD_RANGE(0, 15); 1236 uint32_t IntraRefreshUnitInMB : MOS_BITFIELD_RANGE(16, 23); 1237 uint32_t IntraRefreshQPDelta : MOS_BITFIELD_RANGE(24, 31); 1238 }; 1239 struct 1240 { 1241 uint32_t Value; 1242 }; 1243 } DW3; 1244 1245 union 1246 { 1247 struct 1248 { 1249 uint32_t Reserved; 1250 }; 1251 struct 1252 { 1253 uint32_t Value; 1254 }; 1255 } DW4_15[12]; 1256 1257 union 1258 { 1259 struct 1260 { 1261 uint32_t BTI_CU_Record; 1262 }; 1263 struct 1264 { 1265 uint32_t Value; 1266 }; 1267 } DW16; 1268 1269 union 1270 { 1271 struct 1272 { 1273 uint32_t BTI_PAK_Obj; 1274 }; 1275 struct 1276 { 1277 uint32_t Value; 1278 }; 1279 } DW17; 1280 1281 union 1282 { 1283 struct 1284 { 1285 uint32_t BTI_Slice_Map; 1286 }; 1287 struct 1288 { 1289 uint32_t Value; 1290 }; 1291 } DW18; 1292 1293 union 1294 { 1295 struct 1296 { 1297 uint32_t BTI_Brc_Input; 1298 }; 1299 struct 1300 { 1301 uint32_t Value; 1302 }; 1303 } DW19; 1304 1305 union 1306 { 1307 struct 1308 { 1309 uint32_t BTI_LCU_Qp; 1310 }; 1311 struct 1312 { 1313 uint32_t Value; 1314 }; 1315 } DW20; 1316 1317 union 1318 { 1319 struct 1320 { 1321 uint32_t BTI_Brc_Data; 1322 }; 1323 struct 1324 { 1325 uint32_t Value; 1326 }; 1327 } DW21; 1328 1329 union 1330 { 1331 struct 1332 { 1333 uint32_t BTI_MB_Data; 1334 }; 1335 struct 1336 { 1337 uint32_t Value; 1338 }; 1339 } DW22; 1340 1341 union 1342 { 1343 struct 1344 { 1345 uint32_t BTI_MVP_Surface; 1346 }; 1347 struct 1348 { 1349 uint32_t Value; 1350 }; 1351 } DW23; 1352 1353 union 1354 { 1355 struct 1356 { 1357 uint32_t BTI_WA_PAK_Data; 1358 }; 1359 struct 1360 { 1361 uint32_t Value; 1362 }; 1363 } DW24; 1364 1365 union 1366 { 1367 struct 1368 { 1369 uint32_t BTI_WA_PAK_Obj; 1370 }; 1371 struct 1372 { 1373 uint32_t Value; 1374 }; 1375 } DW25; 1376 1377 union 1378 { 1379 struct 1380 { 1381 uint32_t BTI_Debug; 1382 }; 1383 struct 1384 { 1385 uint32_t Value; 1386 }; 1387 } DW26; 1388 1389 }; 1390 1391 using PCODECHAL_ENC_HEVC_B_PAK_CURBE_G9 = struct CODECHAL_ENC_HEVC_B_PAK_CURBE_G9*; 1392 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_ENC_HEVC_B_PAK_CURBE_G9)) == 27); 1393 1394 struct CODECHAL_ENC_HEVC_DS_COMBINED_CURBE_G9 1395 { 1396 union { 1397 struct { 1398 uint32_t Pak_BitDepth_Chroma : MOS_BITFIELD_RANGE(0, 7); 1399 uint32_t Pak_BitDepth_Luma : MOS_BITFIELD_RANGE(8, 15); 1400 uint32_t Enc_BitDepth_Chroma : MOS_BITFIELD_RANGE(16, 23); 1401 uint32_t Enc_BitDepth_Luma : MOS_BITFIELD_RANGE(24, 30); 1402 uint32_t Rounding_Value : MOS_BITFIELD_BIT(31); 1403 }; 1404 1405 uint32_t Value; 1406 } DW0; 1407 1408 union { 1409 struct { 1410 uint32_t PicFormat : MOS_BITFIELD_RANGE(0, 7); 1411 uint32_t PicConvertFlag : MOS_BITFIELD_BIT(8); 1412 uint32_t PicDownscale : MOS_BITFIELD_RANGE(9, 11); 1413 uint32_t PicMBStatOutputCntrl : MOS_BITFIELD_BIT(12); 1414 uint32_t MBZ : MOS_BITFIELD_RANGE(13, 31); 1415 }; 1416 uint32_t Value; 1417 } DW1; 1418 1419 union { 1420 struct { 1421 uint32_t OrigPicWidth : MOS_BITFIELD_RANGE(0, 15); 1422 uint32_t OrigPicHeight : MOS_BITFIELD_RANGE(16, 31); 1423 }; 1424 uint32_t Value; 1425 } DW2; 1426 1427 union { 1428 struct { 1429 uint32_t BTI_Surface_P010 : MOS_BITFIELD_RANGE(0, 31); 1430 }; 1431 uint32_t Value; 1432 } DW3; 1433 1434 union { 1435 struct { 1436 uint32_t BTI_Surface_NV12 : MOS_BITFIELD_RANGE(0, 31); 1437 }; 1438 uint32_t Value; 1439 } DW4; 1440 1441 union { 1442 struct { 1443 uint32_t BTI_Src_Y_4xDownScaled : MOS_BITFIELD_RANGE(0, 31); 1444 }; 1445 uint32_t Value; 1446 } DW5; 1447 1448 union { 1449 struct { 1450 uint32_t BTI_Surf_MBState : MOS_BITFIELD_RANGE(0, 31); 1451 }; 1452 uint32_t Value; 1453 } DW6; 1454 1455 union { 1456 struct { 1457 uint32_t BTI_Src_Y_2xDownScaled : MOS_BITFIELD_RANGE(0, 31); 1458 }; 1459 uint32_t Value; 1460 } DW7; 1461 }; 1462 1463 using PCODECHAL_ENC_HEVC_DS_COMBINED_CURBE_G9 = struct CODECHAL_ENC_HEVC_DS_COMBINED_CURBE_G9*; 1464 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_ENC_HEVC_DS_COMBINED_CURBE_G9)) == 8 ); 1465 1466 //! HEVC dual-pipe encoder class for GEN9 1467 /*! 1468 This class defines the member fields, functions for GEN9 platform 1469 */ 1470 class CodechalEncHevcStateG9 : public CodechalEncHevcState 1471 { 1472 protected: 1473 static constexpr uint32_t NUM_CONCURRENT_THREAD = 2; //!< Number of concurrent threads 1474 static constexpr uint32_t MAX_NUM_KERNEL_SPLIT = 8; //!< Maximal kernel split number 1475 static constexpr uint32_t BRC_CONSTANT_SURFACE_WIDTH = 64; //!< BRC constant surface width 1476 static constexpr uint32_t BRC_CONSTANT_SURFACE_HEIGHT= 53; //!< BRC constant surface height 1477 static constexpr uint32_t BRC_HISTORY_BUFFER_SIZE = 576; //!< BRC history buffer size 1478 1479 //! Encoder surface index 1480 enum SURFACE_ID 1481 { 1482 SURFACE_RAW_Y = 0, 1483 SURFACE_RAW_Y_UV, 1484 SURFACE_Y_2X, 1485 SURFACE_32x32_PU_OUTPUT, 1486 SURFACE_SLICE_MAP, 1487 SURFACE_Y_2X_VME, 1488 SURFACE_BRC_INPUT, 1489 SURFACE_LCU_QP, 1490 SURFACE_ROI, 1491 SURFACE_BRC_DATA, 1492 SURFACE_KERNEL_DEBUG, 1493 SURFACE_SIMPLIFIED_INTRA, 1494 SURFACE_HME_MVP, 1495 SURFACE_HME_DIST, 1496 SURFACE_16x16PU_SAD, 1497 SURFACE_RAW_VME, 1498 SURFACE_VME_8x8, 1499 SURFACE_CU_RECORD, 1500 SURFACE_INTRA_MODE, 1501 SURFACE_HCP_PAK, 1502 SURFACE_INTRA_DIST, 1503 SURFACE_MIN_DIST, 1504 SURFACE_VME_UNI_SIC_DATA, 1505 SURFACE_COL_MB_MV, 1506 SURFACE_CONCURRENT_THREAD, 1507 SURFACE_MB_MV_INDEX = SURFACE_CONCURRENT_THREAD + NUM_CONCURRENT_THREAD, 1508 SURFACE_MVP_INDEX, 1509 SURFACE_REF_FRAME_VME, 1510 SURFACE_Y_4X, 1511 SURFACE_Y_4X_VME, 1512 SURFACE_BRC_HISTORY, 1513 SURFACE_BRC_ME_DIST, 1514 SURFACE_BRC_PAST_PAK_INFO, 1515 SURFACE_BRC_HCP_PIC_STATE, 1516 SURFACE_RAW_10bit_Y, 1517 SURFACE_RAW_10bit_Y_UV, 1518 SURFACE_RAW_FC_8bit_Y, 1519 SURFACE_RAW_FC_8bit_Y_UV, 1520 SURFACE_RAW_MBSTAT, 1521 // Statistics output 1522 SURFACE_PU_STATS, 1523 SURFACE_8X8_PU_HAAR_DIST, 1524 SURFACE_8X8_PU_FRAME_STATS, 1525 SURFACE_MB_ENC_STATS, 1526 SURFACE_MB_ENC_FRAME_STATS, 1527 // HEVC FEI 1528 SURFACE_FEI_EXTERNAL_MVP, 1529 SURFACE_FEI_PER_LCU_QP, 1530 SURFACE_FEI_PER_CTB_CTRL, 1531 SURFACE_FEI_CTB_DISTORTION, 1532 SURFACE_NUM_TOTAL 1533 }; 1534 1535 static const uint8_t m_ftqBasedSkip[NUM_TARGET_USAGE_MODES]; //!< FTP Skip LUT 1536 static const uint8_t m_meMethod[NUM_TARGET_USAGE_MODES]; //!< ME method LUT 1537 static const uint8_t m_superCombineDist[NUM_TARGET_USAGE_MODES + 1]; //!< m_superCombineDist LUT 1538 static const uint16_t m_skipValB[2][2][64]; //!< Skip value LUT 1539 static const double m_modeCostLut[3][12]; //!< Mode cost LUT 1540 static const double m_mvCostLut[3][8]; //!< MV cost LUT 1541 static const uint32_t m_brcMvCostHaar[][416]; //!< BRC MV cost LUT 1542 static const uint32_t m_brcLambdaHaar[QP_NUM * 4]; //!< BRC lambda LUT 1543 static const uint16_t m_skipThread[][QP_NUM]; //!< Skip thread LUT 1544 static const double m_qpLambdaMdLut[3][QP_NUM]; //!< Mode decision lambda LUT 1545 static const double m_qpLambdaMeLut[3][QP_NUM]; //!< ME lambda LUT 1546 static const uint32_t m_encBTu1BCurbeInit[56]; //!< Initialization ENC curbe for TU1 B frame 1547 static const uint32_t m_encBTu4BCurbeInit[56]; //!< Initialization ENC curbe for TU4 B frame 1548 static const uint32_t m_encBTu7BCurbeInit[56]; //!< Initialization ENC curbe for TU7 B frame 1549 static const uint32_t m_encBTu1PCurbeInit[56]; //!< Initialization ENC curbe for TU1 P frame 1550 static const uint32_t m_encBTu4PCurbeInit[56]; //!< Initialization ENC curbe for TU4 P frame 1551 static const uint32_t m_encBTu7PCurbeInit[56]; //!< Initialization ENC curbe for TU7 P frame 1552 static const uint32_t m_encBTu7ICurbeInit[56]; //!< Initialization ENC curbe for TU1 I frame 1553 static const uint32_t m_brcInitCurbeInit[32]; //!< Initialization BRCInit curbe 1554 static const uint32_t m_brcUpdateCurbeInit[16]; //!< Initialization BRCUpdate curbe 1555 static const uint32_t m_meCurbeInit[39]; //!< Initialization HME curbe 1556 1557 PCODECHAL_SURFACE_CODEC_PARAMS m_surfaceParams = nullptr; //!< Pointer to surface parameters 1558 1559 uint32_t m_numMb8x8IntraKernelSplit = 0; //!< MB 8x8 intra kernel region number 1560 uint32_t m_numMbBKernelSplit = 0; //!< Mb B kernel region number 1561 1562 PCODECHAL_ENCODE_HEVC_SLICE_MAP m_sliceMap = nullptr; //!< Pointer to HEVC slice map 1563 uint32_t m_lastNumSlices = 0; //!< Number of slices from previous frame 1564 uint8_t m_modeCost[14] = { 0 }; //!< Mode Cost 1565 uint8_t m_modeCostSp = 0; //!< Mode Cost Sp 1566 uint8_t m_mvCost[8] = { 0 }; //!< Motion vector cost 1567 uint32_t m_simplestIntraInterThreshold = 0; //!< Intra/Inter threshold 1568 uint32_t m_fixedPointLambda = 0; //!< Fixed point lambda value 1569 uint32_t m_fixedPointLambdaForLuma = 0; //!< Fixed point lambda value for luma 1570 uint32_t m_fixedPointLambdaForChroma = 0; //!< Fixed point lambda value for chroma 1571 double m_qpLambdaMd[3][QP_NUM] = { { 0.0 } }; //!< Mode decision lambda table 1572 double m_qpLambdaMe[3][QP_NUM] = { { 0.0 } }; //!< Motion search lambda table 1573 1574 // Resources for the render engine 1575 MOS_SURFACE m_scaled2xSurface; //!< 2x scaled surfaces 1576 MOS_SURFACE m_sliceMapSurface; //!< Slice map surface 1577 CODECHAL_ENCODE_BUFFER m_32x32PuOutputData; //!< 32x32 PU output buffer 1578 CODECHAL_ENCODE_BUFFER m_sad16x16Pu; //!< SAD 16x16 PU buffer 1579 CODECHAL_ENCODE_BUFFER m_vme8x8Mode; //!< VME 8x8 mode buffer 1580 CODECHAL_ENCODE_BUFFER m_intraMode; //!< Intra mode buffer 1581 CODECHAL_ENCODE_BUFFER m_intraDist; //!< Intra distortion buffer 1582 MOS_SURFACE m_simplestIntraSurface; //!< Simplest intra surface 1583 MOS_SURFACE m_roiSurface; //!< ROI surface 1584 MOS_SURFACE m_concurrentThreadSurface[NUM_CONCURRENT_THREAD]; //!< Concurrent thread surface 1585 uint32_t m_concurrentThreadIndex = 0; //!< Concurrent thread index 1586 bool m_powerSavingEnabled = false; //!< Power saving enable flag 1587 CODECHAL_ENCODE_HEVC_WALKINGPATTERN_PARAM m_walkingPatternParam; //!< WalkingPattern parameter 1588 MOS_SURFACE m_minDistortion; //!< Min distortion surface 1589 CODECHAL_ENCODE_BUFFER m_vmeSavedUniSic; //!< VME UniSic buffer 1590 CODECHAL_ENCODE_BUFFER m_mvIndex; //!< MV index buffer 1591 CODECHAL_ENCODE_BUFFER m_mvpIndex; //!< MVP index buffer 1592 1593 // Rolling I or intra refresh 1594 bool m_firstIntraRefresh = false; //!< First intra fresh flag 1595 uint32_t m_frameNumInGob = 0; //!< Frame number in GOP 1596 uint32_t m_frameNumWithoutIntraRefresh = 0; //!< Frame number without intra fresh 1597 1598 public: 1599 //! 1600 //! \brief Constructor 1601 //! 1602 CodechalEncHevcStateG9(CodechalHwInterface* hwInterface, 1603 CodechalDebugInterface* debugInterface, 1604 PCODECHAL_STANDARD_INFO standardInfo); 1605 1606 //! 1607 //! \brief Destructor 1608 //! ~CodechalEncHevcStateG9()1609 ~CodechalEncHevcStateG9() {}; 1610 1611 protected: 1612 1613 // inherited virtual functions 1614 virtual MOS_STATUS Initialize(CodechalSetting * settings); 1615 MOS_STATUS InitKernelState(); 1616 uint32_t GetMaxBtCount(); 1617 MOS_STATUS EncodeKernelFunctions(); 1618 MOS_STATUS AllocateEncResources(); 1619 MOS_STATUS FreeEncResources(); 1620 MOS_STATUS SetSliceStructs(); 1621 MOS_STATUS UserFeatureKeyReport(); 1622 MOS_STATUS InitSurfaceInfoTable(); 1623 MOS_STATUS SetSequenceStructs(); 1624 MOS_STATUS SetPictureStructs(); 1625 MOS_STATUS CalcScaledDimensions(); 1626 void GetMaxRefFrames(uint8_t& maxNumRef0, uint8_t& maxNumRef1); 1627 1628 //! 1629 //! \brief Set ME kenrel surface state 1630 //! 1631 //! \param [in] hwInterface 1632 //! Pointer to HW interface 1633 //! \param [in] cmdBuffer 1634 //! Pointer to command buffer 1635 //! \param [in] params 1636 //! Pointer to ME surface parameters 1637 //! 1638 //! \return MOS_STATUS 1639 //! MOS_STATUS_SUCCESS if success, else fail reason 1640 //! 1641 MOS_STATUS SendMeSurfaces( 1642 CodechalHwInterface *hwInterface, 1643 PMOS_COMMAND_BUFFER cmdBuffer, 1644 MeSurfaceParams *params); 1645 1646 //! 1647 //! \brief Initialize MHW 1648 //! 1649 //! \return MOS_STATUS 1650 //! MOS_STATUS_SUCCESS if success, else fail reason 1651 //! 1652 MOS_STATUS InitMhw(); 1653 1654 //! \brief Generate walking control region 1655 //! 1656 //! \return MOS_STATUS 1657 //! MOS_STATUS_SUCCESS if success, else fail reason 1658 //! 1659 MOS_STATUS GenerateWalkingControlRegion(); 1660 1661 //! 1662 //! \brief Initialize media walker parameters for 26Z walking pattern 1663 //! 1664 //! \param [in] numRegionInSlice 1665 //! Number of Region 1666 //! \param [in] maxSliceHeight 1667 //! Max slice height 1668 //! 1669 //! \return void 1670 //! 1671 void InitParamForWalkerVfe26z(uint32_t numRegionInSlice, uint32_t maxSliceHeight); 1672 1673 //! 1674 //! \brief Initialize media walker parameters for 26 walking pattern 1675 //! 1676 //! \param [in] numRegionInSlice 1677 //! Number of Region 1678 //! \param [in] maxSliceHeight 1679 //! Max slice height 1680 //! 1681 //! \return void 1682 //! 1683 void InitParamForWalkerVfe26(uint32_t numRegionInSlice, uint32_t maxSliceHeight); 1684 1685 //! 1686 //! \brief Request surface state heap(SSH) and validate command buffer size 1687 //! 1688 //! \param [in] kernelState 1689 //! Pointer to kernel state 1690 //! 1691 //! \return MOS_STATUS 1692 //! MOS_STATUS_SUCCESS if success, else fail reason 1693 //! 1694 MOS_STATUS RequestSshAndVerifyCommandBufferSize(PMHW_KERNEL_STATE kernelState); 1695 1696 //! 1697 //! \brief Send generic kernel commands and set binding table 1698 //! 1699 //! \param [in] cmdBuffer 1700 //! Pointer to command buffer 1701 //! \param [in] kernelState 1702 //! Pointer to kernel state 1703 //! \param [in] mediaStateType 1704 //! Media state type 1705 //! \param [in] customScoreBoard 1706 //! Pointer to custom score board setting 1707 //! 1708 //! \return MOS_STATUS 1709 //! MOS_STATUS_SUCCESS if success, else fail reason 1710 //! 1711 MOS_STATUS SendKernelCmdsAndBindingTable( 1712 PMOS_COMMAND_BUFFER cmdBuffer, 1713 PMHW_KERNEL_STATE kernelState, 1714 CODECHAL_MEDIA_STATE_TYPE mediaStateType, 1715 PMHW_VFE_SCOREBOARD customScoreBoard); 1716 1717 //! 1718 //! \brief Add curbe data to dynamic state heap 1719 //! 1720 //! \param [in] kernelState 1721 //! Pointer to kernel state 1722 //! \param [in] mediaStateType 1723 //! Media state type 1724 //! \param [in] curbe 1725 //! Pointer to curbe data 1726 //! \param [in] curbeSize 1727 //! Curbe data size 1728 //! 1729 //! \return MOS_STATUS 1730 //! MOS_STATUS_SUCCESS if success, else fail reason 1731 //! 1732 MOS_STATUS AddCurbeToStateHeap( 1733 PMHW_KERNEL_STATE kernelState, 1734 CODECHAL_MEDIA_STATE_TYPE mediaStateType, 1735 void* curbe, 1736 uint32_t curbeSize); 1737 1738 //! 1739 //! \brief End kernel function and submit command buffer 1740 //! 1741 //! \param [in] mediaStateType 1742 //! Media state type 1743 //! \param [in] kernelState 1744 //! Pointer to kernel state 1745 //! \param [in] cmdBuffer 1746 //! Pointer to command buffer 1747 //! 1748 //! \return MOS_STATUS 1749 //! MOS_STATUS_SUCCESS if success, else fail reason 1750 //! 1751 MOS_STATUS EndKernelCall( 1752 CODECHAL_MEDIA_STATE_TYPE mediaStateType, 1753 PMHW_KERNEL_STATE kernelState, 1754 PMOS_COMMAND_BUFFER cmdBuffer); 1755 1756 //! 1757 //! \brief Initialize MbEnc kernel state 1758 //! 1759 //! \return MOS_STATUS 1760 //! MOS_STATUS_SUCCESS if success, else fail reason 1761 //! 1762 MOS_STATUS InitKernelStateMbEnc(); 1763 1764 //! 1765 //! \brief Initialize BRC kernel state 1766 //! 1767 //! \return MOS_STATUS 1768 //! MOS_STATUS_SUCCESS if success, else fail reason 1769 //! 1770 MOS_STATUS InitKernelStateBrc(); 1771 1772 //! 1773 //! \brief Set MbEnc kernel parameters 1774 //! 1775 //! \param [in] kernelParams 1776 //! Pointer to kernel parameters 1777 //! \param [in] idx 1778 //! MbEnc kernel index 1779 //! 1780 //! \return MOS_STATUS 1781 //! MOS_STATUS_SUCCESS if success, else fail reason 1782 //! 1783 MOS_STATUS SetMbEncKernelParams(MHW_KERNEL_PARAM* kernelParams, uint32_t idx); 1784 1785 //! 1786 //! \brief Set BRC kernel parameters 1787 //! 1788 //! \param [in] kernelParams 1789 //! Pointer to kernel parameters 1790 //! \param [in] idx 1791 //! BRC kernel index 1792 //! 1793 //! \return MOS_STATUS 1794 //! MOS_STATUS_SUCCESS if success, else fail reason 1795 //! 1796 MOS_STATUS SetBrcKernelParams(MHW_KERNEL_PARAM* kernelParams, uint32_t idx); 1797 1798 //! 1799 //! \brief Set MbEnc kernel binding table 1800 //! 1801 //! \param [in] bindingTable 1802 //! Pointer to binding table 1803 //! \param [in] idx 1804 //! MbEnc kernel index 1805 //! 1806 //! \return MOS_STATUS 1807 //! MOS_STATUS_SUCCESS if success, else fail reason 1808 //! 1809 MOS_STATUS SetMbEncBindingTable(PCODECHAL_ENCODE_BINDING_TABLE_GENERIC bindingTable, uint32_t idx); 1810 1811 //! 1812 //! \brief Set BRC kernel binding table 1813 //! 1814 //! \param [in] bindingTable 1815 //! Pointer to binding table 1816 //! \param [in] idx 1817 //! BRC kernel index 1818 //! 1819 //! \return MOS_STATUS 1820 //! MOS_STATUS_SUCCESS if success, else fail reason 1821 //! 1822 MOS_STATUS SetBrcBindingTable(PCODECHAL_ENCODE_BINDING_TABLE_GENERIC bindingTable, uint32_t idx); 1823 1824 //! 1825 //! \brief Get MbEnc B kernel default setting 1826 //! 1827 //! \param [in, out] curbeSize 1828 //! Curbe data size 1829 //! 1830 //! \return uint32_t* 1831 //! Pointer to MbEnc B kernel default curbe setting 1832 //! 1833 uint32_t* GetDefaultCurbeEncBKernel(uint32_t& curbeSize); 1834 1835 //! 1836 //! \brief Get reference picture QP value 1837 //! 1838 //! \param [in] list 1839 //! Reference list number 1840 //! \param [in] index 1841 //! Reference picture index 1842 //! 1843 //! \return QP value of specified reference picture 1844 //! 1845 uint8_t GetQPValueFromRefList(uint32_t list, uint32_t index); 1846 1847 //! 1848 //! \brief Invoke down scaling kernel 1849 //! 1850 //! \return MOS_STATUS 1851 //! MOS_STATUS_SUCCESS if success, else fail reason 1852 //! 1853 MOS_STATUS EncodeDSKernel(); 1854 1855 //! 1856 //! \brief Invoke BRC Init/Reset kernel 1857 //! 1858 //! \return MOS_STATUS 1859 //! MOS_STATUS_SUCCESS if success, else fail reason 1860 //! 1861 MOS_STATUS EncodeBrcInitResetKernel(); 1862 1863 //! 1864 //! \brief Invoke BRC update kernel 1865 //! 1866 //! \return MOS_STATUS 1867 //! MOS_STATUS_SUCCESS if success, else fail reason 1868 //! 1869 MOS_STATUS EncodeBrcUpdateKernel(); 1870 1871 //! 1872 //! \brief Invoke BRC update (LCU based) kernel 1873 //! 1874 //! \param [in] curbe 1875 //! Pointer to BRC_UPDATE curbe structure 1876 //! 1877 //! \return MOS_STATUS 1878 //! MOS_STATUS_SUCCESS if success, else fail reason 1879 //! 1880 MOS_STATUS EncodeBrcUpdateLCUBasedKernel(struct CODECHAL_ENC_HEVC_BRC_UPDATE_CURBE_G9* curbe); 1881 1882 //! 1883 //! \brief Invoke coarse intra16x16 kernel 1884 //! 1885 //! \return MOS_STATUS 1886 //! MOS_STATUS_SUCCESS if success, else fail reason 1887 //! 1888 MOS_STATUS EncodeCoarseIntra16x16Kernel(); 1889 1890 //! 1891 //! \brief Invoke 8x8 B MbEnc kernel 1892 //! 1893 //! \return MOS_STATUS 1894 //! MOS_STATUS_SUCCESS if success, else fail reason 1895 //! 1896 MOS_STATUS Encode8x8PBMbEncKernel(); 1897 1898 //! 1899 //! \brief Invoke 8x8 B Pak kernel 1900 //! 1901 //! \param [in] curbe 1902 //! Pointer to B_MB_ENC curbe structure 1903 //! 1904 //! \return MOS_STATUS 1905 //! MOS_STATUS_SUCCESS if success, else fail reason 1906 //! 1907 MOS_STATUS Encode8x8BPakKernel(struct CODECHAL_ENC_HEVC_B_MB_ENC_CURBE_G9* curbe); 1908 1909 //! 1910 //! \brief Invoke 2x down scaling kernel 1911 //! 1912 //! \return MOS_STATUS 1913 //! MOS_STATUS_SUCCESS if success, else fail reason 1914 //! 1915 MOS_STATUS Encode2xScalingKernel(); 1916 1917 //! 1918 //! \brief Invoke 32x32 PU mode decision kernel 1919 //! 1920 //! \return MOS_STATUS 1921 //! MOS_STATUS_SUCCESS if success, else fail reason 1922 //! 1923 MOS_STATUS Encode32x32PuModeDecisionKernel(); 1924 1925 //! 1926 //! \brief Invoke 32x32 B intra check kernel 1927 //! 1928 //! \return MOS_STATUS 1929 //! MOS_STATUS_SUCCESS if success, else fail reason 1930 //! 1931 MOS_STATUS Encode32X32BIntraCheckKernel(); 1932 1933 //! 1934 //! \brief Invoke 16x16 PU SAD computation kernel 1935 //! 1936 //! \return MOS_STATUS 1937 //! MOS_STATUS_SUCCESS if success, else fail reason 1938 //! 1939 MOS_STATUS Encode16x16SadPuComputationKernel(); 1940 1941 //! 1942 //! \brief Invoke 16x16 PU mode decision kernel 1943 //! 1944 //! \return MOS_STATUS 1945 //! MOS_STATUS_SUCCESS if success, else fail reason 1946 //! 1947 MOS_STATUS Encode16x16PuModeDecisionKernel(); 1948 1949 //! 1950 //! \brief Invoke 8x8 PU kernel 1951 //! 1952 //! \return MOS_STATUS 1953 //! MOS_STATUS_SUCCESS if success, else fail reason 1954 //! 1955 MOS_STATUS Encode8x8PUKernel(); 1956 1957 //! 1958 //! \brief Invoke 8x8 PU FMode kernel 1959 //! 1960 //! \return MOS_STATUS 1961 //! MOS_STATUS_SUCCESS if success, else fail reason 1962 //! 1963 MOS_STATUS Encode8x8PUFMODEKernel(); 1964 1965 //! 1966 //! \brief Invoke down scale and format conversion kernel 1967 //! 1968 //! \param [in] downScaleStage 1969 //! Down scale stage 1970 //! \param [in] index 1971 //! Index to formatConvertedSurface array 1972 //! \param [in] refListIdx 1973 //! Reference list index 1974 //! 1975 //! \return MOS_STATUS 1976 //! MOS_STATUS_SUCCESS if success, else fail reason 1977 //! 1978 MOS_STATUS EncodeDSCombinedKernel( 1979 DsStage downScaleStage, 1980 uint32_t index, 1981 uint32_t refListIdx); 1982 1983 //! 1984 //! \brief Convert picture coding type to HEVC frame type 1985 //! 1986 //! \param [in] picType 1987 //! Picture coding type 1988 //! 1989 //! \return HEVC frame type 1990 //! 1991 uint32_t PicCodingTypeToFrameType(uint32_t picType); 1992 1993 //! 1994 //! \brief Calculate lambda value 1995 //! 1996 //! \param [in] sliceType 1997 //! Slice Type 1998 //! \param [in] intraSADTransform 1999 //! Intra SAD transform type 2000 //! 2001 //! \return void 2002 //! 2003 void CalcLambda(uint8_t sliceType, uint8_t intraSADTransform); 2004 2005 //! 2006 //! \brief Load cost table 2007 //! 2008 //! \param [in] sliceType 2009 //! Slice Type 2010 //! \param [in] qp 2011 //! QP value 2012 //! \param [in] intraSADTransform 2013 //! Intra SAD transform type 2014 //! 2015 //! \return void 2016 //! 2017 void LoadCosts(uint8_t sliceType, uint8_t qp, uint8_t intraSADTransform); 2018 2019 //! 2020 //! \brief Calcuate forward transform coefficient threshold 2021 //! 2022 //! \param [in, out] forwardCoeffThresh 2023 //! Forward transform coefficient threshold 2024 //! \param [in] qp 2025 //! QP value 2026 //! 2027 //! \return void 2028 //! 2029 void CalcForwardCoeffThd(uint8_t* forwardCoeffThresh, int32_t qp); 2030 2031 //! 2032 //! \brief Add checking BRC PAK statistics command to command buffer 2033 //! 2034 //! \param [in] cmdBuffer 2035 //! Pointer to command buffer 2036 //! 2037 //! \return MOS_STATUS 2038 //! MOS_STATUS_SUCCESS if success, else fail reason 2039 //! 2040 MOS_STATUS CheckBrcPakStasBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 2041 2042 //! 2043 //! \brief Setup ROI surface 2044 //! 2045 //! \return MOS_STATUS 2046 //! MOS_STATUS_SUCCESS if success, else fail reason 2047 //! 2048 MOS_STATUS SetupROISurface(); 2049 2050 //! 2051 //! \brief Setup ROI in BRC_UPDATE curbe 2052 //! 2053 //! \param [in] curbe 2054 //! Pointer to BRC_UPDATE curbe structure 2055 //! 2056 //! \return MOS_STATUS 2057 //! MOS_STATUS_SUCCESS if success, else fail reason 2058 //! 2059 MOS_STATUS SetupROICurbe(struct CODECHAL_ENC_HEVC_BRC_UPDATE_CURBE_G9* curbe); 2060 2061 //! 2062 //! \brief Setup BRC constant data 2063 //! 2064 //! \param [in, out] brcConstantData 2065 //! Pointer to BRC constant data surface 2066 //! 2067 //! \return MOS_STATUS 2068 //! MOS_STATUS_SUCCESS if success, else fail reason 2069 //! 2070 MOS_STATUS SetupBrcConstantTable(PMOS_SURFACE brcConstantData); 2071 2072 //! 2073 //! \brief Convert input 1 byte QP per LCU to 2 bytes per LCU 2074 //! 2075 //! \param [in] lcuQPIn 2076 //! Pointer to input LCU QP data surface 2077 //! \param [out] lcuQPOut 2078 //! Pointer to output LCU QP data surface 2079 //! 2080 //! \return MOS_STATUS 2081 //! MOS_STATUS_SUCCESS if success, else fail reason 2082 //! 2083 MOS_STATUS Convert1byteTo2bytesQPperLCU(PMOS_SURFACE lcuQPIn, PMOS_SURFACE lcuQPOut); 2084 //! 2085 //! \brief Generate slice map 2086 //! 2087 //! \return MOS_STATUS 2088 //! MOS_STATUS_SUCCESS if success, else fail reason 2089 //! 2090 MOS_STATUS GenerateSliceMap(); 2091 2092 //! 2093 //! \brief Help function to set up surface state 2094 //! 2095 //! \param [in] kernelState 2096 //! Pointer to kernel state 2097 //! \param [in] cmdBuffer 2098 //! Pointer to command buffer 2099 //! \param [in] surfaceId 2100 //! Surface index 2101 //! \param [in] bindingTableOffset 2102 //! Pointer to binding table offset 2103 //! \param [in] addr 2104 //! Surface address (can be nullptr) 2105 //! \param [in] width 2106 //! Width to be used of the Surface (can be 0, then the surface state would use surface width by default). 2107 //! \param [in] height 2108 //! Height to be used of the Surface (can be 0, then the surface state would use surface height by default). 2109 //! 2110 //! \return MOS_STATUS 2111 //! MOS_STATUS_SUCCESS if success, else fail reason 2112 //! 2113 MOS_STATUS SetSurfacesState( 2114 PMHW_KERNEL_STATE kernelState, 2115 PMOS_COMMAND_BUFFER cmdBuffer, 2116 SURFACE_ID surfaceId, 2117 uint32_t *bindingTableOffset, 2118 void* addr = nullptr, 2119 uint32_t width = 0, 2120 uint32_t height = 0); 2121 2122 //! 2123 //! \brief Convert picture coding type to slice type 2124 //! 2125 //! \param [in] pictureCodingType 2126 //! Picture coding type 2127 //! 2128 //! \return HEVC slice type 2129 //! 2130 uint8_t PicCodingTypeToSliceType(uint16_t pictureCodingType); 2131 2132 //! 2133 //! \brief Help function to convert kernel operation function to media state 2134 //! 2135 //! \param [in] op 2136 //! Kernel operation function 2137 //! \param [in] idx 2138 //! Kernel state index 2139 //! 2140 //! \return Kernel media state value 2141 //! ConvertKrnOpsToMediaState(EncOperation op,uint32_t idx)2142 inline uint32_t ConvertKrnOpsToMediaState(EncOperation op, uint32_t idx) 2143 { 2144 return ((uint32_t)op << 16) | idx; 2145 } 2146 2147 //! 2148 //! \brief Check if specific platform control flag needs to enabled for kernel setting 2149 //! 2150 //! \return Value of platform control flag 2151 //! 2152 virtual bool UsePlatformControlFlag() = 0; 2153 2154 //! \brief Program Curbe for ME kernel 2155 //! 2156 //! \param [in] params 2157 //! Input params to program ME curbe 2158 //! 2159 //! \return MOS_STATUS 2160 //! MOS_STATUS_SUCCESS if success, else fail reason 2161 //! 2162 MOS_STATUS SetCurbeMe(MeCurbeParams* params); 2163 }; 2164 2165 //! \brief typedef of class CodechalEncHevcStateG9* 2166 using PCODECHAL_ENC_HEVC_STATE_G9 = class CodechalEncHevcStateG9*; 2167 2168 #endif // __CODECHAL_ENCODE_HEVC_G9_H__ 2169