1 /* 2 * Copyright (c) 2017-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_encode_hevc_g12.h 24 //! \brief HEVC dual-pipe encoder for GEN12 platform. 25 //! 26 27 #ifndef __CODECHAL_ENCODE_HEVC_G12_H__ 28 #define __CODECHAL_ENCODE_HEVC_G12_H__ 29 30 #include "codechal_encode_hevc.h" 31 #include "codechal_encode_sw_scoreboard_g12.h" 32 #include "codechal_encode_sw_scoreboard_mdf_g12.h" 33 #include "codechal_encode_wp_mdf_g12.h" 34 #include "mhw_vdbox_g12_X.h" 35 #include "codechal_kernel_intra_dist.h" 36 #include "codechal_encode_hevc_brc_g12.h" 37 #include "codechal_encode_singlepipe_virtualengine.h" 38 #include "codechal_encode_scalability.h" 39 40 #define VDBOX_HUC_PAK_INTEGRATION_KERNEL_DESCRIPTOR 15 41 #define BRC_IMG_STATE_SIZE_PER_PASS_G12 192 42 #define HEVC_BRC_LONG_TERM_REFRENCE_FLAG 0x8000 43 #define MAX_CONCURRENT_GROUP 4 44 45 //! 46 //! \struct HucPakStitchDmemEncG12 47 //! \brief The struct of Huc Com Dmem 48 //! 49 struct HucPakStitchDmemEncG12 50 { 51 uint32_t TileSizeRecord_offset[5]; // Tile Size Records, start offset in byte, 0xffffffff means unavailable 52 uint32_t VDENCSTAT_offset[5]; // needed for HEVC VDEnc, VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 53 uint32_t HEVC_PAKSTAT_offset[5]; //needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 54 uint32_t HEVC_Streamout_offset[5]; //needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 55 uint32_t VP9_PAK_STAT_offset[5]; //needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 56 uint32_t Vp9CounterBuffer_offset[5]; //needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 57 uint32_t LastTileBS_StartInBytes;// last tile in bitstream for region 4 and region 5 58 uint32_t SliceHeaderSizeinBits;// needed for HEVC dual pipe BRC 59 uint16_t TotalSizeInCommandBuffer; // Total size in bytes of valid data in the command buffer 60 uint16_t OffsetInCommandBuffer; // Byte offset of the to-be-updated Length (uint32_t) in the command buffer, 0xffff means unavailable 61 uint16_t PicWidthInPixel; // Picture width in pixel 62 uint16_t PicHeightInPixel; // Picture hieght in pixel 63 uint16_t TotalNumberOfPAKs; // [2..4] 64 uint16_t NumSlices[4]; // this is number of slices from each PAK 65 uint16_t NumTiles[4]; // this is number of tiles from each PAK 66 uint16_t PIC_STATE_StartInBytes;// offset for region 7 and region 8 67 uint8_t Codec; // 1: HEVC DP; 2: HEVC VDEnc; 3: VP9 VDEnc 68 uint8_t MAXPass; // Max number of BRC pass >=1 69 uint8_t CurrentPass; // Current BRC pass [1..MAXPass] 70 uint8_t MinCUSize; // Minimum CU size (3: 8x8, 4:16x16), HEVC only. 71 uint8_t CabacZeroWordFlag; // cabac zero flag, HEVC only 72 uint8_t bitdepth_luma; // luma bitdepth, HEVC only 73 uint8_t bitdepth_chroma; // chroma bitdepth, HEVC only 74 uint8_t ChromaFormatIdc; // chroma format idc, HEVC only 75 uint8_t currFrameBRClevel; // Hevc dual pipe only 76 uint8_t brcUnderFlowEnable; // Hevc dual pipe only 77 uint8_t StitchEnable;// enable stitch cmd for Hevc dual pipe 78 uint8_t reserved1; 79 uint16_t StitchCommandOffset; // offset in region 10 which is the second level batch buffer 80 uint16_t reserved2; 81 uint32_t BBEndforStitch; 82 uint8_t RSVD[16]; //mbz 83 }; 84 85 //! 86 //! \struct HucInputCmdG12 87 //! \brief The struct of Huc input command 88 //! 89 struct HucInputCmdG12 90 { 91 uint8_t SelectionForIndData = 0; 92 uint8_t CmdMode = 0; 93 uint16_t LengthOfTable = 0; 94 95 uint32_t SrcBaseOffset = 0; 96 uint32_t DestBaseOffset = 0; 97 98 uint32_t Reserved[3] = { 0 }; 99 100 uint32_t CopySize = 0; // use this as indicator of size for copy base addr cmd. Since encode will not implement CopySize for copy cmd 101 102 uint32_t ReservedCounter[4] = {0}; 103 104 uint32_t SrcAddrBottom = 0; 105 uint32_t SrcAddrTop = 0; 106 uint32_t DestAddrBottom = 0; 107 uint32_t DestAddrTop = 0; 108 }; 109 110 //! HEVC dual-pipe encoder class for GEN12 111 /*! 112 This class defines the member fields, functions for GEN12 platform 113 */ 114 class CodechalEncHevcStateG12 : public CodechalEncHevcState 115 { 116 public: 117 118 //!< Constants for mode bits look-up-tables 119 enum 120 { 121 LUTMODEBITS_INTRA_64X64 = 0x00, 122 LUTMODEBITS_INTRA_32X32 = 0x01, 123 LUTMODEBITS_INTRA_16X16 = 0x02, 124 LUTMODEBITS_INTRA_8X8 = 0x03, 125 LUTMODEBITS_INTRA_NXN = 0x04, 126 LUTMODEBITS_INTRA_MPM = 0x07, 127 LUTMODEBITS_INTRA_CHROMA = 0x08, 128 LUTMODEBITS_INTRA_DC_32X32 = 0x09, 129 LUTMODEBITS_INTRA_DC_8X8 = 0x0A, 130 LUTMODEBITS_INTRA_NONDC_32X32 = 0x0B, 131 LUTMODEBITS_INTRA_NONDC_16X16 = 0x0C, // only used by CRE 132 LUTMODEBITS_INTRA_NONDC_8X8 = 0x0D, 133 LUTMODEBITS_INTER_64X64 = 0x0E, // only used by Kernel 134 LUTMODEBITS_INTER_64X32 = 0x0F, 135 LUTMODEBITS_INTER_32X64 = 0x0F, 136 LUTMODEBITS_INTER_32X32 = 0x10, 137 LUTMODEBITS_INTER_32X16 = 0x11, 138 LUTMODEBITS_INTER_16X32 = 0x11, 139 LUTMODEBITS_INTER_AMP = 0x11, 140 LUTMODEBITS_INTER_16X8 = 0x13, 141 LUTMODEBITS_INTER_8X16 = 0x13, 142 LUTMODEBITS_INTER_8X8 = 0x14, 143 LUTMODEBITS_INTER_BIDIR = 0x15, 144 LUTMODEBITS_INTER_REFID = 0x16, 145 LUTMODEBITS_MERGE_64X64 = 0x17, 146 LUTMODEBITS_MERGE_32X32 = 0x18, 147 LUTMODEBITS_MERGE_16X16 = 0x19, 148 LUTMODEBITS_MERGE_8X8 = 0x1A, 149 LUTMODEBITS_INTER_SKIP = 0x1B, // only used by CRE 150 LUTMODEBITS_SKIP_64X64 = 0x1C, 151 LUTMODEBITS_SKIP_32X32 = 0x1D, 152 LUTMODEBITS_SKIP_16X16 = 0x1E, 153 LUTMODEBITS_SKIP_8X8 = 0x1F, 154 LUTMODEBITS_TU_DEPTH_0 = 0x23, // shared by HEVC & VP9 155 LUTMODEBITS_TU_DEPTH_1 = 0x24, // shared by HEVC & VP9 156 LUTMODEBITS_INTER_16X16 = 0x12, 157 LUTMODEBITS_CBF = 0x26, 158 LUTMODEBITS_INTRA_CBF_32X32 = LUTMODEBITS_CBF + 0, 159 LUTMODEBITS_INTRA_CBF_16X16 = LUTMODEBITS_CBF + 1, 160 LUTMODEBITS_INTRA_CBF_8X8 = LUTMODEBITS_CBF + 2, 161 LUTMODEBITS_INTRA_CBF_4X4 = LUTMODEBITS_CBF + 3, 162 LUTMODEBITS_INTER_CBF_32X32 = LUTMODEBITS_CBF + 4, 163 LUTMODEBITS_INTER_CBF_16X16 = LUTMODEBITS_CBF + 5, 164 LUTMODEBITS_INTER_CBF_8X8 = LUTMODEBITS_CBF + 6, 165 LUTMODEBITS_INTER_CBF_4X4 = LUTMODEBITS_CBF + 7, 166 NUM_LUTMODEBITS = 46 167 }; 168 169 //!< Constants for CRE costing look-up-tables 170 enum 171 { 172 LUTCREMODE_INTRA_NONPRED = 0x00, // MPM 173 LUTCREMODE_INTRA_32X32 = 0x01, 174 LUTCREMODE_INTRA_16X16 = 0x02, 175 LUTCREMODE_INTRA_8X8 = 0x03, 176 LUTCREMODE_INTER_32X16 = 0x04, 177 LUTCREMODE_INTER_16X32 = 0x04, 178 LUTCREMODE_INTER_AMP = 0x04, 179 LUTCREMODE_INTER_16X16 = 0x05, 180 LUTCREMODE_INTER_16X8 = 0x06, 181 LUTCREMODE_INTER_8X16 = 0x06, 182 LUTCREMODE_INTER_8X8 = 0x07, 183 LUTCREMODE_INTER_32X32 = 0x08, 184 LUTCREMODE_INTER_BIDIR = 0x09, 185 LUTCREMODE_REF_ID = 0x0A, 186 LUTCREMODE_INTRA_CHROMA = 0x0B, 187 LUTCREMODE_INTER_SKIP = 0x0C, 188 LUTCREMODE_INTRA_NONDC_32X32 = 0x0D, 189 LUTCREMODE_INTRA_NONDC_16X16 = 0x0E, 190 LUTCREMODE_INTRA_NONDC_8X8 = 0x0F, 191 NUM_LUTCREMODE = 16 192 }; 193 194 //!< Constants for RDE costing look-up-tables 195 enum 196 { 197 LUTRDEMODE_INTRA_64X64 = 0x00, 198 LUTRDEMODE_INTRA_32X32 = 0x01, 199 LUTRDEMODE_INTRA_16X16 = 0x02, 200 LUTRDEMODE_INTRA_8X8 = 0x03, 201 LUTRDEMODE_INTRA_NXN = 0x04, 202 LUTRDEMODE_INTRA_MPM = 0x07, 203 LUTRDEMODE_INTRA_DC_32X32 = 0x08, 204 LUTRDEMODE_INTRA_DC_8X8 = 0x09, 205 LUTRDEMODE_INTRA_NONDC_32X32 = 0x0A, 206 LUTRDEMODE_INTRA_NONDC_8X8 = 0x0B, 207 LUTRDEMODE_INTER_BIDIR = 0x0C, 208 LUTRDEMODE_INTER_REFID = 0x0D, 209 LUTRDEMODE_SKIP_64X64 = 0x0E, 210 LUTRDEMODE_SKIP_32X32 = 0x0F, 211 LUTRDEMODE_SKIP_16X16 = 0x10, 212 LUTRDEMODE_SKIP_8X8 = 0x11, 213 LUTRDEMODE_MERGE_64X64 = 0x12, 214 LUTRDEMODE_MERGE_32X32 = 0x13, 215 LUTRDEMODE_MERGE_16X16 = 0x14, 216 LUTRDEMODE_MERGE_8X8 = 0x15, 217 LUTRDEMODE_INTER_32X32 = 0x16, 218 LUTRDEMODE_INTER_32X16 = 0x17, 219 LUTRDEMODE_INTER_16X32 = 0x17, 220 LUTRDEMODE_INTER_AMP = 0x17, 221 LUTRDEMODE_INTER_16X16 = 0x18, 222 LUTRDEMODE_INTER_16X8 = 0x19, 223 LUTRDEMODE_INTER_8X16 = 0x19, 224 LUTRDEMODE_INTER_8X8 = 0x1A, 225 LUTRDEMODE_TU_DEPTH_0 = 0x1E, 226 LUTRDEMODE_TU_DEPTH_1 = 0x1F, 227 LUTRDEMODE_CBF = 0x21, 228 LUTRDEMODE_INTRA_CBF_32X32 = LUTRDEMODE_CBF+0, 229 LUTRDEMODE_INTRA_CBF_16X16 = LUTRDEMODE_CBF+1, 230 LUTRDEMODE_INTRA_CBF_8X8 = LUTRDEMODE_CBF+2, 231 LUTRDEMODE_INTRA_CBF_4X4 = LUTRDEMODE_CBF+3, 232 LUTRDEMODE_INTER_CBF_32X32 = LUTRDEMODE_CBF+4, 233 LUTRDEMODE_INTER_CBF_16X16 = LUTRDEMODE_CBF+5, 234 LUTRDEMODE_INTER_CBF_8X8 = LUTRDEMODE_CBF+6, 235 LUTRDEMODE_INTER_CBF_4X4 = LUTRDEMODE_CBF+7, 236 NUM_LUTRDEMODE = 41, 237 }; 238 239 //!< MBENC kernel index 240 enum 241 { 242 MBENC_LCU32_KRNIDX = 0, 243 MBENC_LCU64_KRNIDX = 1, 244 MBENC_NUM_KRN 245 }; 246 247 //!< Binding table offset 248 enum 249 { 250 //BRC Init/Reset 251 BRC_INIT_RESET_BEGIN = 0, 252 BRC_INIT_RESET_HISTORY = BRC_INIT_RESET_BEGIN, 253 BRC_INIT_RESET_DISTORTION, 254 BRC_INIT_RESET_END, 255 256 //BRC Update (frame based) 257 BRC_UPDATE_BEGIN = 0, 258 BRC_UPDATE_HISTORY = BRC_UPDATE_BEGIN, 259 BRC_UPDATE_PREV_PAK, 260 BRC_UPDATE_PIC_STATE_R, 261 BRC_UPDATE_PIC_STATE_W, 262 BRC_UPDATE_ENC_OUTPUT, 263 BRC_UPDATE_DISTORTION, 264 BRC_UPDATE_BRCDATA, 265 BRC_UPDATE_MB_STATS, 266 BRC_UPDATE_MV_AND_DISTORTION_SUM, 267 BRC_UPDATE_END, 268 269 //BRC Update (LCU-based) 270 BRC_LCU_UPDATE_BEGIN = 0, 271 BRC_LCU_UPDATE_HISTORY = BRC_LCU_UPDATE_BEGIN, 272 BRC_LCU_UPDATE_DISTORTION, 273 BRC_LCU_UPDATE_MB_STATS, 274 BRC_LCU_UPDATE_MB_QP, 275 BRC_LCU_UPDATE_ROI, 276 BRC_LCU_UPDATE_END, 277 278 // MBEnc I-kernel 279 MBENC_I_FRAME_BEGIN = 0, 280 MBENC_I_FRAME_VME_PRED_CURR_PIC_IDX0 = MBENC_I_FRAME_BEGIN, 281 MBENC_I_FRAME_VME_PRED_FWD_PIC_IDX0, 282 MBENC_I_FRAME_VME_PRED_BWD_PIC_IDX0, 283 MBENC_I_FRAME_VME_PRED_FWD_PIC_IDX1, 284 MBENC_I_FRAME_VME_PRED_BWD_PIC_IDX1, 285 MBENC_I_FRAME_VME_PRED_FWD_PIC_IDX2, 286 MBENC_I_FRAME_VME_PRED_BWD_PIC_IDX2, 287 MBENC_I_FRAME_VME_PRED_FWD_PIC_IDX3, 288 MBENC_I_FRAME_VME_PRED_BWD_PIC_IDX3, 289 MBENC_I_FRAME_CURR_Y, 290 MBENC_I_FRAME_CURR_UV, 291 MBENC_I_FRAME_CURR_Y_WITH_RECON_BOUNDARY_PIX, 292 MBENC_I_FRAME_INTERMEDIATE_CU_RECORD, 293 MBENC_I_FRAME_PAK_OBJ, 294 MBENC_I_FRAME_PAK_CU_RECORD, 295 MBENC_I_FRAME_SW_SCOREBOARD, 296 MBENC_I_FRAME_SCRATCH_SURFACE, 297 MBENC_I_FRAME_CU_QP_DATA, 298 MBENC_I_FRAME_LCU_LEVEL_DATA_INPUT, 299 MBENC_I_FRAME_ENC_CONST_TABLE, 300 MBENC_I_FRAME_CONCURRENT_TG_DATA, 301 MBENC_I_FRAME_BRC_COMBINED_ENC_PARAMETER_SURFACE, 302 MBENC_I_FRAME_DEBUG_DUMP, 303 MBENC_I_FRAME_END, 304 305 //MBEnc B-Kernel 306 MBENC_B_FRAME_BEGIN = 0, 307 MBENC_B_FRAME_ENCODER_COMBINED_BUFFER1 = MBENC_B_FRAME_BEGIN, 308 MBENC_B_FRAME_ENCODER_COMBINED_BUFFER2, 309 MBENC_B_FRAME_VME_PRED_CURR_PIC_IDX0, 310 MBENC_B_FRAME_VME_PRED_FWD_PIC_IDX0, 311 MBENC_B_FRAME_VME_PRED_BWD_PIC_IDX0, 312 MBENC_B_FRAME_VME_PRED_FWD_PIC_IDX1, 313 MBENC_B_FRAME_VME_PRED_BWD_PIC_IDX1, 314 MBENC_B_FRAME_VME_PRED_FWD_PIC_IDX2, 315 MBENC_B_FRAME_VME_PRED_BWD_PIC_IDX2, 316 MBENC_B_FRAME_VME_PRED_FWD_PIC_IDX3, 317 MBENC_B_FRAME_VME_PRED_BWD_PIC_IDX3, 318 MBENC_B_FRAME_CURR_Y, 319 MBENC_B_FRAME_CURR_UV, 320 MBENC_B_FRAME_CURR_Y_WITH_RECON_BOUNDARY_PIX, 321 MBENC_B_FRAME_ENC_CU_RECORD, 322 MBENC_B_FRAME_PAK_OBJ, 323 MBENC_B_FRAME_PAK_CU_RECORD, 324 MBENC_B_FRAME_SW_SCOREBOARD, 325 MBENC_B_FRAME_SCRATCH_SURFACE, 326 MBENC_B_FRAME_CU_QP_DATA, 327 MBENC_B_FRAME_LCU_LEVEL_DATA_INPUT, 328 MBENC_B_FRAME_ENC_CONST_TABLE, 329 MBENC_B_FRAME_COLOCATED_CU_MV_DATA, 330 MBENC_B_FRAME_HME_MOTION_PREDICTOR_DATA, 331 MBENC_B_FRAME_CONCURRENT_TG_DATA, 332 MBENC_B_FRAME_BRC_COMBINED_ENC_PARAMETER_SURFACE, 333 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_CURR, 334 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_FWD_PIC_IDX0, 335 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_BWD_PIC_IDX0, 336 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_FWD_PIC_IDX1, 337 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_BWD_PIC_IDX1, 338 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_FWD_PIC_IDX2, 339 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_BWD_PIC_IDX2, 340 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_FWD_PIC_IDX3, 341 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_BWD_PIC_IDX3, 342 MBENC_B_FRAME_ENCODER_HISTORY_INPUT_BUFFER, 343 MBENC_B_FRAME_ENCODER_HISTORY_OUTPUT_BUFFER, 344 MBENC_B_FRAME_DEBUG_SURFACE, 345 MBENC_B_FRAME_DEBUG_SURFACE1, 346 MBENC_B_FRAME_DEBUG_SURFACE2, 347 MBENC_B_FRAME_DEBUG_SURFACE3, 348 MBENC_B_FRAME_END, 349 }; 350 351 //!< Constants for TU based params 352 enum 353 { 354 IntraSpotCheckFlagTuParam, 355 EnableCu64CheckTuParam, 356 DynamicOrderThTuParam, 357 Dynamic64ThTuParam, 358 Dynamic64OrderTuParam, 359 Dynamic64EnableTuParam, 360 IncreaseExitThreshTuParam, 361 Log2TUMaxDepthInterTuParam, 362 Log2TUMaxDepthIntraTuParam, 363 MaxNumIMESearchCenterTuParam, 364 Fake32EnableTuParam, 365 Dynamic64Min32, 366 TotalTuParams 367 }; 368 369 //! \cond SKIP_DOXYGEN 370 //! Kernel Header structure 371 struct CODECHAL_HEVC_KERNEL_HEADER 372 { 373 int nKernelCount; 374 union 375 { 376 struct 377 { 378 CODECHAL_KERNEL_HEADER HEVC_Enc_LCU32; 379 CODECHAL_KERNEL_HEADER HEVC_Enc_LCU64; 380 CODECHAL_KERNEL_HEADER HEVC_brc_init; 381 CODECHAL_KERNEL_HEADER HEVC_brc_reset; 382 CODECHAL_KERNEL_HEADER HEVC_brc_update; 383 CODECHAL_KERNEL_HEADER HEVC_brc_lcuqp; 384 }; 385 }; 386 }; 387 using PCODECHAL_HEVC_KERNEL_HEADER = CODECHAL_HEVC_KERNEL_HEADER*; 388 389 static const uint32_t MAX_MULTI_FRAME_NUMBER = 4; 390 391 //! MBENC LCU32 kernel BTI structure 392 struct MBENC_LCU32_BTI 393 { 394 uint32_t Combined1DSurIndexMF1[MAX_MULTI_FRAME_NUMBER]; 395 uint32_t Combined1DSurIndexMF2[MAX_MULTI_FRAME_NUMBER]; 396 uint32_t VMEInterPredictionSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 397 uint32_t SrcSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 398 uint32_t SrcReconSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 399 uint32_t CURecordSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 400 uint32_t PAKObjectSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 401 uint32_t CUPacketSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 402 uint32_t SWScoreBoardSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 403 uint32_t QPCU16SurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 404 uint32_t LCULevelDataSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 405 uint32_t TemporalMVSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 406 uint32_t HmeDataSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 407 uint32_t HEVCCnstLutSurfIndex; 408 uint32_t LoadBalenceSurfIndex; 409 uint32_t ReservedBTI0; 410 uint32_t ReservedBTI1; 411 uint32_t DebugSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 412 }; 413 using PMBENC_LCU32_BTI = MBENC_LCU32_BTI*; 414 415 //! MBENC LCU64 kernel BTI structure 416 struct MBENC_LCU64_BTI 417 { 418 uint32_t Combined1DSurIndexMF1[MAX_MULTI_FRAME_NUMBER]; 419 uint32_t Combined1DSurIndexMF2[MAX_MULTI_FRAME_NUMBER]; 420 uint32_t VMEInterPredictionSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 421 uint32_t SrcSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 422 uint32_t SrcReconSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 423 uint32_t CURecordSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 424 uint32_t PAKObjectSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 425 uint32_t CUPacketSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 426 uint32_t SWScoreBoardSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 427 uint32_t QPCU16SurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 428 uint32_t LCULevelDataSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 429 uint32_t TemporalMVSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 430 uint32_t HmeDataSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 431 uint32_t VME2XInterPredictionSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 432 uint32_t HEVCCnstLutSurfIndex; 433 uint32_t LoadBalenceSurfIndex; 434 uint32_t DebugSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 435 }; 436 using PMBENC_LCU64_BTI = MBENC_LCU64_BTI*; 437 438 struct MBENC_COMBINED_BTI 439 { MBENC_COMBINED_BTIMBENC_COMBINED_BTI440 MBENC_COMBINED_BTI() 441 { 442 MOS_ZeroMemory(this, sizeof(*this)); 443 } 444 union 445 { 446 MBENC_LCU32_BTI BTI_LCU32; 447 MBENC_LCU64_BTI BTI_LCU64; 448 }; 449 }; 450 451 //! BRC Init/Reset kernel Curbe structure 452 struct BRC_INITRESET_CURBE 453 { 454 // uint32_t 0 455 uint32_t DW0_ProfileLevelMaxFrame : MOS_BITFIELD_RANGE(0, 31); 456 457 // uint32_t 1 458 uint32_t DW1_InitBufFull : MOS_BITFIELD_RANGE(0, 31); 459 460 // uint32_t 2 461 uint32_t DW2_BufSize : MOS_BITFIELD_RANGE(0, 31); 462 463 // uint32_t 3 464 uint32_t DW3_TargetBitRate : MOS_BITFIELD_RANGE(0, 31); 465 466 // uint32_t 4 467 uint32_t DW4_MaximumBitRate : MOS_BITFIELD_RANGE(0, 31); 468 469 // uint32_t 5 470 uint32_t DW5_MinimumBitRate : MOS_BITFIELD_RANGE(0, 31); 471 472 // uint32_t 6 473 uint32_t DW6_FrameRateM : MOS_BITFIELD_RANGE(0, 31); 474 475 // uint32_t 7 476 uint32_t DW7_FrameRateD : MOS_BITFIELD_RANGE(0, 31); 477 478 // uint32_t 8 479 uint32_t DW8_BRCFlag : MOS_BITFIELD_RANGE(0, 15); 480 uint32_t DW8_BRCGopP : MOS_BITFIELD_RANGE(16, 31); 481 482 // uint32_t 9 483 uint32_t DW9_BRCGopB : MOS_BITFIELD_RANGE(0, 15); 484 uint32_t DW9_FrameWidth : MOS_BITFIELD_RANGE(16, 31); 485 486 // uint32_t 10 487 uint32_t DW10_FrameHeight : MOS_BITFIELD_RANGE(0, 15); 488 uint32_t DW10_AVBRAccuracy : MOS_BITFIELD_RANGE(16, 31); 489 490 // uint32_t 11 491 uint32_t DW11_AVBRConvergence : MOS_BITFIELD_RANGE(0, 15); 492 uint32_t DW11_MinimumQP : MOS_BITFIELD_RANGE(16, 31); 493 494 // uint32_t 12 495 uint32_t DW12_MaximumQP : MOS_BITFIELD_RANGE(0, 15); 496 uint32_t DW12_NumberSlice : MOS_BITFIELD_RANGE(16, 31); 497 498 // uint32_t 13 499 uint32_t DW13_Reserved_0 : MOS_BITFIELD_RANGE(0, 15); 500 uint32_t DW13_BRCGopB1 : MOS_BITFIELD_RANGE(16, 31); 501 502 // uint32_t 14 503 uint32_t DW14_BRCGopB2 : MOS_BITFIELD_RANGE(0, 15); 504 uint32_t DW14_MaxBRCLevel : MOS_BITFIELD_RANGE(16, 31); 505 506 // uint32_t 15 507 uint32_t DW15_LongTermInterval : MOS_BITFIELD_RANGE(0, 15); 508 uint32_t DW15_Reserved_0 : MOS_BITFIELD_RANGE(16, 31); 509 510 // uint32_t 16 511 uint32_t DW16_InstantRateThreshold0_Pframe : MOS_BITFIELD_RANGE(0, 7); 512 uint32_t DW16_InstantRateThreshold1_Pframe : MOS_BITFIELD_RANGE(8, 15); 513 uint32_t DW16_InstantRateThreshold2_Pframe : MOS_BITFIELD_RANGE(16, 23); 514 uint32_t DW16_InstantRateThreshold3_Pframe : MOS_BITFIELD_RANGE(24, 31); 515 516 // uint32_t 17 517 uint32_t DW17_InstantRateThreshold0_Bframe : MOS_BITFIELD_RANGE(0, 7); 518 uint32_t DW17_InstantRateThreshold1_Bframe : MOS_BITFIELD_RANGE(8, 15); 519 uint32_t DW17_InstantRateThreshold2_Bframe : MOS_BITFIELD_RANGE(16, 23); 520 uint32_t DW17_InstantRateThreshold3_Bframe : MOS_BITFIELD_RANGE(24, 31); 521 522 // uint32_t 18 523 uint32_t DW18_InstantRateThreshold0_Iframe : MOS_BITFIELD_RANGE(0, 7); 524 uint32_t DW18_InstantRateThreshold1_Iframe : MOS_BITFIELD_RANGE(8, 15); 525 uint32_t DW18_InstantRateThreshold2_Iframe : MOS_BITFIELD_RANGE(16, 23); 526 uint32_t DW18_InstantRateThreshold3_Iframe : MOS_BITFIELD_RANGE(24, 31); 527 528 // uint32_t 19 529 uint32_t DW19_DeviationThreshold0_PBframe : MOS_BITFIELD_RANGE(0, 7); 530 uint32_t DW19_DeviationThreshold1_PBframe : MOS_BITFIELD_RANGE(8, 15); 531 uint32_t DW19_DeviationThreshold2_PBframe : MOS_BITFIELD_RANGE(16, 23); 532 uint32_t DW19_DeviationThreshold3_PBframe : MOS_BITFIELD_RANGE(24, 31); 533 534 // uint32_t 20 535 uint32_t DW20_DeviationThreshold4_PBframe : MOS_BITFIELD_RANGE(0, 7); 536 uint32_t DW20_DeviationThreshold5_PBframe : MOS_BITFIELD_RANGE(8, 15); 537 uint32_t DW20_DeviationThreshold6_PBframe : MOS_BITFIELD_RANGE(16, 23); 538 uint32_t DW20_DeviationThreshold7_PBframe : MOS_BITFIELD_RANGE(24, 31); 539 540 // uint32_t 21 541 uint32_t DW21_DeviationThreshold0_VBRcontrol : MOS_BITFIELD_RANGE(0, 7); 542 uint32_t DW21_DeviationThreshold1_VBRcontrol : MOS_BITFIELD_RANGE(8, 15); 543 uint32_t DW21_DeviationThreshold2_VBRcontrol : MOS_BITFIELD_RANGE(16, 23); 544 uint32_t DW21_DeviationThreshold3_VBRcontrol : MOS_BITFIELD_RANGE(24, 31); 545 546 // uint32_t 22 547 uint32_t DW22_DeviationThreshold4_VBRcontrol : MOS_BITFIELD_RANGE(0, 7); 548 uint32_t DW22_DeviationThreshold5_VBRcontrol : MOS_BITFIELD_RANGE(8, 15); 549 uint32_t DW22_DeviationThreshold6_VBRcontrol : MOS_BITFIELD_RANGE(16, 23); 550 uint32_t DW22_DeviationThreshold7_VBRcontrol : MOS_BITFIELD_RANGE(24, 31); 551 552 // uint32_t 23 553 uint32_t DW23_DeviationThreshold0_Iframe : MOS_BITFIELD_RANGE(0, 7); 554 uint32_t DW23_DeviationThreshold1_Iframe : MOS_BITFIELD_RANGE(8, 15); 555 uint32_t DW23_DeviationThreshold2_Iframe : MOS_BITFIELD_RANGE(16, 23); 556 uint32_t DW23_DeviationThreshold3_Iframe : MOS_BITFIELD_RANGE(24, 31); 557 558 // uint32_t 24 559 uint32_t DW24_DeviationThreshold4_Iframe : MOS_BITFIELD_RANGE(0, 7); 560 uint32_t DW24_DeviationThreshold5_Iframe : MOS_BITFIELD_RANGE(8, 15); 561 uint32_t DW24_DeviationThreshold6_Iframe : MOS_BITFIELD_RANGE(16, 23); 562 uint32_t DW24_DeviationThreshold7_Iframe : MOS_BITFIELD_RANGE(24, 31); 563 564 // uint32_t 25 565 uint32_t DW25_ACQPBuffer : MOS_BITFIELD_RANGE(0, 7); 566 uint32_t DW25_IntraSADTransform : MOS_BITFIELD_RANGE(8, 15); 567 uint32_t DW25_Log2MaxCuSize : MOS_BITFIELD_RANGE(16, 23); 568 uint32_t DW25_SlidingWindowSize : MOS_BITFIELD_RANGE(24, 31); 569 570 // uint32_t 26 571 uint32_t DW26_BGOPSize : MOS_BITFIELD_RANGE(0, 7); 572 uint32_t DW26_RandomAccess : MOS_BITFIELD_RANGE(8, 15); 573 uint32_t DW26_Reserved_0 : MOS_BITFIELD_RANGE(16, 31); 574 575 // uint32_t 27 576 uint32_t DW27_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 577 578 // uint32_t 28 579 uint32_t DW28_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 580 581 // uint32_t 29 582 uint32_t DW29_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 583 584 // uint32_t 30 585 uint32_t DW30_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 586 587 // uint32_t 31 588 uint32_t DW31_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 589 590 }; 591 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(BRC_INITRESET_CURBE)) == 32); 592 using PBRC_INITRESET_CURBE = BRC_INITRESET_CURBE*; 593 594 //! BRC Update kernel Curbe structure 595 struct BRCUPDATE_CURBE 596 { 597 // uint32_t 0 598 uint32_t DW0_TargetSize : MOS_BITFIELD_RANGE(0, 31); 599 600 // uint32_t 1 601 uint32_t DW1_FrameNumber : MOS_BITFIELD_RANGE(0, 31); 602 603 // uint32_t 2 604 uint32_t DW2_PictureHeaderSize : MOS_BITFIELD_RANGE(0, 31); 605 606 // uint32_t 3 607 uint32_t DW3_StartGAdjFrame0 : MOS_BITFIELD_RANGE(0, 15); 608 uint32_t DW3_StartGAdjFrame1 : MOS_BITFIELD_RANGE(16, 31); 609 610 // uint32_t 4 611 uint32_t DW4_StartGAdjFrame2 : MOS_BITFIELD_RANGE(0, 15); 612 uint32_t DW4_StartGAdjFrame3 : MOS_BITFIELD_RANGE(16, 31); 613 614 // uint32_t 5 615 uint32_t DW5_TargetSize_Flag : MOS_BITFIELD_RANGE(0, 7); 616 uint32_t DW5_Reserved_0 : MOS_BITFIELD_RANGE(8, 15); 617 uint32_t DW5_MaxNumPAKs : MOS_BITFIELD_RANGE(16, 23); 618 uint32_t DW5_CurrFrameBrcLevel : MOS_BITFIELD_RANGE(24, 31); 619 620 // uint32_t 6 621 uint32_t DW6_NumSkippedFrames : MOS_BITFIELD_RANGE(0, 7); 622 uint32_t DW6_CqpValue : MOS_BITFIELD_RANGE(8, 15); 623 uint32_t DW6_ROIEnable : MOS_BITFIELD_RANGE(16, 16); 624 uint32_t DW6_BRCROIEnable : MOS_BITFIELD_RANGE(17, 17); 625 uint32_t DW6_LowDelayEnable : MOS_BITFIELD_RANGE(18, 18); 626 uint32_t DW6_Reserved1 : MOS_BITFIELD_RANGE(19, 19); 627 uint32_t DW6_SlidingWindowEnable : MOS_BITFIELD_RANGE(20, 20); 628 uint32_t DW6_Reserved2 : MOS_BITFIELD_RANGE(21, 23); 629 uint32_t DW6_RoiRatio : MOS_BITFIELD_RANGE(24, 31); 630 631 // uint32_t 7 632 uint32_t DW7_Reserved_0 : MOS_BITFIELD_RANGE(0, 15); 633 uint32_t DW7_FrameMinQP : MOS_BITFIELD_RANGE(16, 23); 634 uint32_t DW7_FrameMaxQP : MOS_BITFIELD_RANGE(24, 31); 635 636 // uint32_t 8 637 uint32_t DW8_StartGlobalAdjustMult0 : MOS_BITFIELD_RANGE(0, 7); 638 uint32_t DW8_StartGlobalAdjustMult1 : MOS_BITFIELD_RANGE(8, 15); 639 uint32_t DW8_StartGlobalAdjustMult2 : MOS_BITFIELD_RANGE(16, 23); 640 uint32_t DW8_StartGlobalAdjustMult3 : MOS_BITFIELD_RANGE(24, 31); 641 642 // uint32_t 9 643 uint32_t DW9_StartGlobalAdjustMult4 : MOS_BITFIELD_RANGE(0, 7); 644 uint32_t DW9_StartGlobalAdjustDivd0 : MOS_BITFIELD_RANGE(8, 15); 645 uint32_t DW9_StartGlobalAdjustDivd1 : MOS_BITFIELD_RANGE(16, 23); 646 uint32_t DW9_StartGlobalAdjustDivd2 : MOS_BITFIELD_RANGE(24, 31); 647 648 // uint32_t 10 649 uint32_t DW10_StartGlobalAdjustDivd3 : MOS_BITFIELD_RANGE(0, 7); 650 uint32_t DW10_StartGlobalAdjustDivd4 : MOS_BITFIELD_RANGE(8, 15); 651 uint32_t DW10_QPThreshold0 : MOS_BITFIELD_RANGE(16, 23); 652 uint32_t DW10_QPThreshold1 : MOS_BITFIELD_RANGE(24, 31); 653 654 // uint32_t 11 655 uint32_t DW11_QPThreshold2 : MOS_BITFIELD_RANGE(0, 7); 656 uint32_t DW11_QPThreshold3 : MOS_BITFIELD_RANGE(8, 15); 657 uint32_t DW11_gRateRatioThreshold0 : MOS_BITFIELD_RANGE(16, 23); 658 uint32_t DW11_gRateRatioThreshold1 : MOS_BITFIELD_RANGE(24, 31); 659 660 // uint32_t 12 661 uint32_t DW12_gRateRatioThreshold2 : MOS_BITFIELD_RANGE(0, 7); 662 uint32_t DW12_gRateRatioThreshold3 : MOS_BITFIELD_RANGE(8, 15); 663 uint32_t DW12_gRateRatioThreshold4 : MOS_BITFIELD_RANGE(16, 23); 664 uint32_t DW12_gRateRatioThreshold5 : MOS_BITFIELD_RANGE(24, 31); 665 666 // uint32_t 13 667 uint32_t DW13_gRateRatioThreshold6 : MOS_BITFIELD_RANGE(0, 7); 668 uint32_t DW13_gRateRatioThreshold7 : MOS_BITFIELD_RANGE(8, 15); 669 uint32_t DW13_gRateRatioThreshold8 : MOS_BITFIELD_RANGE(16, 23); 670 uint32_t DW13_gRateRatioThreshold9 : MOS_BITFIELD_RANGE(24, 31); 671 672 // uint32_t 14 673 uint32_t DW14_gRateRatioThreshold10 : MOS_BITFIELD_RANGE(0, 7); 674 uint32_t DW14_gRateRatioThreshold11 : MOS_BITFIELD_RANGE(8, 15); 675 uint32_t DW14_gRateRatioThreshold12 : MOS_BITFIELD_RANGE(16, 23); 676 uint32_t DW14_ParallelMode : MOS_BITFIELD_RANGE(24, 31); 677 678 // uint32_t 15 679 uint32_t DW15_SizeOfSkippedFrames : MOS_BITFIELD_RANGE(0, 31); 680 681 // uint32_t 16 682 uint32_t DW16_UserMaxFrameSize : MOS_BITFIELD_RANGE(0, 31); 683 684 // uint32_t 17 685 uint32_t DW17_LongTerm_Current : MOS_BITFIELD_RANGE(0, 7); 686 uint32_t DW17_Reserved_0 : MOS_BITFIELD_RANGE(8, 31); 687 688 // uint32_t 18 - 23 reserved 689 uint32_t DW18_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 690 uint32_t DW19_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 691 uint32_t DW20_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 692 uint32_t DW21_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 693 uint32_t DW22_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 694 uint32_t DW23_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 695 }; 696 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(BRCUPDATE_CURBE)) == 24); 697 using PBRCUPDATE_CURBE = BRCUPDATE_CURBE*; 698 699 //! LCU level data structure 700 struct LCU_LEVEL_DATA 701 { 702 uint16_t SliceStartLcuIndex; 703 uint16_t SliceEndLcuIndex; 704 uint16_t TileId; 705 uint16_t SliceId; 706 uint16_t TileStartCoordinateX; 707 uint16_t TileStartCoordinateY; 708 uint16_t TileEndCoordinateX; 709 uint16_t TileEndCoordinateY; 710 }; 711 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(LCU_LEVEL_DATA)) == 4); 712 using PLCU_LEVEL_DATA = LCU_LEVEL_DATA*; 713 714 //! Concurrent thread group data structure 715 struct CONCURRENT_THREAD_GROUP_DATA 716 { 717 uint16_t CurrSliceStartLcuX; 718 uint16_t CurrSliceStartLcuY; 719 uint16_t CurrSliceEndLcuX; 720 uint16_t CurrSliceEndLcuY; 721 uint16_t CurrTgStartLcuX; 722 uint16_t CurrTgStartLcuY; 723 uint16_t CurrTgEndLcuX; 724 uint16_t CurrTgEndLcuY; 725 uint16_t Reserved[24]; 726 }; 727 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CONCURRENT_THREAD_GROUP_DATA)) == 16); 728 using PCONCURRENT_THREAD_GROUP_DATA = CONCURRENT_THREAD_GROUP_DATA*; 729 730 struct MBENC_CURBE 731 { MBENC_CURBEMBENC_CURBE732 MBENC_CURBE() 733 { 734 MOS_SecureMemcpy(this, sizeof(*this), m_mbencCurbeInit, sizeof(m_mbencCurbeInit)); 735 } 736 737 //R1.0 //DW0 738 union 739 { 740 uint32_t R1_0; 741 struct 742 { 743 uint32_t FrameWidthInSamples : 16; 744 uint32_t FrameHeightInSamples : 16; 745 }; 746 }; 747 748 //R1.1 //DW1 749 union 750 { 751 uint32_t R1_1; 752 struct 753 { 754 uint32_t Log2MaxCUSize : 4; 755 uint32_t Log2MinCUSize : 4; 756 uint32_t Log2MaxTUSize : 4; 757 uint32_t Log2MinTUSize : 4; 758 uint32_t MaxNumIMESearchCenter : 3; 759 uint32_t MaxIntraRdeIter : 3; 760 uint32_t ROIEnable : 1; 761 uint32_t QPType : 2; 762 uint32_t MaxTransformDepthInter : 2; //<= Log2TUMaxDepthInter 763 uint32_t MaxTransformDepthIntra : 2; //<= Log2TUMaxDepthIntra 764 uint32_t Log2ParallelMergeLevel : 3; 765 766 }; 767 }; 768 769 //R1.2 //DW2 770 union 771 { 772 uint32_t R1_2; 773 struct 774 { 775 uint32_t CornerNeighborPixel : 8; 776 uint32_t IntraNeighborAvailFlags : 6; 777 uint32_t ChromaFormatType : 2; 778 uint32_t SubPelMode : 2; //Unin R0.3[16:17] SubPelMode 779 uint32_t IntraSpotCheck : 2; 780 uint32_t InterSADMeasure : 2; //Unin R0.3[20:21] InterSADMeasure 781 uint32_t IntraSADMeasure : 2; //Unin R0.3[22:23] IntraSADMeasureAdj 782 uint32_t IntraPrediction : 3; //UninR0.1 LumaIntraPartMask 783 uint32_t RefIDCostMode : 1; //UninR0.1[22] RefIDCostMode 784 uint32_t TUBasedCostSetting : 3; 785 uint32_t MBZ_1_2_1 : 1; 786 }; 787 }; 788 789 //R1.3 //DW3 790 union 791 { 792 uint32_t R1_3; 793 struct 794 { //UniversalInputSegmentPhase0_2: DW R1.0 795 uint32_t ExplictModeEn : 1; // [0] 796 uint32_t AdaptiveEn : 1; // [1] ImageState.AdaptiveEn 797 uint32_t MBZ_1_3_1 : 3; // [4:2] 798 uint32_t EarlyImeSuccessEn : 1; // [5] imageState.EarlyImeSuccessEn 799 uint32_t IntraSpeedMode : 1; // [6] 800 uint32_t IMECostCentersSel : 1; // [7] L0/L1 801 802 uint32_t RDEQuantRoundValue : 8; // [15:8] 0 803 804 uint32_t IMERefWindowSize : 2; // [17:16] m_ImageState.ImeRefWindowSize 805 uint32_t IntraComputeType : 1; // [18] 0 806 uint32_t Depth0IntraPredition : 1; // [19] 0 807 uint32_t TUDepthControl : 2; // [21:20] 808 uint32_t IntraTuRecFeedbackDisable : 1; // [22] 809 uint32_t MergeListBiDisable : 1; // [23] 810 811 uint32_t EarlyImeStop : 8; // [31:24] imageState->EarlyImeStopThres 812 }; 813 }; 814 815 //R1.4 //DW4 816 union 817 { 818 uint32_t R1_4; 819 struct 820 { 821 uint32_t FrameQP : 7; 822 uint32_t FrameQPSign : 1; 823 uint32_t ConcurrentGroupNum : 4; 824 uint32_t MBZ_Reserved : 3; 825 uint32_t WaveFrontSplitVQFix : 1; 826 uint32_t NumofUnitInWaveFront : 16; 827 }; 828 }; 829 830 //R1.5 //DW5 831 union 832 { 833 uint32_t R1_5; 834 struct 835 { 836 uint32_t LoadBalenceEnable : 1; 837 uint32_t NumberofMultiFrame : 3; 838 uint32_t MBZ_1_4_1 : 4; 839 uint32_t Degree45 : 1; 840 uint32_t Break12Dependency : 1; 841 uint32_t Fake32Enable : 1; 842 uint32_t MBZ_1_4_2 : 5; 843 uint32_t ThreadNumber : 8; 844 uint32_t MBZ_1_4_3 : 8; 845 }; 846 }; 847 848 //R1.6 - R2.7 //DW6 - DW15 849 uint32_t Reserved1[10]; 850 851 //R3.0 //DW16 852 union 853 { 854 uint32_t R3_0; 855 struct 856 { 857 uint32_t Pic_init_qp_B : 8; 858 uint32_t Pic_init_qp_P : 8; 859 uint32_t Pic_init_qp_I : 8; 860 uint32_t MBZ_3_0_0 : 8; 861 }; 862 }; 863 864 //R3.1 //DW17 865 union 866 { 867 uint32_t R3_1; 868 struct 869 { 870 uint32_t MBZ_3_1_0 : 16; 871 uint32_t NumofRowTile : 8; 872 uint32_t NumofColumnTile : 8; 873 }; 874 }; 875 876 //R3.2 //DW18 877 union 878 { 879 uint32_t R3_2; 880 struct 881 { 882 uint32_t TransquantBypassEnableFlag : 1; //<= EnableTransquantBypass (need in Pak data setup) 883 uint32_t PCMEnabledFlag : 1; //<= EnableIPCM 884 uint32_t MBZ_3_2_0 : 2; //reserved 885 uint32_t CuQpDeltaEnabledFlag : 1; //<= CuQpDeltaEnabledFlag 886 uint32_t Stepping : 2; 887 uint32_t WaveFrontSplitsEnable : 1; 888 uint32_t HMEFlag : 2; 889 uint32_t SuperHME : 1; 890 uint32_t UltraHME : 1; 891 uint32_t MBZ_3_2_2 : 4; //reserved 892 uint32_t Cu64SkipCheckOnly : 1; 893 uint32_t EnableCu64Check : 1; 894 uint32_t Cu642Nx2NCheckOnly : 1; 895 uint32_t EnableCu64AmpCheck : 1; 896 uint32_t MBZ_3_2_3 : 1; //reserved 897 uint32_t DisablePIntra : 1; 898 uint32_t DisableIntraTURec : 1; 899 uint32_t InheritIntraModeFromTU0 : 1; 900 uint32_t MBZ_3_2_4 : 3; //reserved 901 uint32_t CostScalingForRA : 1; 902 uint32_t DisableIntraNxN : 1; 903 uint32_t MBZ_3_2_5 : 3; //reserved 904 }; 905 }; 906 907 //R3.3 //DW19 908 union 909 { 910 uint32_t R3_3; 911 struct 912 { 913 uint32_t MaxRefIdxL0 : 8; 914 uint32_t MaxRefIdxL1 : 8; 915 uint32_t MaxBRefIdxL0 : 8; 916 uint32_t MBZ_3_3_0 : 8; 917 }; 918 }; 919 920 //R3.4 //DW20 921 union 922 { 923 uint32_t R3_4; 924 struct 925 { 926 uint32_t SkipEarlyTermination : 2; 927 uint32_t SkipEarlyTermSize : 2; 928 uint32_t Dynamic64Enable : 2; 929 uint32_t Dynamic64Order : 2; 930 uint32_t Dynamic64Th : 4; 931 uint32_t DynamicOrderTh : 4; 932 uint32_t PerBFrameQPOffset : 8; 933 uint32_t IncreaseExitThresh : 4; 934 uint32_t Dynamic64Min32 : 2; 935 uint32_t MBZ_3_4_0 : 1; //reserved 936 uint32_t LastFrameIsIntra : 1; 937 }; 938 }; 939 940 //R3.5 //DW21 941 union 942 { 943 uint32_t R3_5; 944 struct 945 { 946 uint32_t LenSP : 8; //Unin R1.2[16:23] LenSP 947 uint32_t MaxNumSU : 8; //Unin R1.2[24:31] MaxNumSU 948 uint32_t MBZ_3_5_1 : 16; 949 }; 950 }; 951 952 //R3.6 //DW22 953 union 954 { 955 uint32_t R3_6; 956 struct 957 { 958 uint32_t CostTableIndex : 8; 959 uint32_t MBZ_3_6_1 : 24; 960 }; 961 }; 962 963 //R3.7 //DW23 964 union 965 { 966 uint32_t R3_7; 967 struct 968 { 969 uint32_t SliceType : 2; 970 uint32_t TemporalMvpEnableFlag : 1; //<= EnableTemporalMvp 971 uint32_t CollocatedFromL0Flag : 1; 972 uint32_t theSameRefList : 1; 973 uint32_t IsLowDelay : 1; 974 uint32_t DisableTemporal16and8 : 1; 975 uint32_t MBZ_3_7_1 : 1; 976 uint32_t MaxNumMergeCand : 8; 977 uint32_t NumRefIdxL0 : 8; 978 uint32_t NumRefIdxL1 : 8; 979 980 }; 981 }; 982 983 //R4.0 //DW24 984 union 985 { 986 uint32_t R4_0; 987 struct 988 { 989 uint32_t FwdPocNumber_L0_mTb_0 : 8; 990 uint32_t BwdPocNumber_L1_mTb_0 : 8; 991 uint32_t FwdPocNumber_L0_mTb_1 : 8; 992 uint32_t BwdPocNumber_L1_mTb_1 : 8; 993 }; 994 }; 995 996 //R4.1 //DW25 997 union 998 { 999 uint32_t R4_1; 1000 struct 1001 { 1002 uint32_t FwdPocNumber_L0_mTb_2 : 8; 1003 uint32_t BwdPocNumber_L1_mTb_2 : 8; 1004 uint32_t FwdPocNumber_L0_mTb_3 : 8; 1005 uint32_t BwdPocNumber_L1_mTb_3 : 8; 1006 }; 1007 }; 1008 1009 //R4.2 //DW26 1010 union 1011 { 1012 uint32_t R4_2; 1013 struct 1014 { 1015 uint32_t FwdPocNumber_L0_mTb_4 : 8; 1016 uint32_t BwdPocNumber_L1_mTb_4 : 8; 1017 uint32_t FwdPocNumber_L0_mTb_5 : 8; 1018 uint32_t BwdPocNumber_L1_mTb_5 : 8; 1019 }; 1020 }; 1021 1022 //R4.3 //DW27 1023 union 1024 { 1025 uint32_t R4_3; 1026 struct 1027 { 1028 uint32_t FwdPocNumber_L0_mTb_6 : 8; 1029 uint32_t BwdPocNumber_L1_mTb_6 : 8; 1030 uint32_t FwdPocNumber_L0_mTb_7 : 8; 1031 uint32_t BwdPocNumber_L1_mTb_7 : 8; 1032 }; 1033 }; 1034 1035 //R4.4 //DW28 1036 union 1037 { 1038 uint32_t R4_4; 1039 struct 1040 { 1041 uint32_t LongTermReferenceFlags_L0 : 16; 1042 uint32_t LongTermReferenceFlags_L1 : 16; 1043 }; 1044 }; 1045 1046 //R4.5 //DW29 1047 union 1048 { 1049 uint32_t R4_5; 1050 struct 1051 { 1052 uint32_t RefFrameWinWidth : 16; 1053 uint32_t RefFrameWinHeight : 16; 1054 }; 1055 }; 1056 1057 //R4.6 //DW30 1058 union 1059 { 1060 uint32_t R4_6; 1061 struct 1062 { 1063 uint32_t RoundingInter : 8; 1064 uint32_t RoundingIntra : 8; 1065 uint32_t MaxThreadWidth : 8; 1066 uint32_t MaxThreadHeight : 8; 1067 }; 1068 }; 1069 1070 //R4.7 - R5.7 1071 uint32_t Reserved2[9]; 1072 }; 1073 1074 static uint32_t const hevcCurbeBufferConstSize = 256; 1075 C_ASSERT(hevcCurbeBufferConstSize > sizeof(MBENC_CURBE)); 1076 1077 static const uint32_t maxColorBitSupport = 256; 1078 1079 struct CONCURRENT_THREAD_GROUP_DATA_BUF 1080 { 1081 CONCURRENT_THREAD_GROUP_DATA item[maxColorBitSupport]; 1082 }; 1083 1084 struct MBENC_COMBINED_BUFFER1 1085 { MBENC_COMBINED_BUFFER1MBENC_COMBINED_BUFFER11086 MBENC_COMBINED_BUFFER1() 1087 { 1088 MOS_ZeroMemory(&(this->concurrent), sizeof(this->concurrent)); 1089 } 1090 union 1091 { 1092 MBENC_CURBE Curbe; 1093 uint8_t Data[hevcCurbeBufferConstSize]; 1094 }; 1095 CONCURRENT_THREAD_GROUP_DATA_BUF concurrent; 1096 }; 1097 using PMBENC_COMBINED_BUFFER1 = MBENC_COMBINED_BUFFER1*; 1098 1099 static const uint32_t HEVC_HISTORY_BUF_CONST_SIZE = 64; 1100 static const uint32_t HEVC_FRAMEBRC_BUF_CONST_SIZE = 1024; 1101 1102 struct MBENC_COMBINED_BUFFER2 1103 { 1104 uint8_t ucBrcCombinedEncBuffer[HEVC_FRAMEBRC_BUF_CONST_SIZE]; 1105 uint8_t ucHistoryInBuffer[HEVC_HISTORY_BUF_CONST_SIZE]; 1106 }; 1107 using PMBENC_COMBINED_BUFFER2 = MBENC_COMBINED_BUFFER2*; 1108 1109 struct CODECHAL_HEVC_VIRTUAL_ENGINE_OVERRIDE 1110 { 1111 union { 1112 uint8_t VdBox[MOS_MAX_ENGINE_INSTANCE_PER_CLASS]; 1113 uint64_t Value; 1114 }; 1115 }; 1116 1117 //! \endcond 1118 1119 static const uint8_t m_maxNumVmeL0Ref = 4; //!< Maximum number of L0 references 1120 static const uint8_t m_maxNumVmeL1Ref = 4; //!< Maximum number of L1 references 1121 static const uint16_t m_maxThreadsPerLcuB = 8; //!< Maximum number of threads per LCU B 1122 static const uint16_t m_minThreadsPerLcuB = 3; //!< Minimum number of threads per LCU B 1123 static const uint8_t m_maxMultiFrames = 4; //!< Maximum number of supported multi-frames 1124 static const uint8_t m_maxMfeSurfaces = 32; //!< Maximum number of surfaces per mfe stream 1125 1126 static const uint32_t m_encConstantDataLutSize = 81920; //!< Constant data LUT size in ints for B-kernel 1127 static const uint32_t m_brcBufferSize = 1024; //!< Size of the BRC buffer for Enc kernel 1128 static const uint32_t m_debugSurfaceSize = (8192 * 1024); //!< 8MB for the debug surface 1129 static const uint32_t m_maxThreadGprs = 256; //!< Maximum number of thread groups 1130 static const uint32_t m_brcLambdaModeCostTableSize = 416; //!< Size in DWs of Lambda Mode cost table for BRC 1131 static const uint32_t m_mvdistSummationSurfSize = 32; //!< Size of MV distortion summation surface 1132 static const uint8_t m_sumMVThreshold = 16; 1133 uint8_t m_hevcThreadTaskDataNum = 2; 1134 uint32_t m_maxWavefrontsforTU1 = 2; 1135 uint32_t m_maxWavefrontsforTU4 = 2; 1136 static const uint32_t m_loadBalanceSize = (256 * 16); //!< Load balance size used for load balance array. 1137 double m_alignReconFactor = 1.0; 1138 uint32_t m_threadMapSize = (256 * 16); //!< Thread map surface size will be updated depending on various gen 1139 1140 static const uint8_t m_meMethod[NUM_TARGET_USAGE_MODES]; //!< ME method 1141 static const uint8_t m_aStep = 1; //!< A Stepping 1142 1143 static const uint32_t m_encLcu32ConstantDataLut[m_encConstantDataLutSize/sizeof(uint32_t)]; //!< Constant data table for B kernel 1144 static const uint32_t m_encLcu64ConstantDataLut[m_encConstantDataLutSize/sizeof(uint32_t)]; //!< Constant data table for B kernel 1145 static const uint32_t m_brcLcu32x32LambdaModeCostInit[m_brcLambdaModeCostTableSize]; //!< Lambda mode cost table for BRC LCU32x32 1146 static const uint32_t m_brcLcu64x64LambdaModeCostInit[m_brcLambdaModeCostTableSize]; //!< Lambda mode cost table for BRC LCU64x64 1147 1148 static const uint32_t m_mbencCurbeInit[40]; //!< Initialization data for MBENC B kernel 1149 static const BRC_INITRESET_CURBE m_brcInitResetCurbeInit; //!< Initialization data for BRC Init/Reset kernel 1150 static const BRCUPDATE_CURBE m_brcUpdateCurbeInit; //!< Initialization data for BRC update kernel 1151 static const uint8_t m_tuSettings[TotalTuParams][3]; //!< Table for TU based settings for different params 1152 1153 static const double m_modeBits[2][46][3]; //!< Mode bits LUT based on LCUType/Mode/SliceType 1154 static const double m_modeBitsScale[46][3]; //!< Mode bits LUT based on [mode][SliceType] 1155 1156 MOS_SURFACE m_currPicWithReconBoundaryPix; //!< Current Picture with Reconstructed boundary pixels 1157 MOS_SURFACE m_lcuLevelInputDataSurface[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM]; //!< In Gen11 Lculevel Data is a 2D surface instead of Buffer 1158 MOS_SURFACE m_encoderHistoryInputBuffer; //!< Encoder History Input Data 1159 MOS_SURFACE m_encoderHistoryOutputBuffer; //!< Encoder History Output Data 1160 MOS_SURFACE m_intermediateCuRecordSurfaceLcu32; //!< Intermediate CU Record surface for I and B kernel 1161 MOS_SURFACE m_scratchSurface; //!< Scratch surface for I-kernel 1162 MOS_SURFACE m_16x16QpInputData; //!< CU 16x16 QP data input surface 1163 MOS_RESOURCE m_SAORowStoreBuffer = {}; //!< SAO RowStore buffer 1164 CODECHAL_ENCODE_BUFFER m_debugSurface[4]; //!< Debug surface used in MBENC kernels 1165 CODECHAL_ENCODE_BUFFER m_encConstantTableForB; //!< Enc constant table for B LCU32 1166 CODECHAL_ENCODE_BUFFER m_mvAndDistortionSumSurface; //!< Mv and Distortion summation surface 1167 1168 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 m_tileParams = nullptr; //!< Pointer to the Tile params 1169 PCODECHAL_ENCODE_SCALABILITY_STATE m_scalabilityState = nullptr; //!< Scalability state 1170 1171 bool m_colorBitMfeEnabled = false; //!< enable color bit for MFE: combine frames into one mbenc kernel 1172 bool m_multiWalkerEnabled = false; //!< enable multiple hw walkder 1173 bool m_useMdf = false; //!< Use MDF for MBEnc kernels. 1174 bool m_enableTileStitchByHW = false; //!< Enable HW to stitch commands in scalable mode 1175 bool m_enableHWSemaphore = false; //!< Enable HW semaphore 1176 bool m_weightedPredictionSupported = false; //!< Enable WP support 1177 bool m_useWeightedSurfaceForL0 = false; //!< Flag indicating if L0 Ref using weighted reference frame 1178 bool m_useWeightedSurfaceForL1 = false; //!< Flag indicating if L1 Ref using weighted reference frame 1179 bool m_sseEnabled = false; //!< Flag indicating if SSE is enabled in PAK 1180 bool m_degree45Needed = false; //!< Flag indicating if 45 degree dispatch pattern is used 1181 bool m_pakPiplStrmOutEnable = false; 1182 bool m_loadKernelInput = false; 1183 char m_loadKernelInputDataFolder[MOS_USER_CONTROL_MAX_DATA_SIZE] = {0}; //!< kernel input load from data folder name 1184 bool m_HierchGopBRCEnabled = false; //!< Flag indicating if hierarchical Gop is enabled in BRC 1185 1186 uint16_t m_totalNumThreadsPerLcu = 0; //!< Total number of threads per LCU 1187 uint8_t m_modeCostRde[42] = { 0 }; //!< RDE cost 1188 uint8_t m_modeCostCre[16] = { 0 }; //!< CRE cost 1189 uint32_t m_lambdaRD = 0; //!< Lambda value to multiply the RD costs 1190 1191 uint8_t m_numberEncKernelSubThread = m_hevcThreadTaskDataNum; 1192 uint32_t m_numberConcurrentGroup = MAX_CONCURRENT_GROUP; // can dividie one picture into several groups 1193 uint32_t m_numWavefrontInOneRegion = 0; 1194 uint16_t m_lastPictureCodingType = I_TYPE; 1195 uint8_t* m_swScoreboard = nullptr; 1196 bool m_useSwInitScoreboard = false; 1197 CODECHAL_ENCODE_BUFFER m_encBCombinedBuffer1[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM]; 1198 CODECHAL_ENCODE_BUFFER m_encBCombinedBuffer2[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM]; 1199 PCODECHAL_ENCODE_BUFFER m_brcInputForEncKernelBuffer = nullptr; 1200 uint8_t m_lastRecycledBufIdx = CODECHAL_ENCODE_RECYCLED_BUFFER_NUM - 1; 1201 uint32_t m_historyOutBufferSize = 0; 1202 uint32_t m_historyOutBufferOffset = 0; 1203 uint32_t m_threadTaskBufferSize = 0; 1204 uint32_t m_threadTaskBufferOffset = 0; 1205 bool m_initEncConstTable = true; 1206 bool m_initEncLoadBalence = true; 1207 bool m_enableBrcLTR = 1; //!< flag to enable long term reference BRC feature. 1208 bool m_isFrameLTR = 0; //!<flag to check if current frame is set as long term reference 1209 uint32_t m_ltrInterval = 0; //!< long term reference interval 1210 1211 CodechalKernelIntraDist *m_intraDistKernel = nullptr; 1212 CodechalEncodeSwScoreboardG12 *m_swScoreboardState = nullptr; //!< pointer to SW scoreboard ini state. 1213 CodecHalHevcBrcG12* m_hevcBrcG12 = nullptr; 1214 1215 // scalability 1216 unsigned char m_numPipe = 1; //!< Number of pipes 1217 unsigned char m_numPassesInOnePipe = 1; //!< Number of PAK passes in one pipe 1218 CODECHAL_ENCODE_BUFFER m_resPakSliceLevelStreamoutData; //!< Surface for slice level stream out data from PAK 1219 CODECHAL_HEVC_VIRTUAL_ENGINE_OVERRIDE m_kmdVeOveride; //!< KMD override virtual engine index 1220 uint32_t m_numTiles = 1; //!< Number of tiles 1221 CODECHAL_ENCODE_BUFFER m_resHcpScalabilitySyncBuffer; //!< Hcp sync buffer for scalability 1222 CODECHAL_ENCODE_BUFFER m_resTileBasedStatisticsBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC]; 1223 CODECHAL_ENCODE_BUFFER m_resHuCPakAggregatedFrameStatsBuffer; 1224 CODECHAL_ENCODE_BUFFER m_tileRecordBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC]; 1225 HEVC_TILE_STATS_INFO m_hevcTileStatsOffset = {}; //!< Page aligned offsets used to program HCP / VDEnc pipe and HuC PAK Integration kernel input 1226 HEVC_TILE_STATS_INFO m_hevcFrameStatsOffset = {}; //!< Page aligned offsets used to program HuC PAK Integration kernel output, HuC BRC kernel input 1227 HEVC_TILE_STATS_INFO m_hevcStatsSize = {}; //!< HEVC Statistics size 1228 bool m_enableTestMediaReset = 0; //!< enable media reset test. driver will send cmd to make hang happens 1229 bool m_forceScalability = false; //!< force scalability for resolution < 4K if other checking for scalability passed 1230 bool m_enableFramePanicMode = true; //!< Flag to control frame panic feature 1231 1232 // HuC PAK stitch kernel 1233 bool m_hucPakStitchEnabled = false; //!< HuC PAK stitch enabled flag 1234 MOS_RESOURCE m_resHucPakStitchDmemBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][CODECHAL_DP_MAX_NUM_BRC_PASSES] = {}; //!< HuC Pak Integration Dmem data for each pass 1235 MOS_RESOURCE m_resBrcDataBuffer = {}; //!< Resource of bitrate control data buffer 1236 MOS_RESOURCE m_resHucStitchDataBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][CODECHAL_HEVC_MAX_NUM_BRC_PASSES] = {}; // data buffer for huc input cmd generation 1237 MHW_BATCH_BUFFER m_HucStitchCmdBatchBuffer = {}; //!< SLB for huc stitch cmd 1238 1239 // BRC panic mode 1240 struct SkipFrameInfo 1241 { 1242 uint32_t numSlices = 0; 1243 MOS_RESOURCE m_resMbCodeSkipFrameSurface; //!< PAK obj and CU records 1244 } 1245 m_skipFrameInfo; 1246 1247 // virtual engine 1248 // virtual engine 1249 bool m_useVirtualEngine = false; //!< Virtual engine enable flag 1250 MOS_COMMAND_BUFFER m_veBatchBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC][CODECHAL_HEVC_MAX_NUM_HCP_PIPE][CODECHAL_HEVC_MAX_NUM_BRC_PASSES]; //!< Virtual engine batch buffers 1251 MOS_COMMAND_BUFFER m_realCmdBuffer; //!< Virtual engine command buffer 1252 uint32_t m_sizeOfVeBatchBuffer = 0; //!< Virtual engine batch buffer size 1253 unsigned char m_virtualEngineBbIndex = 0; //!< Virtual engine batch buffer index 1254 CODECHAL_ENCODE_BUFFER m_resBrcSemaphoreMem[CODECHAL_HEVC_MAX_NUM_HCP_PIPE]; //!< BRC HW semaphore 1255 CODECHAL_ENCODE_BUFFER m_resBrcPakSemaphoreMem; //!< BRC PAK HW semaphore 1256 MOS_RESOURCE m_resPipeStartSemaMem; //!< HW semaphore for scalability pipe start at the same time 1257 MOS_RESOURCE m_resPipeCompleteSemaMem; 1258 MOS_RESOURCE m_resDelayMinus = {}; 1259 uint32_t m_numDelay = 0; 1260 1261 1262 // the following constant integers and tables are from the kernel for score board computation 1263 static uint32_t const m_ct = 3; 1264 static uint32_t const m_maxNumDependency = 32; 1265 static uint32_t const m_numDependencyHorizontal = 1; 1266 static uint32_t const m_numDependencyVertical = 1; 1267 static uint32_t const m_numDependency45Degree = 2; 1268 static uint32_t const m_numDependency26Degree = 3; 1269 static uint32_t const m_numDependency45xDegree = 3 + (m_ct - 1); 1270 static uint32_t const m_numDependency26xDegree = 4 + (m_ct - 1); 1271 static uint32_t const m_numDependency45xDegreeAlt = 2; 1272 static uint32_t const m_numDependency26xDegreeAlt = 3; 1273 static uint32_t const m_numDependency45xVp9Degree = 4; 1274 static uint32_t const m_numDependency26zDegree = 5; 1275 static uint32_t const m_numDependency26ZigDegree = 6; 1276 static uint32_t const m_numDependencyNone = 0; 1277 static uint32_t const m_numDependencyCustom = 0; 1278 static const char m_dxWavefrontHorizontal[m_maxNumDependency]; 1279 static const char m_dyWavefrontHorizontal[m_maxNumDependency]; 1280 static const char m_dxWavefrontVertical[m_maxNumDependency]; 1281 static const char m_dyWavefrontVertical[m_maxNumDependency]; 1282 static const char m_dxWavefront45Degree[m_maxNumDependency]; 1283 static const char m_dyWavefront45Degree[m_maxNumDependency]; 1284 static const char m_dxWavefront26Degree[m_maxNumDependency]; 1285 static const char m_dyWavefront26Degree[m_maxNumDependency]; 1286 static const char m_dxWavefront45xDegree[m_maxNumDependency]; 1287 static const char m_dyWavefront45xDegree[m_maxNumDependency]; 1288 static const char m_dxWavefront26xDegree[m_maxNumDependency]; 1289 static const char m_dyWavefront26xDegree[m_maxNumDependency]; 1290 static const char m_dxWavefront45xDegreeAlt[m_maxNumDependency]; 1291 static const char m_dyWavefront45xDegreeAlt[m_maxNumDependency]; 1292 static const char m_dxWavefront26xDegreeAlt[m_maxNumDependency]; 1293 static const char m_dyWavefront26xDegreeAlt[m_maxNumDependency]; 1294 static const char m_dxWavefront45xVp9Degree[m_maxNumDependency]; 1295 static const char m_dyWavefront45xVp9Degree[m_maxNumDependency]; 1296 static const char m_dxWavefront26zDegree[m_maxNumDependency]; 1297 static const char m_dyWavefront26zDegree[m_maxNumDependency]; 1298 static const char m_dxWavefront26ZigDegree[m_maxNumDependency]; 1299 static const char m_dyWavefront26ZigDegree[m_maxNumDependency]; 1300 static const char m_dxWavefrontNone[m_maxNumDependency]; 1301 static const char m_dyWavefrontNone[m_maxNumDependency]; 1302 static const char m_dxWavefrontCustom[m_maxNumDependency]; 1303 static const char m_dyWavefrontCustom[m_maxNumDependency]; 1304 1305 //! 1306 //! \brief Constructor 1307 //! 1308 CodechalEncHevcStateG12(CodechalHwInterface* hwInterface, 1309 CodechalDebugInterface* debugInterface, 1310 PCODECHAL_STANDARD_INFO standardInfo); 1311 1312 //! 1313 //! \brief Copy constructor 1314 //! 1315 CodechalEncHevcStateG12(const CodechalEncHevcStateG12&) = delete; 1316 1317 //! 1318 //! \brief Copy assignment operator 1319 //! 1320 CodechalEncHevcStateG12& operator=(const CodechalEncHevcStateG12&) = delete; 1321 1322 //! 1323 //! \brief Destructor 1324 //! 1325 virtual ~CodechalEncHevcStateG12(); 1326 1327 //! 1328 //! \brief Entry to allocate and intialize the encode instance 1329 //! \param [in] codecHalSettings 1330 //! The settings to inialize the encode instance 1331 //! \return MOS_STATUS 1332 //! MOS_STATUS_SUCCESS if success, else fail reason 1333 //! 1334 MOS_STATUS Allocate(CodechalSetting * codecHalSettings) override; 1335 1336 1337 //! 1338 //! \brief Help function to get current pipe 1339 //! 1340 //! \return Current pipe value 1341 //! GetCurrentPipe()1342 int GetCurrentPipe() 1343 { 1344 if (m_numPipe <= 1) 1345 { 1346 return 0; 1347 } 1348 1349 return (int)(m_currPass) % (int)m_numPipe; 1350 } 1351 1352 //! 1353 //! \brief Help function to get current PAK pass 1354 //! 1355 //! \return Current PAK pass 1356 //! GetCurrentPass()1357 int GetCurrentPass() override 1358 { 1359 if (m_numPipe <= 1) 1360 { 1361 return m_currPass; 1362 } 1363 1364 return (int)(m_currPass) / (int)m_numPipe; 1365 } 1366 1367 //! 1368 //! \brief Help function to check if current pipe is first pipe 1369 //! 1370 //! \return True if current pipe is first pipe, otherwise return false 1371 //! IsFirstPipe()1372 bool IsFirstPipe() 1373 { 1374 return GetCurrentPipe() == 0 ? true : false; 1375 } 1376 1377 //! 1378 //! \brief Help function to check if current pipe is last pipe 1379 //! 1380 //! \return True if current pipe is last pipe, otherwise return false 1381 //! IsLastPipe()1382 bool IsLastPipe() 1383 { 1384 return GetCurrentPipe() == m_numPipe - 1 ? true : false; 1385 } 1386 1387 //! 1388 //! \brief Help function to check if current PAK pass is first pass 1389 //! 1390 //! \return True if current PAK pass is first pass, otherwise return false 1391 //! IsFirstPass()1392 bool IsFirstPass() override 1393 { 1394 return GetCurrentPass() == 0 ? true : false; 1395 } 1396 1397 //! 1398 //! \brief Help function to check if current PAK pass is last pass 1399 //! 1400 //! \return True if current PAK pass is last pass, otherwise return false 1401 //! IsLastPass()1402 bool IsLastPass() override 1403 { 1404 return GetCurrentPass() == m_numPassesInOnePipe ? true : false; 1405 } 1406 1407 //! 1408 //! \brief Help function to check if current PAK pass is the panic mode pass 1409 //! 1410 //! \return True if current PAK pass is the panic mode pass, otherwise return false 1411 //! IsPanicModePass()1412 bool IsPanicModePass() 1413 { 1414 return GetCurrentPass() == CODECHAL_HEVC_MAX_NUM_BRC_PASSES ? true : false; 1415 } 1416 1417 // inherited virtual functions 1418 MOS_STATUS SetPictureStructs() override; 1419 1420 MOS_STATUS CalcScaledDimensions() override; 1421 1422 MOS_STATUS InitializePicture(const EncoderParams& params) override; 1423 1424 MOS_STATUS ExecutePictureLevel() override; 1425 1426 MOS_STATUS ExecuteSliceLevel() override; 1427 1428 MOS_STATUS Initialize(CodechalSetting * settings) override; 1429 1430 virtual MOS_STATUS InitKernelState() override; 1431 1432 virtual uint32_t GetMaxBtCount() override; 1433 1434 bool CheckSupportedFormat(PMOS_SURFACE surface) override; 1435 1436 MOS_STATUS EncodeKernelFunctions() override; 1437 1438 MOS_STATUS EncodeMeKernel() override; 1439 1440 virtual MOS_STATUS EncodeIntraDistKernel(); 1441 1442 virtual MOS_STATUS AllocateEncResources() override; 1443 1444 virtual MOS_STATUS FreeEncResources() override; 1445 1446 MOS_STATUS AllocatePakResources() override; 1447 1448 MOS_STATUS FreePakResources() override; 1449 1450 virtual MOS_STATUS GetFrameBrcLevel() override; 1451 1452 void CreateMhwParams() override; 1453 1454 void GetMaxRefFrames(uint8_t& maxNumRef0, uint8_t& maxNumRef1) override; 1455 1456 void SetHcpSliceStateCommonParams(MHW_VDBOX_HEVC_SLICE_STATE& sliceStateParams) override; 1457 1458 MOS_STATUS PlatformCapabilityCheck() override; 1459 1460 MOS_STATUS GetStatusReport( 1461 EncodeStatus *encodeStatus, 1462 EncodeStatusReport *encodeStatusReport) override; 1463 MOS_STATUS SetRegionsHuCPakIntegrate(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams); 1464 MOS_STATUS SetDmemHuCPakIntegrate(PMHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams); 1465 MOS_STATUS SetRegionsHuCPakIntegrateCqp(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams); 1466 MOS_STATUS SetDmemHuCPakIntegrateCqp(PMHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams); 1467 MOS_STATUS ReadBrcPakStatisticsForScalability(PMOS_COMMAND_BUFFER cmdBuffer); 1468 #if (_DEBUG || _RELEASE_INTERNAL) 1469 MOS_STATUS ResetImgCtrlRegInPAKStatisticsBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 1470 #endif 1471 1472 MOS_STATUS GetCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer) override; 1473 1474 MOS_STATUS ReturnCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer) override; 1475 1476 MOS_STATUS SubmitCommandBuffer( 1477 PMOS_COMMAND_BUFFER cmdBuffer, 1478 bool bNullRendering) override; 1479 1480 MOS_STATUS SetSliceStructs() override; 1481 1482 MOS_STATUS AllocateTileStatistics(); 1483 1484 void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams) override; 1485 void SetHcpPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams) override; 1486 void SetHcpPicStateParams(MHW_VDBOX_HEVC_PIC_STATE& picStateParams) override; 1487 1488 MOS_STATUS ReadSseStatistics(PMOS_COMMAND_BUFFER cmdBuffer) override; 1489 1490 MOS_STATUS SetGpuCtxCreatOption() override; 1491 1492 //! 1493 //! \brief Decide number of pipes used for encoding 1494 //! \details called inside PlatformCapabilityCheck 1495 //! 1496 //! \return MOS_STATUS 1497 //! MOS_STATUS_SUCCESS if success, else fail reason 1498 //! 1499 MOS_STATUS DecideEncodingPipeNumber(); 1500 1501 //! 1502 //! \brief Get U62 Mode bits 1503 //! 1504 //! \return 8 bit mode cost for RDE 1505 //! GetU62ModeBits(float mcost)1506 inline uint8_t GetU62ModeBits(float mcost) 1507 { 1508 return (uint8_t)(mcost * 4 + 0.5); 1509 } 1510 1511 //! 1512 //! \brief Update surface info for YUY2 input 1513 //! 1514 //! \param [in] surface 1515 //! Reference to input surface 1516 //! \param [in] is10Bit 1517 //! Flag to indicate if 10 bit 1518 //! 1519 //! \return MOS_STATUS 1520 //! MOS_STATUS_SUCCESS if success, else fail reason 1521 //! 1522 MOS_STATUS UpdateYUY2SurfaceInfo( 1523 MOS_SURFACE& surface, 1524 bool is10Bit); 1525 1526 //! 1527 //! \brief Allocate ME resources 1528 //! 1529 //! \return MOS_STATUS 1530 //! MOS_STATUS_SUCCESS if success, else fail reason 1531 //! 1532 MOS_STATUS AllocateMeResources(); 1533 1534 //! 1535 //! \brief Free ME resources 1536 //! 1537 //! \return MOS_STATUS 1538 //! MOS_STATUS_SUCCESS if success, else fail reason 1539 //! 1540 MOS_STATUS FreeMeResources(); 1541 1542 //! 1543 //! \brief Encode command at tile level 1544 //! 1545 //! \return MOS_STATUS 1546 //! MOS_STATUS_SUCCESS if success, else fail reason 1547 //! 1548 MOS_STATUS EncTileLevel(); 1549 1550 //! 1551 //! \brief Get encoder kernel header and kernel size 1552 //! 1553 //! \param [in] binary 1554 //! Pointer to kernel binary 1555 //! \param [in] operation 1556 //! Enc kernel operation 1557 //! \param [in] krnStateIdx 1558 //! Kernel state index 1559 //! \param [out] krnHeader 1560 //! Pointer to kernel header 1561 //! \param [out] krnSize 1562 //! Pointer to kernel size 1563 //! 1564 //! \return MOS_STATUS 1565 //! MOS_STATUS_SUCCESS if success, else fail reason 1566 //! 1567 static MOS_STATUS GetKernelHeaderAndSize( 1568 void* binary, 1569 EncOperation operation, 1570 uint32_t krnStateIdx, 1571 void* krnHeader, 1572 uint32_t* krnSize); 1573 1574 //! 1575 //! \brief Get encoder kernel header and kernel size 1576 //! 1577 //! \param [in] encOperation 1578 //! Specifies the media function type 1579 //! \param [in] kernelParams 1580 //! Pointer to kernel parameters 1581 //! \param [in] idx 1582 //! MbEnc/BRC kernel index 1583 //! 1584 //! \return MOS_STATUS 1585 //! MOS_STATUS_SUCCESS if success, else fail reason 1586 //! 1587 MOS_STATUS SetKernelParams( 1588 EncOperation encOperation, 1589 MHW_KERNEL_PARAM* kernelParams, 1590 uint32_t idx); 1591 1592 //! 1593 //! \brief Set Binding table for different kernelsge 1594 //! 1595 //! \param [in] encOperation 1596 //! Specifies the media function type 1597 //! \param [in] hevcEncBindingTable 1598 //! Pointer to the binding table 1599 //! \param [in] idx 1600 //! MbEnc/BRC kernel index 1601 //! 1602 //! \return MOS_STATUS 1603 //! MOS_STATUS_SUCCESS if success, else fail reason 1604 //! 1605 MOS_STATUS SetBindingTable( 1606 EncOperation encOperation, 1607 PCODECHAL_ENCODE_BINDING_TABLE_GENERIC hevcEncBindingTable, 1608 uint32_t idx); 1609 1610 //! 1611 //! \brief Initialize MbEnc kernel state 1612 //! 1613 //! \return MOS_STATUS 1614 //! MOS_STATUS_SUCCESS if success, else fail reason 1615 //! 1616 MOS_STATUS InitKernelStateMbEnc(); 1617 1618 //! 1619 //! \brief Initialize BRC kernel state 1620 //! 1621 //! \return MOS_STATUS 1622 //! MOS_STATUS_SUCCESS if success, else fail reason 1623 //! 1624 virtual MOS_STATUS InitKernelStateBrc(); 1625 1626 //! 1627 //! \brief Invoke BRC Init/Reset kernel 1628 //! 1629 //! \return MOS_STATUS 1630 //! MOS_STATUS_SUCCESS if success, else fail reason 1631 //! 1632 virtual MOS_STATUS EncodeBrcInitResetKernel(); 1633 1634 //! 1635 //! \brief Send surfaces BRC Init/Reset kernel 1636 //! 1637 //! \param [in] cmdBuffer 1638 //! Pointer to command buffer 1639 //! \param [in] krnIdx 1640 //! Index of the BRC kernel for which surfaces are being sent 1641 //! \return MOS_STATUS 1642 //! MOS_STATUS_SUCCESS if success, else fail reason 1643 //! 1644 MOS_STATUS SendBrcInitResetSurfaces( 1645 PMOS_COMMAND_BUFFER cmdBuffer, 1646 CODECHAL_HEVC_BRC_KRNIDX krnIdx); 1647 1648 //! 1649 //! \brief Setup Curbe for BRC Init/Reset kernel 1650 //! 1651 //! \param [in] brcKrnIdx 1652 //! Index of the BRC kernel for which Curbe is setup 1653 //! \return MOS_STATUS 1654 //! MOS_STATUS_SUCCESS if success, else fail reason 1655 //! 1656 MOS_STATUS SetCurbeBrcInitReset(CODECHAL_HEVC_BRC_KRNIDX brcKrnIdx); 1657 1658 //! 1659 //! \brief Invoke frame level BRC update kernel 1660 //! 1661 //! \return MOS_STATUS 1662 //! MOS_STATUS_SUCCESS if success, else fail reason 1663 //! 1664 virtual MOS_STATUS EncodeBrcFrameUpdateKernel(); 1665 1666 //! 1667 //! \brief Send surfaces for BRC Frame Update kernel 1668 //! 1669 //! \param [in] cmdBuffer 1670 //! Pointer to command buffer 1671 //! \return MOS_STATUS 1672 //! MOS_STATUS_SUCCESS if success, else fail reason 1673 //! 1674 MOS_STATUS SendBrcFrameUpdateSurfaces(PMOS_COMMAND_BUFFER cmdBuffer); 1675 1676 //! 1677 //! \brief Setup Curbe for BRC Update kernel 1678 //! 1679 //! \param [in] brcKrnIdx 1680 //! Index of the BRC update kernel(frame or lcu) for which Curbe is setup 1681 //! \return MOS_STATUS 1682 //! MOS_STATUS_SUCCESS if success, else fail reason 1683 //! 1684 MOS_STATUS SetCurbeBrcUpdate(CODECHAL_HEVC_BRC_KRNIDX brcKrnIdx); 1685 1686 //! 1687 //! \brief Invoke LCU level BRC update kernel 1688 //! 1689 //! \return MOS_STATUS 1690 //! MOS_STATUS_SUCCESS if success, else fail reason 1691 //! 1692 virtual MOS_STATUS EncodeBrcLcuUpdateKernel(); 1693 1694 //! 1695 //! \brief Send surfaces for BRC LCU Update kernel 1696 //! 1697 //! \param [in] cmdBuffer 1698 //! Pointer to command buffer 1699 //! \return MOS_STATUS 1700 //! MOS_STATUS_SUCCESS if success, else fail reason 1701 //! 1702 virtual MOS_STATUS SendBrcLcuUpdateSurfaces(PMOS_COMMAND_BUFFER cmdBuffer); 1703 1704 //! 1705 //! \brief Top level function for invoking MBenc kernel 1706 //! \details I, B or LCU64_B MBEnc kernel, based on EncFunctionType 1707 //! \param [in] encFunctionType 1708 //! Specifies the media state type 1709 //! \return MOS_STATUS 1710 //! MOS_STATUS_SUCCESS if success, else fail reason 1711 //! 1712 virtual MOS_STATUS EncodeMbEncKernel(CODECHAL_MEDIA_STATE_TYPE encFunctionType); 1713 1714 //! 1715 //! \brief Send Surfaces for MbEnc I kernel 1716 //! 1717 //! \param [in] cmdBuffer 1718 //! Pointer to command buffer 1719 //! 1720 //! \return MOS_STATUS 1721 //! MOS_STATUS_SUCCESS if success, else fail reason 1722 //! 1723 MOS_STATUS SendMbEncSurfacesIKernel(PMOS_COMMAND_BUFFER cmdBuffer); 1724 1725 //! 1726 //! \brief Setup Curbe for MbEnc I kernel 1727 //! 1728 //! \return MOS_STATUS 1729 //! MOS_STATUS_SUCCESS if success, else fail reason 1730 //! 1731 MOS_STATUS SetCurbeMbEncIKernel(); 1732 1733 //! 1734 //! \brief Send Surfaces for MbEnc B kernel 1735 //! 1736 //! \param [in] cmdBuffer 1737 //! Pointer to command buffer 1738 //! 1739 //! \return MOS_STATUS 1740 //! MOS_STATUS_SUCCESS if success, else fail reason 1741 //! 1742 MOS_STATUS SendMbEncSurfacesBKernel(PMOS_COMMAND_BUFFER cmdBuffer); 1743 1744 //! 1745 //! \brief Setup Curbe for MbEnc B LCU32 and LCU64_32 Kernels 1746 //! 1747 //! \return MOS_STATUS 1748 //! MOS_STATUS_SUCCESS if success, else fail reason 1749 //! 1750 MOS_STATUS SetCurbeMbEncBKernel(); 1751 1752 //! 1753 //! \brief Generate LCU Level Data 1754 //! 1755 //! \param [in] lcuLevelInputDataSurfaceParam 1756 //! input lcu surface 1757 //! \return MOS_STATUS 1758 //! MOS_STATUS_SUCCESS if success, else fail reason 1759 //! 1760 MOS_STATUS GenerateLcuLevelData(MOS_SURFACE &lcuLevelInputDataSurfaceParam); 1761 1762 //! 1763 //! \brief Generate 'Skip frame' mbCodeSurface 1764 //! 1765 //! \param [in] skipframeInfo 1766 //! skip frame surface 1767 //! \return MOS_STATUS 1768 //! MOS_STATUS_SUCCESS if success, else fail reason 1769 //! 1770 MOS_STATUS GenerateSkipFrameMbCodeSurface(SkipFrameInfo &skipframeInfo); 1771 1772 //! 1773 //! \brief Load cost table 1774 //! 1775 //! \param [in] sliceType 1776 //! Slice Type 1777 //! \param [in] qp 1778 //! QP value 1779 //! 1780 //! \return void 1781 //! 1782 void LoadCosts(uint8_t sliceType, uint8_t qp); 1783 1784 //! 1785 //! \brief Prepare walker params for custom pattern thread dispatch 1786 //! 1787 //! \param [in] walkerParams 1788 //! Pointer to HW walker params 1789 //! \param [in] walkerCodecParams 1790 //! Input params to program the HW walker 1791 //! 1792 //! \return MOS_STATUS 1793 //! MOS_STATUS_SUCCESS if success, else fail reason 1794 //! 1795 MOS_STATUS GetCustomDispatchPattern( 1796 PMHW_WALKER_PARAMS walkerParams, 1797 PCODECHAL_WALKER_CODEC_PARAMS walkerCodecParams); 1798 1799 //! 1800 //! \brief Generate concurrent thread group data 1801 //! 1802 //! \param [in] concurrentThreadGroupData 1803 //! reference to the concurrentThreadGroupData surface 1804 //! \return MOS_STATUS 1805 //! MOS_STATUS_SUCCESS if success, else fail reason 1806 //! 1807 MOS_STATUS GenerateConcurrentThreadGroupData(MOS_RESOURCE & concurrentThreadGroupData); 1808 1809 //! 1810 //! \brief Load Pak command and CuRecord from file 1811 //! 1812 //! \return MOS_STATUS 1813 //! MOS_STATUS_SUCCESS if success, else fail reason 1814 //! 1815 MOS_STATUS LoadPakCommandAndCuRecordFromFile(); 1816 1817 //! 1818 //! \brief Load source surface and 2xDownScaled references from file 1819 //! 1820 //! \param [in] pRef2xSurface 1821 //! reference surface to be dumped 1822 //! \param [in] pSrc2xSurface 1823 //! source surface to be dumped 1824 //! \param [in] reflist 1825 //! ref list, l0 or l1 1826 //! \param [in] refIdx 1827 //! ref index to the ref list 1828 //! \return MOS_STATUS 1829 //! MOS_STATUS_SUCCESS if success, else fail reason 1830 //! 1831 MOS_STATUS LoadSourceAndRef2xDSFromFile(PMOS_SURFACE pRef2xSurface, PMOS_SURFACE pSrc2xSurface, uint8_t reflist, uint8_t refIdx); 1832 1833 //! 1834 //! \brief Re-calculate buffer size and offets during resolution reset 1835 //! 1836 //! \return void 1837 //! 1838 void ResizeBufferOffset(); 1839 1840 //! 1841 //! \brief Set HCP_SLICE_STATE parameters that are different at slice level 1842 //! 1843 //! \param [in, out] sliceState 1844 //! HCP_SLICE_STATE parameters 1845 //! \param [in] slcData 1846 //! Pointer to CODEC_ENCODE_SLCDATA 1847 //! \param [in] slcCount 1848 //! Current slice index 1849 //! \param [in] tileCodingParams 1850 //! Pointer to TileCodingParams 1851 //! \param [in] lastSliceInTile 1852 //! Flag to indicate if slice is the last one in the tile 1853 //! \param [in] idx 1854 //! Index of the tile 1855 //! 1856 //! \return void 1857 //! 1858 void SetHcpSliceStateParams( 1859 MHW_VDBOX_HEVC_SLICE_STATE& sliceState, 1860 PCODEC_ENCODER_SLCDATA slcData, 1861 uint16_t slcCount, 1862 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 tileCodingParams, 1863 bool lastSliceInTile, 1864 uint32_t idx); 1865 1866 //! 1867 //! \brief Set MFX_VIDEO_COPY commands for HW stitch in scalable mode 1868 //! 1869 //! \param [in] cmdBuffer 1870 //! Pointer to the command buffer 1871 //! 1872 //! \return MOS_STATUS 1873 //! MOS_STATUS_SUCCESS if success, else fail reason 1874 //! 1875 MOS_STATUS SetMfxVideoCopyCmdParams( 1876 PMOS_COMMAND_BUFFER cmdBuffer); 1877 1878 //! 1879 //! \brief Setup BRC constant data 1880 //! 1881 //! \param [in, out] brcConstantData 1882 //! Pointer to BRC constant data surface 1883 //! 1884 //! \return MOS_STATUS 1885 //! MOS_STATUS_SUCCESS if success, else fail reason 1886 //! 1887 MOS_STATUS SetupBrcConstantTable(PMOS_SURFACE brcConstantData); 1888 1889 //! 1890 //! \brief Check whether Scalability is enabled or not, 1891 //! Set number of VDBoxes accordingly 1892 //! 1893 //! \return MOS_STATUS 1894 //! MOS_STATUS_SUCCESS if success, else fail reason 1895 //! 1896 MOS_STATUS GetSystemPipeNumberCommon(); 1897 1898 //! 1899 //! \brief Set And Populate VE Hint parameters 1900 //! \details Set Virtual Engine hint parameter and populate it to primary cmd buffer attributes 1901 //! \param [in] cmdBuffer 1902 //! Pointer to primary cmd buffer 1903 //! \return MOS_STATUS 1904 //! MOS_STATUS_SUCCESS if success, else fail reason 1905 //! 1906 MOS_STATUS SetAndPopulateVEHintParams( 1907 PMOS_COMMAND_BUFFER cmdBuffer); 1908 1909 bool IsDegree45Needed(); 1910 1911 virtual void DecideConcurrentGroupAndWaveFrontNumber(); 1912 virtual void InitSwScoreBoardParams(CodechalEncodeSwScoreboard::KernelParams & swScoreboardKernelParames); 1913 1914 MOS_STATUS UserFeatureKeyReport() override; 1915 1916 MOS_STATUS SetupSwScoreBoard(CodechalEncodeSwScoreboard::KernelParams *params); 1917 void InitSWScoreboard( 1918 uint8_t* scoreboard, 1919 uint32_t scoreboardWidth, 1920 uint32_t scoreboardHeight, 1921 uint32_t dependencyPattern, 1922 char childThreadNumber); 1923 1924 uint8_t PicCodingTypeToSliceType(uint16_t pictureCodingType); 1925 1926 MOS_STATUS InitMediaObjectWalker( 1927 uint32_t threadSpaceWidth, 1928 uint32_t threadSpaceHeight, 1929 uint32_t colorCountMinusOne, 1930 DependencyPattern dependencyPattern, 1931 uint32_t childThreadNumber, 1932 uint32_t localLoopExecCount, 1933 MHW_WALKER_PARAMS& walkerParams); 1934 1935 void SetDependency(uint8_t &numDependencies, 1936 char* scoreboardDeltaX, 1937 char* scoreboardDeltaY, 1938 uint32_t dependencyPattern, 1939 char childThreadNumber); 1940 1941 //! 1942 //! \brief Dump HuC based debug output buffers 1943 //! 1944 //! \return MOS_STATUS 1945 //! MOS_STATUS_SUCCESS if success, else fail reason 1946 //! 1947 MOS_STATUS DumpHucDebugOutputBuffers(); 1948 1949 void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams) override; 1950 MOS_STATUS AddHcpPipeModeSelectCmd(MOS_COMMAND_BUFFER* cmdBuffer) override; 1951 MOS_STATUS AddHcpSurfaceStateCmds(MOS_COMMAND_BUFFER* cmdBuffer) override; 1952 MOS_STATUS AddHcpPictureStateCmd(MOS_COMMAND_BUFFER* cmdBuffer) override; 1953 1954 MOS_STATUS CalculatePictureStateCommandSize() override; 1955 1956 MOS_STATUS AddHcpPipeBufAddrCmd( 1957 PMOS_COMMAND_BUFFER cmdBuffer) override; 1958 1959 //! 1960 //! \brief Is slice in the current tile 1961 //! 1962 //! \param [in] sliceNumber 1963 //! Slice number 1964 //! \param [in] currentTile 1965 //! Pointer to current tile coding params 1966 //! \param [out] sliceInTile 1967 //! Pointer to return if slice in tile 1968 //! \param [out] lastSliceInTile 1969 //! Pointer to return if last slice in tile 1970 //! 1971 //! \return MOS_STATUS 1972 //! MOS_STATUS_SUCCESS if success, else fail reason 1973 //! 1974 MOS_STATUS IsSliceInTile( 1975 uint32_t sliceNumber, 1976 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 currentTile, 1977 bool *sliceInTile, 1978 bool *lastSliceInTile); 1979 1980 //! 1981 //! \brief Set tile data 1982 //! 1983 //! \param [in] tileCodingParams 1984 //! Pointer to tile coding params 1985 //! \return MOS_STATUS 1986 //! MOS_STATUS_SUCCESS if success, else fail reason 1987 //! 1988 MOS_STATUS SetTileData(MHW_VDBOX_HCP_TILE_CODING_PARAMS_G12* tileCodingParams, uint32_t bistreamBufSize); 1989 1990 MOS_STATUS AddHcpRefIdxCmd( 1991 PMOS_COMMAND_BUFFER cmdBuffer, 1992 PMHW_BATCH_BUFFER batchBuffer, 1993 PMHW_VDBOX_HEVC_SLICE_STATE params) override; 1994 1995 //! 1996 //! \brief Help function to verify command buffer size 1997 //! 1998 //! \return MOS_STATUS 1999 //! MOS_STATUS_SUCCESS if success, else fail reason 2000 //! 2001 MOS_STATUS VerifyCommandBufferSize() override; 2002 2003 //! 2004 //! \brief Help function to send prolog with frame tracking information 2005 //! 2006 //! \param [in] cmdBuffer 2007 //! Pointer to command buffer 2008 //! \param [in] frameTrackingRequested 2009 //! True if frame tracking info is needed, false otherwise 2010 //! 2011 //! \return MOS_STATUS 2012 //! MOS_STATUS_SUCCESS if success, else fail reason 2013 //! 2014 virtual MOS_STATUS SendPrologWithFrameTracking( 2015 PMOS_COMMAND_BUFFER cmdBuffer, 2016 bool frameTrackingRequested, 2017 MHW_MI_MMIOREGISTERS *mmioRegister = nullptr) override; 2018 2019 //! 2020 //! \brief HuC PAK integrate 2021 //! 2022 //! \param [in] cmdBuffer 2023 //! Pointer to command buffer 2024 //! 2025 //! \return MOS_STATUS 2026 //! MOS_STATUS_SUCCESS if success, else fail reason 2027 //! 2028 MOS_STATUS HucPakIntegrate( 2029 PMOS_COMMAND_BUFFER cmdBuffer); 2030 2031 //! 2032 //! \brief Resize buffers due to resoluton change. 2033 //! \details Resize buffers due to resoluton change. 2034 //! 2035 //! \return void 2036 //! 2037 virtual void ResizeOnResChange() override; 2038 2039 MOS_STATUS InitMmcState() override; 2040 2041 MOS_STATUS UpdateCmdBufAttribute( 2042 PMOS_COMMAND_BUFFER cmdBuffer, 2043 bool renderEngineInUse) override; 2044 2045 //! 2046 //! \brief Configue stitch data buffer as Huc Pak Integration input 2047 //! 2048 //! \return MOS_STATUS 2049 //! MOS_STATUS_SUCCESS if success, else fail reason 2050 //! 2051 MOS_STATUS ConfigStitchDataBuffer(); 2052 2053 MOS_STATUS AddMediaVfeCmd( 2054 PMOS_COMMAND_BUFFER cmdBuffer, 2055 SendKernelCmdsParams *params) override; 2056 2057 //! 2058 //! \brief allocate resources with sizes varying from frame to frame 2059 //! \return MOS_STATUS 2060 //! MOS_STATUS_SUCCESS if success, else fail reason 2061 //! 2062 MOS_STATUS AllocateResourcesVariableSize(); 2063 2064 #if USE_CODECHAL_DEBUG_TOOL 2065 //! 2066 //! \brief Dump PAK output buffer 2067 //! 2068 //! \return MOS_STATUS 2069 //! MOS_STATUS_SUCCESS if success, else fail reason 2070 //! 2071 MOS_STATUS DumpPakOutput(); 2072 2073 MOS_STATUS DumpFrameStatsBuffer(CodechalDebugInterface *debugInterface) override; 2074 #endif 2075 2076 uint32_t CodecHalHevc_GetFileSize(char* fileName); 2077 }; 2078 2079 //! \brief typedef of class CodechalEncHevcStateG12* 2080 using PCODECHAL_ENC_HEVC_STATE_G12 = class CodechalEncHevcStateG12*; 2081 2082 #endif // __CODECHAL_ENCODE_HEVC_G12_H__ 2083