1 /* 2 * Copyright (c) 2015-2020, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi_g12_X.h 24 //! \brief Defines functions for constructing HW commands on Gen12-based platforms 25 //! 26 27 #ifndef __MHW_MI_G12_X_H__ 28 #define __MHW_MI_G12_X_H__ 29 30 #include "mhw_mi_generic.h" 31 #include "mhw_mi_hwcmd_g12_X.h" 32 #include "mhw_mmio_g12.h" 33 34 typedef struct _MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS : public _MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS 35 { 36 bool enableEndCurrentBatchBuffLevel; 37 uint32_t compareOperation; 38 enum PARAMS_TYPE 39 { 40 ENHANCED_PARAMS = 1 41 }; 42 } MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS, *PMHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS; 43 44 //! 45 //! \brief Gen12 MHW MI command interface 46 //! \details The Gen12 MHW MI interface contains functions to add Gen12 MI commands to command buffer or batch buffer 47 //! 48 struct MhwMiInterfaceG12 : public MhwMiInterfaceGeneric<mhw_mi_g12_X> 49 { MhwMiInterfaceG12MhwMiInterfaceG1250 MhwMiInterfaceG12( 51 MhwCpInterface *cpInterface, 52 PMOS_INTERFACE osInterface) : 53 MhwMiInterfaceGeneric(cpInterface, osInterface) 54 { 55 MHW_FUNCTION_ENTER; 56 InitMmioRegisters(); 57 } 58 ~MhwMiInterfaceG12MhwMiInterfaceG1259 ~MhwMiInterfaceG12() { MHW_FUNCTION_ENTER; }; 60 61 MOS_STATUS AddMiConditionalBatchBufferEndCmd( 62 PMOS_COMMAND_BUFFER cmdBuffer, 63 PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS params) override; 64 65 MOS_STATUS AddMiSetPredicateCmd( 66 PMOS_COMMAND_BUFFER cmdBuffer, 67 MHW_MI_SET_PREDICATE_ENABLE enableFlag) override; 68 69 MOS_STATUS AddMiBatchBufferStartCmd( 70 PMOS_COMMAND_BUFFER cmdBuffer, 71 PMHW_BATCH_BUFFER batchBuffer) override; 72 73 MOS_STATUS AddMiBatchBufferStartCmd( 74 PMOS_COMMAND_BUFFER cmdBuffer, 75 PMHW_BATCH_BUFFER batchBuffer, 76 bool useChainedBB = false); 77 78 MOS_STATUS AddMiStoreRegisterMemCmd( 79 PMOS_COMMAND_BUFFER cmdBuffer, 80 PMHW_MI_STORE_REGISTER_MEM_PARAMS params) override; 81 82 MOS_STATUS AddMiLoadRegisterMemCmd( 83 PMOS_COMMAND_BUFFER cmdBuffer, 84 PMHW_MI_STORE_REGISTER_MEM_PARAMS params) override; 85 86 MOS_STATUS AddMiLoadRegisterImmCmd( 87 PMOS_COMMAND_BUFFER cmdBuffer, 88 PMHW_MI_LOAD_REGISTER_IMM_PARAMS params) override; 89 90 MOS_STATUS AddMiLoadRegisterRegCmd( 91 PMOS_COMMAND_BUFFER cmdBuffer, 92 PMHW_MI_LOAD_REGISTER_REG_PARAMS params) override; 93 94 MOS_STATUS AddMiSemaphoreWaitCmd( 95 PMOS_COMMAND_BUFFER cmdBuffer, 96 PMHW_MI_SEMAPHORE_WAIT_PARAMS params) override; 97 98 MOS_STATUS AddMiForceWakeupCmd( 99 PMOS_COMMAND_BUFFER cmdBuffer, 100 PMHW_MI_FORCE_WAKEUP_PARAMS params) override; 101 102 MOS_STATUS AddPipeControl( 103 PMOS_COMMAND_BUFFER cmdBuffer, 104 PMHW_BATCH_BUFFER batchBuffer, 105 PMHW_PIPE_CONTROL_PARAMS params) override; 106 107 MOS_STATUS AddMediaStateFlush( 108 PMOS_COMMAND_BUFFER cmdBuffer, 109 PMHW_BATCH_BUFFER batchBuffer, 110 PMHW_MEDIA_STATE_FLUSH_PARAM params = nullptr) override; 111 112 MOS_STATUS SkipMiBatchBufferEndBb( 113 PMHW_BATCH_BUFFER batchBuffer) override; 114 115 MOS_STATUS AddMiFlushDwCmd( 116 PMOS_COMMAND_BUFFER cmdBuffer, 117 PMHW_MI_FLUSH_DW_PARAMS params) override; 118 119 //! 120 //! \brief Adds Mi Vd control state cmd in command buffer 121 //! 122 //! \param [in] cmdBuffer 123 //! Command buffer to which HW command is added 124 //! \param [in] params 125 //! Params structure used to populate the HW command 126 //! 127 //! \return MOS_STATUS 128 //! MOS_STATUS_SUCCESS if success, else fail reason 129 //! 130 MOS_STATUS AddMiVdControlStateCmd( 131 PMOS_COMMAND_BUFFER cmdBuffer, 132 PMHW_MI_VD_CONTROL_STATE_PARAMS params) override; 133 134 void InitMmioRegisters(); 135 136 MOS_STATUS SetWatchdogTimerThreshold( 137 uint32_t frameWidth, 138 uint32_t frameHeight, 139 bool isEncoder = true) override; 140 141 MOS_STATUS SetWatchdogTimerRegisterOffset( 142 MOS_GPU_CONTEXT gpuContext) override; 143 144 MOS_STATUS AddWatchdogTimerStartCmd( 145 PMOS_COMMAND_BUFFER cmdBuffer) override; 146 147 MOS_STATUS AddWatchdogTimerStopCmd( 148 PMOS_COMMAND_BUFFER cmdBuffer) override; 149 150 private: 151 // MMIO Range 0x1C0000 - 0x200000 is used for Media VDBox or VEBox 152 // Each media engine has a range from 0 to 0x3FFF for relative access 153 // 154 static const uint32_t m_mmioMaxRelativeOffset = M_MMIO_MAX_RELATIVE_OFFSET; //!< Max reg relative offset in an engine 155 static const uint32_t m_mmioMediaLowOffset = M_MMIO_MEDIA_LOW_OFFSET; //!< Low bound of VDBox and VEBox MMIO offset 156 static const uint32_t m_mmioMediaHighOffset = M_MMIO_MEDIA_HIGH_OFFSET; //!< High bound of VDBox and VEBox MMIO offset 157 158 //! 159 //! \brief Check and convert meida registers to relative offset 160 //! \details Check if an abusolute register offset is VDbox or VEBox register and convert it to relative if so 161 //! \param [in/out] reg 162 //! Register to be checked and converted 163 //! \return bool 164 //! Return true if it is VDBox or VEBox register 165 //! IsRelativeMMIOMhwMiInterfaceG12166 bool IsRelativeMMIO(uint32_t ®) 167 { 168 if (nullptr == m_osInterface) 169 { 170 MHW_ASSERTMESSAGE("invalid m_osInterface for RelativeMMIO"); 171 return false; 172 } 173 MOS_GPU_CONTEXT gpuContext = m_osInterface->pfnGetGpuContext(m_osInterface); 174 175 if ((MOS_VCS_ENGINE_USED(gpuContext) || MOS_VECS_ENGINE_USED(gpuContext)) && 176 (reg >= m_mmioMediaLowOffset && reg < m_mmioMediaHighOffset)) 177 { 178 reg &= m_mmioMaxRelativeOffset; 179 return true; 180 } 181 return false; 182 } 183 184 //! 185 //! \brief Check RCS and CCS remap offset 186 //! \details Check if a RCS register offset is set and remap it to RCS/CCS register offset if so. 187 //! \param [in] reg 188 //! Register to be checked and converted 189 //! \return bool 190 //! Return true if it is RCS register 191 //! IsRemappingMMIOMhwMiInterfaceG12192 bool IsRemappingMMIO(uint32_t ®) 193 { 194 if (nullptr == m_osInterface) 195 { 196 MHW_ASSERTMESSAGE("invalid m_osInterface for RemappingMMIO"); 197 return false; 198 } 199 MOS_GPU_CONTEXT gpuContext = m_osInterface->pfnGetGpuContext(m_osInterface); 200 201 if (MOS_RCS_ENGINE_USED(gpuContext) && 202 ((M_MMIO_RCS_HW_FE_REMAP_RANGE_BEGIN <= reg && reg <= M_MMIO_RCS_HW_FE_REMAP_RANGE_END) 203 ||(M_MMIO_RCS_AUX_TBL_REMAP_RANGE_BEGIN <= reg && reg <= M_MMIO_RCS_AUX_TBL_REMAP_RANGE_END) 204 ||(M_MMIO_RCS_TRTT_REMAP_RANGE_BEGIN <= reg && reg <= M_MMIO_RCS_TRTT_REMAP_RANGE_END) 205 ||(M_MMIO_CCS0_HW_FRONT_END_BASE_BEGIN <= reg && reg <= M_MMIO_CCS0_HW_FRONT_END_BASE_END) 206 ||(M_MMIO_CCS1_HW_FRONT_END_BASE_BEGIN <= reg && reg <= M_MMIO_CCS1_HW_FRONT_END_BASE_END) 207 ||(M_MMIO_CCS2_HW_FRONT_END_BASE_BEGIN <= reg && reg <= M_MMIO_CCS2_HW_FRONT_END_BASE_END) 208 ||(M_MMIO_CCS3_HW_FRONT_END_BASE_BEGIN <= reg && reg <= M_MMIO_CCS3_HW_FRONT_END_BASE_END))) 209 { 210 return true; 211 } 212 else 213 { 214 return false; 215 } 216 } 217 218 public: 219 static const uint32_t m_mmioRcsAuxTableBaseLow = M_MMIO_RCS_AUX_TABLE_BASE_LOW; 220 static const uint32_t m_mmioRcsAuxTableBaseHigh = M_MMIO_RCS_AUX_TABLE_BASE_HIGH; 221 static const uint32_t m_mmioRcsAuxTableInvalidate = M_MMIO_RCS_AUX_TABLE_INVALIDATE; 222 static const uint32_t m_mmioVd0AuxTableBaseLow = M_MMIO_VD0_AUX_TABLE_BASE_LOW; 223 static const uint32_t m_mmioVd0AuxTableBaseHigh = M_MMIO_VD0_AUX_TABLE_BASE_HIGH; 224 static const uint32_t m_mmioVd0AuxTableInvalidate = M_MMIO_VD0_AUX_TABLE_INVALIDATE; 225 static const uint32_t m_mmioVd1AuxTableBaseLow = M_MMIO_VD1_AUX_TABLE_BASE_LOW; 226 static const uint32_t m_mmioVd1AuxTableBaseHigh = M_MMIO_VD1_AUX_TABLE_BASE_HIGH; 227 static const uint32_t m_mmioVd1AuxTableInvalidate = M_MMIO_VD1_AUX_TABLE_INVALIDATE; 228 static const uint32_t m_mmioVd2AuxTableBaseLow = M_MMIO_VD2_AUX_TABLE_BASE_LOW; 229 static const uint32_t m_mmioVd2AuxTableBaseHigh = M_MMIO_VD2_AUX_TABLE_BASE_HIGH; 230 static const uint32_t m_mmioVd2AuxTableInvalidate = M_MMIO_VD2_AUX_TABLE_INVALIDATE; 231 static const uint32_t m_mmioVd3AuxTableBaseLow = M_MMIO_VD3_AUX_TABLE_BASE_LOW; 232 static const uint32_t m_mmioVd3AuxTableBaseHigh = M_MMIO_VD3_AUX_TABLE_BASE_HIGH; 233 static const uint32_t m_mmioVd3AuxTableInvalidate = M_MMIO_VD3_AUX_TABLE_INVALIDATE; 234 static const uint32_t m_mmioVe0AuxTableBaseLow = M_MMIO_VE0_AUX_TABLE_BASE_LOW; 235 static const uint32_t m_mmioVe0AuxTableBaseHigh = M_MMIO_VE0_AUX_TABLE_BASE_HIGH; 236 static const uint32_t m_mmioVe0AuxTableInvalidate = M_MMIO_VE0_AUX_TABLE_INVALIDATE; 237 static const uint32_t m_mmioVe1AuxTableBaseLow = M_MMIO_VE1_AUX_TABLE_BASE_LOW; 238 static const uint32_t m_mmioVe1AuxTableBaseHigh = M_MMIO_VE1_AUX_TABLE_BASE_HIGH; 239 static const uint32_t m_mmioVe1AuxTableInvalidate = M_MMIO_VE1_AUX_TABLE_INVALIDATE; 240 static const uint32_t m_mmioCcs0AuxTableBaseLow = M_MMIO_CCS0_AUX_TABLE_BASE_LOW; 241 static const uint32_t m_mmioCcs0AuxTableBaseHigh = M_MMIO_CCS0_AUX_TABLE_BASE_HIGH; 242 static const uint32_t m_mmioCcs0AuxTableInvalidate = M_MMIO_CCS0_AUX_TABLE_INVALIDATE; 243 }; 244 #endif 245