1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_encode_hevc_g11.h 24 //! \brief HEVC dual-pipe encoder for GEN11 platform. 25 //! 26 27 #ifndef __CODECHAL_ENCODE_HEVC_G11_H__ 28 #define __CODECHAL_ENCODE_HEVC_G11_H__ 29 30 #include "codechal_encode_hevc.h" 31 #include "codechal_kernel_intra_dist.h" 32 #include "codechal_encode_sw_scoreboard_g11.h" 33 #include "mhw_vdbox_vdenc_g11_X.h" 34 #include "codechal_encode_singlepipe_virtualengine.h" 35 #include "codechal_encode_scalability.h" 36 37 #define VDBOX_HUC_PAK_INTEGRATION_KERNEL_DESCRIPTOR 15 38 #define HEVC_BRC_HISTORY_BUFFER_SIZE_G11 (1088) 39 #define HEVC_BRC_LONG_TERM_REFRENCE_FLAG 0x8000 40 41 //! 42 //! \struct HucPakStitchDmemEncG11 43 //! \brief The struct of Huc Com Dmem 44 //! 45 struct HucPakStitchDmemEncG11 46 { 47 uint32_t TileSizeRecord_offset[5]; // Tile Size Records, start offset in byte, 0xffffffff means unavailable 48 uint32_t VDENCSTAT_offset[5]; // needed for HEVC VDEnc, VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 49 uint32_t HEVC_PAKSTAT_offset[5]; //needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 50 uint32_t HEVC_Streamout_offset[5]; //needed for HEVC VDEnc, start offset in byte, 0xffffffff means unavailable 51 uint32_t VP9_PAK_STAT_offset[5]; //needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 52 uint32_t Vp9CounterBuffer_offset[5]; //needed for VP9 VDEnc, start offset in byte, 0xffffffff means unavailable 53 uint32_t LastTileBS_StartInBytes;// last tile in bitstream for region 4 and region 5 54 uint32_t SliceHeaderSizeinBits;// needed for HEVC dual pipe BRC 55 uint16_t TotalSizeInCommandBuffer; // Total size in bytes of valid data in the command buffer 56 uint16_t OffsetInCommandBuffer; // Byte offset of the to-be-updated Length (uint32_t) in the command buffer, 0xffff means unavailable 57 uint16_t PicWidthInPixel; // Picture width in pixel 58 uint16_t PicHeightInPixel; // Picture hieght in pixel 59 uint16_t TotalNumberOfPAKs; // [2..4] 60 uint16_t NumSlices[4]; // this is number of slices from each PAK 61 uint16_t NumTiles[4]; // this is number of tiles from each PAK 62 uint16_t PIC_STATE_StartInBytes;// offset for region 7 and region 8 63 uint8_t Codec; // 1: HEVC DP; 2: HEVC VDEnc; 3: VP9 VDEnc 64 uint8_t MAXPass; // Max number of BRC pass >=1 65 uint8_t CurrentPass; // Current BRC pass [1..MAXPass] 66 uint8_t MinCUSize; // Minimum CU size (3: 8x8, 4:16x16), HEVC only. 67 uint8_t CabacZeroWordFlag; // cabac zero flag, HEVC only 68 uint8_t bitdepth_luma; // luma bitdepth, HEVC only 69 uint8_t bitdepth_chroma; // chroma bitdepth, HEVC only 70 uint8_t ChromaFormatIdc; // chroma format idc, HEVC only 71 uint8_t currFrameBRClevel; // Hevc dual pipe only 72 uint8_t brcUnderFlowEnable; // Hevc dual pipe only 73 uint8_t StitchEnable;// enable stitch cmd for Hevc dual pipe 74 uint8_t reserved1; 75 uint16_t StitchCommandOffset; // offset in region 10 which is the second level batch buffer 76 uint16_t reserved2; 77 uint32_t BBEndforStitch; 78 uint8_t RSVD[16]; //mbz 79 }; 80 81 //! 82 //! \struct HucInputCmdG11 83 //! \brief The struct of Huc input command 84 //! 85 struct HucInputCmdG11 86 { 87 uint8_t SelectionForIndData = 0; 88 uint8_t CmdMode = 0; 89 uint16_t LengthOfTable = 0; 90 91 uint32_t SrcBaseOffset = 0; 92 uint32_t DestBaseOffset = 0; 93 94 uint32_t Reserved[3] = { 0 }; 95 96 uint32_t CopySize = 0; // use this as indicator of size for copy base addr cmd. Since encode will not implement CopySize for copy cmd 97 98 uint32_t ReservedCounter[4] = {0}; 99 100 uint32_t SrcAddrBottom = 0; 101 uint32_t SrcAddrTop = 0; 102 uint32_t DestAddrBottom = 0; 103 uint32_t DestAddrTop = 0; 104 }; 105 106 //! HEVC dual-pipe encoder class for GEN11 107 /*! 108 This class defines the member fields, functions for GEN11 platform 109 */ 110 class CodechalEncHevcStateG11 : public CodechalEncHevcState 111 { 112 public: 113 114 //!< Constants for mode bits look-up-tables 115 enum 116 { 117 LUTMODEBITS_INTRA_64X64 = 0x00, 118 LUTMODEBITS_INTRA_32X32 = 0x01, 119 LUTMODEBITS_INTRA_16X16 = 0x02, 120 LUTMODEBITS_INTRA_8X8 = 0x03, 121 LUTMODEBITS_INTRA_NXN = 0x04, 122 LUTMODEBITS_INTRA_MPM = 0x07, 123 LUTMODEBITS_INTRA_CHROMA = 0x08, 124 LUTMODEBITS_INTRA_DC_32X32 = 0x09, 125 LUTMODEBITS_INTRA_DC_8X8 = 0x0A, 126 LUTMODEBITS_INTRA_NONDC_32X32 = 0x0B, 127 LUTMODEBITS_INTRA_NONDC_16X16 = 0x0C, // only used by CRE 128 LUTMODEBITS_INTRA_NONDC_8X8 = 0x0D, 129 LUTMODEBITS_INTER_64X64 = 0x0E, // only used by Kernel 130 LUTMODEBITS_INTER_64X32 = 0x0F, 131 LUTMODEBITS_INTER_32X64 = 0x0F, 132 LUTMODEBITS_INTER_32X32 = 0x10, 133 LUTMODEBITS_INTER_32X16 = 0x11, 134 LUTMODEBITS_INTER_16X32 = 0x11, 135 LUTMODEBITS_INTER_AMP = 0x11, 136 LUTMODEBITS_INTER_16X8 = 0x13, 137 LUTMODEBITS_INTER_8X16 = 0x13, 138 LUTMODEBITS_INTER_8X8 = 0x14, 139 LUTMODEBITS_INTER_BIDIR = 0x15, 140 LUTMODEBITS_INTER_REFID = 0x16, 141 LUTMODEBITS_MERGE_64X64 = 0x17, 142 LUTMODEBITS_MERGE_32X32 = 0x18, 143 LUTMODEBITS_MERGE_16X16 = 0x19, 144 LUTMODEBITS_MERGE_8X8 = 0x1A, 145 LUTMODEBITS_INTER_SKIP = 0x1B, // only used by CRE 146 LUTMODEBITS_SKIP_64X64 = 0x1C, 147 LUTMODEBITS_SKIP_32X32 = 0x1D, 148 LUTMODEBITS_SKIP_16X16 = 0x1E, 149 LUTMODEBITS_SKIP_8X8 = 0x1F, 150 LUTMODEBITS_TU_DEPTH_0 = 0x23, // shared by HEVC & VP9 151 LUTMODEBITS_TU_DEPTH_1 = 0x24, // shared by HEVC & VP9 152 LUTMODEBITS_INTER_16X16 = 0x12, 153 LUTMODEBITS_CBF = 0x26, 154 LUTMODEBITS_INTRA_CBF_32X32 = LUTMODEBITS_CBF + 0, 155 LUTMODEBITS_INTRA_CBF_16X16 = LUTMODEBITS_CBF + 1, 156 LUTMODEBITS_INTRA_CBF_8X8 = LUTMODEBITS_CBF + 2, 157 LUTMODEBITS_INTRA_CBF_4X4 = LUTMODEBITS_CBF + 3, 158 LUTMODEBITS_INTER_CBF_32X32 = LUTMODEBITS_CBF + 4, 159 LUTMODEBITS_INTER_CBF_16X16 = LUTMODEBITS_CBF + 5, 160 LUTMODEBITS_INTER_CBF_8X8 = LUTMODEBITS_CBF + 6, 161 LUTMODEBITS_INTER_CBF_4X4 = LUTMODEBITS_CBF + 7, 162 NUM_LUTMODEBITS = 46 163 }; 164 165 //!< Constants for CRE costing look-up-tables 166 enum 167 { 168 LUTCREMODE_INTRA_NONPRED = 0x00, // MPM 169 LUTCREMODE_INTRA_32X32 = 0x01, 170 LUTCREMODE_INTRA_16X16 = 0x02, 171 LUTCREMODE_INTRA_8X8 = 0x03, 172 LUTCREMODE_INTER_32X16 = 0x04, 173 LUTCREMODE_INTER_16X32 = 0x04, 174 LUTCREMODE_INTER_AMP = 0x04, 175 LUTCREMODE_INTER_16X16 = 0x05, 176 LUTCREMODE_INTER_16X8 = 0x06, 177 LUTCREMODE_INTER_8X16 = 0x06, 178 LUTCREMODE_INTER_8X8 = 0x07, 179 LUTCREMODE_INTER_32X32 = 0x08, 180 LUTCREMODE_INTER_BIDIR = 0x09, 181 LUTCREMODE_REF_ID = 0x0A, 182 LUTCREMODE_INTRA_CHROMA = 0x0B, 183 LUTCREMODE_INTER_SKIP = 0x0C, 184 LUTCREMODE_INTRA_NONDC_32X32 = 0x0D, 185 LUTCREMODE_INTRA_NONDC_16X16 = 0x0E, 186 LUTCREMODE_INTRA_NONDC_8X8 = 0x0F, 187 NUM_LUTCREMODE = 16 188 }; 189 190 //!< Constants for RDE costing look-up-tables 191 enum 192 { 193 LUTRDEMODE_INTRA_64X64 = 0x00, 194 LUTRDEMODE_INTRA_32X32 = 0x01, 195 LUTRDEMODE_INTRA_16X16 = 0x02, 196 LUTRDEMODE_INTRA_8X8 = 0x03, 197 LUTRDEMODE_INTRA_NXN = 0x04, 198 LUTRDEMODE_INTRA_MPM = 0x07, 199 LUTRDEMODE_INTRA_DC_32X32 = 0x08, 200 LUTRDEMODE_INTRA_DC_8X8 = 0x09, 201 LUTRDEMODE_INTRA_NONDC_32X32 = 0x0A, 202 LUTRDEMODE_INTRA_NONDC_8X8 = 0x0B, 203 LUTRDEMODE_INTER_BIDIR = 0x0C, 204 LUTRDEMODE_INTER_REFID = 0x0D, 205 LUTRDEMODE_SKIP_64X64 = 0x0E, 206 LUTRDEMODE_SKIP_32X32 = 0x0F, 207 LUTRDEMODE_SKIP_16X16 = 0x10, 208 LUTRDEMODE_SKIP_8X8 = 0x11, 209 LUTRDEMODE_MERGE_64X64 = 0x12, 210 LUTRDEMODE_MERGE_32X32 = 0x13, 211 LUTRDEMODE_MERGE_16X16 = 0x14, 212 LUTRDEMODE_MERGE_8X8 = 0x15, 213 LUTRDEMODE_INTER_32X32 = 0x16, 214 LUTRDEMODE_INTER_32X16 = 0x17, 215 LUTRDEMODE_INTER_16X32 = 0x17, 216 LUTRDEMODE_INTER_AMP = 0x17, 217 LUTRDEMODE_INTER_16X16 = 0x18, 218 LUTRDEMODE_INTER_16X8 = 0x19, 219 LUTRDEMODE_INTER_8X16 = 0x19, 220 LUTRDEMODE_INTER_8X8 = 0x1A, 221 LUTRDEMODE_TU_DEPTH_0 = 0x1E, 222 LUTRDEMODE_TU_DEPTH_1 = 0x1F, 223 LUTRDEMODE_CBF = 0x21, 224 LUTRDEMODE_INTRA_CBF_32X32 = LUTRDEMODE_CBF+0, 225 LUTRDEMODE_INTRA_CBF_16X16 = LUTRDEMODE_CBF+1, 226 LUTRDEMODE_INTRA_CBF_8X8 = LUTRDEMODE_CBF+2, 227 LUTRDEMODE_INTRA_CBF_4X4 = LUTRDEMODE_CBF+3, 228 LUTRDEMODE_INTER_CBF_32X32 = LUTRDEMODE_CBF+4, 229 LUTRDEMODE_INTER_CBF_16X16 = LUTRDEMODE_CBF+5, 230 LUTRDEMODE_INTER_CBF_8X8 = LUTRDEMODE_CBF+6, 231 LUTRDEMODE_INTER_CBF_4X4 = LUTRDEMODE_CBF+7, 232 NUM_LUTRDEMODE = 41, 233 }; 234 235 //!< MBENC kernel index 236 enum 237 { 238 MBENC_LCU32_KRNIDX = 0, 239 MBENC_LCU64_KRNIDX = 1, 240 MBENC_NUM_KRN 241 }; 242 243 //!< Binding table offset 244 enum 245 { 246 //BRC Init/Reset 247 BRC_INIT_RESET_BEGIN = 0, 248 BRC_INIT_RESET_HISTORY = BRC_INIT_RESET_BEGIN, 249 BRC_INIT_RESET_DISTORTION, 250 BRC_INIT_RESET_END, 251 252 //BRC Update (frame based) 253 BRC_UPDATE_BEGIN = 0, 254 BRC_UPDATE_HISTORY = BRC_UPDATE_BEGIN, 255 BRC_UPDATE_PREV_PAK, 256 BRC_UPDATE_PIC_STATE_R, 257 BRC_UPDATE_PIC_STATE_W, 258 BRC_UPDATE_ENC_OUTPUT, 259 BRC_UPDATE_DISTORTION, 260 BRC_UPDATE_BRCDATA, 261 BRC_UPDATE_MB_STATS, 262 BRC_UPDATE_MV_AND_DISTORTION_SUM, 263 BRC_UPDATE_END, 264 265 //BRC Update (LCU-based) 266 BRC_LCU_UPDATE_BEGIN = 0, 267 BRC_LCU_UPDATE_HISTORY = BRC_LCU_UPDATE_BEGIN, 268 BRC_LCU_UPDATE_DISTORTION, 269 BRC_LCU_UPDATE_MB_STATS, 270 BRC_LCU_UPDATE_MB_QP, 271 BRC_LCU_UPDATE_ROI, 272 BRC_LCU_UPDATE_END, 273 274 // MBEnc I-kernel 275 MBENC_I_FRAME_BEGIN = 0, 276 MBENC_I_FRAME_VME_PRED_CURR_PIC_IDX0 = MBENC_I_FRAME_BEGIN, 277 MBENC_I_FRAME_VME_PRED_FWD_PIC_IDX0, 278 MBENC_I_FRAME_VME_PRED_BWD_PIC_IDX0, 279 MBENC_I_FRAME_VME_PRED_FWD_PIC_IDX1, 280 MBENC_I_FRAME_VME_PRED_BWD_PIC_IDX1, 281 MBENC_I_FRAME_VME_PRED_FWD_PIC_IDX2, 282 MBENC_I_FRAME_VME_PRED_BWD_PIC_IDX2, 283 MBENC_I_FRAME_VME_PRED_FWD_PIC_IDX3, 284 MBENC_I_FRAME_VME_PRED_BWD_PIC_IDX3, 285 MBENC_I_FRAME_CURR_Y, 286 MBENC_I_FRAME_CURR_UV, 287 MBENC_I_FRAME_CURR_Y_WITH_RECON_BOUNDARY_PIX, 288 MBENC_I_FRAME_INTERMEDIATE_CU_RECORD, 289 MBENC_I_FRAME_PAK_OBJ, 290 MBENC_I_FRAME_PAK_CU_RECORD, 291 MBENC_I_FRAME_SW_SCOREBOARD, 292 MBENC_I_FRAME_SCRATCH_SURFACE, 293 MBENC_I_FRAME_CU_QP_DATA, 294 MBENC_I_FRAME_LCU_LEVEL_DATA_INPUT, 295 MBENC_I_FRAME_ENC_CONST_TABLE, 296 MBENC_I_FRAME_CONCURRENT_TG_DATA, 297 MBENC_I_FRAME_BRC_COMBINED_ENC_PARAMETER_SURFACE, 298 MBENC_I_FRAME_DEBUG_DUMP, 299 MBENC_I_FRAME_END, 300 301 //MBEnc B-Kernel 302 MBENC_B_FRAME_BEGIN = 0, 303 MBENC_B_FRAME_ENCODER_COMBINED_BUFFER1 = MBENC_B_FRAME_BEGIN, 304 MBENC_B_FRAME_ENCODER_COMBINED_BUFFER2, 305 MBENC_B_FRAME_VME_PRED_CURR_PIC_IDX0, 306 MBENC_B_FRAME_VME_PRED_FWD_PIC_IDX0, 307 MBENC_B_FRAME_VME_PRED_BWD_PIC_IDX0, 308 MBENC_B_FRAME_VME_PRED_FWD_PIC_IDX1, 309 MBENC_B_FRAME_VME_PRED_BWD_PIC_IDX1, 310 MBENC_B_FRAME_VME_PRED_FWD_PIC_IDX2, 311 MBENC_B_FRAME_VME_PRED_BWD_PIC_IDX2, 312 MBENC_B_FRAME_VME_PRED_FWD_PIC_IDX3, 313 MBENC_B_FRAME_VME_PRED_BWD_PIC_IDX3, 314 MBENC_B_FRAME_CURR_Y, 315 MBENC_B_FRAME_CURR_UV, 316 MBENC_B_FRAME_CURR_Y_WITH_RECON_BOUNDARY_PIX, 317 MBENC_B_FRAME_ENC_CU_RECORD, 318 MBENC_B_FRAME_PAK_OBJ, 319 MBENC_B_FRAME_PAK_CU_RECORD, 320 MBENC_B_FRAME_SW_SCOREBOARD, 321 MBENC_B_FRAME_SCRATCH_SURFACE, 322 MBENC_B_FRAME_CU_QP_DATA, 323 MBENC_B_FRAME_LCU_LEVEL_DATA_INPUT, 324 MBENC_B_FRAME_ENC_CONST_TABLE, 325 MBENC_B_FRAME_COLOCATED_CU_MV_DATA, 326 MBENC_B_FRAME_HME_MOTION_PREDICTOR_DATA, 327 MBENC_B_FRAME_CONCURRENT_TG_DATA, 328 MBENC_B_FRAME_BRC_COMBINED_ENC_PARAMETER_SURFACE, 329 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_CURR, 330 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_FWD_PIC_IDX0, 331 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_BWD_PIC_IDX0, 332 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_FWD_PIC_IDX1, 333 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_BWD_PIC_IDX1, 334 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_FWD_PIC_IDX2, 335 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_BWD_PIC_IDX2, 336 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_FWD_PIC_IDX3, 337 MBENC_B_FRAME_VME_PRED_FOR_2X_DS_BWD_PIC_IDX3, 338 MBENC_B_FRAME_ENCODER_HISTORY_INPUT_BUFFER, 339 MBENC_B_FRAME_ENCODER_HISTORY_OUTPUT_BUFFER, 340 MBENC_B_FRAME_DEBUG_SURFACE, 341 MBENC_B_FRAME_DEBUG_SURFACE1, 342 MBENC_B_FRAME_DEBUG_SURFACE2, 343 MBENC_B_FRAME_DEBUG_SURFACE3, 344 MBENC_B_FRAME_END, 345 }; 346 347 //!< Constants for TU based params 348 enum 349 { 350 IntraSpotCheckFlagTuParam, 351 EnableCu64CheckTuParam, 352 DynamicOrderThTuParam, 353 Dynamic64ThTuParam, 354 Dynamic64OrderTuParam, 355 Dynamic64EnableTuParam, 356 IncreaseExitThreshTuParam, 357 Log2TUMaxDepthInterTuParam, 358 Log2TUMaxDepthIntraTuParam, 359 MaxNumIMESearchCenterTuParam, 360 Fake32EnableTuParam, 361 Dynamic64Min32, 362 TotalTuParams 363 }; 364 365 //! \cond SKIP_DOXYGEN 366 //! Kernel Header structure 367 struct CODECHAL_HEVC_KERNEL_HEADER 368 { 369 int nKernelCount; 370 union 371 { 372 struct 373 { 374 CODECHAL_KERNEL_HEADER HEVC_Enc_LCU32; 375 CODECHAL_KERNEL_HEADER HEVC_Enc_LCU64; 376 CODECHAL_KERNEL_HEADER HEVC_brc_init; 377 CODECHAL_KERNEL_HEADER HEVC_brc_reset; 378 CODECHAL_KERNEL_HEADER HEVC_brc_update; 379 CODECHAL_KERNEL_HEADER HEVC_brc_lcuqp; 380 }; 381 }; 382 }; 383 using PCODECHAL_HEVC_KERNEL_HEADER = CODECHAL_HEVC_KERNEL_HEADER*; 384 385 static const uint32_t MAX_MULTI_FRAME_NUMBER = 4; 386 387 //! MBENC LCU32 kernel BTI structure 388 struct MBENC_LCU32_BTI 389 { 390 uint32_t Combined1DSurIndexMF1[MAX_MULTI_FRAME_NUMBER]; 391 uint32_t Combined1DSurIndexMF2[MAX_MULTI_FRAME_NUMBER]; 392 uint32_t VMEInterPredictionSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 393 uint32_t SrcSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 394 uint32_t SrcReconSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 395 uint32_t CURecordSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 396 uint32_t PAKObjectSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 397 uint32_t CUPacketSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 398 uint32_t SWScoreBoardSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 399 uint32_t QPCU16SurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 400 uint32_t LCULevelDataSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 401 uint32_t TemporalMVSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 402 uint32_t HmeDataSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 403 uint32_t HEVCCnstLutSurfIndex; 404 uint32_t LoadBalenceSurfIndex; 405 uint32_t ReservedBTI0; 406 uint32_t ReservedBTI1; 407 uint32_t DebugSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 408 }; 409 using PMBENC_LCU32_BTI = MBENC_LCU32_BTI*; 410 411 //! MBENC LCU64 kernel BTI structure 412 struct MBENC_LCU64_BTI 413 { 414 uint32_t Combined1DSurIndexMF1[MAX_MULTI_FRAME_NUMBER]; 415 uint32_t Combined1DSurIndexMF2[MAX_MULTI_FRAME_NUMBER]; 416 uint32_t VMEInterPredictionSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 417 uint32_t SrcSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 418 uint32_t SrcReconSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 419 uint32_t CURecordSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 420 uint32_t PAKObjectSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 421 uint32_t CUPacketSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 422 uint32_t SWScoreBoardSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 423 uint32_t QPCU16SurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 424 uint32_t LCULevelDataSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 425 uint32_t TemporalMVSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 426 uint32_t HmeDataSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 427 uint32_t VME2XInterPredictionSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 428 uint32_t HEVCCnstLutSurfIndex; 429 uint32_t LoadBalenceSurfIndex; 430 uint32_t DebugSurfIndexMF[MAX_MULTI_FRAME_NUMBER]; 431 }; 432 using PMBENC_LCU64_BTI = MBENC_LCU64_BTI*; 433 434 struct MBENC_COMBINED_BTI 435 { MBENC_COMBINED_BTIMBENC_COMBINED_BTI436 MBENC_COMBINED_BTI() 437 { 438 MOS_ZeroMemory(this, sizeof(*this)); 439 } 440 union 441 { 442 MBENC_LCU32_BTI BTI_LCU32; 443 MBENC_LCU64_BTI BTI_LCU64; 444 }; 445 }; 446 447 //! BRC Init/Reset kernel Curbe structure 448 struct BRC_INITRESET_CURBE 449 { 450 // DWORD 0 451 uint32_t DW0_ProfileLevelMaxFrame : MOS_BITFIELD_RANGE(0, 31); 452 453 // DWORD 1 454 uint32_t DW1_InitBufFull : MOS_BITFIELD_RANGE(0, 31); 455 456 // DWORD 2 457 uint32_t DW2_BufSize : MOS_BITFIELD_RANGE(0, 31); 458 459 // DWORD 3 460 uint32_t DW3_TargetBitRate : MOS_BITFIELD_RANGE(0, 31); 461 462 // DWORD 4 463 uint32_t DW4_MaximumBitRate : MOS_BITFIELD_RANGE(0, 31); 464 465 // DWORD 5 466 uint32_t DW5_MinimumBitRate : MOS_BITFIELD_RANGE(0, 31); 467 468 // DWORD 6 469 uint32_t DW6_FrameRateM : MOS_BITFIELD_RANGE(0, 31); 470 471 // DWORD 7 472 uint32_t DW7_FrameRateD : MOS_BITFIELD_RANGE(0, 31); 473 474 // DWORD 8 475 uint32_t DW8_BRCFlag : MOS_BITFIELD_RANGE(0, 15); 476 uint32_t DW8_BRCGopP : MOS_BITFIELD_RANGE(16, 31); 477 478 // DWORD 9 479 uint32_t DW9_BRCGopB : MOS_BITFIELD_RANGE(0, 15); 480 uint32_t DW9_FrameWidth : MOS_BITFIELD_RANGE(16, 31); 481 482 // DWORD 10 483 uint32_t DW10_FrameHeight : MOS_BITFIELD_RANGE(0, 15); 484 uint32_t DW10_AVBRAccuracy : MOS_BITFIELD_RANGE(16, 31); 485 486 // DWORD 11 487 uint32_t DW11_AVBRConvergence : MOS_BITFIELD_RANGE(0, 15); 488 uint32_t DW11_MinimumQP : MOS_BITFIELD_RANGE(16, 31); 489 490 // DWORD 12 491 uint32_t DW12_MaximumQP : MOS_BITFIELD_RANGE(0, 15); 492 uint32_t DW12_NumberSlice : MOS_BITFIELD_RANGE(16, 31); 493 494 // DWORD 13 495 uint32_t DW13_Reserved_0 : MOS_BITFIELD_RANGE(0, 15); 496 uint32_t DW13_BRCGopB1 : MOS_BITFIELD_RANGE(16, 31); 497 498 // DWORD 14 499 uint32_t DW14_BRCGopB2 : MOS_BITFIELD_RANGE(0, 15); 500 uint32_t DW14_MaxBRCLevel : MOS_BITFIELD_RANGE(16, 31); 501 502 // DWORD 15 503 uint32_t DW15_LongTermInterval : MOS_BITFIELD_RANGE(0, 15); 504 uint32_t DW15_Reserved_0 : MOS_BITFIELD_RANGE(16, 31); 505 506 // DWORD 16 507 uint32_t DW16_InstantRateThreshold0_Pframe : MOS_BITFIELD_RANGE(0, 7); 508 uint32_t DW16_InstantRateThreshold1_Pframe : MOS_BITFIELD_RANGE(8, 15); 509 uint32_t DW16_InstantRateThreshold2_Pframe : MOS_BITFIELD_RANGE(16, 23); 510 uint32_t DW16_InstantRateThreshold3_Pframe : MOS_BITFIELD_RANGE(24, 31); 511 512 // DWORD 17 513 uint32_t DW17_InstantRateThreshold0_Bframe : MOS_BITFIELD_RANGE(0, 7); 514 uint32_t DW17_InstantRateThreshold1_Bframe : MOS_BITFIELD_RANGE(8, 15); 515 uint32_t DW17_InstantRateThreshold2_Bframe : MOS_BITFIELD_RANGE(16, 23); 516 uint32_t DW17_InstantRateThreshold3_Bframe : MOS_BITFIELD_RANGE(24, 31); 517 518 // DWORD 18 519 uint32_t DW18_InstantRateThreshold0_Iframe : MOS_BITFIELD_RANGE(0, 7); 520 uint32_t DW18_InstantRateThreshold1_Iframe : MOS_BITFIELD_RANGE(8, 15); 521 uint32_t DW18_InstantRateThreshold2_Iframe : MOS_BITFIELD_RANGE(16, 23); 522 uint32_t DW18_InstantRateThreshold3_Iframe : MOS_BITFIELD_RANGE(24, 31); 523 524 // DWORD 19 525 uint32_t DW19_DeviationThreshold0_PBframe : MOS_BITFIELD_RANGE(0, 7); 526 uint32_t DW19_DeviationThreshold1_PBframe : MOS_BITFIELD_RANGE(8, 15); 527 uint32_t DW19_DeviationThreshold2_PBframe : MOS_BITFIELD_RANGE(16, 23); 528 uint32_t DW19_DeviationThreshold3_PBframe : MOS_BITFIELD_RANGE(24, 31); 529 530 // DWORD 20 531 uint32_t DW20_DeviationThreshold4_PBframe : MOS_BITFIELD_RANGE(0, 7); 532 uint32_t DW20_DeviationThreshold5_PBframe : MOS_BITFIELD_RANGE(8, 15); 533 uint32_t DW20_DeviationThreshold6_PBframe : MOS_BITFIELD_RANGE(16, 23); 534 uint32_t DW20_DeviationThreshold7_PBframe : MOS_BITFIELD_RANGE(24, 31); 535 536 // DWORD 21 537 uint32_t DW21_DeviationThreshold0_VBRcontrol : MOS_BITFIELD_RANGE(0, 7); 538 uint32_t DW21_DeviationThreshold1_VBRcontrol : MOS_BITFIELD_RANGE(8, 15); 539 uint32_t DW21_DeviationThreshold2_VBRcontrol : MOS_BITFIELD_RANGE(16, 23); 540 uint32_t DW21_DeviationThreshold3_VBRcontrol : MOS_BITFIELD_RANGE(24, 31); 541 542 // DWORD 22 543 uint32_t DW22_DeviationThreshold4_VBRcontrol : MOS_BITFIELD_RANGE(0, 7); 544 uint32_t DW22_DeviationThreshold5_VBRcontrol : MOS_BITFIELD_RANGE(8, 15); 545 uint32_t DW22_DeviationThreshold6_VBRcontrol : MOS_BITFIELD_RANGE(16, 23); 546 uint32_t DW22_DeviationThreshold7_VBRcontrol : MOS_BITFIELD_RANGE(24, 31); 547 548 // DWORD 23 549 uint32_t DW23_DeviationThreshold0_Iframe : MOS_BITFIELD_RANGE(0, 7); 550 uint32_t DW23_DeviationThreshold1_Iframe : MOS_BITFIELD_RANGE(8, 15); 551 uint32_t DW23_DeviationThreshold2_Iframe : MOS_BITFIELD_RANGE(16, 23); 552 uint32_t DW23_DeviationThreshold3_Iframe : MOS_BITFIELD_RANGE(24, 31); 553 554 // DWORD 24 555 uint32_t DW24_DeviationThreshold4_Iframe : MOS_BITFIELD_RANGE(0, 7); 556 uint32_t DW24_DeviationThreshold5_Iframe : MOS_BITFIELD_RANGE(8, 15); 557 uint32_t DW24_DeviationThreshold6_Iframe : MOS_BITFIELD_RANGE(16, 23); 558 uint32_t DW24_DeviationThreshold7_Iframe : MOS_BITFIELD_RANGE(24, 31); 559 560 // DWORD 25 561 uint32_t DW25_ACQPBuffer : MOS_BITFIELD_RANGE(0, 7); 562 uint32_t DW25_IntraSADTransform : MOS_BITFIELD_RANGE(8, 15); 563 uint32_t DW25_Log2MaxCuSize : MOS_BITFIELD_RANGE(16, 23); 564 uint32_t DW25_SlidingWindowSize : MOS_BITFIELD_RANGE(24, 31); 565 566 // DWORD 26 567 uint32_t DW26_BGOPSize : MOS_BITFIELD_RANGE(0, 7); 568 uint32_t DW26_RandomAccess : MOS_BITFIELD_RANGE(8, 15); 569 uint32_t DW26_Reserved_0 : MOS_BITFIELD_RANGE(16, 31); 570 571 // DWORD 27 572 uint32_t DW27_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 573 574 // DWORD 28 575 uint32_t DW28_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 576 577 // DWORD 29 578 uint32_t DW29_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 579 580 // DWORD 30 581 uint32_t DW30_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 582 583 // DWORD 31 584 uint32_t DW31_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 585 586 }; 587 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(BRC_INITRESET_CURBE)) == 32); 588 using PBRC_INITRESET_CURBE = BRC_INITRESET_CURBE*; 589 590 //! BRC Update kernel Curbe structure 591 struct BRCUPDATE_CURBE 592 { 593 // DWORD 0 594 uint32_t DW0_TargetSize : MOS_BITFIELD_RANGE(0, 31); 595 596 // DWORD 1 597 uint32_t DW1_FrameNumber : MOS_BITFIELD_RANGE(0, 31); 598 599 // DWORD 2 600 uint32_t DW2_PictureHeaderSize : MOS_BITFIELD_RANGE(0, 31); 601 602 // DWORD 3 603 uint32_t DW3_StartGAdjFrame0 : MOS_BITFIELD_RANGE(0, 15); 604 uint32_t DW3_StartGAdjFrame1 : MOS_BITFIELD_RANGE(16, 31); 605 606 // DWORD 4 607 uint32_t DW4_StartGAdjFrame2 : MOS_BITFIELD_RANGE(0, 15); 608 uint32_t DW4_StartGAdjFrame3 : MOS_BITFIELD_RANGE(16, 31); 609 610 // DWORD 5 611 uint32_t DW5_TargetSize_Flag : MOS_BITFIELD_RANGE(0, 7); 612 uint32_t DW5_Reserved_0 : MOS_BITFIELD_RANGE(8, 15); 613 uint32_t DW5_MaxNumPAKs : MOS_BITFIELD_RANGE(16, 23); 614 uint32_t DW5_CurrFrameBrcLevel : MOS_BITFIELD_RANGE(24, 31); 615 616 // DWORD 6 617 uint32_t DW6_NumSkippedFrames : MOS_BITFIELD_RANGE(0, 7); 618 uint32_t DW6_CqpValue : MOS_BITFIELD_RANGE(8, 15); 619 uint32_t DW6_ROIEnable : MOS_BITFIELD_RANGE(16, 16); 620 uint32_t DW6_BRCROIEnable : MOS_BITFIELD_RANGE(17, 17); 621 uint32_t DW6_LowDelayEnable : MOS_BITFIELD_RANGE(18, 18); 622 uint32_t DW6_Reserved1 : MOS_BITFIELD_RANGE(19, 19); 623 uint32_t DW6_SlidingWindowEnable : MOS_BITFIELD_RANGE(20, 20); 624 uint32_t DW6_Reserved2 : MOS_BITFIELD_RANGE(21, 23); 625 uint32_t DW6_RoiRatio : MOS_BITFIELD_RANGE(24, 31); 626 627 // DWORD 7 628 uint32_t DW7_Reserved_0 : MOS_BITFIELD_RANGE(0, 15); 629 uint32_t DW7_FrameMinQP : MOS_BITFIELD_RANGE(16, 23); 630 uint32_t DW7_FrameMaxQP : MOS_BITFIELD_RANGE(24, 31); 631 632 // DWORD 8 633 uint32_t DW8_StartGlobalAdjustMult0 : MOS_BITFIELD_RANGE(0, 7); 634 uint32_t DW8_StartGlobalAdjustMult1 : MOS_BITFIELD_RANGE(8, 15); 635 uint32_t DW8_StartGlobalAdjustMult2 : MOS_BITFIELD_RANGE(16, 23); 636 uint32_t DW8_StartGlobalAdjustMult3 : MOS_BITFIELD_RANGE(24, 31); 637 638 // DWORD 9 639 uint32_t DW9_StartGlobalAdjustMult4 : MOS_BITFIELD_RANGE(0, 7); 640 uint32_t DW9_StartGlobalAdjustDivd0 : MOS_BITFIELD_RANGE(8, 15); 641 uint32_t DW9_StartGlobalAdjustDivd1 : MOS_BITFIELD_RANGE(16, 23); 642 uint32_t DW9_StartGlobalAdjustDivd2 : MOS_BITFIELD_RANGE(24, 31); 643 644 // DWORD 10 645 uint32_t DW10_StartGlobalAdjustDivd3 : MOS_BITFIELD_RANGE(0, 7); 646 uint32_t DW10_StartGlobalAdjustDivd4 : MOS_BITFIELD_RANGE(8, 15); 647 uint32_t DW10_QPThreshold0 : MOS_BITFIELD_RANGE(16, 23); 648 uint32_t DW10_QPThreshold1 : MOS_BITFIELD_RANGE(24, 31); 649 650 // DWORD 11 651 uint32_t DW11_QPThreshold2 : MOS_BITFIELD_RANGE(0, 7); 652 uint32_t DW11_QPThreshold3 : MOS_BITFIELD_RANGE(8, 15); 653 uint32_t DW11_gRateRatioThreshold0 : MOS_BITFIELD_RANGE(16, 23); 654 uint32_t DW11_gRateRatioThreshold1 : MOS_BITFIELD_RANGE(24, 31); 655 656 // DWORD 12 657 uint32_t DW12_gRateRatioThreshold2 : MOS_BITFIELD_RANGE(0, 7); 658 uint32_t DW12_gRateRatioThreshold3 : MOS_BITFIELD_RANGE(8, 15); 659 uint32_t DW12_gRateRatioThreshold4 : MOS_BITFIELD_RANGE(16, 23); 660 uint32_t DW12_gRateRatioThreshold5 : MOS_BITFIELD_RANGE(24, 31); 661 662 // DWORD 13 663 uint32_t DW13_gRateRatioThreshold6 : MOS_BITFIELD_RANGE(0, 7); 664 uint32_t DW13_gRateRatioThreshold7 : MOS_BITFIELD_RANGE(8, 15); 665 uint32_t DW13_gRateRatioThreshold8 : MOS_BITFIELD_RANGE(16, 23); 666 uint32_t DW13_gRateRatioThreshold9 : MOS_BITFIELD_RANGE(24, 31); 667 668 // DWORD 14 669 uint32_t DW14_gRateRatioThreshold10 : MOS_BITFIELD_RANGE(0, 7); 670 uint32_t DW14_gRateRatioThreshold11 : MOS_BITFIELD_RANGE(8, 15); 671 uint32_t DW14_gRateRatioThreshold12 : MOS_BITFIELD_RANGE(16, 23); 672 uint32_t DW14_ParallelMode : MOS_BITFIELD_RANGE(24, 31); 673 674 // DWORD 15 675 uint32_t DW15_SizeOfSkippedFrames : MOS_BITFIELD_RANGE(0, 31); 676 677 // DWORD 16 678 uint32_t DW16_UserMaxFrameSize : MOS_BITFIELD_RANGE(0, 31); 679 680 // DWORD 17 681 uint32_t DW17_LongTerm_Current : MOS_BITFIELD_RANGE(0, 7); 682 uint32_t DW17_Reserved_0 : MOS_BITFIELD_RANGE(8, 31); 683 684 // DWORD 18 - 23 reserved 685 uint32_t DW18_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 686 uint32_t DW19_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 687 uint32_t DW20_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 688 uint32_t DW21_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 689 uint32_t DW22_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 690 uint32_t DW23_Reserved_0 : MOS_BITFIELD_RANGE(0, 31); 691 }; 692 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(BRCUPDATE_CURBE)) == 24); 693 using PBRCUPDATE_CURBE = BRCUPDATE_CURBE*; 694 695 //! LCU level data structure 696 struct LCU_LEVEL_DATA 697 { 698 uint16_t SliceStartLcuIndex; 699 uint16_t SliceEndLcuIndex; 700 uint16_t TileId; 701 uint16_t SliceId; 702 uint16_t TileStartCoordinateX; 703 uint16_t TileStartCoordinateY; 704 uint16_t TileEndCoordinateX; 705 uint16_t TileEndCoordinateY; 706 }; 707 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(LCU_LEVEL_DATA)) == 4); 708 using PLCU_LEVEL_DATA = LCU_LEVEL_DATA*; 709 710 //! Concurrent thread group data structure 711 struct CONCURRENT_THREAD_GROUP_DATA 712 { 713 uint16_t CurrSliceStartLcuX; 714 uint16_t CurrSliceStartLcuY; 715 uint16_t CurrSliceEndLcuX; 716 uint16_t CurrSliceEndLcuY; 717 uint16_t CurrTgStartLcuX; 718 uint16_t CurrTgStartLcuY; 719 uint16_t CurrTgEndLcuX; 720 uint16_t CurrTgEndLcuY; 721 uint16_t Reserved[24]; 722 }; 723 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CONCURRENT_THREAD_GROUP_DATA)) == 16); 724 using PCONCURRENT_THREAD_GROUP_DATA = CONCURRENT_THREAD_GROUP_DATA*; 725 726 struct MBENC_CURBE 727 { MBENC_CURBEMBENC_CURBE728 MBENC_CURBE() 729 { 730 MOS_SecureMemcpy(this, sizeof(*this), m_mbencCurbeInit, sizeof(m_mbencCurbeInit)); 731 } 732 733 //R1.0 //DW0 734 union 735 { 736 uint32_t R1_0; 737 struct 738 { 739 uint32_t FrameWidthInSamples : 16; 740 uint32_t FrameHeightInSamples : 16; 741 }; 742 }; 743 744 //R1.1 //DW1 745 union 746 { 747 uint32_t R1_1; 748 struct 749 { 750 uint32_t Log2MaxCUSize : 4; 751 uint32_t Log2MinCUSize : 4; 752 uint32_t Log2MaxTUSize : 4; 753 uint32_t Log2MinTUSize : 4; 754 uint32_t MaxNumIMESearchCenter : 3; 755 uint32_t MaxIntraRdeIter : 3; 756 uint32_t ROIEnable : 1; 757 uint32_t QPType : 2; 758 uint32_t MaxTransformDepthInter : 2; //<= Log2TUMaxDepthInter 759 uint32_t MaxTransformDepthIntra : 2; //<= Log2TUMaxDepthIntra 760 uint32_t Log2ParallelMergeLevel : 3; 761 762 }; 763 }; 764 765 //R1.2 //DW2 766 union 767 { 768 uint32_t R1_2; 769 struct 770 { 771 uint32_t CornerNeighborPixel : 8; 772 uint32_t IntraNeighborAvailFlags : 6; 773 uint32_t ChromaFormatType : 2; 774 uint32_t SubPelMode : 2; //Unin R0.3[16:17] SubPelMode 775 uint32_t IntraSpotCheck : 2; //reserved 776 uint32_t InterSADMeasure : 2; //Unin R0.3[20:21] InterSADMeasure 777 uint32_t IntraSADMeasure : 2; //Unin R0.3[22:23] IntraSADMeasureAdj 778 uint32_t IntraPrediction : 3; //UninR0.1 LumaIntraPartMask 779 uint32_t RefIDCostMode : 1; //UninR0.1[22] RefIDCostMode 780 uint32_t TUBasedCostSetting : 3; 781 uint32_t MBZ_1_2_1 : 1; 782 }; 783 }; 784 785 //R1.3 //DW3 786 union 787 { 788 uint32_t R1_3; 789 struct 790 { //UniversalInputSegmentPhase0_2: DW R1.0 791 uint32_t ExplictModeEn : 1; // [0] 792 uint32_t AdaptiveEn : 1; // [1] ImageState.AdaptiveEn 793 uint32_t MBZ_1_3_1 : 3; // [4:2] 794 uint32_t EarlyImeSuccessEn : 1; // [5] imageState.EarlyImeSuccessEn 795 uint32_t IntraSpeedMode : 1; // [6] 796 uint32_t IMECostCentersSel : 1; // [7] L0/L1 797 798 uint32_t RDEQuantRoundValue : 8; // [15:8] 0 799 800 uint32_t IMERefWindowSize : 2; // [17:16] m_ImageState.ImeRefWindowSize 801 uint32_t IntraComputeType : 1; // [18] 0 802 uint32_t Depth0IntraPredition : 1; // [19] 0 803 uint32_t TUDepthControl : 2; // [21:20] 804 uint32_t IntraTuRecFeedbackDisable : 1; // [22] 805 uint32_t MergeListBiDisable : 1; // [23] 806 807 uint32_t EarlyImeStop : 8; // [31:24] imageState->EarlyImeStopThres 808 }; 809 }; 810 811 //R1.4 //DW4 812 union 813 { 814 uint32_t R1_4; 815 struct 816 { 817 uint32_t FrameQP : 7; 818 uint32_t FrameQPSign : 1; 819 uint32_t ConcurrentGroupNum : 8; 820 uint32_t NumofUnitInWaveFront : 16; 821 }; 822 }; 823 824 //R1.5 //DW5 825 union 826 { 827 uint32_t R1_5; 828 struct 829 { 830 uint32_t LoadBalenceEnable : 1; 831 uint32_t NumberofMultiFrame : 3; 832 uint32_t MBZ_1_4_1 : 4; 833 uint32_t Degree45 : 1; 834 uint32_t Break12Dependency : 1; 835 uint32_t Fake32Enable : 1; 836 uint32_t MBZ_1_4_2 : 5; 837 uint32_t ThreadNumber : 8; 838 uint32_t MBZ_1_4_3 : 8; 839 }; 840 }; 841 842 //R1.6 - R2.7 //DW6 - DW15 843 uint32_t Reserved1[10]; 844 845 //R3.0 //DW16 846 union 847 { 848 uint32_t R3_0; 849 struct 850 { 851 uint32_t Pic_init_qp_B : 8; 852 uint32_t Pic_init_qp_P : 8; 853 uint32_t Pic_init_qp_I : 8; 854 uint32_t MBZ_3_0_0 : 8; 855 }; 856 }; 857 858 //R3.1 //DW17 859 union 860 { 861 uint32_t R3_1; 862 struct 863 { 864 uint32_t MBZ_3_1_0 : 16; 865 uint32_t NumofRowTile : 8; 866 uint32_t NumofColumnTile : 8; 867 }; 868 }; 869 870 //R3.2 //DW18 871 union 872 { 873 uint32_t R3_2; 874 struct 875 { 876 uint32_t TransquantBypassEnableFlag : 1; //<= EnableTransquantBypass (need in Pak data setup) 877 uint32_t PCMEnabledFlag : 1; //<= EnableIPCM 878 uint32_t MBZ_3_2_0 : 2; //reserved 879 uint32_t CuQpDeltaEnabledFlag : 1; //<= CuQpDeltaEnabledFlag 880 uint32_t Stepping : 2; 881 uint32_t WaveFrontSplitsEnable : 1; 882 uint32_t HMEFlag : 2; 883 uint32_t SuperHME : 1; 884 uint32_t UltraHME : 1; 885 uint32_t MBZ_3_2_2 : 4; //reserved 886 uint32_t Cu64SkipCheckOnly : 1; 887 uint32_t EnableCu64Check : 1; 888 uint32_t Cu642Nx2NCheckOnly : 1; 889 uint32_t EnableCu64AmpCheck : 1; 890 uint32_t MBZ_3_2_3 : 1; //reserved 891 uint32_t DisablePIntra : 1; 892 uint32_t DisableIntraTURec : 1; 893 uint32_t InheritIntraModeFromTU0 : 1; 894 uint32_t MBZ_3_2_4 : 3; //reserved 895 uint32_t CostScalingForRA : 1; 896 uint32_t DisableIntraNxN : 1; 897 uint32_t MBZ_3_2_5 : 3; //reserved 898 }; 899 }; 900 901 //R3.3 //DW19 902 union 903 { 904 uint32_t R3_3; 905 struct 906 { 907 uint32_t MaxRefIdxL0 : 8; 908 uint32_t MaxRefIdxL1 : 8; 909 uint32_t MaxBRefIdxL0 : 8; 910 uint32_t MBZ_3_3_0 : 8; 911 }; 912 }; 913 914 //R3.4 //DW20 915 union 916 { 917 uint32_t R3_4; 918 struct 919 { 920 uint32_t SkipEarlyTermination : 2; 921 uint32_t SkipEarlyTermSize : 2; 922 uint32_t Dynamic64Enable : 2; 923 uint32_t Dynamic64Order : 2; 924 uint32_t Dynamic64Th : 4; 925 uint32_t DynamicOrderTh : 4; 926 uint32_t PerBFrameQPOffset : 8; 927 uint32_t IncreaseExitThresh : 4; 928 uint32_t Dynamic64Min32 : 2; 929 uint32_t MBZ_3_4_0 : 1; //reserved 930 uint32_t LastFrameIsIntra : 1; 931 }; 932 }; 933 934 //R3.5 //DW21 935 union 936 { 937 uint32_t R3_5; 938 struct 939 { 940 uint32_t LenSP : 8; //Unin R1.2[16:23] LenSP 941 uint32_t MaxNumSU : 8; //Unin R1.2[24:31] MaxNumSU 942 uint32_t MBZ_3_5_1 : 16; 943 }; 944 }; 945 946 //R3.6 //DW22 947 union 948 { 949 uint32_t R3_6; 950 struct 951 { 952 uint32_t CostTableIndex : 8; 953 uint32_t MBZ_3_6_1 : 24; 954 }; 955 }; 956 957 //R3.7 //DW23 958 union 959 { 960 uint32_t R3_7; 961 struct 962 { 963 uint32_t SliceType : 2; 964 uint32_t TemporalMvpEnableFlag : 1; //<= EnableTemporalMvp 965 uint32_t CollocatedFromL0Flag : 1; 966 uint32_t theSameRefList : 1; 967 uint32_t IsLowDelay : 1; 968 uint32_t DisableTemporal16and8 : 1; 969 uint32_t MBZ_3_7_1 : 1; 970 uint32_t MaxNumMergeCand : 8; 971 uint32_t NumRefIdxL0 : 8; 972 uint32_t NumRefIdxL1 : 8; 973 974 }; 975 }; 976 977 //R4.0 //DW24 978 union 979 { 980 uint32_t R4_0; 981 struct 982 { 983 uint32_t FwdPocNumber_L0_mTb_0 : 8; 984 uint32_t BwdPocNumber_L1_mTb_0 : 8; 985 uint32_t FwdPocNumber_L0_mTb_1 : 8; 986 uint32_t BwdPocNumber_L1_mTb_1 : 8; 987 }; 988 }; 989 990 //R4.1 //DW25 991 union 992 { 993 uint32_t R4_1; 994 struct 995 { 996 uint32_t FwdPocNumber_L0_mTb_2 : 8; 997 uint32_t BwdPocNumber_L1_mTb_2 : 8; 998 uint32_t FwdPocNumber_L0_mTb_3 : 8; 999 uint32_t BwdPocNumber_L1_mTb_3 : 8; 1000 }; 1001 }; 1002 1003 //R4.2 //DW26 1004 union 1005 { 1006 uint32_t R4_2; 1007 struct 1008 { 1009 uint32_t FwdPocNumber_L0_mTb_4 : 8; 1010 uint32_t BwdPocNumber_L1_mTb_4 : 8; 1011 uint32_t FwdPocNumber_L0_mTb_5 : 8; 1012 uint32_t BwdPocNumber_L1_mTb_5 : 8; 1013 }; 1014 }; 1015 1016 //R4.3 //DW27 1017 union 1018 { 1019 uint32_t R4_3; 1020 struct 1021 { 1022 uint32_t FwdPocNumber_L0_mTb_6 : 8; 1023 uint32_t BwdPocNumber_L1_mTb_6 : 8; 1024 uint32_t FwdPocNumber_L0_mTb_7 : 8; 1025 uint32_t BwdPocNumber_L1_mTb_7 : 8; 1026 }; 1027 }; 1028 1029 //R4.4 //DW28 1030 union 1031 { 1032 uint32_t R4_4; 1033 struct 1034 { 1035 uint32_t LongTermReferenceFlags_L0 : 16; 1036 uint32_t LongTermReferenceFlags_L1 : 16; 1037 }; 1038 }; 1039 1040 //R4.5 //DW29 1041 union 1042 { 1043 uint32_t R4_5; 1044 struct 1045 { 1046 uint32_t RefFrameWinWidth : 16; 1047 uint32_t RefFrameWinHeight : 16; 1048 }; 1049 }; 1050 1051 //R4.6 //DW30 1052 union 1053 { 1054 uint32_t R4_6; 1055 struct 1056 { 1057 uint32_t RoundingInter : 8; 1058 uint32_t RoundingIntra : 8; 1059 uint32_t MaxThreadWidth : 8; 1060 uint32_t MaxThreadHeight : 8; 1061 }; 1062 }; 1063 1064 //R4.7 - R5.7 1065 uint32_t Reserved2[9]; 1066 }; 1067 1068 static uint32_t const hevcCurbeBufferConstSize = 256; 1069 C_ASSERT(hevcCurbeBufferConstSize > sizeof(MBENC_CURBE)); 1070 1071 static const uint32_t maxColorBitSupport = 256; 1072 1073 struct CONCURRENT_THREAD_GROUP_DATA_BUF 1074 { 1075 CONCURRENT_THREAD_GROUP_DATA item[maxColorBitSupport]; 1076 }; 1077 1078 struct MBENC_COMBINED_BUFFER1 1079 { MBENC_COMBINED_BUFFER1MBENC_COMBINED_BUFFER11080 MBENC_COMBINED_BUFFER1() 1081 { 1082 MOS_ZeroMemory(&(this->concurrent), sizeof(this->concurrent)); 1083 } 1084 union 1085 { 1086 MBENC_CURBE Curbe; 1087 uint8_t Data[hevcCurbeBufferConstSize]; 1088 }; 1089 CONCURRENT_THREAD_GROUP_DATA_BUF concurrent; 1090 }; 1091 using PMBENC_COMBINED_BUFFER1 = MBENC_COMBINED_BUFFER1*; 1092 1093 static const uint32_t HEVC_HISTORY_BUF_CONST_SIZE = 64; 1094 static const uint32_t HEVC_FRAMEBRC_BUF_CONST_SIZE = 1024; 1095 static const uint32_t ENC_FRAME_LEVEL_DISTORTION_BUFFER = 64; 1096 1097 struct MBENC_COMBINED_BUFFER2 1098 { 1099 uint8_t ucBrcCombinedEncBuffer[HEVC_FRAMEBRC_BUF_CONST_SIZE]; 1100 uint8_t ucHistoryInBuffer[HEVC_HISTORY_BUF_CONST_SIZE]; 1101 }; 1102 using PMBENC_COMBINED_BUFFER2 = MBENC_COMBINED_BUFFER2*; 1103 1104 struct CODECHAL_HEVC_VIRTUAL_ENGINE_OVERRIDE 1105 { 1106 union { 1107 uint8_t VdBox[MOS_MAX_ENGINE_INSTANCE_PER_CLASS]; 1108 uint64_t Value; 1109 }; 1110 }; 1111 1112 //! \endcond 1113 1114 static const uint8_t m_maxNumVmeL0Ref = 4; //!< Maximum number of L0 references 1115 static const uint8_t m_maxNumVmeL1Ref = 4; //!< Maximum number of L1 references 1116 static const uint16_t m_maxThreadsPerLcuB = 8; //!< Maximum number of threads per LCU B 1117 static const uint16_t m_minThreadsPerLcuB = 3; //!< Minimum number of threads per LCU B 1118 1119 static const uint32_t m_encConstantDataLutSize = 81920; //!< Constant data LUT size in ints for B-kernel 1120 static const uint32_t m_brcBufferSize = 1024; //!< Size of the BRC buffer for Enc kernel 1121 static const uint32_t m_debugSurfaceSize = (8192 * 1024); //!< 8MB for the debug surface 1122 static const uint32_t m_maxThreadGprs = 256; //!< Maximum number of thread groups 1123 static const uint32_t m_brcLambdaModeCostTableSize = 416; //!< Size in DWs of Lambda Mode cost table for BRC 1124 static const uint32_t m_mvdistSummationSurfSize = 32; //!< Size of MV distortion summation surface 1125 static const uint8_t m_sumMVThreshold = 16; 1126 static const uint32_t m_hevcThreadTaskDataNum = 2; 1127 static const uint32_t m_maxWavefrontsforTU1 = 2; 1128 1129 static const uint8_t m_meMethod[NUM_TARGET_USAGE_MODES]; //!< ME method 1130 static const uint8_t m_aStep = 1; //!< A Stepping 1131 1132 static const uint32_t m_encLcu32ConstantDataLut[m_encConstantDataLutSize/sizeof(uint32_t)]; //!< Constant data table for B kernel 1133 static const uint32_t m_encLcu64ConstantDataLut[m_encConstantDataLutSize/sizeof(uint32_t)]; //!< Constant data table for B kernel 1134 static const uint32_t m_brcLcu32x32LambdaModeCostInit[m_brcLambdaModeCostTableSize]; //!< Lambda mode cost table for BRC LCU32x32 1135 static const uint32_t m_brcLcu64x64LambdaModeCostInit[m_brcLambdaModeCostTableSize]; //!< Lambda mode cost table for BRC LCU64x64 1136 1137 static const uint32_t m_mbencCurbeInit[40]; //!< Initialization data for MBENC B kernel 1138 static const BRC_INITRESET_CURBE m_brcInitResetCurbeInit; //!< Initialization data for BRC Init/Reset kernel 1139 static const BRCUPDATE_CURBE m_brcUpdateCurbeInit; //!< Initialization data for BRC update kernel 1140 static const uint8_t m_tuSettings[TotalTuParams][3]; //!< Table for TU based settings for different params 1141 1142 static const double m_modeBits[2][46][3]; //!< Mode bits LUT based on LCUType/Mode/SliceType 1143 static const double m_modeBitsScale[46][3]; //!< Mode bits LUT based on [mode][SliceType] 1144 1145 MOS_SURFACE m_currPicWithReconBoundaryPix = {}; //!< Current Picture with Reconstructed boundary pixels 1146 MOS_SURFACE m_lcuLevelInputDataSurface[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM] = {}; //!< In Gen11 Lculevel Data is a 2D surface instead of Buffer 1147 MOS_SURFACE m_intermediateCuRecordSurfaceLcu32 = {}; //!< Intermediate CU Record surface for I and B kernel 1148 MOS_SURFACE m_scratchSurface = {}; //!< Scratch surface for I-kernel 1149 CODECHAL_ENCODE_BUFFER m_debugSurface[4] = {}; //!< Debug surface used in MBENC kernels 1150 CODECHAL_ENCODE_BUFFER m_encConstantTableForB = {}; //!< Enc constant table for B LCU32 1151 CODECHAL_ENCODE_BUFFER m_mvAndDistortionSumSurface = {}; //!< Mv and Distortion summation surface 1152 1153 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 m_tileParams = nullptr; //!< Pointer to the Tile params 1154 1155 bool m_enableTileStitchByHW = false; //!< Enable HW to stitch commands in scalable mode 1156 bool m_enableHWSemaphore = false; //!< Enable HW semaphore 1157 bool m_weightedPredictionSupported = false; //!< Enable WP support 1158 bool m_useWeightedSurfaceForL0 = false; //!< Flag indicating if L0 Ref using weighted reference frame 1159 bool m_useWeightedSurfaceForL1 = false; //!< Flag indicating if L1 Ref using weighted reference frame 1160 bool m_sseEnabled = false; //!< Flag indicating if SSE is enabled in PAK 1161 bool m_degree45Needed = false; // Flag indicating if 45 degree dispatch pattern is used 1162 bool m_pakPiplStrmOutEnable = false; 1163 1164 uint16_t m_totalNumThreadsPerLcu = 0; //!< Total number of threads per LCU 1165 uint8_t m_modeCostRde[42] = { 0 }; //!< RDE cost 1166 uint8_t m_modeCostCre[16] = { 0 }; //!< CRE cost 1167 uint32_t m_lambdaRD = 0; //!< Lambda value to multiply the RD costs 1168 1169 uint32_t m_syntaxElementOnlyBitCnt = 0; 1170 uint8_t m_numberEncKernelSubThread = m_hevcThreadTaskDataNum; 1171 uint32_t m_numberConcurrentGroup = 4; // GEN11 can dividie one picture into several groups 1172 uint32_t m_numWavefrontInOneRegion = 0; 1173 uint16_t m_lastPictureCodingType = I_TYPE; 1174 uint8_t* m_swScoreboard = nullptr; 1175 bool m_useSwInitScoreboard = false; 1176 CODECHAL_ENCODE_BUFFER m_encBCombinedBuffer1[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM] = {}; 1177 CODECHAL_ENCODE_BUFFER m_encBCombinedBuffer2[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM] = {}; 1178 PCODECHAL_ENCODE_BUFFER m_brcInputForEncKernelBuffer = nullptr; 1179 uint8_t m_lastRecycledBufIdx = CODECHAL_ENCODE_RECYCLED_BUFFER_NUM - 1; 1180 uint32_t m_historyOutBufferSize = 0; 1181 uint32_t m_historyOutBufferOffset = 0; 1182 uint32_t m_threadTaskBufferSize = 0; 1183 uint32_t m_threadTaskBufferOffset = 0; 1184 uint32_t m_encFrameLevelDistortionBufferSize = 0; 1185 uint32_t m_encCtuLevelDistortionBufferSize = 0; 1186 bool m_initEncConstTable = true; 1187 bool m_enableBrcLTR = 1; //!< flag to enable long term reference BRC feature. 1188 bool m_isFrameLTR = 0; //!<flag to check if current frame is set as long term reference 1189 uint32_t m_ltrInterval = 0; //!< long term reference interval 1190 1191 CodechalKernelIntraDist *m_intraDistKernel = nullptr; 1192 CodechalEncodeSwScoreboard *m_swScoreboardState = nullptr; //!< pointer to SW scoreboard ini state. 1193 // scalability 1194 unsigned char m_numPipe = 1; //!< Number of pipes 1195 unsigned char m_numPassesInOnePipe = 1; //!< Number of PAK passes in one pipe 1196 CODECHAL_ENCODE_BUFFER m_resPakSliceLevelStreamoutData = {}; //!< Surface for slice level stream out data from PAK 1197 CODECHAL_HEVC_VIRTUAL_ENGINE_OVERRIDE m_kmdVeOveride = {}; //!< KMD override virtual engine index 1198 uint32_t m_numTiles = 1; //!< Number of tiles 1199 CODECHAL_ENCODE_BUFFER m_resHcpScalabilitySyncBuffer = {}; //!< Hcp sync buffer for scalability 1200 CODECHAL_ENCODE_BUFFER m_resTileBasedStatisticsBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC] = {}; 1201 CODECHAL_ENCODE_BUFFER m_resHuCPakAggregatedFrameStatsBuffer = {}; 1202 CODECHAL_ENCODE_BUFFER m_tileRecordBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC] = {}; 1203 HEVC_TILE_STATS_INFO m_hevcTileStatsOffset = {}; //!< Page aligned offsets used to program HCP / VDEnc pipe and HuC PAK Integration kernel input 1204 HEVC_TILE_STATS_INFO m_hevcFrameStatsOffset = {}; //!< Page aligned offsets used to program HuC PAK Integration kernel output, HuC BRC kernel input 1205 HEVC_TILE_STATS_INFO m_hevcStatsSize = {}; //!< HEVC Statistics size 1206 bool m_enableTestMediaReset = 0; //!< enable media reset test. driver will send cmd to make hang happens 1207 bool m_forceScalability = false; //!< force scalability for resolution < 4K if other checking for scalability passed 1208 1209 // HuC PAK stitch kernel 1210 bool m_hucPakStitchEnabled = false; //!< HuC PAK stitch enabled flag 1211 MOS_RESOURCE m_resHucPakStitchDmemBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][CODECHAL_DP_MAX_NUM_BRC_PASSES] = {}; 1212 MOS_RESOURCE m_resBrcDataBuffer = {}; //!< Resource of bitrate control data buffer 1213 MOS_RESOURCE m_resHucStitchDataBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][CODECHAL_HEVC_MAX_NUM_BRC_PASSES] = {}; // data buffer for huc input cmd generation 1214 MHW_BATCH_BUFFER m_HucStitchCmdBatchBuffer = {}; //!< SLB for huc stitch cmd 1215 1216 // virtual engine 1217 bool m_useVirtualEngine = false; //!< Virtual engine enable flag 1218 MOS_COMMAND_BUFFER m_veBatchBuffer[CODECHAL_NUM_UNCOMPRESSED_SURFACE_HEVC][CODECHAL_HEVC_MAX_NUM_HCP_PIPE][CODECHAL_HEVC_MAX_NUM_BRC_PASSES] = {}; //!< Virtual engine batch buffers 1219 MOS_COMMAND_BUFFER m_realCmdBuffer = {}; //!< Virtual engine command buffer 1220 uint32_t m_sizeOfVeBatchBuffer = 0; //!< Virtual engine batch buffer size 1221 unsigned char m_virtualEngineBbIndex = 0; //!< Virtual engine batch buffer index 1222 CODECHAL_ENCODE_BUFFER m_resBrcSemaphoreMem[CODECHAL_HEVC_MAX_NUM_HCP_PIPE] = {}; //!< BRC HW semaphore 1223 CODECHAL_ENCODE_BUFFER m_resBrcPakSemaphoreMem = {}; //!< BRC PAK HW semaphore 1224 MOS_RESOURCE m_resPipeStartSemaMem = {}; //!< HW semaphore for scalability pipe start at the same time 1225 MOS_RESOURCE m_resPipeCompleteSemaMem = {}; //!< HW semaphore for scalability pipe start at the same time 1226 PCODECHAL_ENCODE_SCALABILITY_STATE m_scalabilityState = nullptr; //!< Scalability state 1227 MOS_RESOURCE m_resDelayMinus = {}; 1228 uint32_t m_numDelay = 0; 1229 1230 // the following constant integers and tables are from the kernel for score board computation 1231 static uint32_t const m_ct = 3; 1232 static uint32_t const m_maxNumDependency = 32; 1233 static uint32_t const m_numDependencyHorizontal = 1; 1234 static uint32_t const m_numDependencyVertical = 1; 1235 static uint32_t const m_numDependency45Degree = 2; 1236 static uint32_t const m_numDependency26Degree = 3; 1237 static uint32_t const m_numDependency45xDegree = 3 + (m_ct - 1); 1238 static uint32_t const m_numDependency26xDegree = 4 + (m_ct - 1); 1239 static uint32_t const m_numDependency45xDegreeAlt = 2; 1240 static uint32_t const m_numDependency26xDegreeAlt = 3; 1241 static uint32_t const m_numDependency45xVp9Degree = 4; 1242 static uint32_t const m_numDependency26zDegree = 5; 1243 static uint32_t const m_numDependency26ZigDegree = 6; 1244 static uint32_t const m_numDependencyNone = 0; 1245 static uint32_t const m_numDependencyCustom = 0; 1246 static const char m_dxWavefrontHorizontal[m_maxNumDependency]; 1247 static const char m_dyWavefrontHorizontal[m_maxNumDependency]; 1248 static const char m_dxWavefrontVertical[m_maxNumDependency]; 1249 static const char m_dyWavefrontVertical[m_maxNumDependency]; 1250 static const char m_dxWavefront45Degree[m_maxNumDependency]; 1251 static const char m_dyWavefront45Degree[m_maxNumDependency]; 1252 static const char m_dxWavefront26Degree[m_maxNumDependency]; 1253 static const char m_dyWavefront26Degree[m_maxNumDependency]; 1254 static const char m_dxWavefront45xDegree[m_maxNumDependency]; 1255 static const char m_dyWavefront45xDegree[m_maxNumDependency]; 1256 static const char m_dxWavefront26xDegree[m_maxNumDependency]; 1257 static const char m_dyWavefront26xDegree[m_maxNumDependency]; 1258 static const char m_dxWavefront45xDegreeAlt[m_maxNumDependency]; 1259 static const char m_dyWavefront45xDegreeAlt[m_maxNumDependency]; 1260 static const char m_dxWavefront26xDegreeAlt[m_maxNumDependency]; 1261 static const char m_dyWavefront26xDegreeAlt[m_maxNumDependency]; 1262 static const char m_dxWavefront45xVp9Degree[m_maxNumDependency]; 1263 static const char m_dyWavefront45xVp9Degree[m_maxNumDependency]; 1264 static const char m_dxWavefront26zDegree[m_maxNumDependency]; 1265 static const char m_dyWavefront26zDegree[m_maxNumDependency]; 1266 static const char m_dxWavefront26ZigDegree[m_maxNumDependency]; 1267 static const char m_dyWavefront26ZigDegree[m_maxNumDependency]; 1268 static const char m_dxWavefrontNone[m_maxNumDependency]; 1269 static const char m_dyWavefrontNone[m_maxNumDependency]; 1270 static const char m_dxWavefrontCustom[m_maxNumDependency]; 1271 static const char m_dyWavefrontCustom[m_maxNumDependency]; 1272 1273 //! 1274 //! \brief Constructor 1275 //! 1276 CodechalEncHevcStateG11(CodechalHwInterface* hwInterface, 1277 CodechalDebugInterface* debugInterface, 1278 PCODECHAL_STANDARD_INFO standardInfo); 1279 1280 //! 1281 //! \brief Copy constructor 1282 //! 1283 CodechalEncHevcStateG11(const CodechalEncHevcStateG11&) = delete; 1284 1285 //! 1286 //! \brief Copy assignment operator 1287 //! 1288 CodechalEncHevcStateG11& operator=(const CodechalEncHevcStateG11&) = delete; 1289 1290 //! 1291 //! \brief Destructor 1292 //! 1293 ~CodechalEncHevcStateG11(); 1294 1295 //! 1296 //! \brief Help function to get current pipe 1297 //! 1298 //! \return Current pipe value 1299 //! GetCurrentPipe()1300 int GetCurrentPipe() 1301 { 1302 if (m_numPipe <= 1) 1303 { 1304 return 0; 1305 } 1306 1307 return (int)(m_currPass) % (int)m_numPipe; 1308 } 1309 1310 //! 1311 //! \brief Help function to get current PAK pass 1312 //! 1313 //! \return Current PAK pass 1314 //! GetCurrentPass()1315 int GetCurrentPass() 1316 { 1317 if (m_numPipe <= 1) 1318 { 1319 return m_currPass; 1320 } 1321 1322 return (int)(m_currPass) / (int)m_numPipe; 1323 } 1324 1325 //! 1326 //! \brief Help function to check if current pipe is first pipe 1327 //! 1328 //! \return True if current pipe is first pipe, otherwise return false 1329 //! IsFirstPipe()1330 bool IsFirstPipe() 1331 { 1332 return GetCurrentPipe() == 0 ? true : false; 1333 } 1334 1335 //! 1336 //! \brief Help function to check if current pipe is last pipe 1337 //! 1338 //! \return True if current pipe is last pipe, otherwise return false 1339 //! IsLastPipe()1340 bool IsLastPipe() 1341 { 1342 return GetCurrentPipe() == m_numPipe - 1 ? true : false; 1343 } 1344 1345 //! 1346 //! \brief Help function to check if current PAK pass is first pass 1347 //! 1348 //! \return True if current PAK pass is first pass, otherwise return false 1349 //! IsFirstPass()1350 bool IsFirstPass() 1351 { 1352 return GetCurrentPass() == 0 ? true : false; 1353 } 1354 1355 //! 1356 //! \brief Help function to check if current PAK pass is last pass 1357 //! 1358 //! \return True if current PAK pass is last pass, otherwise return false 1359 //! IsLastPass()1360 bool IsLastPass() 1361 { 1362 return GetCurrentPass() == m_numPassesInOnePipe ? true : false; 1363 } 1364 1365 // inherited virtual functions 1366 MOS_STATUS SetPictureStructs(); 1367 1368 MOS_STATUS CalcScaledDimensions(); 1369 1370 MOS_STATUS InitializePicture(const EncoderParams& params); 1371 1372 MOS_STATUS ExecutePictureLevel(); 1373 1374 MOS_STATUS ExecuteSliceLevel(); 1375 1376 MOS_STATUS Initialize(CodechalSetting * settings); 1377 1378 virtual MOS_STATUS InitKernelState(); 1379 1380 uint32_t GetMaxBtCount(); 1381 1382 bool CheckSupportedFormat(PMOS_SURFACE surface); 1383 1384 MOS_STATUS EncodeKernelFunctions(); 1385 1386 virtual MOS_STATUS EncodeMeKernel(); 1387 1388 virtual MOS_STATUS AllocateEncResources(); 1389 1390 virtual MOS_STATUS FreeEncResources(); 1391 1392 MOS_STATUS AllocatePakResources(); 1393 1394 MOS_STATUS FreePakResources(); 1395 1396 void CreateMhwParams(); 1397 1398 void GetMaxRefFrames(uint8_t& maxNumRef0, uint8_t& maxNumRef1); 1399 1400 void SetHcpSliceStateCommonParams(MHW_VDBOX_HEVC_SLICE_STATE& sliceStateParams); 1401 1402 MOS_STATUS PlatformCapabilityCheck(); 1403 1404 MOS_STATUS GetStatusReport( 1405 EncodeStatus *encodeStatus, 1406 EncodeStatusReport *encodeStatusReport); 1407 MOS_STATUS SetRegionsHuCPakIntegrate(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams); 1408 MOS_STATUS SetDmemHuCPakIntegrate(PMHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams); 1409 MOS_STATUS SetRegionsHuCPakIntegrateCqp(PMHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams); 1410 MOS_STATUS SetDmemHuCPakIntegrateCqp(PMHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams); 1411 MOS_STATUS ReadBrcPakStatisticsForScalability(PMOS_COMMAND_BUFFER cmdBuffer); 1412 1413 #if (_DEBUG || _RELEASE_INTERNAL) 1414 MOS_STATUS ResetImgCtrlRegInPAKStatisticsBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 1415 #endif 1416 1417 MOS_STATUS VerifyCommandBufferSize(); 1418 1419 MOS_STATUS GetCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 1420 1421 MOS_STATUS ReturnCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer); 1422 1423 MOS_STATUS SubmitCommandBuffer( 1424 PMOS_COMMAND_BUFFER cmdBuffer, 1425 bool bNullRendering); 1426 1427 MOS_STATUS SendPrologWithFrameTracking( 1428 PMOS_COMMAND_BUFFER cmdBuffer, 1429 bool frameTrackingRequested, 1430 MHW_MI_MMIOREGISTERS *mmioRegister = nullptr); 1431 1432 MOS_STATUS SetSliceStructs(); 1433 1434 MOS_STATUS AllocateTileStatistics(); 1435 1436 void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams); 1437 void SetHcpPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams); 1438 void SetHcpPicStateParams(MHW_VDBOX_HEVC_PIC_STATE& picStateParams); 1439 1440 MOS_STATUS ReadSseStatistics(PMOS_COMMAND_BUFFER cmdBuffer); 1441 1442 MOS_STATUS SetGpuCtxCreatOption(); 1443 1444 //! 1445 //! \brief Decide number of pipes used for encoding 1446 //! \details called inside PlatformCapabilityCheck 1447 //! 1448 //! \return MOS_STATUS 1449 //! MOS_STATUS_SUCCESS if success, else fail reason 1450 //! 1451 MOS_STATUS DecideEncodingPipeNumber(); 1452 1453 //! 1454 //! \brief Get U62 Mode bits 1455 //! 1456 //! \return 8 bit mode cost for RDE 1457 //! GetU62ModeBits(float mcost)1458 inline uint8_t GetU62ModeBits(float mcost) 1459 { 1460 return (uint8_t)(mcost * 4 + 0.5); 1461 } 1462 1463 //! 1464 //! \brief Update surface info for YUY2 input 1465 //! 1466 //! \param [in] surface 1467 //! Reference to input surface 1468 //! \param [in] is10Bit 1469 //! Flag to indicate if 10 bit 1470 //! 1471 //! \return MOS_STATUS 1472 //! MOS_STATUS_SUCCESS if success, else fail reason 1473 //! 1474 MOS_STATUS UpdateYUY2SurfaceInfo( 1475 MOS_SURFACE& surface, 1476 bool is10Bit); 1477 1478 //! 1479 //! \brief Allocate ME resources 1480 //! 1481 //! \return MOS_STATUS 1482 //! MOS_STATUS_SUCCESS if success, else fail reason 1483 //! 1484 MOS_STATUS AllocateMeResources(); 1485 1486 //! 1487 //! \brief Free ME resources 1488 //! 1489 //! \return MOS_STATUS 1490 //! MOS_STATUS_SUCCESS if success, else fail reason 1491 //! 1492 MOS_STATUS FreeMeResources(); 1493 1494 //! 1495 //! \brief Encode command at tile level 1496 //! 1497 //! \return MOS_STATUS 1498 //! MOS_STATUS_SUCCESS if success, else fail reason 1499 //! 1500 MOS_STATUS EncTileLevel(); 1501 1502 //! 1503 //! \brief Get encoder kernel header and kernel size 1504 //! 1505 //! \param [in] binary 1506 //! Pointer to kernel binary 1507 //! \param [in] operation 1508 //! Enc kernel operation 1509 //! \param [in] krnStateIdx 1510 //! Kernel state index 1511 //! \param [out] krnHeader 1512 //! Pointer to kernel header 1513 //! \param [out] krnSize 1514 //! Pointer to kernel size 1515 //! 1516 //! \return MOS_STATUS 1517 //! MOS_STATUS_SUCCESS if success, else fail reason 1518 //! 1519 static MOS_STATUS GetKernelHeaderAndSize( 1520 void* binary, 1521 EncOperation operation, 1522 uint32_t krnStateIdx, 1523 void* krnHeader, 1524 uint32_t* krnSize); 1525 1526 //! 1527 //! \brief Get encoder kernel header and kernel size 1528 //! 1529 //! \param [in] encOperation 1530 //! Specifies the media function type 1531 //! \param [in] kernelParams 1532 //! Pointer to kernel parameters 1533 //! \param [in] idx 1534 //! MbEnc/BRC kernel index 1535 //! 1536 //! \return MOS_STATUS 1537 //! MOS_STATUS_SUCCESS if success, else fail reason 1538 //! 1539 MOS_STATUS SetKernelParams( 1540 EncOperation encOperation, 1541 MHW_KERNEL_PARAM* kernelParams, 1542 uint32_t idx); 1543 1544 //! 1545 //! \brief Set Binding table for different kernelsge 1546 //! 1547 //! \param [in] encOperation 1548 //! Specifies the media function type 1549 //! \param [in] hevcEncBindingTable 1550 //! Pointer to the binding table 1551 //! \param [in] idx 1552 //! MbEnc/BRC kernel index 1553 //! 1554 //! \return MOS_STATUS 1555 //! MOS_STATUS_SUCCESS if success, else fail reason 1556 //! 1557 MOS_STATUS SetBindingTable( 1558 EncOperation encOperation, 1559 PCODECHAL_ENCODE_BINDING_TABLE_GENERIC hevcEncBindingTable, 1560 uint32_t idx); 1561 1562 //! 1563 //! \brief Initialize MbEnc kernel state 1564 //! 1565 //! \return MOS_STATUS 1566 //! MOS_STATUS_SUCCESS if success, else fail reason 1567 //! 1568 MOS_STATUS InitKernelStateMbEnc(); 1569 1570 //! 1571 //! \brief Initialize BRC kernel state 1572 //! 1573 //! \return MOS_STATUS 1574 //! MOS_STATUS_SUCCESS if success, else fail reason 1575 //! 1576 MOS_STATUS InitKernelStateBrc(); 1577 1578 //! 1579 //! \brief Invoke BRC Init/Reset kernel 1580 //! 1581 //! \return MOS_STATUS 1582 //! MOS_STATUS_SUCCESS if success, else fail reason 1583 //! 1584 MOS_STATUS EncodeBrcInitResetKernel(); 1585 1586 //! 1587 //! \brief Send surfaces BRC Init/Reset kernel 1588 //! 1589 //! \param [in] cmdBuffer 1590 //! Pointer to command buffer 1591 //! \param [in] krnIdx 1592 //! Index of the BRC kernel for which surfaces are being sent 1593 //! \return MOS_STATUS 1594 //! MOS_STATUS_SUCCESS if success, else fail reason 1595 //! 1596 MOS_STATUS SendBrcInitResetSurfaces( 1597 PMOS_COMMAND_BUFFER cmdBuffer, 1598 CODECHAL_HEVC_BRC_KRNIDX krnIdx); 1599 1600 //! 1601 //! \brief Setup Curbe for BRC Init/Reset kernel 1602 //! 1603 //! \param [in] brcKrnIdx 1604 //! Index of the BRC kernel for which Curbe is setup 1605 //! \return MOS_STATUS 1606 //! MOS_STATUS_SUCCESS if success, else fail reason 1607 //! 1608 MOS_STATUS SetCurbeBrcInitReset(CODECHAL_HEVC_BRC_KRNIDX brcKrnIdx); 1609 1610 //! 1611 //! \brief Invoke frame level BRC update kernel 1612 //! 1613 //! \return MOS_STATUS 1614 //! MOS_STATUS_SUCCESS if success, else fail reason 1615 //! 1616 MOS_STATUS EncodeBrcFrameUpdateKernel(); 1617 1618 //! 1619 //! \brief Send surfaces for BRC Frame Update kernel 1620 //! 1621 //! \param [in] cmdBuffer 1622 //! Pointer to command buffer 1623 //! \return MOS_STATUS 1624 //! MOS_STATUS_SUCCESS if success, else fail reason 1625 //! 1626 MOS_STATUS SendBrcFrameUpdateSurfaces(PMOS_COMMAND_BUFFER cmdBuffer); 1627 1628 //! 1629 //! \brief Setup Curbe for BRC Update kernel 1630 //! 1631 //! \param [in] brcKrnIdx 1632 //! Index of the BRC update kernel(frame or lcu) for which Curbe is setup 1633 //! \return MOS_STATUS 1634 //! MOS_STATUS_SUCCESS if success, else fail reason 1635 //! 1636 MOS_STATUS SetCurbeBrcUpdate(CODECHAL_HEVC_BRC_KRNIDX brcKrnIdx); 1637 1638 //! 1639 //! \brief Invoke LCU level BRC update kernel 1640 //! 1641 //! \return MOS_STATUS 1642 //! MOS_STATUS_SUCCESS if success, else fail reason 1643 //! 1644 MOS_STATUS EncodeBrcLcuUpdateKernel(); 1645 1646 //! 1647 //! \brief Send surfaces for BRC LCU Update kernel 1648 //! 1649 //! \param [in] cmdBuffer 1650 //! Pointer to command buffer 1651 //! \return MOS_STATUS 1652 //! MOS_STATUS_SUCCESS if success, else fail reason 1653 //! 1654 MOS_STATUS SendBrcLcuUpdateSurfaces(PMOS_COMMAND_BUFFER cmdBuffer); 1655 1656 //! 1657 //! \brief Top level function for invoking MBenc kernel 1658 //! \details I, B or LCU64_B MBEnc kernel, based on encFunctionType 1659 //! \param [in] encFunctionType 1660 //! Specifies the media state type 1661 //! \return MOS_STATUS 1662 //! MOS_STATUS_SUCCESS if success, else fail reason 1663 //! 1664 virtual MOS_STATUS EncodeMbEncKernel(CODECHAL_MEDIA_STATE_TYPE encFunctionType); 1665 1666 //! 1667 //! \brief Send Surfaces for MbEnc kernel 1668 //! 1669 //! \param [in] cmdBuffer 1670 //! Pointer to command buffer 1671 //! 1672 //! \return MOS_STATUS 1673 //! MOS_STATUS_SUCCESS if success, else fail reason 1674 //! 1675 MOS_STATUS SendMbEncSurfacesKernel(PMOS_COMMAND_BUFFER cmdBuffer); 1676 1677 //! 1678 //! \brief Setup Curbe for MbEnc LCU32 and LCU64_32 Kernels 1679 //! 1680 //! \return MOS_STATUS 1681 //! MOS_STATUS_SUCCESS if success, else fail reason 1682 //! 1683 MOS_STATUS SetCurbeMbEncKernel(); 1684 1685 //! 1686 //! \brief Generate LCU Level Data 1687 //! 1688 //! \param [in] lcuLevelInputDataSurfaceParam 1689 //! input lcu surface 1690 //! \return MOS_STATUS 1691 //! MOS_STATUS_SUCCESS if success, else fail reason 1692 //! 1693 MOS_STATUS GenerateLcuLevelData(MOS_SURFACE &lcuLevelInputDataSurfaceParam); 1694 1695 //! 1696 //! \brief Load cost table 1697 //! 1698 //! \param [in] sliceType 1699 //! Slice Type 1700 //! \param [in] qp 1701 //! QP value 1702 //! 1703 //! \return void 1704 //! 1705 void LoadCosts(uint8_t sliceType, uint8_t qp); 1706 1707 //! 1708 //! \brief Prepare walker params for custom pattern thread dispatch 1709 //! 1710 //! \param [in] walkerParams 1711 //! Pointer to HW walker params 1712 //! \param [in] walkerCodecParams 1713 //! Input params to program the HW walker 1714 //! 1715 //! \return MOS_STATUS 1716 //! MOS_STATUS_SUCCESS if success, else fail reason 1717 //! 1718 MOS_STATUS GetCustomDispatchPattern( 1719 PMHW_WALKER_PARAMS walkerParams, 1720 PCODECHAL_WALKER_CODEC_PARAMS walkerCodecParams); 1721 1722 //! 1723 //! \brief Generate concurrent thread group data 1724 //! 1725 //! \return MOS_STATUS 1726 //! MOS_STATUS_SUCCESS if success, else fail reason 1727 //! 1728 MOS_STATUS GenerateConcurrentThreadGroupData(); 1729 1730 //! 1731 //! \brief Load Pak command and CuRecord from file 1732 //! 1733 //! \return MOS_STATUS 1734 //! MOS_STATUS_SUCCESS if success, else fail reason 1735 //! 1736 MOS_STATUS LoadPakCommandAndCuRecordFromFile(); 1737 1738 //! 1739 //! \brief Resize buffers due to resoluton change. 1740 //! \details Resize buffers due to resoluton change. 1741 //! 1742 //! \return void 1743 //! 1744 virtual void ResizeOnResChange(); 1745 1746 //! 1747 //! \brief Re-calculate buffer size and offets during resolution reset 1748 //! 1749 //! \return void 1750 //! 1751 void ResizeBufferOffset(); 1752 1753 //! 1754 //! \brief Set HCP_SLICE_STATE parameters that are different at slice level 1755 //! 1756 //! \param [in, out] sliceState 1757 //! HCP_SLICE_STATE parameters 1758 //! \param [in] slcData 1759 //! Pointer to CODEC_ENCODE_SLCDATA 1760 //! \param [in] slcCount 1761 //! Current slice index 1762 //! \param [in] tileCodingParams 1763 //! Pointer to TileCodingParams 1764 //! \param [in] lastSliceInTile 1765 //! Flag to indicate if slice is the last one in the tile 1766 //! \param [in] idx 1767 //! Index of the tile 1768 //! 1769 //! \return void 1770 //! 1771 void SetHcpSliceStateParams( 1772 MHW_VDBOX_HEVC_SLICE_STATE& sliceState, 1773 PCODEC_ENCODER_SLCDATA slcData, 1774 uint16_t slcCount, 1775 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 tileCodingParams, 1776 bool lastSliceInTile, 1777 uint32_t idx); 1778 1779 //! 1780 //! \brief Setup BRC constant data 1781 //! 1782 //! \param [in, out] brcConstantData 1783 //! Pointer to BRC constant data surface 1784 //! 1785 //! \return MOS_STATUS 1786 //! MOS_STATUS_SUCCESS if success, else fail reason 1787 //! 1788 MOS_STATUS SetupBrcConstantTable(PMOS_SURFACE brcConstantData); 1789 1790 //! 1791 //! \brief Check whether Scalability is enabled or not, 1792 //! Set number of VDBoxes accordingly 1793 //! 1794 //! \return MOS_STATUS 1795 //! MOS_STATUS_SUCCESS if success, else fail reason 1796 //! 1797 MOS_STATUS GetSystemPipeNumberCommon(); 1798 1799 bool IsDegree45Needed(); 1800 1801 void DecideConcurrentGroupAndWaveFrontNumber(); 1802 1803 MOS_STATUS UserFeatureKeyReport(); 1804 1805 MOS_STATUS SetupSwScoreBoard(CodechalEncodeSwScoreboard::KernelParams *params); 1806 1807 void InitSWScoreboard( 1808 uint8_t* scoreboard, 1809 uint32_t scoreboardWidth, 1810 uint32_t scoreboardHeight, 1811 uint32_t dependencyPattern, 1812 char childThreadNumber); 1813 1814 uint8_t PicCodingTypeToSliceType(uint16_t pictureCodingType); 1815 1816 MOS_STATUS InitMediaObjectWalker( 1817 uint32_t threadSpaceWidth, 1818 uint32_t threadSpaceHeight, 1819 uint32_t colorCountMinusOne, 1820 DependencyPattern dependencyPattern, 1821 uint32_t childThreadNumber, 1822 uint32_t localLoopExecCount, 1823 MHW_WALKER_PARAMS& walkerParams); 1824 1825 void SetDependency(uint8_t &numDependencies, 1826 char* scoreboardDeltaX, 1827 char* scoreboardDeltaY, 1828 uint32_t dependencyPattern, 1829 char childThreadNumber); 1830 1831 //! 1832 //! \brief Dump HuC based debug output buffers 1833 //! 1834 //! \return MOS_STATUS 1835 //! MOS_STATUS_SUCCESS if success, else fail reason 1836 //! 1837 MOS_STATUS DumpHucDebugOutputBuffers(); 1838 1839 void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams); 1840 MOS_STATUS AddHcpPipeModeSelectCmd(MOS_COMMAND_BUFFER* cmdBuffer); 1841 1842 MOS_STATUS CalculatePictureStateCommandSize(); 1843 1844 MOS_STATUS AddHcpPipeBufAddrCmd( 1845 PMOS_COMMAND_BUFFER cmdBuffer); 1846 1847 //! 1848 //! \brief Is slice in the current tile 1849 //! 1850 //! \param [in] sliceNumber 1851 //! Slice number 1852 //! \param [in] currentTile 1853 //! Pointer to current tile coding params 1854 //! \param [out] sliceInTile 1855 //! Pointer to return if slice in tile 1856 //! \param [out] lastSliceInTile 1857 //! Pointer to return if last slice in tile 1858 //! 1859 //! \return MOS_STATUS 1860 //! MOS_STATUS_SUCCESS if success, else fail reason 1861 //! 1862 MOS_STATUS IsSliceInTile( 1863 uint32_t sliceNumber, 1864 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 currentTile, 1865 bool *sliceInTile, 1866 bool *lastSliceInTile); 1867 1868 //! 1869 //! \brief Set tile data 1870 //! 1871 //! \param [in] tileCodingParams 1872 //! Pointer to tile coding params 1873 //! \return MOS_STATUS 1874 //! MOS_STATUS_SUCCESS if success, else fail reason 1875 //! 1876 MOS_STATUS SetTileData(MHW_VDBOX_HCP_TILE_CODING_PARAMS_G11* tileCodingParams, uint32_t bistreamBufSize); 1877 1878 //! 1879 //! \brief Set And Populate VE Hint parameters 1880 //! \details Set Virtual Engine hint parameter and populate it to primary cmd buffer attributes 1881 //! \param [in] cmdBuffer 1882 //! Pointer to primary cmd buffer 1883 //! \return MOS_STATUS 1884 //! MOS_STATUS_SUCCESS if success, else fail reason 1885 //! 1886 MOS_STATUS SetAndPopulateVEHintParams( 1887 PMOS_COMMAND_BUFFER cmdBuffer); 1888 1889 //! 1890 //! \brief HuC PAK integrate 1891 //! 1892 //! \param [in] cmdBuffer 1893 //! Pointer to command buffer 1894 //! 1895 //! \return MOS_STATUS 1896 //! MOS_STATUS_SUCCESS if success, else fail reason 1897 //! 1898 MOS_STATUS HucPakIntegrate( 1899 PMOS_COMMAND_BUFFER cmdBuffer); 1900 1901 MOS_STATUS UpdateCmdBufAttribute( 1902 PMOS_COMMAND_BUFFER cmdBuffer, 1903 bool renderEngineInUse); 1904 1905 //! 1906 //! \brief Configue stitch data buffer as Huc Pak Integration input 1907 //! 1908 //! \return MOS_STATUS 1909 //! MOS_STATUS_SUCCESS if success, else fail reason 1910 //! 1911 MOS_STATUS ConfigStitchDataBuffer(); 1912 1913 //! 1914 //! \brief allocate resources with sizes varying from frame to frame 1915 //! \return MOS_STATUS 1916 //! MOS_STATUS_SUCCESS if success, else fail reason 1917 //! 1918 MOS_STATUS AllocateResourcesVariableSize(); 1919 1920 #if USE_CODECHAL_DEBUG_TOOL 1921 //! 1922 //! \brief Dump PAK output buffer 1923 //! 1924 //! \return MOS_STATUS 1925 //! MOS_STATUS_SUCCESS if success, else fail reason 1926 //! 1927 MOS_STATUS DumpPakOutput(); 1928 1929 MOS_STATUS DumpFrameStatsBuffer(CodechalDebugInterface* debugInterface); 1930 #endif 1931 }; 1932 1933 //! \brief typedef of class CodechalEncHevcStateG11* 1934 using PCODECHAL_ENC_HEVC_STATE_G11 = class CodechalEncHevcStateG11*; 1935 1936 #endif // __CODECHAL_ENCODE_HEVC_G11_H__ 1937