1 /*
2 * Copyright (c) 2021-2022, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_vdbox_hcp_cmdpar.h
24 //! \brief MHW command parameters
25 //! \details
26 //!
27
28 #ifndef __MHW_VDBOX_HCP_CMDPAR_H__
29 #define __MHW_VDBOX_HCP_CMDPAR_H__
30
31 #include <functional>
32 #include "codec_def_decode_hevc.h"
33 #include "codec_def_encode_hevc.h"
34 #include "mhw_vdbox.h"
35 #include "mhw_vdbox_cmdpar.h"
36
37 namespace mhw
38 {
39 namespace vdbox
40 {
41 namespace hcp
42 {
43 enum class SURFACE_FORMAT
44 {
45 SURFACE_FORMAT_YUY2FORMAT = 0, //!< No additional details
46 SURFACE_FORMAT_RGB8FORMAT = 1, //!< No additional details
47 SURFACE_FORMAT_AYUV4444FORMAT = 2, //!< No additional details
48 SURFACE_FORMAT_P010VARIANT = 3, //!< No additional details
49 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details
50 SURFACE_FORMAT_YCRCBSWAPYFORMAT = 5, //!< No additional details
51 SURFACE_FORMAT_YCRCBSWAPUVFORMAT = 6, //!< No additional details
52 SURFACE_FORMAT_YCRCBSWAPUVYFORMAT = 7, //!< No additional details
53 SURFACE_FORMAT_Y216Y210FORMAT = 8, //!< Same value is used to represent Y216 and Y210
54 SURFACE_FORMAT_RGB10FORMAT = 9, //!< No additional details
55 SURFACE_FORMAT_Y410FORMAT = 10, //!< No additional details
56 SURFACE_FORMAT_NV21PLANAR4208FORMAT = 11, //!< No additional details
57 SURFACE_FORMAT_Y416FORMAT = 12, //!< No additional details
58 SURFACE_FORMAT_P010 = 13, //!< No additional details
59 SURFACE_FORMAT_P016 = 14, //!< No additional details
60 SURFACE_FORMAT_Y8FORMAT = 15, //!< No additional details
61 SURFACE_FORMAT_Y16FORMAT = 16, //!< No additional details
62 SURFACE_FORMAT_Y216VARIANT = 17, //!< Y216Variant is the modifed Y210/Y216 format, 8 bit planar 422 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The chroma is UV interleaved with identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma.
63 SURFACE_FORMAT_Y416VARIANT = 18, //!< Y416Variant is the modifed Y410/Y412/Y416 format,8 bit planar 444 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The U channel is below the luma, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma The V channel is below the U, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma.
64 SURFACE_FORMAT_YUY2VARIANT = 19, //!< YUY2Variant is the modifed YUY2 format, 8 bit planar 422. The chroma is UV interleaved and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma.
65 SURFACE_FORMAT_AYUV4444VARIANT = 20, //!< AYUV4444Variant is the modifed AYUV4444 format, 8 bit planar 444 format. The U channel is below the luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. The V channel is below the and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma.
66 };
67
68 enum class HCP_INTERNAL_BUFFER_TYPE
69 {
70 DBLK_LINE = 0x0,
71 DBLK_TILE_LINE,
72 DBLK_TILE_COL,
73 MV_UP_RT_COL,
74 META_LINE,
75 META_TILE_LINE,
76 META_TILE_COL,
77 TR_NBR,
78 SAO_LINE,
79 SAO_TILE_LINE,
80 SAO_TILE_COL,
81 HSSE_RS,
82 HSAO_RS,
83 CURR_MV_TEMPORAL,
84 COLL_MV_TEMPORAL,
85 SLC_STATE_STREAMOUT,
86 CABAC_STREAMOUT,
87 MV_UP_RIGHT_COL,
88 INTRA_PRED_UP_RIGHT_COL,
89 INTRA_PRED_LFT_RECON_COL,
90 SEGMENT_ID,
91 HVD_LINE,
92 HVD_TILE
93 };
94
95 struct HcpMmioRegisters
96 {
97 uint32_t watchdogCountCtrlOffset;
98 uint32_t watchdogCountThresholdOffset;
99 uint32_t hcpDebugFEStreamOutSizeRegOffset;
100 uint32_t hcpEncImageStatusMaskRegOffset;
101 uint32_t hcpEncImageStatusCtrlRegOffset;
102 uint32_t hcpEncBitstreamBytecountFrameRegOffset;
103 uint32_t hcpEncBitstreamSeBitcountFrameRegOffset;
104 uint32_t hcpEncBitstreamBytecountFrameNoHeaderRegOffset;
105 uint32_t hcpEncQpStatusCountRegOffset;
106 uint32_t hcpEncSliceCountRegOffset;
107 uint32_t hcpEncVdencModeTimerRegOffset;
108 uint32_t hcpVp9EncBitstreamBytecountFrameRegOffset;
109 uint32_t hcpVp9EncBitstreamBytecountFrameNoHeaderRegOffset;
110 uint32_t hcpVp9EncImageStatusMaskRegOffset;
111 uint32_t hcpVp9EncImageStatusCtrlRegOffset;
112 uint32_t csEngineIdOffset;
113 uint32_t hcpDecStatusRegOffset;
114 uint32_t hcpCabacStatusRegOffset;
115 uint32_t hcpFrameCrcRegOffset;
116 };
117
118 struct HcpBufferSizePar
119 {
120 HCP_INTERNAL_BUFFER_TYPE bufferType;
121 uint8_t ucMaxBitDepth;
122 uint8_t ucChromaFormat;
123 uint32_t dwCtbLog2SizeY;
124 uint32_t dwPicWidth;
125 uint32_t dwPicHeight;
126 uint32_t dwMaxFrameSize;
127 uint32_t dwBufferSize;
128 };
129
130 struct HcpVdboxRowStorePar
131 {
132 uint32_t Mode;
133 uint32_t dwPicWidth;
134 uint32_t bMbaff;
135 bool bIsFrame;
136 uint8_t ucBitDepthMinus8;
137 uint8_t ucChromaFormat;
138 uint8_t ucLCUSize;
139 };
140
141 struct HCPPakHWTileSizeRecord
142 {
143 uint32_t Address_31_0; //DW0
144 uint32_t Address_63_32; //DW1
145 uint32_t Length; //DW2 Bitstream length per tile; includes header len in first tile, and tail len in last tile
146 uint32_t TileSize; //DW3 In Vp9, it is used for back annotation, In Hevc, it is the mmio register bytecountNoHeader
147 uint32_t AddressOffset; //DW4 Cacheline offset
148
149 //DW5
150 uint32_t
151 ByteOffset : 6, //[5:0] // Byte offset within cacheline
152 Res_95_70 : 26; //[31:6]
153
154 uint32_t Hcp_Bs_SE_Bitcount_Tile; //DW6 Bitstream size for syntax element per tile
155 uint32_t Hcp_Cabac_BinCnt_Tile; //DW7 Bitstream size for syntax element per tile
156 uint32_t Res_DW8_31_0; //DW8
157 uint32_t Hcp_Image_Status_Ctrl; //DW9 Image status control per tile
158 uint32_t Hcp_Qp_Status_Count; //DW10 Qp status count per tile
159 uint32_t Hcp_Slice_Count_Tile; //DW11 Number of slices per tile
160 uint32_t Res_DW12_DW15[4]; //DW12-15 Reserved bits added so that QwordDisables are set correctly
161 };
162
163 enum CommandsNumberOfAddresses
164 {
165 MI_BATCH_BUFFER_START_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
166 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
167 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
168 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
169 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
170 MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 4, // 4 DW for 2 address fields
171 MI_SEMAPHORE_WAIT_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address fields
172 MI_ATOMIC_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field
173
174 MFX_WAIT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
175
176 HCP_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
177 HCP_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
178 HCP_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 45, // 45 address fields
179 HCP_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 11, // 22 DW for 11 address field
180 HCP_QM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
181 HCP_FQM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
182 HCP_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
183 HCP_REF_IDX_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
184 HCP_WEIGHTOFFSET_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
185 HCP_SLICE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
186 HCP_PAK_INSERT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
187 HCP_TILE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
188 HCP_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
189 HCP_VP9_SEGMENT_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
190 HCP_VP9_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
191 HCP_TILE_CODING_COMMAND_NUMBER_OF_ADDRESSES = 1, // 0 DW for address fields
192 HCP_PALETTE_INITIALIZER_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields
193
194 VDENC_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 12, // 12 DW for 12 address fields
195 VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields
196 };
197
198 static constexpr uint32_t MAX_REF_FRAME_NUM = 15;
199
_MHW_PAR_T(HCP_PIC_STATE)200 struct _MHW_PAR_T(HCP_PIC_STATE)
201 {
202 bool bDecodeInUse = false;
203 uint16_t framewidthinmincbminus1 = 0;
204 bool transformSkipEnabled = false;
205 uint16_t frameheightinmincbminus1 = 0;
206 uint8_t mincusize = 0;
207 uint8_t ctbsizeLcusize = 0;
208 uint8_t maxtusize = 0;
209 uint8_t mintusize = 0;
210 uint8_t maxpcmsize = 0;
211 uint8_t minpcmsize = 0;
212 bool sampleAdaptiveOffsetEnabled = false;
213 bool pcmEnabledFlag = false;
214 bool cuQpDeltaEnabledFlag = false;
215 uint8_t diffCuQpDeltaDepth = 0;
216 bool pcmLoopFilterDisableFlag = false;
217 bool constrainedIntraPredFlag = false;
218 uint8_t log2ParallelMergeLevelMinus2 = 0;
219 bool signDataHidingFlag = false;
220 bool weightedPredFlag = false;
221 bool weightedBipredFlag = false;
222 bool fieldpic = false;
223 bool bottomfield = false;
224 bool ampEnabledFlag = false;
225 bool transquantBypassEnableFlag = false;
226 bool strongIntraSmoothingEnableFlag = false;
227 uint8_t picCbQpOffset = 0;
228 uint8_t picCrQpOffset = 0;
229 uint8_t maxTransformHierarchyDepthIntra = 0;
230 uint8_t maxTransformHierarchyDepthInter = 0;
231 uint8_t pcmSampleBitDepthChromaMinus1 = 0;
232 uint8_t pcmSampleBitDepthLumaMinus1 = 0;
233 uint8_t bitDepthChromaMinus8 = 0;
234 uint8_t bitDepthLumaMinus8 = 0;
235 uint16_t lcuMaxBitsizeAllowed = 0;
236 uint8_t lcuMaxBitSizeAllowedMsb2its = 0;
237 bool rdoqEnable = false;
238 bool sseEnable = true;
239 bool rhodomainRateControlEnable = true;
240 uint8_t rhodomainframelevelqp = 0;
241 bool fractionalQpAdjustmentEnable = true;
242 bool pakDynamicSliceModeEnable = false;
243 uint8_t slicePicParameterSetId = false;
244 bool nalunittypeflag = false;
245 bool noOutputOfPriorPicsFlag = false;
246 uint32_t sliceSizeThresholdInBytes = 0;
247 uint32_t targetSliceSizeInBytes = 0;
248 bool tilesEnabledFlag = false;
249 uint8_t chromaSubsampling = 0;
250 uint8_t log2Maxtransformskipsize = 0;
251 bool loopFilterAcrossTilesEnabled = false;
252 bool entropyCodingSyncEnabled = false;
253 bool intratucountbasedrdoqdisable = false;
254 uint16_t rdoqintratuthreshold = 0;
255 bool intraBoundaryFilteringDisabledFlag = false;
256 uint8_t motionVectorResolutionControlIdc = 0;
257 bool ppsCurrPicRefEnabledFlag = false;
258 uint8_t ibcMotionCompensationBufferReferenceIdc = 0;
259 uint8_t ibcConfiguration = 0;
260 bool paletteModeEnabledFlag = 0;
261 uint8_t paletteMaxSize = 0;
262 uint8_t deltaPaletteMaxPredictorSize = 0;
263 uint8_t lumaBitDepthEntryMinus8 = 0;
264 uint8_t chromaBitDepthEntryMinus8 = 0;
265 bool partialFrameUpdateMode = false;
266 bool temporalMvPredDisable = false;
267 uint16_t minframesize = 0;
268 uint8_t minframesizeunits = 0;
269 uint8_t ucRecNotFilteredID = 0;
270 bool deblockingFilterOverrideEnabled = false;
271 bool ppsDeblockingFilterDisabled = false;
272 bool requestCRC = false;
273 uint8_t bNotFirstPass = 0;
274 PCODEC_HEVC_EXT_PIC_PARAMS pHevcExtPicParams = nullptr;
275 PCODEC_HEVC_SCC_PIC_PARAMS pHevcSccPicParams = nullptr;
276 bool vdaqmEnable = false;
277 };
278
_MHW_PAR_T(HCP_SURFACE_STATE)279 struct _MHW_PAR_T(HCP_SURFACE_STATE)
280 {
281 uint8_t surfaceStateId = 0;
282 uint32_t surfacePitchMinus1 = 0;
283 SURFACE_FORMAT surfaceFormat = SURFACE_FORMAT::SURFACE_FORMAT_PLANAR4208;
284 uint32_t yOffsetForUCbInPixel = 0;
285 uint32_t defaultAlphaValue = 0;
286 uint16_t yOffsetForVCr = 0;
287 MOS_MEMCOMP_STATE mmcState = MOS_MEMCOMP_DISABLED;
288 uint8_t mmcSkipMask = 0;
289 uint32_t dwCompressionFormat = 0;
290 uint8_t refsMmcEnable = 0;
291 uint8_t refsMmcType = 0;
292 };
293
_MHW_PAR_T(HCP_PIPE_MODE_SELECT)294 struct _MHW_PAR_T(HCP_PIPE_MODE_SELECT)
295 {
296 std::function<MOS_STATUS(uint32_t *cmdData)> setProtectionSettings;
297
298 uint8_t codecStandardSelect = 0;
299 bool bAdvancedRateControlEnable = false;
300 bool bStreamOutEnabled = false;
301 bool bBRCEnabled = false;
302 bool pakPiplnStrmoutEnabled = false;
303 bool bDeblockerStreamOutEnable = false;
304 bool bVdencEnabled = false;
305 bool bRdoqEnable = false;
306 bool pakFrmLvlStrmoutEnable = false;
307 bool bTileBasedReplayMode = false;
308 bool bDynamicScalingEnabled = false;
309 uint8_t codecSelect = 1;
310 uint8_t ucPhaseIndicator = 0;
311 bool bHEVCSeparateTileProgramming = false;
312 bool prefetchDisable = false;
313 uint32_t mediaSoftResetCounterPer1000Clocks = 0;
314
315 MHW_VDBOX_HCP_PIPE_WORK_MODE pipeWorkMode = MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY;
316 MHW_VDBOX_HCP_MULTI_ENGINE_MODE multiEngineMode = MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY;
317 };
318
_MHW_PAR_T(HCP_SLICE_STATE)319 struct _MHW_PAR_T(HCP_SLICE_STATE)
320 {
321 uint32_t slicestartctbxOrSliceStartLcuXEncoder = 0;
322 uint32_t slicestartctbyOrSliceStartLcuYEncoder = 0;
323 uint32_t nextslicestartctbxOrNextSliceStartLcuXEncoder = 0;
324 uint32_t nextslicestartctbyOrNextSliceStartLcuYEncoder = 0;
325 uint8_t sliceType = 0;
326 bool lastsliceofpic = false;
327 bool sliceqpSignFlag = false;
328 bool dependentSliceFlag = false;
329 bool sliceTemporalMvpEnableFlag = false;
330 uint8_t sliceqp = 0;
331 uint8_t sliceCbQpOffset = 0;
332 uint8_t sliceCrQpOffset = 0;
333 bool intrareffetchdisable = false;
334 bool deblockingFilterDisable = false;
335 char tcOffsetDiv2 = 0;
336 char betaOffsetDiv2 = 0;
337 bool loopFilterAcrossSlicesEnabled = false;
338 bool saoLumaFlag = false;
339 bool saoChromaFlag = false;
340 bool mvdL1ZeroFlag = false;
341 bool isLowDelay = false;
342 bool collocatedFromL0Flag = false;
343 uint8_t chromalog2Weightdenom = 0;
344 uint8_t lumaLog2WeightDenom = 0;
345 bool cabacInitFlag = false;
346 uint8_t maxmergeidx = 0;
347 uint8_t collocatedrefidx = 0;
348 uint32_t sliceheaderlength = 0;
349 bool cabaczerowordinsertionenable = false;
350 bool emulationbytesliceinsertenable = false;
351 bool tailInsertionEnable = false;
352 bool slicedataEnable = false;
353 bool headerInsertionEnable = false;
354 uint32_t indirectPakBseDataStartOffsetWrite = 0;
355 uint16_t transformskiplambda = 0;
356 uint8_t transformskipNumzerocoeffsFactor0 = 0;
357 uint8_t transformskipNumnonzerocoeffsFactor0 = 0;
358 uint8_t transformskipNumzerocoeffsFactor1 = 0;
359 uint8_t transformskipNumnonzerocoeffsFactor1 = 0;
360 bool lastSliceInTile = false;
361 bool lastSliceInTileColumn = false;
362 uint32_t roundinter = 0;
363 uint32_t roundintra = 0;
364 bool cuChromaQpOffsetEnable = false;
365 bool bIsNotFirstTile = false; //!< Not first tile in slice
366 uint32_t originalSliceStartCtbX = 0;
367 uint32_t originalSliceStartCtbY = 0;
368 uint32_t dependentSliceDueToTileSplit = 0;
369 uint32_t sliceActYQpOffset = 0;
370 uint32_t sliceActCbQpOffset = 0;
371 uint32_t sliceActCrQpOffset = 0;
372 uint32_t useIntegerMvFlag = 0;
373 };
374
_MHW_PAR_T(HCP_IND_OBJ_BASE_ADDR_STATE)375 struct _MHW_PAR_T(HCP_IND_OBJ_BASE_ADDR_STATE)
376 {
377 bool bDecodeInUse = 0;
378 PMOS_RESOURCE presDataBuffer = nullptr;
379 uint32_t dwDataSize = 0;
380 uint32_t dwDataOffset = 0;
381 PMOS_RESOURCE presMvObjectBuffer = nullptr;
382 uint32_t dwMvObjectSize = 0;
383 uint32_t dwMvObjectOffset = 0;
384 PMOS_RESOURCE presPakBaseObjectBuffer = nullptr;
385 uint32_t dwPakBaseObjectSize = 0;
386 uint32_t dwPakBaseObjectOffset = 0;
387 PMOS_RESOURCE presPakTileSizeStasBuffer = nullptr;
388 uint32_t dwPakTileSizeStasBufferSize = 0;
389 uint32_t dwPakTileSizeRecordOffset = 0;
390 PMOS_RESOURCE presCompressedHeaderBuffer = nullptr;
391 uint32_t dwCompressedHeaderSize = 0;
392 PMOS_RESOURCE presProbabilityDeltaBuffer = nullptr;
393 uint32_t dwProbabilityDeltaSize = 0;
394 PMOS_RESOURCE presProbabilityCounterBuffer = nullptr;
395 uint32_t dwProbabilityCounterOffset = 0;
396 uint32_t dwProbabilityCounterSize = 0;
397 PMOS_RESOURCE presTileRecordBuffer = nullptr;
398 uint32_t dwTileRecordSize = 0;
399 PMOS_RESOURCE presCuStatsBuffer = nullptr;
400 uint32_t dwCuStatsSize = 0;
401 PMOS_RESOURCE presStreamOutObjectBuffer = nullptr;
402 uint32_t dwStreamOutObjectSize = 0;
403 uint32_t dwStreamOutObjectOffset = 0;
404 };
405
_MHW_PAR_T(HCP_QM_STATE)406 struct _MHW_PAR_T(HCP_QM_STATE)
407 {
408 uint8_t predictionType = 0;
409 uint8_t sizeid = 0;
410 uint8_t colorComponent = 0;
411 uint8_t dcCoefficient = 0;
412 uint32_t quantizermatrix[16] = {};
413 };
414
_MHW_PAR_T(HCP_FQM_STATE)415 struct _MHW_PAR_T(HCP_FQM_STATE)
416 {
417 uint8_t intraInter = 0;
418 uint8_t sizeid = 0;
419 uint8_t colorComponent = 0;
420 uint16_t fqmDcValue1Dc = 0;
421 uint32_t quantizermatrix[32] = {};
422 };
423
_MHW_PAR_T(HCP_BSD_OBJECT)424 struct _MHW_PAR_T(HCP_BSD_OBJECT)
425 {
426 uint32_t bsdDataLength = 0;
427 uint32_t bsdDataStartOffset = 0;
428 };
429
_MHW_PAR_T(HCP_TILE_STATE)430 struct _MHW_PAR_T(HCP_TILE_STATE)
431 {
432 uint16_t *pTileColWidth = nullptr;
433 uint16_t *pTileRowHeight = nullptr;
434 uint8_t numTileColumnsMinus1 = 0;
435 uint8_t numTileRowsMinus1 = 0;
436 };
437
_MHW_PAR_T(HCP_REF_IDX_STATE)438 struct _MHW_PAR_T(HCP_REF_IDX_STATE)
439 {
440 uint8_t ucList = 0;
441 uint8_t ucNumRefForList = 0;
442 uint8_t numRefIdxLRefpiclistnumActiveMinus1 = 0;
443 uint8_t listEntryLxReferencePictureFrameIdRefaddr07[MAX_REF_FRAME_NUM + 1] = {};
444 uint32_t referencePictureTbValue[MAX_REF_FRAME_NUM + 1] = {};
445 bool longtermreference[MAX_REF_FRAME_NUM + 1] = {};
446 bool fieldPicFlag[MAX_REF_FRAME_NUM + 1] = {};
447 bool bottomFieldFlag[MAX_REF_FRAME_NUM + 1] = {};
448 bool bDummyReference = false;
449 bool bDecodeInUse = false;
450 };
451
_MHW_PAR_T(HCP_WEIGHTOFFSET_STATE)452 struct _MHW_PAR_T(HCP_WEIGHTOFFSET_STATE)
453 {
454 uint8_t ucList = 0;
455 char LumaWeights[2][15] = {};
456 int16_t LumaOffsets[2][15] = {};
457 char ChromaWeights[2][15][2] = {};
458 int16_t ChromaOffsets[2][15][2] = {};
459 };
460
_MHW_PAR_T(HCP_PIPE_BUF_ADDR_STATE)461 struct _MHW_PAR_T(HCP_PIPE_BUF_ADDR_STATE)
462 {
463 uint32_t Mode = 0;
464 PMOS_SURFACE psPreDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface
465 MOS_MEMCOMP_STATE PreDeblockSurfMmcState = MOS_MEMCOMP_DISABLED;
466 PMOS_SURFACE psPostDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface
467 MOS_MEMCOMP_STATE PostDeblockSurfMmcState = MOS_MEMCOMP_DISABLED;
468 PMOS_SURFACE psRawSurface = nullptr; // Pointer to MOS_SURFACE of raw surface
469 MOS_MEMCOMP_STATE RawSurfMmcState = MOS_MEMCOMP_DISABLED;
470 PMOS_SURFACE ps4xDsSurface = nullptr;
471 MOS_MEMCOMP_STATE Ps4xDsSurfMmcState = MOS_MEMCOMP_DISABLED;
472 PMOS_SURFACE ps8xDsSurface = nullptr;
473 MOS_MEMCOMP_STATE Ps8xDsSurfMmcState = MOS_MEMCOMP_DISABLED;
474 PMOS_RESOURCE presDataBuffer = nullptr; // Handle of residual difference surface
475 PMOS_RESOURCE presReferences[CODEC_MAX_NUM_REF_FRAME] = {};
476 PMOS_RESOURCE presMfdIntraRowStoreScratchBuffer = nullptr; // Handle of MFD Intra Row Store Scratch data surface
477 PMOS_RESOURCE presMfdDeblockingFilterRowStoreScratchBuffer = nullptr; // Handle of MFD Deblocking Filter Row Store Scratch data surface
478 PMOS_RESOURCE presStreamOutBuffer = nullptr;
479 MOS_MEMCOMP_STATE StreamOutBufMmcState = MOS_MEMCOMP_DISABLED;
480 PMOS_RESOURCE presMacroblockIldbStreamOutBuffer1 = nullptr;
481 PMOS_RESOURCE presMacroblockIldbStreamOutBuffer2 = nullptr;
482 PMOS_RESOURCE presSliceSizeStreamOutBuffer = nullptr;
483 PMOS_SURFACE psFwdRefSurface0 = nullptr;
484 PMOS_SURFACE psFwdRefSurface1 = nullptr;
485 PMOS_SURFACE psFwdRefSurface2 = nullptr;
486 bool bDynamicScalingEnable = false;
487
488 PMOS_RESOURCE presVdencIntraRowStoreScratchBuffer = nullptr; // For VDEnc, Handle of VDEnc Intra Row Store Scratch data surface
489 PMOS_RESOURCE presVdencTileRowStoreBuffer = nullptr;
490 PMOS_RESOURCE presVdencStreamOutBuffer = nullptr;
491 PMOS_RESOURCE presVdencCuObjStreamOutBuffer = nullptr;
492 PMOS_RESOURCE presVdencPakObjCmdStreamOutBuffer = nullptr;
493 PMOS_RESOURCE presVdencStreamInBuffer = nullptr;
494 PMOS_RESOURCE presVdencReferences[CODEC_MAX_NUM_REF_FRAME] = {};
495 PMOS_RESOURCE presVdenc4xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {};
496 PMOS_RESOURCE presVdenc8xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {};
497
498 PMOS_RESOURCE presVdencColocatedMVWriteBuffer = nullptr; // For AVC only
499 PMOS_RESOURCE presVdencColocatedMVReadBuffer = nullptr; // For AVC only
500 PMOS_RESOURCE presDeblockingFilterTileRowStoreScratchBuffer = nullptr; // For HEVC, VP9
501 PMOS_RESOURCE presDeblockingFilterColumnRowStoreScratchBuffer = nullptr; // For HEVC, VP9
502 PMOS_RESOURCE presMetadataLineBuffer = nullptr; // For HEVC, VP9
503 PMOS_RESOURCE presMetadataTileLineBuffer = nullptr; // For HEVC, VP9
504 PMOS_RESOURCE presMetadataTileColumnBuffer = nullptr; // For HEVC, VP9
505 PMOS_RESOURCE presSaoLineBuffer = nullptr; // For HEVC only
506 PMOS_RESOURCE presSaoTileLineBuffer = nullptr; // For HEVC only
507 PMOS_RESOURCE presSaoTileColumnBuffer = nullptr; // For HEVC only
508 PMOS_RESOURCE presCurMvTempBuffer = nullptr; // For HEVC, VP9
509 PMOS_RESOURCE presColMvTempBuffer[CODEC_MAX_NUM_REF_FRAME] = {}; // For HEVC, VP9
510 PMOS_RESOURCE presLcuBaseAddressBuffer = nullptr; // For HEVC only
511 PMOS_RESOURCE presLcuILDBStreamOutBuffer = nullptr; // For HEVC only
512 PMOS_RESOURCE presVp9ProbBuffer = nullptr; // For VP9 only
513 PMOS_RESOURCE presVp9SegmentIdBuffer = nullptr; // For VP9 only
514 PMOS_RESOURCE presHvdLineRowStoreBuffer = nullptr; // For VP9 only
515 PMOS_RESOURCE presHvdTileRowStoreBuffer = nullptr; // For VP9 only
516 PMOS_RESOURCE presSaoStreamOutBuffer = nullptr; // For HEVC only
517 PMOS_RESOURCE presSaoRowStoreBuffer = nullptr; // For HEVC only
518 PMOS_SURFACE presP010RTSurface = nullptr; // For HEVC only
519 PMOS_RESOURCE presFrameStatStreamOutBuffer = nullptr;
520 PMOS_RESOURCE presSseSrcPixelRowStoreBuffer = nullptr;
521 PMOS_RESOURCE presSegmentMapStreamIn = nullptr;
522 PMOS_RESOURCE presSegmentMapStreamOut = nullptr;
523 PMOS_RESOURCE presPakCuLevelStreamoutBuffer = nullptr;
524 PMHW_VDBOX_SURFACE_PARAMS pRawSurfParam = nullptr;
525 PMHW_VDBOX_SURFACE_PARAMS pDecodedReconParam = nullptr;
526 bool bVdencEnabled = false;
527 bool bRawIs10Bit = false;
528 bool bDecodecReconIs10Bit = false;
529 uint32_t dwNumRefIdxL0ActiveMinus1 = 0;
530 uint32_t dwNumRefIdxL1ActiveMinus1 = 0;
531 uint32_t dwLcuStreamOutOffset = 0;
532 uint32_t dwFrameStatStreamOutOffset = 0;
533 uint32_t dwVdencStatsStreamOutOffset = 0;
534 bool oneOnOneMapping = false; // Flag for indicating using 1:1 ref index mapping for vdenc
535 bool isLowDelayB = true; // Flag to indicate if it is LDB
536 bool isIFrame = false; // Flag to indicate if it is I frame
537 bool isPFrame = false; // Flag to indicate if it is P frame
538 bool bIBCEnabled = false;
539 uint8_t IBCRefIdxMask = 0;
540 PMOS_RESOURCE presVdencCumulativeCuCountStreamoutSurface = nullptr;
541
542 //Scalable
543 PMOS_RESOURCE presSliceStateStreamOutBuffer = nullptr;
544 PMOS_RESOURCE presMvUpRightColStoreBuffer = nullptr;
545 PMOS_RESOURCE presIntraPredUpRightColStoreBuffer = nullptr;
546 PMOS_RESOURCE presIntraPredLeftReconColStoreBuffer = nullptr;
547 PMOS_RESOURCE presCABACSyntaxStreamOutBuffer = nullptr;
548 PMOS_RESOURCE presCABACSyntaxStreamOutMaxAddr = nullptr;
549 };
550
_MHW_PAR_T(HCP_PAK_INSERT_OBJECT)551 struct _MHW_PAR_T(HCP_PAK_INSERT_OBJECT)
552 {
553 PBSBuffer pBsBuffer = nullptr;
554 uint32_t dwBitSize = 0;
555 uint32_t dwOffset = 0;
556 uint32_t uiSkipEmulationCheckCount = 0;
557 bool bLastPicInSeq = false;
558 bool bLastPicInStream = false;
559 bool bLastHeader = false;
560 bool bEmulationByteBitsInsert = false;
561 bool bSetLastPicInStreamData = false;
562 bool bSliceHeaderIndicator = false;
563 bool bHeaderLengthExcludeFrmSize = false;
564 uint32_t * pdwMpeg2PicHeaderTotalBufferSize = nullptr;
565 uint32_t * pdwMpeg2PicHeaderDataStartOffset = nullptr;
566 bool bResetBitstreamStartingPos = false;
567 bool bEndOfSlice = false;
568 uint32_t dwLastPicInSeqData = 0;
569 uint32_t dwLastPicInStreamData = 0;
570 PMHW_BATCH_BUFFER pBatchBufferForPakSlices = nullptr;
571 bool bVdencInUse = false;
572 uint32_t dataBitsInLastDw = 0;
573 uint8_t databyteoffset = 0;
574 uint32_t dwPadding = 0;
575 bool bIndirectPayloadEnable = false;
576 };
577
_MHW_PAR_T(HCP_VP9_PIC_STATE)578 struct _MHW_PAR_T(HCP_VP9_PIC_STATE)
579 {
580 uint32_t frameWidthInPixelsMinus1 = 0;
581 uint32_t frameHeightInPixelsMinus1 = 0;
582 uint32_t frameType = 0;
583 uint32_t adaptProbabilitiesFlag = 0;
584 uint32_t intraOnlyFlag = 0;
585 uint32_t allowHiPrecisionMv = 0;
586 uint32_t mcompFilterType = 0;
587 uint32_t refFrameSignBias02 = 0;
588 uint32_t hybridPredictionMode = 0;
589 uint32_t selectableTxMode = 0;
590 uint32_t usePrevInFindMvReferences = 0;
591 uint32_t lastFrameType = 0;
592 uint32_t refreshFrameContext = 0;
593 uint32_t errorResilientMode = 0;
594 uint32_t frameParallelDecodingMode = 0;
595 uint32_t filterLevel = 0;
596 uint32_t sharpnessLevel = 0;
597 uint32_t segmentationEnabled = 0;
598 uint32_t segmentationUpdateMap = 0;
599 uint32_t segmentationTemporalUpdate = 0;
600 uint32_t losslessMode = 0;
601 uint32_t segmentIdStreamOutEnable = 0;
602 uint32_t segmentIdStreamInEnable = 0;
603 uint32_t log2TileColumn = 0;
604 uint32_t log2TileRow = 0;
605 uint32_t sseEnable = 0;
606 uint32_t chromaSamplingFormat = 0;
607 uint32_t bitdepthMinus8 = 0;
608 uint32_t profileLevel = 0;
609 uint32_t verticalScaleFactorForLast = 0;
610 uint32_t horizontalScaleFactorForLast = 0;
611 uint32_t verticalScaleFactorForGolden = 0;
612 uint32_t horizontalScaleFactorForGolden = 0;
613 uint32_t verticalScaleFactorForAltref = 0;
614 uint32_t horizontalScaleFactorForAltref = 0;
615 uint32_t lastFrameWidthInPixelsMinus1 = 0;
616 uint32_t lastFrameHeightInPixelsMinus1 = 0;
617 uint32_t goldenFrameWidthInPixelsMinus1 = 0;
618 uint32_t goldenFrameHeightInPixelsMinus1 = 0;
619 uint32_t altrefFrameWidthInPixelsMinus1 = 0;
620 uint32_t altrefFrameHeightInPixelsMinus1 = 0;
621 uint32_t uncompressedHeaderLengthInBytes70 = 0;
622 uint32_t firstPartitionSizeInBytes150 = 0;
623 uint32_t baseQIndexSameAsLumaAc = 0;
624 uint32_t headerInsertionEnable = 0;
625 uint32_t chromaAcQIndexDelta = 0;
626 uint32_t chromaDcQIndexDelta = 0;
627 uint32_t lumaDcQIndexDelta = 0;
628 uint32_t lfRefDelta0 = 0;
629 uint32_t lfRefDelta1 = 0;
630 uint32_t lfRefDelta2 = 0;
631 uint32_t lfRefDelta3 = 0;
632 uint32_t lfModeDelta0 = 0;
633 uint32_t lfModeDelta1 = 0;
634 uint32_t bitOffsetForLfRefDelta = 0;
635 uint32_t bitOffsetForLfModeDelta = 0;
636 uint32_t bitOffsetForQIndex = 0;
637 uint32_t bitOffsetForLfLevel = 0;
638 uint32_t vdencPakOnlyPass = 0;
639 uint32_t bitOffsetForFirstPartitionSize = 0;
640 uint32_t dWordLength = 0;
641 bool bDecodeInUse = false;
642 };
643
_MHW_PAR_T(HCP_VP9_SEGMENT_STATE)644 struct _MHW_PAR_T(HCP_VP9_SEGMENT_STATE)
645 {
646 uint32_t segmentId = 0;
647 uint32_t segmentSkipped = 0;
648 uint32_t segmentReference = 0;
649 uint32_t segmentReferenceEnabled = 0;
650 uint32_t filterLevelRef0Mode0 = 0;
651 uint32_t filterLevelRef0Mode1 = 0;
652 uint32_t filterLevelRef1Mode0 = 0;
653 uint32_t filterLevelRef1Mode1 = 0;
654 uint32_t filterLevelRef2Mode0 = 0;
655 uint32_t filterLevelRef2Mode1 = 0;
656 uint32_t filterLevelRef3Mode0 = 0;
657 uint32_t filterLevelRef3Mode1 = 0;
658 uint32_t lumaDcQuantScaleDecodeModeOnly = 0;
659 uint32_t lumaAcQuantScaleDecodeModeOnly = 0;
660 uint32_t chromaDcQuantScaleDecodeModeOnly = 0;
661 uint32_t chromaAcQuantScaleDecodeModeOnly = 0;
662 uint32_t segmentQindexDeltaEncodeModeOnly = 0;
663 uint32_t segmentLfLevelDeltaEncodeModeOnly = 0;
664 };
665
_MHW_PAR_T(HEVC_VP9_RDOQ_STATE)666 struct _MHW_PAR_T(HEVC_VP9_RDOQ_STATE)
667 {
668 bool disableHtqPerformanceFix0 = false;
669 bool disableHtqPerformanceFix1 = false;
670 uint16_t lambdaTab[2][2][76] = {};
671 };
672
_MHW_PAR_T(HCP_TILE_CODING)673 struct _MHW_PAR_T(HCP_TILE_CODING)
674 {
675 uint32_t numOfTileColumnsInFrame = 0;
676 uint32_t tileStartLCUX = 0;
677 uint32_t tileStartLCUY = 0;
678 uint16_t tileHeightInMinCbMinus1 = 0;
679 uint16_t tileWidthInMinCbMinus1 = 0;
680 bool isLastTileofColumn = false;
681 bool isLastTileofRow = false;
682 uint32_t tileRowStoreSelect = 0;
683 uint32_t tileColumnStoreSelect = 0;
684 bool nonFirstPassTile = false;
685 bool bitstreamByteOffsetEnable = false;
686 uint32_t numberOfActiveBePipes = 0;
687 uint32_t bitstreamByteOffset = 0;
688 uint32_t pakTileStatisticsOffset = 0;
689 uint32_t cuLevelStreamoutOffset = 0;
690 uint32_t sliceSizeStreamoutOffset = 0;
691 uint32_t cuRecordOffset = 0;
692 uint32_t sseRowstoreOffset = 0;
693 uint32_t saoRowstoreOffset = 0;
694 uint32_t tileSizeStreamoutOffset = 0;
695 uint32_t vp9ProbabilityCounterStreamoutOffset = 0;
696 };
697
_MHW_PAR_T(HCP_PALETTE_INITIALIZER_STATE)698 struct _MHW_PAR_T(HCP_PALETTE_INITIALIZER_STATE)
699 {
700 uint8_t predictorPaletteSize = 0;
701 uint16_t predictorPaletteEntries[3][128] = {};
702 uint32_t hevcSccPaletteSize = 0;
703 };
704
705 } // namespace hcp
706 } // namespace vdbox
707 } // namespace mhw
708
709 #endif // __MHW_VDBOX_HCP_CMDPAR_H__
710