1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SMBIOS_H 4 #define SMBIOS_H 5 6 #include <types.h> 7 #include <memory_info.h> 8 9 #define update_max(len, max_len, stmt) \ 10 do { \ 11 int tmp = stmt; \ 12 \ 13 max_len = MAX(max_len, tmp); \ 14 len += tmp; \ 15 } while (0) 16 17 unsigned long smbios_write_tables(unsigned long start); 18 int smbios_add_string(u8 *start, const char *str); 19 int smbios_string_table_len(u8 *start); 20 21 struct smbios_header; 22 int smbios_full_table_len(struct smbios_header *header, u8 *str_table_start); 23 void *smbios_carve_table(unsigned long start, u8 type, u8 length, u16 handle); 24 25 /* Used by mainboard to add an on-board device */ 26 enum misc_slot_type; 27 enum misc_slot_length; 28 enum misc_slot_usage; 29 enum slot_data_bus_bandwidth; 30 int smbios_write_type9(unsigned long *current, int *handle, 31 const char *name, const enum misc_slot_type type, 32 const enum slot_data_bus_bandwidth bandwidth, 33 const enum misc_slot_usage usage, 34 const enum misc_slot_length length, 35 const u16 id, u8 slot_char1, u8 slot_char2, 36 u8 segment_group, u8 bus, u8 dev_func); 37 enum smbios_bmc_interface_type; 38 int smbios_write_type38(unsigned long *current, int *handle, 39 const enum smbios_bmc_interface_type interface_type, 40 const u8 ipmi_rev, const u8 i2c_addr, const u8 nv_addr, 41 const u64 base_addr, const u8 base_modifier, 42 const u8 irq); 43 int smbios_write_type41(unsigned long *current, int *handle, 44 const char *name, u8 instance, u16 segment_group, 45 u8 bus, u8 device, u8 function, u8 device_type); 46 enum smbios_temp_location; 47 enum smbios_temp_status; 48 int smbios_write_type28(unsigned long *current, int *handle, 49 const char *name, 50 const enum smbios_temp_location location, 51 const enum smbios_temp_status status, 52 u16 max_value, u16 min_value, 53 u16 resolution, u16 tolerance, 54 u16 accuracy, 55 u32 oem, 56 u16 nominal_value); 57 58 int smbios_write_type43(unsigned long *current, int *handle, const u32 vendor_id, 59 const u8 major_spec_ver, const u8 minor_spec_ver, 60 const u32 fw_ver1, const u32 fw_ver2, const char *description, 61 const u64 characteristics, const u32 oem_defined); 62 63 struct device; 64 int get_smbios_data(struct device *dev, int *handle, unsigned long *current); 65 66 const char *smbios_system_manufacturer(void); 67 const char *smbios_system_product_name(void); 68 const char *smbios_system_serial_number(void); 69 const char *smbios_system_version(void); 70 void smbios_system_set_uuid(u8 *uuid); 71 const char *smbios_system_sku(void); 72 73 void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count); 74 unsigned int smbios_cpu_get_max_speed_mhz(void); 75 unsigned int smbios_cpu_get_current_speed_mhz(void); 76 unsigned int smbios_cpu_get_voltage(void); 77 78 const char *smbios_mainboard_manufacturer(void); 79 const char *smbios_mainboard_product_name(void); 80 const char *smbios_mainboard_serial_number(void); 81 const char *smbios_mainboard_version(void); 82 83 const char *smbios_mainboard_bios_version(void); 84 const char *smbios_mainboard_asset_tag(void); 85 u8 smbios_mainboard_feature_flags(void); 86 const char *smbios_mainboard_location_in_chassis(void); 87 const char *smbios_chassis_version(void); 88 const char *smbios_chassis_serial_number(void); 89 const char *smbios_processor_serial_number(void); 90 u8 smbios_chassis_power_cords(void); 91 92 /* This string could be filled late in payload. */ 93 void smbios_type0_bios_version(uintptr_t address); 94 95 void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); 96 97 unsigned int smbios_processor_external_clock(void); 98 unsigned int smbios_processor_characteristics(void); 99 struct cpuid_result; 100 unsigned int smbios_processor_family(struct cpuid_result res); 101 102 unsigned int smbios_cache_error_correction_type(u8 level); 103 unsigned int smbios_cache_sram_type(void); 104 unsigned int smbios_cache_conf_operation_mode(u8 level); 105 106 /* Used by mainboard to add port information of type 8 */ 107 struct port_information; 108 int smbios_write_type8(unsigned long *current, int *handle, 109 const struct port_information *port, 110 size_t num_ports); 111 112 #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) 113 #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) 114 #define BIOS_CHARACTERISTICS_PNP (1 << 9) 115 #define BIOS_CHARACTERISTICS_APM (1 << 10) 116 #define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) 117 #define BIOS_CHARACTERISTICS_SHADOW (1 << 12) 118 #define BIOS_CHARACTERISTICS_BOOT_FROM_CD (1 << 15) 119 #define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) 120 #define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) 121 122 #define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) 123 #define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) 124 125 #define BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING (1 << 3) 126 #define BIOS_MEMORY_ECC_DOUBLE_BIT_CORRECTING (1 << 4) 127 #define BIOS_MEMORY_ECC_SCRUBBING (1 << 5) 128 129 #define MEMORY_TYPE_DETAIL_OTHER (1 << 1) 130 #define MEMORY_TYPE_DETAIL_UNKNOWN (1 << 2) 131 #define MEMORY_TYPE_DETAIL_FAST_PAGED (1 << 3) 132 #define MEMORY_TYPE_DETAIL_STATIC_COLUMN (1 << 4) 133 #define MEMORY_TYPE_DETAIL_PSEUDO_STATIC (1 << 5) 134 #define MEMORY_TYPE_DETAIL_RAMBUS (1 << 6) 135 #define MEMORY_TYPE_DETAIL_SYNCHRONOUS (1 << 7) 136 #define MEMORY_TYPE_DETAIL_CMOS (1 << 8) 137 #define MEMORY_TYPE_DETAIL_EDO (1 << 9) 138 #define MEMORY_TYPE_DETAIL_WINDOW_DRAM (1 << 10) 139 #define MEMORY_TYPE_DETAIL_CACHE_DRAM (1 << 11) 140 #define MEMORY_TYPE_DETAIL_NON_VOLATILE (1 << 12) 141 #define MEMORY_TYPE_DETAIL_REGISTERED (1 << 13) 142 #define MEMORY_TYPE_DETAIL_UNBUFFERED (1 << 14) 143 #define MEMORY_TYPE_DETAIL_LRDIMM (1 << 15) 144 145 #define MEMORY_TECHNOLOGY_OTHER 0x01 146 #define MEMORY_TECHNOLOGY_UNKNOWN 0x02 147 #define MEMORY_TECHNOLOGY_DRAM 0x03 148 #define MEMORY_TECHNOLOGY_NVDIMM_N 0x04 149 #define MEMORY_TECHNOLOGY_NVDIMM_F 0x05 150 #define MEMORY_TECHNOLOGY_NVDIMM_P 0x06 151 #define MEMORY_TECHNOLOGY_INTEL_PERSISTENT 0x07 152 153 #define MEMORY_OPERATING_MODE_CAP_OTHER (1 << 1) 154 #define MEMORY_OPERATING_MODE_CAP_UNKNOWN (1 << 2) 155 #define MEMORY_OPERATING_MODE_CAP_VOLATILE (1 << 3) 156 #define MEMORY_OPERATING_MODE_CAP_BYTE_ACCESS_PERSISTENT (1 << 4) 157 #define MEMORY_OPERATING_MODE_CAP_BLOCK_ACCESS_PERSISTENT (1 << 5) 158 159 typedef enum { 160 MEMORY_BUS_WIDTH_8 = 0, 161 MEMORY_BUS_WIDTH_16 = 1, 162 MEMORY_BUS_WIDTH_32 = 2, 163 MEMORY_BUS_WIDTH_64 = 3, 164 MEMORY_BUS_WIDTH_128 = 4, 165 MEMORY_BUS_WIDTH_256 = 5, 166 MEMORY_BUS_WIDTH_512 = 6, 167 MEMORY_BUS_WIDTH_1024 = 7, 168 MEMORY_BUS_WIDTH_MAX = 7, 169 } smbios_memory_bus_width; 170 171 typedef enum { 172 MEMORY_FORMFACTOR_OTHER = 0x01, 173 MEMORY_FORMFACTOR_UNKNOWN = 0x02, 174 MEMORY_FORMFACTOR_SIMM = 0x03, 175 MEMORY_FORMFACTOR_SIP = 0x04, 176 MEMORY_FORMFACTOR_CHIP = 0x05, 177 MEMORY_FORMFACTOR_DIP = 0x06, 178 MEMORY_FORMFACTOR_ZIP = 0x07, 179 MEMORY_FORMFACTOR_PROPRIETARY_CARD = 0x08, 180 MEMORY_FORMFACTOR_DIMM = 0x09, 181 MEMORY_FORMFACTOR_TSOP = 0x0a, 182 MEMORY_FORMFACTOR_ROC = 0x0b, 183 MEMORY_FORMFACTOR_RIMM = 0x0c, 184 MEMORY_FORMFACTOR_SODIMM = 0x0d, 185 MEMORY_FORMFACTOR_SRIMM = 0x0e, 186 MEMORY_FORMFACTOR_FBDIMM = 0x0f, 187 MEMORY_FORMFACTOR_DIE = 0x10, 188 } smbios_memory_form_factor; 189 190 typedef enum { 191 MEMORY_TYPE_OTHER = 0x01, 192 MEMORY_TYPE_UNKNOWN = 0x02, 193 MEMORY_TYPE_DRAM = 0x03, 194 MEMORY_TYPE_EDRAM = 0x04, 195 MEMORY_TYPE_VRAM = 0x05, 196 MEMORY_TYPE_SRAM = 0x06, 197 MEMORY_TYPE_RAM = 0x07, 198 MEMORY_TYPE_ROM = 0x08, 199 MEMORY_TYPE_FLASH = 0x09, 200 MEMORY_TYPE_EEPROM = 0x0a, 201 MEMORY_TYPE_FEPROM = 0x0b, 202 MEMORY_TYPE_EPROM = 0x0c, 203 MEMORY_TYPE_CDRAM = 0x0d, 204 MEMORY_TYPE_3DRAM = 0x0e, 205 MEMORY_TYPE_SDRAM = 0x0f, 206 MEMORY_TYPE_SGRAM = 0x10, 207 MEMORY_TYPE_RDRAM = 0x11, 208 MEMORY_TYPE_DDR = 0x12, 209 MEMORY_TYPE_DDR2 = 0x13, 210 MEMORY_TYPE_DDR2_FBDIMM = 0x14, 211 MEMORY_TYPE_DDR3 = 0x18, 212 MEMORY_TYPE_FBD2 = 0x19, 213 MEMORY_TYPE_DDR4 = 0x1a, 214 MEMORY_TYPE_LPDDR = 0x1b, 215 MEMORY_TYPE_LPDDR2 = 0x1c, 216 MEMORY_TYPE_LPDDR3 = 0x1d, 217 MEMORY_TYPE_LPDDR4 = 0x1e, 218 MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f, 219 MEMORY_TYPE_HBM = 0x20, 220 MEMORY_TYPE_HBM2 = 0x21, 221 MEMORY_TYPE_DDR5 = 0x22, 222 MEMORY_TYPE_LPDDR5 = 0x23, 223 MEMORY_TYPE_HBM3 = 0x24, 224 } smbios_memory_type; 225 226 typedef enum { 227 MEMORY_ARRAY_LOCATION_OTHER = 0x01, 228 MEMORY_ARRAY_LOCATION_UNKNOWN = 0x02, 229 MEMORY_ARRAY_LOCATION_SYSTEM_BOARD = 0x03, 230 MEMORY_ARRAY_LOCATION_ISA_ADD_ON = 0x04, 231 MEMORY_ARRAY_LOCATION_EISA_ADD_ON = 0x05, 232 MEMORY_ARRAY_LOCATION_PCI_ADD_ON = 0x06, 233 MEMORY_ARRAY_LOCATION_MCA_ADD_ON = 0x07, 234 MEMORY_ARRAY_LOCATION_PCMCIA_ADD_ON = 0x08, 235 MEMORY_ARRAY_LOCATION_PROPRIETARY_ADD_ON = 0x09, 236 MEMORY_ARRAY_LOCATION_NUBUS = 0x0a, 237 MEMORY_ARRAY_LOCATION_PC_98_C20_ADD_ON = 0xa0, 238 MEMORY_ARRAY_LOCATION_PC_98_C24_ADD_ON = 0xa1, 239 MEMORY_ARRAY_LOCATION_PC_98_E_ADD_ON = 0xa2, 240 MEMORY_ARRAY_LOCATION_PC_98_LOCAL_BUS_ADD_ON = 0xa3, 241 MEMORY_ARRAY_LOCATION_CXL_FLEXBUS_1_0_ADD_ON = 0xa4, 242 } smbios_memory_array_location; 243 244 typedef enum { 245 MEMORY_ARRAY_USE_OTHER = 0x01, 246 MEMORY_ARRAY_USE_UNKNOWN = 0x02, 247 MEMORY_ARRAY_USE_SYSTEM = 0x03, 248 MEMORY_ARRAY_USE_VIDEO = 0x04, 249 MEMORY_ARRAY_USE_FLASH = 0x05, 250 MEMORY_ARRAY_USE_NVRAM = 0x06, 251 MEMORY_ARRAY_USE_CACHE = 0x07, 252 } smbios_memory_array_use; 253 254 typedef enum { 255 MEMORY_ARRAY_ECC_OTHER = 0x01, 256 MEMORY_ARRAY_ECC_UNKNOWN = 0x02, 257 MEMORY_ARRAY_ECC_NONE = 0x03, 258 MEMORY_ARRAY_ECC_PARITY = 0x04, 259 MEMORY_ARRAY_ECC_SINGLE_BIT = 0x05, 260 MEMORY_ARRAY_ECC_MULTI_BIT = 0x06, 261 MEMORY_ARRAY_ECC_CRC = 0x07, 262 } smbios_memory_array_ecc; 263 264 #define SMBIOS_STATE_SAFE 3 265 typedef enum { 266 SMBIOS_BIOS_INFORMATION = 0, 267 SMBIOS_SYSTEM_INFORMATION = 1, 268 SMBIOS_BOARD_INFORMATION = 2, 269 SMBIOS_SYSTEM_ENCLOSURE = 3, 270 SMBIOS_PROCESSOR_INFORMATION = 4, 271 SMBIOS_CACHE_INFORMATION = 7, 272 SMBIOS_PORT_CONNECTOR_INFORMATION = 8, 273 SMBIOS_SYSTEM_SLOTS = 9, 274 SMBIOS_OEM_STRINGS = 11, 275 SMBIOS_EVENT_LOG = 15, 276 SMBIOS_PHYS_MEMORY_ARRAY = 16, 277 SMBIOS_MEMORY_DEVICE = 17, 278 SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19, 279 SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS = 20, 280 SMBIOS_TEMPERATURE_PROBE = 28, 281 SMBIOS_SYSTEM_BOOT_INFORMATION = 32, 282 SMBIOS_IPMI_DEVICE_INFORMATION = 38, 283 SMBIOS_SYSTEM_POWER_SUPPLY = 39, 284 SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION = 41, 285 SMBIOS_TPM_DEVICE = 43, 286 SMBIOS_END_OF_TABLE = 127, 287 } smbios_struct_type_t; 288 289 struct smbios_entry { 290 u8 anchor[4]; 291 u8 checksum; 292 u8 length; 293 u8 major_version; 294 u8 minor_version; 295 u16 max_struct_size; 296 u8 entry_point_rev; 297 u8 formwatted_area[5]; 298 u8 intermediate_anchor_string[5]; 299 u8 intermediate_checksum; 300 u16 struct_table_length; 301 u32 struct_table_address; 302 u16 struct_count; 303 u8 smbios_bcd_revision; 304 } __packed; 305 306 struct smbios_entry30 { 307 u8 anchor[5]; 308 u8 checksum; 309 u8 length; 310 u8 major_version; 311 u8 minor_version; 312 u8 smbios_doc_rev; 313 u8 entry_point_rev; 314 u8 reserved; 315 u32 struct_table_length; 316 u64 struct_table_address; 317 } __packed; 318 319 struct smbios_header { 320 u8 type; 321 u8 length; 322 u16 handle; 323 } __packed; 324 325 struct smbios_type0 { 326 struct smbios_header header; 327 u8 vendor; 328 u8 bios_version; 329 u16 bios_start_segment; 330 u8 bios_release_date; 331 u8 bios_rom_size; 332 u64 bios_characteristics; 333 u8 bios_characteristics_ext1; 334 u8 bios_characteristics_ext2; 335 u8 system_bios_major_release; 336 u8 system_bios_minor_release; 337 u8 ec_major_release; 338 u8 ec_minor_release; 339 u16 extended_bios_rom_size; 340 u8 eos[2]; 341 } __packed; 342 343 typedef enum { 344 SMBIOS_WAKEUP_TYPE_RESERVED = 0x00, 345 SMBIOS_WAKEUP_TYPE_OTHER = 0x01, 346 SMBIOS_WAKEUP_TYPE_UNKNOWN = 0x02, 347 SMBIOS_WAKEUP_TYPE_APM_TIMER = 0x03, 348 SMBIOS_WAKEUP_TYPE_MODEM_RING = 0x04, 349 SMBIOS_WAKEUP_TYPE_LAN_REMOTE = 0x05, 350 SMBIOS_WAKEUP_TYPE_POWER_SWITCH = 0x06, 351 SMBIOS_WAKEUP_TYPE_PCI_PME = 0x07, 352 SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED = 0x08, 353 } smbios_wakeup_type; 354 355 struct smbios_type1 { 356 struct smbios_header header; 357 u8 manufacturer; 358 u8 product_name; 359 u8 version; 360 u8 serial_number; 361 u8 uuid[16]; 362 u8 wakeup_type; 363 u8 sku; 364 u8 family; 365 u8 eos[2]; 366 } __packed; 367 368 #define SMBIOS_FEATURE_FLAGS_HOSTING_BOARD (1 << 0) 369 #define SMBIOS_FEATURE_FLAGS_REQUIRES_DAUGHTER_CARD (1 << 1) 370 #define SMBIOS_FEATURE_FLAGS_REMOVABLE (1 << 2) 371 #define SMBIOS_FEATURE_FLAGS_REPLACEABLE (1 << 3) 372 #define SMBIOS_FEATURE_FLAGS_HOT_SWAPPABLE (1 << 4) 373 374 typedef enum { 375 SMBIOS_BOARD_TYPE_UNKNOWN = 0x01, 376 SMBIOS_BOARD_TYPE_OTHER = 0x02, 377 SMBIOS_BOARD_TYPE_SERVER_BLADE = 0x03, 378 SMBIOS_BOARD_TYPE_CONNECTIVITY_SWITCH = 0x04, 379 SMBIOS_BOARD_TYPE_SYSTEM_MANAGEMENT_MODULE = 0x05, 380 SMBIOS_BOARD_TYPE_PROCESSOR_MODULE = 0x06, 381 SMBIOS_BOARD_TYPE_IO_MODULE = 0x07, 382 SMBIOS_BOARD_TYPE_MEMORY_MODULE = 0x08, 383 SMBIOS_BOARD_TYPE_DAUGHTER_BOARD = 0x09, 384 SMBIOS_BOARD_TYPE_MOTHERBOARD = 0x0a, 385 SMBIOS_BOARD_TYPE_PROCESSOR_MEMORY_MODULE = 0x0b, 386 SMBIOS_BOARD_TYPE_PROCESSOR_IO_MODULE = 0x0c, 387 SMBIOS_BOARD_TYPE_INTERCONNECT_BOARD = 0x0d, 388 } smbios_board_type; 389 390 struct smbios_type2 { 391 struct smbios_header header; 392 u8 manufacturer; 393 u8 product_name; 394 u8 version; 395 u8 serial_number; 396 u8 asset_tag; 397 u8 feature_flags; 398 u8 location_in_chassis; 399 u16 chassis_handle; 400 u8 board_type; 401 u8 eos[2]; 402 } __packed; 403 404 typedef enum { 405 SMBIOS_ENCLOSURE_OTHER = 0x01, 406 SMBIOS_ENCLOSURE_UNKNOWN = 0x02, 407 SMBIOS_ENCLOSURE_DESKTOP = 0x03, 408 SMBIOS_ENCLOSURE_LOW_PROFILE_DESKTOP = 0x04, 409 SMBIOS_ENCLOSURE_PIZZA_BOX = 0x05, 410 SMBIOS_ENCLOSURE_MINI_TOWER = 0x06, 411 SMBIOS_ENCLOSURE_TOWER = 0x07, 412 SMBIOS_ENCLOSURE_PORTABLE = 0x08, 413 SMBIOS_ENCLOSURE_LAPTOP = 0x09, 414 SMBIOS_ENCLOSURE_NOTEBOOK = 0x0a, 415 SMBIOS_ENCLOSURE_HAND_HELD = 0x0b, 416 SMBIOS_ENCLOSURE_DOCKING_STATION = 0x0c, 417 SMBIOS_ENCLOSURE_ALL_IN_ONE = 0x0d, 418 SMBIOS_ENCLOSURE_SUB_NOTEBOOK = 0x0e, 419 SMBIOS_ENCLOSURE_SPACE_SAVING = 0x0f, 420 SMBIOS_ENCLOSURE_LUNCH_BOX = 0x10, 421 SMBIOS_ENCLOSURE_MAIN_SERVER_CHASSIS = 0x11, 422 SMBIOS_ENCLOSURE_EXPANSION_CHASSIS = 0x12, 423 SMBIOS_ENCLOSURE_SUBCHASSIS = 0x13, 424 SMBIOS_ENCLOSURE_BUS_EXPANSION_CHASSIS = 0x14, 425 SMBIOS_ENCLOSURE_PERIPHERAL_CHASSIS = 0x15, 426 SMBIOS_ENCLOSURE_RAID_CHASSIS = 0x16, 427 SMBIOS_ENCLOSURE_RACK_MOUNT_CHASSIS = 0x17, 428 SMBIOS_ENCLOSURE_SEALED_CASE_PC = 0x18, 429 SMBIOS_ENCLOSURE_MULTI_SYSTEM_CHASSIS = 0x19, 430 SMBIOS_ENCLOSURE_COMPACT_PCI = 0x1a, 431 SMBIOS_ENCLOSURE_ADVANCED_TCA = 0x1b, 432 SMBIOS_ENCLOSURE_BLADE = 0x1c, 433 SMBIOS_ENCLOSURE_BLADE_ENCLOSURE = 0x1d, 434 SMBIOS_ENCLOSURE_TABLET = 0x1e, 435 SMBIOS_ENCLOSURE_CONVERTIBLE = 0x1f, 436 SMBIOS_ENCLOSURE_DETACHABLE = 0x20, 437 SMBIOS_ENCLOSURE_IOT_GATEWAY = 0x21, 438 SMBIOS_ENCLOSURE_EMBEDDED_PC = 0x22, 439 SMBIOS_ENCLOSURE_MINI_PC = 0x23, 440 SMBIOS_ENCLOSURE_STICK_PC = 0x24, 441 } smbios_enclosure_type; 442 443 struct smbios_type3 { 444 struct smbios_header header; 445 u8 manufacturer; 446 u8 _type; 447 u8 version; 448 u8 serial_number; 449 u8 asset_tag_number; 450 u8 bootup_state; 451 u8 power_supply_state; 452 u8 thermal_state; 453 u8 security_status; 454 u32 oem_defined; 455 u8 height; 456 u8 number_of_power_cords; 457 u8 element_count; 458 u8 element_record_length; 459 u8 sku_number; 460 u8 eos[2]; 461 } __packed; 462 463 struct smbios_type4 { 464 struct smbios_header header; 465 u8 socket_designation; 466 u8 processor_type; 467 u8 processor_family; 468 u8 processor_manufacturer; 469 u32 processor_id[2]; 470 u8 processor_version; 471 u8 voltage; 472 u16 external_clock; 473 u16 max_speed; 474 u16 current_speed; 475 u8 status; 476 u8 processor_upgrade; 477 u16 l1_cache_handle; 478 u16 l2_cache_handle; 479 u16 l3_cache_handle; 480 u8 serial_number; 481 u8 asset_tag; 482 u8 part_number; 483 u8 core_count; 484 u8 core_enabled; 485 u8 thread_count; 486 u16 processor_characteristics; 487 u16 processor_family2; 488 u16 core_count2; 489 u16 core_enabled2; 490 u16 thread_count2; 491 u8 eos[2]; 492 } __packed; 493 494 /* defines for smbios_type4 */ 495 496 #define SMBIOS_PROCESSOR_STATUS_POPULATED (1 << 6) 497 #define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED (1 << 0) 498 499 enum smbios_processor_type { 500 SMBIOS_PROCESSOR_TYPE_OTHER = 0x01, 501 SMBIOS_PROCESSOR_TYPE_UNKNOWN = 0x02, 502 SMBIOS_PROCESSOR_TYPE_CENTRAL = 0x03, 503 SMBIOS_PROCESSOR_TYPE_MATH = 0x04, 504 SMBIOS_PROCESSOR_TYPE_DSP = 0x05, 505 SMBIOS_PROCESSOR_TYPE_VIDEO = 0x06, 506 }; 507 508 /* enum for socket type */ 509 enum smbios_processor_upgrade_field { 510 PROCESSOR_UPGRADE_OTHER = 0x01, 511 PROCESSOR_UPGRADE_UNKNOWN = 0x02, 512 PROCESSOR_UPGRADE_DAUGHTER_BOARD = 0x03, 513 PROCESSOR_UPGRADE_ZIF_SOCKET = 0x04, 514 PROCESSOR_UPGRADE_REPLACEABLE_PIGGY_BACK = 0x05, 515 PROCESSOR_UPGRADE_NONE = 0x06, 516 PROCESSOR_UPGRADE_LIF_SOCKET = 0x07, 517 PROCESSOR_UPGRADE_SLOT_1 = 0x08, 518 PROCESSOR_UPGRADE_SLOT_2 = 0x09, 519 PROCESSOR_UPGRADE_370_PIN_SOCKET = 0x0a, 520 PROCESSOR_UPGRADE_SLOT_A = 0x0b, 521 PROCESSOR_UPGRADE_SLOT_M = 0x0c, 522 PROCESSOR_UPGRADE_SOCKET_423 = 0x0d, 523 PROCESSOR_UPGRADE_SOCKET_A = 0x0e, 524 PROCESSOR_UPGRADE_SOCKET_478 = 0x0f, 525 PROCESSOR_UPGRADE_SOCKET_754 = 0x10, 526 PROCESSOR_UPGRADE_SOCKET_940 = 0x11, 527 PROCESSOR_UPGRADE_SOCKET_939 = 0x12, 528 PROCESSOR_UPGRADE_SOCKET_MPGA604 = 0x13, 529 PROCESSOR_UPGRADE_SOCKET_LGA771 = 0x14, 530 PROCESSOR_UPGRADE_SOCKET_LGA775 = 0x15, 531 PROCESSOR_UPGRADE_SOCKET_S1 = 0x16, 532 PROCESSOR_UPGRADE_SOCKET_AM2 = 0x17, 533 PROCESSOR_UPGRADE_SOCKET_F = 0x18, 534 PROCESSOR_UPGRADE_SOCKET_LGA1366 = 0x19, 535 PROCESSOR_UPGRADE_SOCKET_G34 = 0x1a, 536 PROCESSOR_UPGRADE_SOCKET_AM3 = 0x1b, 537 PROCESSOR_UPGRADE_SOCKET_C32 = 0x1c, 538 PROCESSOR_UPGRADE_SOCKET_LGA1156 = 0x1d, 539 PROCESSOR_UPGRADE_SOCKET_LGA1567 = 0x1e, 540 PROCESSOR_UPGRADE_SOCKET_PGA988A = 0x1f, 541 PROCESSOR_UPGRADE_SOCKET_BGA1288 = 0x20, 542 PROCESSOR_UPGRADE_SOCKET_RPGA988B = 0x21, 543 PROCESSOR_UPGRADE_SOCKET_BGA1023 = 0x22, 544 PROCESSOR_UPGRADE_SOCKET_BGA1224 = 0x23, 545 PROCESSOR_UPGRADE_SOCKET_LGA1155 = 0x24, 546 PROCESSOR_UPGRADE_SOCKET_LGA1356 = 0x25, 547 PROCESSOR_UPGRADE_SOCKET_LGA2011 = 0x26, 548 PROCESSOR_UPGRADE_SOCKET_FS1 = 0x27, 549 PROCESSOR_UPGRADE_SOCKET_FS2 = 0x28, 550 PROCESSOR_UPGRADE_SOCKET_FM1 = 0x29, 551 PROCESSOR_UPGRADE_SOCKET_FM2 = 0x2a, 552 PROCESSOR_UPGRADE_SOCKET_LGA2011_3 = 0x2b, 553 PROCESSOR_UPGRADE_SOCKET_LGA1356_3 = 0x2c, 554 PROCESSOR_UPGRADE_SOCKET_LGA1150 = 0x2d, 555 PROCESSOR_UPGRADE_SOCKET_BGA1168 = 0x2e, 556 PROCESSOR_UPGRADE_SOCKET_BGA1234 = 0x2f, 557 PROCESSOR_UPGRADE_SOCKET_BGA1364 = 0x30, 558 PROCESSOR_UPGRADE_SOCKET_AM4 = 0x31, 559 PROCESSOR_UPGRADE_SOCKET_LGA1151 = 0x32, 560 PROCESSOR_UPGRADE_SOCKET_BGA1356 = 0x33, 561 PROCESSOR_UPGRADE_SOCKET_BGA1440 = 0x34, 562 PROCESSOR_UPGRADE_SOCKET_BGA1515 = 0x35, 563 PROCESSOR_UPGRADE_SOCKET_LGA3647_1 = 0x36, 564 PROCESSOR_UPGRADE_SOCKET_SP3 = 0x37, 565 PROCESSOR_UPGRADE_SOCKET_SP3R2 = 0x38, 566 PROCESSOR_UPGRADE_SOCKET_LGA2066 = 0x39, 567 PROCESSOR_UPGRADE_SOCKET_BGA1392 = 0x3a, 568 PROCESSOR_UPGRADE_SOCKET_BGA1510 = 0x3b, 569 PROCESSOR_UPGRADE_SOCKET_BGA1528 = 0x3c, 570 PROCESSOR_UPGRADE_SOCKET_LGA4189 = 0x3d, 571 PROCESSOR_UPGRADE_SOCKET_LGA1200 = 0x3e, 572 PROCESSOR_UPGRADE_SOCKET_LGA4677 = 0x3f, 573 PROCESSOR_UPGRADE_SOCKET_LGA1700 = 0x40, 574 PROCESSOR_UPGRADE_SOCKET_BGA1744 = 0x41, 575 PROCESSOR_UPGRADE_SOCKET_BGA1781 = 0x42, 576 PROCESSOR_UPGRADE_SOCKET_BGA1211 = 0x43, 577 PROCESSOR_UPGRADE_SOCKET_BGA2422 = 0x44, 578 PROCESSOR_UPGRADE_SOCKET_LGA1211 = 0x45, 579 PROCESSOR_UPGRADE_SOCKET_LGA2422 = 0x46, 580 PROCESSOR_UPGRADE_SOCKET_LGA5773 = 0x47, 581 PROCESSOR_UPGRADE_SOCKET_BGA5773 = 0x48, 582 }; 583 584 /* defines for processor family */ 585 #define SMBIOS_PROCESSOR_FAMILY_OTHER 0x01 586 #define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 0x02 587 #define SMBIOS_PROCESSOR_FAMILY_INTEL486 0x06 588 #define SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO 0x0c 589 #define SMBIOS_PROCESSOR_FAMILY_XEON 0xb3 590 #define SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2 0xfe 591 592 /* defines for processor family 2 */ 593 #define SMBIOS_PROCESSOR_FAMILY2_ARMV8 0x101 594 595 /* defines for processor characteristics */ 596 #define PROCESSOR_64BIT_CAPABLE (1 << 2) 597 #define PROCESSOR_MULTI_CORE (1 << 3) 598 #define PROCESSOR_POWER_PERFORMANCE_CONTROL (1 << 7) 599 600 /* defines for supported_sram_type/current_sram_type */ 601 602 #define SMBIOS_CACHE_SRAM_TYPE_OTHER (1 << 0) 603 #define SMBIOS_CACHE_SRAM_TYPE_UNKNOWN (1 << 1) 604 #define SMBIOS_CACHE_SRAM_TYPE_NON_BURST (1 << 2) 605 #define SMBIOS_CACHE_SRAM_TYPE_BURST (1 << 3) 606 #define SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST (1 << 4) 607 #define SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS (1 << 5) 608 #define SMBIOS_CACHE_SRAM_TYPE_ASYNCHRONOUS (1 << 6) 609 610 /* enum for error_correction_type */ 611 612 enum smbios_cache_error_corr { 613 SMBIOS_CACHE_ERROR_CORRECTION_OTHER = 1, 614 SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN, 615 SMBIOS_CACHE_ERROR_CORRECTION_NONE, 616 SMBIOS_CACHE_ERROR_CORRECTION_PARITY, 617 SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT, 618 SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT, 619 }; 620 621 /* enum for system_cache_type */ 622 623 enum smbios_cache_type { 624 SMBIOS_CACHE_TYPE_OTHER = 1, 625 SMBIOS_CACHE_TYPE_UNKNOWN, 626 SMBIOS_CACHE_TYPE_INSTRUCTION, 627 SMBIOS_CACHE_TYPE_DATA, 628 SMBIOS_CACHE_TYPE_UNIFIED, 629 }; 630 631 /* enum for associativity */ 632 633 enum smbios_cache_associativity { 634 SMBIOS_CACHE_ASSOCIATIVITY_OTHER = 1, 635 SMBIOS_CACHE_ASSOCIATIVITY_UNKNOWN, 636 SMBIOS_CACHE_ASSOCIATIVITY_DIRECT, 637 SMBIOS_CACHE_ASSOCIATIVITY_2WAY, 638 SMBIOS_CACHE_ASSOCIATIVITY_4WAY, 639 SMBIOS_CACHE_ASSOCIATIVITY_FULL, 640 SMBIOS_CACHE_ASSOCIATIVITY_8WAY, 641 SMBIOS_CACHE_ASSOCIATIVITY_16WAY, 642 SMBIOS_CACHE_ASSOCIATIVITY_12WAY, 643 SMBIOS_CACHE_ASSOCIATIVITY_24WAY, 644 SMBIOS_CACHE_ASSOCIATIVITY_32WAY, 645 SMBIOS_CACHE_ASSOCIATIVITY_48WAY, 646 SMBIOS_CACHE_ASSOCIATIVITY_64WAY, 647 SMBIOS_CACHE_ASSOCIATIVITY_20WAY, 648 }; 649 650 /* defines for cache_configuration */ 651 652 #define SMBIOS_CACHE_CONF_LEVEL(x) ((((x) - 1) & 0x7) << 0) 653 #define SMBIOS_CACHE_CONF_LOCATION(x) (((x) & 0x3) << 5) 654 #define SMBIOS_CACHE_CONF_ENABLED(x) (((x) & 0x1) << 7) 655 #define SMBIOS_CACHE_CONF_OPERATION_MODE(x) (((x) & 0x3) << 8) 656 657 /* defines for max_cache_size and installed_size */ 658 659 #define SMBIOS_CACHE_SIZE_UNIT_1KB (0 << 15) 660 #define SMBIOS_CACHE_SIZE_UNIT_64KB (1 << 15) 661 #define SMBIOS_CACHE_SIZE_MASK 0x7fff 662 #define SMBIOS_CACHE_SIZE_OVERFLOW 0xffff 663 664 #define SMBIOS_CACHE_SIZE2_UNIT_1KB (0 << 31) 665 #define SMBIOS_CACHE_SIZE2_UNIT_64KB (1UL << 31) 666 #define SMBIOS_CACHE_SIZE2_MASK 0x7fffffff 667 668 /* define for cache operation mode */ 669 670 #define SMBIOS_CACHE_OP_MODE_WRITE_THROUGH 0 671 #define SMBIOS_CACHE_OP_MODE_WRITE_BACK 1 672 #define SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS 2 673 #define SMBIOS_CACHE_OP_MODE_UNKNOWN 3 674 675 struct smbios_type7 { 676 struct smbios_header header; 677 u8 socket_designation; 678 u16 cache_configuration; 679 u16 max_cache_size; 680 u16 installed_size; 681 u16 supported_sram_type; 682 u16 current_sram_type; 683 u8 cache_speed; 684 u8 error_correction_type; 685 u8 system_cache_type; 686 u8 associativity; 687 u32 max_cache_size2; 688 u32 installed_size2; 689 u8 eos[2]; 690 } __packed; 691 692 /* enum for connector types */ 693 typedef enum { 694 CONN_NONE = 0x00, 695 CONN_CENTRONICS = 0x01, 696 CONN_MINI_CENTRONICS = 0x02, 697 CONN_PROPRIETARY = 0x03, 698 CONN_DB_25_PIN_MALE = 0x04, 699 CONN_DB_25_PIN_FEMALE = 0x05, 700 CONN_DB_15_PIN_MALE = 0x06, 701 CONN_DB_15_PIN_FEMALE = 0x07, 702 CONN_DB_9_PIN_MALE = 0x08, 703 CONN_DB_9_PIN_FEMALE = 0x09, 704 CONN_RJ_11 = 0x0A, 705 CONN_RJ_45 = 0x0B, 706 CONN_50_PIN_MINI_SCSI = 0x0C, 707 CONN_MINI_DIN = 0x0D, 708 CONN_MICRO_DIN = 0x0E, 709 CONN_PS_2 = 0x0F, 710 CONN_INFRARED = 0x10, 711 CONN_HP_HIL = 0x11, 712 CONN_ACCESS_BUS_USB = 0x12, 713 CONN_SSA_SCSI = 0x13, 714 CONN_CIRCULAR_DIN_8_MALE = 0x14, 715 CONN_CIRCULAR_DIN_8_FEMALE = 0x15, 716 CONN_ON_BOARD_IDE = 0x16, 717 CONN_ON_BOARD_FLOPPY = 0x17, 718 CONN_9_PIN_DUAL_INLINE = 0x18, 719 CONN_25_PIN_DUAL_INLINE = 0x19, 720 CONN_50_PIN_DUAL_INLINE = 0x1A, 721 CONN_68_PIN_DUAL_INLINE = 0x1B, 722 CONN_ON_BOARD_SOUND_INPUT_FROM_CD_ROM = 0x1C, 723 CONN_MINI_CENTRONICS_TYPE14 = 0x1D, 724 CONN_MINI_CENTRONICS_TYPE26 = 0x1E, 725 CONN_MINI_JACK_HEADPHONES = 0x1F, 726 CONN_BNC = 0x20, 727 CONN_1394 = 0x21, 728 CONN_SAS_SATA = 0x22, 729 CONN_USB_TYPE_C = 0x23, 730 CONN_PC_98 = 0xA0, 731 CONN_PC_98_HIRESO = 0xA1, 732 CONN_PC_H98 = 0xA2, 733 CONN_PC98_NOTE = 0xA3, 734 CONN_PC_98_FULL = 0xA4, 735 CONN_OTHER = 0xFF, 736 } type8_connector_types; 737 738 /* enum for port types */ 739 typedef enum { 740 TYPE_NONE_PORT = 0x00, 741 TYPE_PARALLEL_PORT_XT_AT_COMPATIBLE = 0x01, 742 TYPE_PARALLEL_PORT_PS_2 = 0x02, 743 TYPE_PARALLEL_PORT_ECP = 0x03, 744 TYPE_PARALLEL_PORT_EPP = 0x04, 745 TYPE_PARALLEL_PORT_ECP_EPP = 0x05, 746 TYPE_SERIAL_PORT_XT_AT_COMPATIBLE = 0x06, 747 TYPE_SERIAL_PORT_16450_COMPATIBLE = 0x07, 748 TYPE_SERIAL_PORT_16550_COMPATIBLE = 0x08, 749 TYPE_SERIAL_PORT_16550A_COMPATIBLE = 0x09, 750 TYPE_SCSI_PORT = 0x0A, 751 TYPE_MIDI_PORT = 0x0B, 752 TYPE_JOY_STICK_PORT = 0x0C, 753 TYPE_KEYBOARD_PORT = 0x0D, 754 TYPE_MOUSE_PORT = 0x0E, 755 TYPE_SSA_SCSI = 0x0F, 756 TYPE_USB = 0x10, 757 TYPE_FIREWIRE_IEEE_P1394 = 0x11, 758 TYPE_PCMCIA_TYPE_I = 0x12, 759 TYPE_PCMCIA_TYPE_II = 0x13, 760 TYPE_PCMCIA_TYPE_III = 0x14, 761 TYPE_CARDBUS = 0x15, 762 TYPE_ACCESS_BUS_PORT = 0x16, 763 TYPE_SCSI_II = 0x17, 764 TYPE_SCSI_WIDE = 0x18, 765 TYPE_PC_98 = 0x19, 766 TYPE_PC_98_HIRESO = 0x1A, 767 TYPE_PC_H98 = 0x1B, 768 TYPE_VIDEO_PORT = 0x1C, 769 TYPE_AUDIO_PORT = 0x1D, 770 TYPE_MODEM_PORT = 0x1E, 771 TYPE_NETWORK_PORT = 0x1F, 772 TYPE_SATA = 0x20, 773 TYPE_SAS = 0x21, 774 TYPE_MFDP = 0x22, 775 TYPE_THUNDERBOLT = 0x23, 776 TYPE_8251_COMPATIBLE = 0xA0, 777 TYPE_8251_FIFO_COMPATIBLE = 0xA1, 778 TYPE_OTHER_PORT = 0xFF, 779 } type8_port_types; 780 781 struct port_information { 782 const char *internal_reference_designator; 783 type8_connector_types internal_connector_type; 784 const char *external_reference_designator; 785 type8_connector_types external_connector_type; 786 type8_port_types port_type; 787 }; 788 789 struct smbios_type8 { 790 struct smbios_header header; 791 u8 internal_reference_designator; 792 u8 internal_connector_type; 793 u8 external_reference_designator; 794 u8 external_connector_type; 795 u8 port_type; 796 u8 eos[2]; 797 } __packed; 798 799 /* System Slots - Slot Type */ 800 enum misc_slot_type { 801 SlotTypeOther = 0x01, 802 SlotTypeUnknown = 0x02, 803 SlotTypeIsa = 0x03, 804 SlotTypeMca = 0x04, 805 SlotTypeEisa = 0x05, 806 SlotTypePci = 0x06, 807 SlotTypePcmcia = 0x07, 808 SlotTypeVlVesa = 0x08, 809 SlotTypeProprietary = 0x09, 810 SlotTypeProcessorCardSlot = 0x0A, 811 SlotTypeProprietaryMemoryCardSlot = 0x0B, 812 SlotTypeIORiserCardSlot = 0x0C, 813 SlotTypeNuBus = 0x0D, 814 SlotTypePci66MhzCapable = 0x0E, 815 SlotTypeAgp = 0x0F, 816 SlotTypeApg2X = 0x10, 817 SlotTypeAgp4X = 0x11, 818 SlotTypePciX = 0x12, 819 SlotTypeAgp8X = 0x13, 820 SlotTypeM2Socket1_DP = 0x14, 821 SlotTypeM2Socket1_SD = 0x15, 822 SlotTypeM2Socket2 = 0x16, 823 SlotTypeM2Socket3 = 0x17, 824 SlotTypeMxmTypeI = 0x18, 825 SlotTypeMxmTypeII = 0x19, 826 SlotTypeMxmTypeIIIStandard = 0x1A, 827 SlotTypeMxmTypeIIIHe = 0x1B, 828 SlotTypeMxmTypeIV = 0x1C, 829 SlotTypeMxm30TypeA = 0x1D, 830 SlotTypeMxm30TypeB = 0x1E, 831 SlotTypePciExpressGen2Sff_8639 = 0x1F, 832 SlotTypePciExpressGen3Sff_8639 = 0x20, 833 SlotTypePciExpressMini52pinWithBSKO = 0x21, 834 SlotTypePciExpressMini52pinWithoutBSKO = 0x22, 835 SlotTypePciExpressMini76pin = 0x23, 836 SlotTypePciExpressOCPNIC30SFF = 0x26, 837 SlotTypePC98C20 = 0xA0, 838 SlotTypePC98C24 = 0xA1, 839 SlotTypePC98E = 0xA2, 840 SlotTypePC98LocalBus = 0xA3, 841 SlotTypePC98Card = 0xA4, 842 SlotTypePciExpress = 0xA5, 843 SlotTypePciExpressX1 = 0xA6, 844 SlotTypePciExpressX2 = 0xA7, 845 SlotTypePciExpressX4 = 0xA8, 846 SlotTypePciExpressX8 = 0xA9, 847 SlotTypePciExpressX16 = 0xAA, 848 SlotTypePciExpressGen2 = 0xAB, 849 SlotTypePciExpressGen2X1 = 0xAC, 850 SlotTypePciExpressGen2X2 = 0xAD, 851 SlotTypePciExpressGen2X4 = 0xAE, 852 SlotTypePciExpressGen2X8 = 0xAF, 853 SlotTypePciExpressGen2X16 = 0xB0, 854 SlotTypePciExpressGen3 = 0xB1, 855 SlotTypePciExpressGen3X1 = 0xB2, 856 SlotTypePciExpressGen3X2 = 0xB3, 857 SlotTypePciExpressGen3X4 = 0xB4, 858 SlotTypePciExpressGen3X8 = 0xB5, 859 SlotTypePciExpressGen3X16 = 0xB6, 860 SlotTypePciExpressGen4 = 0xB8, 861 SlotTypePciExpressGen4x1 = 0xB9, 862 SlotTypePciExpressGen4x2 = 0xBA, 863 SlotTypePciExpressGen4x4 = 0xBB, 864 SlotTypePciExpressGen4x8 = 0xBC, 865 SlotTypePciExpressGen4x16 = 0xBD, 866 SlotTypePciExpressGen5 = 0xBE, 867 SlotTypePciExpressGen5x1 = 0xBF, 868 SlotTypePciExpressGen5x2 = 0xC0, 869 SlotTypePciExpressGen5x4 = 0xC1, 870 SlotTypePciExpressGen5x8 = 0xC2, 871 SlotTypePciExpressGen5x16 = 0xC3 872 }; 873 874 /* System Slots - Slot Data Bus Width. */ 875 enum slot_data_bus_bandwidth { 876 SlotDataBusWidthOther = 0x01, 877 SlotDataBusWidthUnknown = 0x02, 878 SlotDataBusWidth8Bit = 0x03, 879 SlotDataBusWidth16Bit = 0x04, 880 SlotDataBusWidth32Bit = 0x05, 881 SlotDataBusWidth64Bit = 0x06, 882 SlotDataBusWidth128Bit = 0x07, 883 SlotDataBusWidth1X = 0x08, 884 SlotDataBusWidth2X = 0x09, 885 SlotDataBusWidth4X = 0x0A, 886 SlotDataBusWidth8X = 0x0B, 887 SlotDataBusWidth12X = 0x0C, 888 SlotDataBusWidth16X = 0x0D, 889 SlotDataBusWidth32X = 0x0E 890 }; 891 892 /* System Slots - Current Usage. */ 893 enum misc_slot_usage { 894 SlotUsageOther = 0x01, 895 SlotUsageUnknown = 0x02, 896 SlotUsageAvailable = 0x03, 897 SlotUsageInUse = 0x04, 898 SlotUsageUnavailable = 0x05 899 }; 900 901 /* System Slots - Slot Length.*/ 902 enum misc_slot_length { 903 SlotLengthOther = 0x01, 904 SlotLengthUnknown = 0x02, 905 SlotLengthShort = 0x03, 906 SlotLengthLong = 0x04 907 }; 908 909 /* System Slots - Slot Characteristics 1. */ 910 #define SMBIOS_SLOT_UNKNOWN (1 << 0) 911 #define SMBIOS_SLOT_5V (1 << 1) 912 #define SMBIOS_SLOT_3P3V (1 << 2) 913 #define SMBIOS_SLOT_SHARED (1 << 3) 914 #define SMBIOS_SLOT_PCCARD_16 (1 << 4) 915 #define SMBIOS_SLOT_PCCARD_CARDBUS (1 << 5) 916 #define SMBIOS_SLOT_PCCARD_ZOOM (1 << 6) 917 #define SMBIOS_SLOT_PCCARD_MODEM_RING (1 << 7) 918 /* System Slots - Slot Characteristics 2. */ 919 #define SMBIOS_SLOT_PME (1 << 0) 920 #define SMBIOS_SLOT_HOTPLUG (1 << 1) 921 #define SMBIOS_SLOT_SMBUS (1 << 2) 922 #define SMBIOS_SLOT_BIFURCATION (1 << 3) 923 924 struct slot_peer_groups { 925 u16 peer_seg_num; 926 u8 peer_bus_num; 927 u8 peer_dev_fn_num; 928 u8 peer_data_bus_width; 929 } __packed; 930 931 struct smbios_type9 { 932 struct smbios_header header; 933 u8 slot_designation; 934 u8 slot_type; 935 u8 slot_data_bus_width; 936 u8 current_usage; 937 u8 slot_length; 938 u16 slot_id; 939 u8 slot_characteristics_1; 940 u8 slot_characteristics_2; 941 u16 segment_group_number; 942 u8 bus_number; 943 u8 device_function_number; 944 u8 data_bus_width; 945 u8 peer_group_count; 946 struct slot_peer_groups peer[0]; 947 u8 eos[2]; 948 } __packed; 949 950 struct smbios_type11 { 951 struct smbios_header header; 952 u8 count; 953 u8 eos[2]; 954 } __packed; 955 956 struct smbios_type15 { 957 struct smbios_header header; 958 u16 area_length; 959 u16 header_offset; 960 u16 data_offset; 961 u8 access_method; 962 u8 log_status; 963 u32 change_token; 964 u32 address; 965 u8 header_format; 966 u8 log_type_descriptors; 967 u8 log_type_descriptor_length; 968 u8 eos[2]; 969 } __packed; 970 971 enum { 972 SMBIOS_EVENTLOG_ACCESS_METHOD_IO8 = 0, 973 SMBIOS_EVENTLOG_ACCESS_METHOD_IO8X2, 974 SMBIOS_EVENTLOG_ACCESS_METHOD_IO16, 975 SMBIOS_EVENTLOG_ACCESS_METHOD_MMIO32, 976 SMBIOS_EVENTLOG_ACCESS_METHOD_GPNV, 977 }; 978 979 enum { 980 SMBIOS_EVENTLOG_STATUS_VALID = 1, /* Bit 0 */ 981 SMBIOS_EVENTLOG_STATUS_FULL = 2, /* Bit 1 */ 982 }; 983 984 #define SMBIOS_USE_EXTENDED_MAX_CAPACITY (1ULL << 31) 985 986 struct smbios_type16 { 987 struct smbios_header header; 988 u8 location; 989 u8 use; 990 u8 memory_error_correction; 991 u32 maximum_capacity; 992 u16 memory_error_information_handle; 993 u16 number_of_memory_devices; 994 u64 extended_maximum_capacity; 995 u8 eos[2]; 996 } __packed; 997 998 struct smbios_type17 { 999 struct smbios_header header; 1000 u16 phys_memory_array_handle; 1001 u16 memory_error_information_handle; 1002 u16 total_width; 1003 u16 data_width; 1004 u16 size; 1005 u8 form_factor; 1006 u8 device_set; 1007 u8 device_locator; 1008 u8 bank_locator; 1009 u8 memory_type; 1010 u16 type_detail; 1011 u16 speed; 1012 u8 manufacturer; 1013 u8 serial_number; 1014 u8 asset_tag; 1015 u8 part_number; 1016 u8 attributes; 1017 u32 extended_size; 1018 u16 clock_speed; 1019 u16 minimum_voltage; 1020 u16 maximum_voltage; 1021 u16 configured_voltage; 1022 u8 eos[2]; 1023 } __packed; 1024 1025 struct smbios_type19 { 1026 struct smbios_header header; 1027 u32 starting_address; 1028 u32 ending_address; 1029 u16 memory_array_handle; 1030 u8 partition_width; 1031 u64 extended_starting_address; 1032 u64 extended_ending_address; 1033 u8 eos[2]; 1034 } __packed; 1035 1036 struct smbios_type20 { 1037 struct smbios_header header; 1038 u32 addr_start; 1039 u32 addr_end; 1040 u16 memory_device_handle; 1041 u16 memory_array_mapped_address_handle; 1042 u8 partition_row_pos; 1043 u8 interleave_pos; 1044 u8 interleave_depth; 1045 u64 ext_addr_start; 1046 u64 ext_addr_end; 1047 u8 eos[2]; 1048 } __packed; 1049 1050 /* Bit[7..5] = Temp status */ 1051 enum smbios_temp_status { 1052 SMBIOS_TEMP_STATUS_OTHER = 0x01, 1053 SMBIOS_TEMP_STATUS_UNKNOWN, 1054 SMBIOS_TEMP_STATUS_OK, 1055 SMBIOS_TEMP_STATUS_NONCRITICAL, 1056 SMBIOS_TEMP_STATUS_CRITICAL, 1057 SMBIOS_TEMP_STATUS_NONREC, // Non-Recoverable. 1058 }; 1059 1060 /* Bit[4..0] = Temp location */ 1061 enum smbios_temp_location { 1062 SMBIOS_TEMP_LOCATION_OTHER = 0x01, 1063 SMBIOS_TEMP_LOCATION_UNKNOWN, 1064 SMBIOS_TEMP_LOCATION_PROCESSOR, 1065 SMBIOS_TEMP_LOCATION_DISK, 1066 SMBIOS_TEMP_LOCATION_BAY, // Peripheral Bay. 1067 SMBIOS_TEMP_LOCATION_SMM, // System Management Module. 1068 SMBIOS_TEMP_LOCATION_BOARD, // Motherboard. 1069 SMBIOS_TEMP_LOCATION_MM, // Memory. 1070 SMBIOS_TEMP_LOCATION_PM, // Processor Module. 1071 SMBIOS_TEMP_LOCATION_POW, // Power Unit. 1072 SMBIOS_TEMP_LOCATION_ADDCARD, 1073 }; 1074 1075 struct smbios_type28 { 1076 struct smbios_header header; 1077 u8 description; 1078 u8 location_and_status; 1079 u16 maximum_value; 1080 u16 minimum_value; 1081 u16 resolution; 1082 u16 tolerance; 1083 u16 accuracy; 1084 u32 oem_defined; 1085 u16 nominal_value; 1086 u8 eos[2]; 1087 } __packed; 1088 1089 1090 struct smbios_type32 { 1091 struct smbios_header header; 1092 u8 reserved[6]; 1093 u8 boot_status; 1094 u8 eos[2]; 1095 } __packed; 1096 1097 struct smbios_type38 { 1098 struct smbios_header header; 1099 u8 interface_type; 1100 u8 ipmi_rev; 1101 u8 i2c_slave_addr; 1102 u8 nv_storage_addr; 1103 u64 base_address; 1104 u8 base_address_modifier; 1105 u8 irq; 1106 u8 eos[2]; 1107 } __packed; 1108 1109 enum smbios_bmc_interface_type { 1110 SMBIOS_BMC_INTERFACE_UNKNOWN = 0, 1111 SMBIOS_BMC_INTERFACE_KCS, 1112 SMBIOS_BMC_INTERFACE_SMIC, 1113 SMBIOS_BMC_INTERFACE_BLOCK, 1114 SMBIOS_BMC_INTERFACE_SMBUS, 1115 }; 1116 1117 typedef enum { 1118 PowerSupplyTypeOther = 1, 1119 PowerSupplyTypeUnknown = 2, 1120 PowerSupplyTypeLinear = 3, 1121 PowerSupplyTypeSwitching = 4, 1122 PowerSupplyTypeBattery = 5, 1123 PowerSupplyTypeUps = 6, 1124 PowerSupplyTypeConverter = 7, 1125 PowerSupplyTypeRegulator = 8 1126 } power_supply_type; 1127 1128 typedef enum { 1129 PowerSupplyStatusOther = 1, 1130 PowerSupplyStatusUnknown = 2, 1131 PowerSupplyStatusOk = 3, 1132 PowerSupplyStatusNonCritical = 4, 1133 PowerSupplyStatusCritical = 5 1134 } power_supply_status; 1135 1136 typedef enum { 1137 PowerSupplyInputVoltageRangeSwitchingOther = 1, 1138 PowerSupplyInputVoltageRangeSwitchingUnknown = 2, 1139 PowerSupplyInputVoltageRangeSwitchingManual = 3, 1140 PowerSupplyInputVoltageRangeSwitchingAutoSwitch = 4, 1141 PowerSupplyInputVoltageRangeSwitchingWideRange = 5, 1142 PowerSupplyInputVoltageRangeSwitchingNotApplicable = 6 1143 } power_supply_input_voltage_range_switching; 1144 1145 struct power_supply_ch { 1146 u16 reserved :2; 1147 u16 power_supply_type :4; 1148 u16 power_supply_status :3; 1149 u16 input_voltage_range_switch :4; 1150 u16 power_supply_unplugged :1; 1151 u16 power_supply_present :1; 1152 u16 power_supply_hot_replaceble :1; 1153 }; 1154 1155 struct smbios_type39 { 1156 struct smbios_header header; 1157 u8 power_unit_group; 1158 u8 location; 1159 u8 device_name; 1160 u8 manufacturer; 1161 u8 serial_number; 1162 u8 asset_tag_number; 1163 u8 model_part_number; 1164 u8 revision_level; 1165 u16 max_power_capacity; 1166 u16 power_supply_characteristics; 1167 u16 input_voltage_probe_handle; 1168 u16 cooling_device_handle; 1169 u16 input_current_probe_handle; 1170 u8 eos[2]; 1171 } __packed; 1172 1173 int smbios_write_type39(unsigned long *current, int *handle, 1174 u8 unit_group, const char *loc, const char *dev_name, 1175 const char *man, const char *serial_num, 1176 const char *tag_num, const char *part_num, 1177 const char *rev_lvl, u16 max_pow_cap, 1178 const struct power_supply_ch *ps_ch); 1179 1180 typedef enum { 1181 SMBIOS_DEVICE_TYPE_OTHER = 0x01, 1182 SMBIOS_DEVICE_TYPE_UNKNOWN, 1183 SMBIOS_DEVICE_TYPE_VIDEO, 1184 SMBIOS_DEVICE_TYPE_SCSI, 1185 SMBIOS_DEVICE_TYPE_ETHERNET, 1186 SMBIOS_DEVICE_TYPE_TOKEN_RING, 1187 SMBIOS_DEVICE_TYPE_SOUND, 1188 SMBIOS_DEVICE_TYPE_PATA, 1189 SMBIOS_DEVICE_TYPE_SATA, 1190 SMBIOS_DEVICE_TYPE_SAS, 1191 SMBIOS_DEVICE_TYPE_WIRELESS_LAN, 1192 SMBIOS_DEVICE_TYPE_BLUETOOTH, 1193 SMBIOS_DEVICE_TYPE_WWAN, 1194 SMBIOS_DEVICE_TYPE_EMMC, 1195 SMBIOS_DEVICE_TYPE_NVME, 1196 SMBIOS_DEVICE_TYPE_UFS, 1197 } smbios_onboard_device_type; 1198 1199 #define SMBIOS_DEVICE_TYPE_COUNT 10 1200 1201 struct smbios_type41 { 1202 struct smbios_header header; 1203 u8 reference_designation; 1204 u8 device_type: 7; 1205 u8 device_status: 1; 1206 u8 device_type_instance; 1207 u16 segment_group_number; 1208 u8 bus_number; 1209 u8 function_number: 3; 1210 u8 device_number: 5; 1211 u8 eos[2]; 1212 } __packed; 1213 1214 1215 #define SMBIOS_TPM_DEVICE_CHARACTERISTICS_NOT_SUPPORTED (1ULL << 2) 1216 #define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_FW_UPD (1ULL << 3) 1217 #define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_PLATFORM_SW_SUPPORT (1ULL << 4) 1218 #define SMBIOS_TPM_DEVICE_FAMILY_CONFIGURABLE_VIA_OEM_PROPRIETARY (1ULL << 5) 1219 1220 struct smbios_type43 { 1221 struct smbios_header header; 1222 u32 vendor_id; 1223 u8 major_spec_ver; 1224 u8 minor_spec_ver; 1225 u32 fw_ver1; 1226 u32 fw_ver2; 1227 u8 description; 1228 u64 characteristics; 1229 u32 oem_defined; 1230 u8 eos[2]; 1231 } __packed; 1232 1233 struct smbios_type127 { 1234 struct smbios_header header; 1235 u8 eos[2]; 1236 } __packed; 1237 1238 /* Provided to help architecture code */ 1239 int smbios_write_type7(unsigned long *current, 1240 const int handle, 1241 const u8 level, 1242 const u8 sram_type, 1243 const enum smbios_cache_associativity associativity, 1244 const enum smbios_cache_type type, 1245 const size_t max_cache_size, 1246 const size_t cache_size); 1247 enum smbios_cache_associativity smbios_cache_associativity(const u8 num); 1248 1249 /* Must be defined by architecture code */ 1250 int smbios_write_type4(unsigned long *current, int handle); 1251 int smbios_write_type7_cache_parameters(unsigned long *current, 1252 int *handle, 1253 int *max_struct_size, 1254 struct smbios_type4 *type4); 1255 1256 void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, 1257 struct smbios_type17 *t); 1258 void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, 1259 struct smbios_type17 *t); 1260 void smbios_fill_dimm_locator(const struct dimm_info *dimm, 1261 struct smbios_type17 *t); 1262 1263 smbios_wakeup_type smbios_system_wakeup_type(void); 1264 smbios_board_type smbios_mainboard_board_type(void); 1265 smbios_enclosure_type smbios_mainboard_enclosure_type(void); 1266 1267 #endif 1268