1 /*
2 * Copyright (C) 2019-2020 Collabora, Ltd.
3 * Copyright (C) 2019 Alyssa Rosenzweig <[email protected]>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #ifndef _MDG_COMPILER_H
26 #define _MDG_COMPILER_H
27
28 #include "helpers.h"
29 #include "midgard.h"
30 #include "midgard_compile.h"
31 #include "midgard_ops.h"
32
33 #include "util/hash_table.h"
34 #include "util/list.h"
35 #include "util/set.h"
36 #include "util/u_dynarray.h"
37 #include "util/u_math.h"
38
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir.h"
41 #include "panfrost/util/lcra.h"
42 #include "panfrost/util/pan_ir.h"
43
44 /* Forward declare */
45 struct midgard_block;
46
47 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
48 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
49 * instruction is actually a discard op. */
50
51 #define TARGET_GOTO 0
52 #define TARGET_BREAK 1
53 #define TARGET_CONTINUE 2
54 #define TARGET_DISCARD 3
55 #define TARGET_TILEBUF_WAIT 4
56
57 typedef struct midgard_branch {
58 /* If conditional, the condition is specified in r31.w */
59 bool conditional;
60
61 /* For conditionals, if this is true, we branch on FALSE. If false, we branch
62 * on TRUE. */
63 bool invert_conditional;
64
65 /* Branch targets: the start of a block, the start of a loop (continue), the
66 * end of a loop (break). Value is one of TARGET_ */
67 unsigned target_type;
68
69 /* The actual target */
70 union {
71 int target_block;
72 int target_break;
73 int target_continue;
74 };
75 } midgard_branch;
76
77 /* Generic in-memory data type repesenting a single logical instruction, rather
78 * than a single instruction group. This is the preferred form for code gen.
79 * Multiple midgard_insturctions will later be combined during scheduling,
80 * though this is not represented in this structure. Its format bridges
81 * the low-level binary representation with the higher level semantic meaning.
82 *
83 * Notably, it allows registers to be specified as block local SSA, for code
84 * emitted before the register allocation pass.
85 */
86
87 #define MIR_SRC_COUNT 4
88 #define MIR_VEC_COMPONENTS 16
89
90 typedef struct midgard_instruction {
91 /* Must be first for casting */
92 struct list_head link;
93
94 unsigned type; /* ALU, load/store, texture */
95
96 /* Instruction arguments represented as block-local SSA
97 * indices, rather than registers. ~0 means unused. */
98 unsigned src[MIR_SRC_COUNT];
99 unsigned dest;
100
101 /* vec16 swizzle, unpacked, per source */
102 unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
103
104 /* Types! */
105 nir_alu_type src_types[MIR_SRC_COUNT];
106 nir_alu_type dest_type;
107
108 /* Packing ops have non-32-bit dest types even though they functionally
109 * work at the 32-bit level, use this as a signal to disable copyprop.
110 * We maybe need synthetic pack ops instead. */
111 bool is_pack;
112
113 /* Modifiers, depending on type */
114 union {
115 struct {
116 bool src_abs[MIR_SRC_COUNT];
117 bool src_neg[MIR_SRC_COUNT];
118 };
119
120 struct {
121 bool src_shift[MIR_SRC_COUNT];
122 };
123 };
124
125 /* Out of the union for csel (could maybe be fixed..) */
126 bool src_invert[MIR_SRC_COUNT];
127
128 /* If the op supports it */
129 enum midgard_roundmode roundmode;
130
131 /* For textures: should helpers execute this instruction (instead of
132 * just helping with derivatives)? Should helpers terminate after? */
133 bool helper_terminate;
134 bool helper_execute;
135
136 /* I.e. (1 << alu_bit) */
137 int unit;
138
139 bool has_constants;
140 midgard_constants constants;
141 uint16_t inline_constant;
142 bool has_inline_constant;
143
144 bool compact_branch;
145 uint8_t writeout;
146 bool last_writeout;
147
148 /* Masks in a saneish format. One bit per channel, not packed fancy.
149 * Use this instead of the op specific ones, and switch over at emit
150 * time */
151
152 uint16_t mask;
153
154 /* Hint for the register allocator not to spill the destination written
155 * from this instruction (because it is a spill/unspill node itself).
156 * Bitmask of spilled classes */
157
158 unsigned no_spill;
159
160 /* Generic hint for intra-pass use */
161 bool hint;
162
163 /* During scheduling, the backwards dependency graph
164 * (DAG). nr_dependencies is the number of unscheduled
165 * instructions that must still be scheduled after
166 * (before) this instruction. dependents are which
167 * instructions need to be scheduled before (after) this
168 * instruction. */
169
170 unsigned nr_dependencies;
171 BITSET_WORD *dependents;
172
173 /* Use this in conjunction with `type` */
174 unsigned op;
175
176 /* This refers to midgard_outmod_float or midgard_outmod_int.
177 * In case of a ALU op, use midgard_is_integer_out_op() to know which
178 * one is used.
179 * If it's a texture op, it's always midgard_outmod_float. */
180 unsigned outmod;
181
182 union {
183 midgard_load_store_word load_store;
184 midgard_texture_word texture;
185
186 midgard_branch branch;
187 };
188
189 unsigned bundle_id;
190 } midgard_instruction;
191
192 typedef struct midgard_block {
193 pan_block base;
194
195 bool scheduled;
196
197 /* List of midgard_bundles emitted (after the scheduler has run) */
198 struct util_dynarray bundles;
199
200 /* Number of quadwords _actually_ emitted, as determined after scheduling */
201 unsigned quadword_count;
202
203 /* Indicates this is a fixed-function fragment epilogue block */
204 bool epilogue;
205
206 /* Are helper invocations required by this block? */
207 bool helpers_in;
208 } midgard_block;
209
210 typedef struct midgard_bundle {
211 /* Tag for the overall bundle */
212 int tag;
213
214 /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
215 * sadd, vadd, smul, vlut, branch) */
216 int instruction_count;
217 midgard_instruction *instructions[6];
218
219 /* Bundle-wide ALU configuration */
220 int padding;
221 int control;
222 bool has_embedded_constants;
223 midgard_constants constants;
224 bool last_writeout;
225 } midgard_bundle;
226
227 enum midgard_rt_id {
228 MIDGARD_COLOR_RT0 = 0,
229 MIDGARD_COLOR_RT1,
230 MIDGARD_COLOR_RT2,
231 MIDGARD_COLOR_RT3,
232 MIDGARD_COLOR_RT4,
233 MIDGARD_COLOR_RT5,
234 MIDGARD_COLOR_RT6,
235 MIDGARD_COLOR_RT7,
236 MIDGARD_ZS_RT,
237 MIDGARD_NUM_RTS,
238 };
239
240 #define MIDGARD_MAX_SAMPLE_ITER 16
241
242 typedef struct compiler_context {
243 const struct panfrost_compile_inputs *inputs;
244 nir_shader *nir;
245 struct pan_shader_info *info;
246 gl_shader_stage stage;
247
248 /* Index to precolour to r0 for an input blend colour */
249 unsigned blend_input;
250
251 /* Index to precolour to r2 for a dual-source blend colour */
252 unsigned blend_src1;
253
254 /* Count of spills and fills for shaderdb */
255 unsigned spills;
256 unsigned fills;
257
258 /* Current NIR function */
259 nir_function *func;
260
261 /* Allocated compiler temporary counter */
262 unsigned temp_alloc;
263
264 /* Unordered list of midgard_blocks */
265 int block_count;
266 struct list_head blocks;
267
268 /* TODO merge with block_count? */
269 unsigned block_source_count;
270
271 /* List of midgard_instructions emitted for the current block */
272 midgard_block *current_block;
273
274 /* If there is a preset after block, use this, otherwise emit_block will
275 * create one if NULL */
276 midgard_block *after_block;
277
278 /* The current "depth" of the loop, for disambiguating breaks/continues
279 * when using nested loops */
280 int current_loop_depth;
281
282 /* Total number of loops for shader-db */
283 unsigned loop_count;
284
285 /* Constants which have been loaded, for later inlining */
286 struct hash_table_u64 *ssa_constants;
287
288 int temp_count;
289 int max_hash;
290
291 /* Count of instructions emitted from NIR overall, across all blocks */
292 int instruction_count;
293
294 unsigned quadword_count;
295
296 /* Bitmask of valid metadata */
297 unsigned metadata;
298
299 /* Model-specific quirk set */
300 uint32_t quirks;
301
302 /* Writeout instructions for each render target */
303 midgard_instruction
304 *writeout_branch[MIDGARD_NUM_RTS][MIDGARD_MAX_SAMPLE_ITER];
305
306 /* Mask of UBOs that need to be uploaded */
307 uint32_t ubo_mask;
308 } compiler_context;
309
310 /* Per-block live_in/live_out */
311 #define MIDGARD_METADATA_LIVENESS (1 << 0)
312
313 /* Helpers for manipulating the above structures (forming the driver IR) */
314
315 /* Append instruction to end of current block */
316
317 static inline midgard_instruction *
mir_upload_ins(struct compiler_context * ctx,struct midgard_instruction ins)318 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
319 {
320 midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
321 memcpy(heap, &ins, sizeof(ins));
322 return heap;
323 }
324
325 static inline midgard_instruction *
emit_mir_instruction(struct compiler_context * ctx,struct midgard_instruction ins)326 emit_mir_instruction(struct compiler_context *ctx,
327 struct midgard_instruction ins)
328 {
329 midgard_instruction *u = mir_upload_ins(ctx, ins);
330 list_addtail(&u->link, &ctx->current_block->base.instructions);
331 return u;
332 }
333
334 static inline struct midgard_instruction *
mir_insert_instruction_before(struct compiler_context * ctx,struct midgard_instruction * tag,struct midgard_instruction ins)335 mir_insert_instruction_before(struct compiler_context *ctx,
336 struct midgard_instruction *tag,
337 struct midgard_instruction ins)
338 {
339 struct midgard_instruction *u = mir_upload_ins(ctx, ins);
340 list_addtail(&u->link, &tag->link);
341 return u;
342 }
343
344 static inline void
mir_remove_instruction(struct midgard_instruction * ins)345 mir_remove_instruction(struct midgard_instruction *ins)
346 {
347 list_del(&ins->link);
348 }
349
350 static inline midgard_instruction *
mir_prev_op(struct midgard_instruction * ins)351 mir_prev_op(struct midgard_instruction *ins)
352 {
353 return list_last_entry(&(ins->link), midgard_instruction, link);
354 }
355
356 static inline midgard_instruction *
mir_next_op(struct midgard_instruction * ins)357 mir_next_op(struct midgard_instruction *ins)
358 {
359 return list_first_entry(&(ins->link), midgard_instruction, link);
360 }
361
362 #define mir_foreach_block(ctx, v) \
363 list_for_each_entry(pan_block, v, &ctx->blocks, link)
364
365 #define mir_foreach_block_from(ctx, from, v) \
366 list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
367
368 #define mir_foreach_instr_in_block(block, v) \
369 list_for_each_entry(struct midgard_instruction, v, \
370 &block->base.instructions, link)
371 #define mir_foreach_instr_in_block_rev(block, v) \
372 list_for_each_entry_rev(struct midgard_instruction, v, \
373 &block->base.instructions, link)
374
375 #define mir_foreach_instr_in_block_safe(block, v) \
376 list_for_each_entry_safe(struct midgard_instruction, v, \
377 &block->base.instructions, link)
378
379 #define mir_foreach_instr_in_block_safe_rev(block, v) \
380 list_for_each_entry_safe_rev(struct midgard_instruction, v, \
381 &block->base.instructions, link)
382
383 #define mir_foreach_instr_in_block_from(block, v, from) \
384 list_for_each_entry_from(struct midgard_instruction, v, from, \
385 &block->base.instructions, link)
386
387 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
388 list_for_each_entry_from_rev(struct midgard_instruction, v, from, \
389 &block->base.instructions, link)
390
391 #define mir_foreach_bundle_in_block(block, v) \
392 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
393
394 #define mir_foreach_bundle_in_block_rev(block, v) \
395 util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
396
397 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
398 midgard_instruction *v; \
399 signed i = 0; \
400 mir_foreach_bundle_in_block_rev(block, _bundle) \
401 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
402 i >= 0; --i, v = (i >= 0) ? _bundle->instructions[i] : NULL)
403
404 #define mir_foreach_instr_global(ctx, v) \
405 mir_foreach_block(ctx, v_block) \
406 mir_foreach_instr_in_block(((midgard_block *)v_block), v)
407
408 #define mir_foreach_instr_global_safe(ctx, v) \
409 mir_foreach_block(ctx, v_block) \
410 mir_foreach_instr_in_block_safe(((midgard_block *)v_block), v)
411
412 /* Based on set_foreach, expanded with automatic type casts */
413
414 #define mir_foreach_predecessor(blk, v) \
415 struct set_entry *_entry_##v; \
416 struct midgard_block *v; \
417 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
418 v = (struct midgard_block *)(_entry_##v ? _entry_##v->key : NULL); \
419 _entry_##v != NULL; \
420 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
421 v = (struct midgard_block *)(_entry_##v ? _entry_##v->key : NULL))
422
423 #define mir_foreach_src(ins, v) \
424 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
425
426 static inline midgard_instruction *
mir_last_in_block(struct midgard_block * block)427 mir_last_in_block(struct midgard_block *block)
428 {
429 return list_last_entry(&block->base.instructions, struct midgard_instruction,
430 link);
431 }
432
433 static inline midgard_block *
mir_get_block(compiler_context * ctx,int idx)434 mir_get_block(compiler_context *ctx, int idx)
435 {
436 struct list_head *lst = &ctx->blocks;
437
438 while ((idx--) + 1)
439 lst = lst->next;
440
441 return (struct midgard_block *)lst;
442 }
443
444 static inline bool
mir_is_alu_bundle(midgard_bundle * bundle)445 mir_is_alu_bundle(midgard_bundle *bundle)
446 {
447 return IS_ALU(bundle->tag);
448 }
449
450 static inline unsigned
make_compiler_temp(compiler_context * ctx)451 make_compiler_temp(compiler_context *ctx)
452 {
453 return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
454 }
455
456 static inline unsigned
make_compiler_temp_reg(compiler_context * ctx)457 make_compiler_temp_reg(compiler_context *ctx)
458 {
459 return ((ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
460 }
461
462 static inline bool
mir_is_ssa(unsigned index)463 mir_is_ssa(unsigned index)
464 {
465 return (index < SSA_FIXED_MINIMUM) && !(index & PAN_IS_REG);
466 }
467
468 static inline unsigned
nir_ssa_index(nir_def * ssa)469 nir_ssa_index(nir_def *ssa)
470 {
471 return (ssa->index << 1) | 0;
472 }
473
474 static inline unsigned
nir_reg_index(nir_def * handle)475 nir_reg_index(nir_def *handle)
476 {
477 return (handle->index << 1) | PAN_IS_REG;
478 }
479
480 static inline unsigned
nir_src_index(compiler_context * ctx,nir_src * src)481 nir_src_index(compiler_context *ctx, nir_src *src)
482 {
483 nir_intrinsic_instr *load = nir_load_reg_for_def(src->ssa);
484
485 if (load)
486 return nir_reg_index(load->src[0].ssa);
487 else
488 return nir_ssa_index(src->ssa);
489 }
490
491 static inline unsigned
nir_def_index_with_mask(nir_def * def,uint16_t * write_mask)492 nir_def_index_with_mask(nir_def *def, uint16_t *write_mask)
493 {
494 nir_intrinsic_instr *store = nir_store_reg_for_def(def);
495
496 if (store) {
497 *write_mask = nir_intrinsic_write_mask(store);
498 return nir_reg_index(store->src[1].ssa);
499 } else {
500 *write_mask = (uint16_t)BITFIELD_MASK(def->num_components);
501 return nir_ssa_index(def);
502 }
503 }
504
505 static inline unsigned
nir_def_index(nir_def * def)506 nir_def_index(nir_def *def)
507 {
508 uint16_t write_mask = 0;
509 return nir_def_index_with_mask(def, &write_mask);
510 }
511
512 /* MIR manipulation */
513
514 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
515 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
516 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
517 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old,
518 unsigned new);
519 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old,
520 unsigned new);
521 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old,
522 unsigned new, unsigned *swizzle);
523 bool mir_single_use(compiler_context *ctx, unsigned value);
524 unsigned mir_use_count(compiler_context *ctx, unsigned value);
525 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins,
526 unsigned node);
527 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins,
528 unsigned i);
529 uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
530 uint16_t mir_bytemask(midgard_instruction *ins);
531 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
532 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
533 signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
534 unsigned mir_components_for_type(nir_alu_type T);
535 unsigned max_bitsize_for_alu(midgard_instruction *ins);
536 midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
537
538 /* MIR printing */
539
540 void mir_print_instruction(midgard_instruction *ins);
541 void mir_print_bundle(midgard_bundle *ctx);
542 void mir_print_block(midgard_block *block);
543 void mir_print_shader(compiler_context *ctx);
544 bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i,
545 bool check_swizzle);
546 bool mir_nontrivial_outmod(midgard_instruction *ins);
547
548 midgard_instruction *mir_insert_instruction_before_scheduled(
549 compiler_context *ctx, midgard_block *block, midgard_instruction *tag,
550 midgard_instruction ins);
551 midgard_instruction *mir_insert_instruction_after_scheduled(
552 compiler_context *ctx, midgard_block *block, midgard_instruction *tag,
553 midgard_instruction ins);
554 void mir_flip(midgard_instruction *ins);
555 void mir_compute_temp_count(compiler_context *ctx);
556
557 #define LDST_GLOBAL (REGISTER_LDST_ZERO << 2)
558 #define LDST_SHARED ((REGISTER_LDST_LOCAL_STORAGE_PTR << 2) | COMPONENT_Z)
559 #define LDST_SCRATCH ((REGISTER_LDST_PC_SP << 2) | COMPONENT_Z)
560
561 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins,
562 nir_src *offset, unsigned seg);
563 void mir_set_ubo_offset(midgard_instruction *ins, nir_src *src, unsigned bias);
564
565 /* 'Intrinsic' move for aliasing */
566
567 static inline midgard_instruction
v_mov(unsigned src,unsigned dest)568 v_mov(unsigned src, unsigned dest)
569 {
570 midgard_instruction ins = {
571 .type = TAG_ALU_4,
572 .mask = 0xF,
573 .src = {~0, src, ~0, ~0},
574 .src_types = {0, nir_type_uint32},
575 .swizzle = SWIZZLE_IDENTITY,
576 .dest = dest,
577 .dest_type = nir_type_uint32,
578 .op = midgard_alu_op_imov,
579 .outmod = midgard_outmod_keeplo,
580 };
581
582 return ins;
583 }
584
585 /* Broad types of register classes so we can handle special
586 * registers */
587
588 #define REG_CLASS_WORK 0
589 #define REG_CLASS_LDST 1
590 #define REG_CLASS_TEXR 3
591 #define REG_CLASS_TEXW 4
592
593 /* Like a move, but to thread local storage! */
594
595 static inline midgard_instruction
v_load_store_scratch(unsigned srcdest,unsigned index,bool is_store,unsigned mask)596 v_load_store_scratch(unsigned srcdest, unsigned index, bool is_store,
597 unsigned mask)
598 {
599 /* We index by 32-bit vec4s */
600 unsigned byte = (index * 4 * 4);
601
602 midgard_instruction ins = {
603 .type = TAG_LOAD_STORE_4,
604 .mask = mask,
605 .dest_type = nir_type_uint32,
606 .dest = ~0,
607 .src = {~0, ~0, ~0, ~0},
608 .swizzle = SWIZZLE_IDENTITY_4,
609 .op = is_store ? midgard_op_st_128 : midgard_op_ld_128,
610 .load_store =
611 {
612 /* For register spilling - to thread local storage */
613 .arg_reg = REGISTER_LDST_LOCAL_STORAGE_PTR,
614 .arg_comp = COMPONENT_X,
615 .bitsize_toggle = true,
616 .index_format = midgard_index_address_u32,
617 .index_reg = REGISTER_LDST_ZERO,
618 },
619
620 /* If we spill an unspill, RA goes into an infinite loop */
621 .no_spill = (1 << REG_CLASS_WORK),
622 };
623
624 ins.constants.u32[0] = byte;
625
626 if (is_store) {
627 ins.src[0] = srcdest;
628 ins.src_types[0] = nir_type_uint32;
629
630 /* Ensure we are tightly swizzled so liveness analysis is
631 * correct */
632
633 for (unsigned i = 0; i < 4; ++i) {
634 if (!(mask & (1 << i)))
635 ins.swizzle[0][i] = COMPONENT_X;
636 }
637 } else
638 ins.dest = srcdest;
639
640 return ins;
641 }
642
643 static inline bool
mir_has_arg(midgard_instruction * ins,unsigned arg)644 mir_has_arg(midgard_instruction *ins, unsigned arg)
645 {
646 if (!ins)
647 return false;
648
649 mir_foreach_src(ins, i) {
650 if (ins->src[i] == arg)
651 return true;
652 }
653
654 return false;
655 }
656
657 /* Scheduling */
658
659 void midgard_schedule_program(compiler_context *ctx);
660
661 void mir_ra(compiler_context *ctx);
662 void mir_squeeze_index(compiler_context *ctx);
663 void mir_lower_special_reads(compiler_context *ctx);
664 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins,
665 unsigned max);
666 void mir_compute_liveness(compiler_context *ctx);
667 void mir_invalidate_liveness(compiler_context *ctx);
668 bool mir_is_live_after(compiler_context *ctx, midgard_block *block,
669 midgard_instruction *start, int src);
670
671 void mir_create_pipeline_registers(compiler_context *ctx);
672 void midgard_promote_uniforms(compiler_context *ctx);
673
674 void midgard_emit_derivatives(compiler_context *ctx,
675 nir_intrinsic_instr *instr);
676
677 void midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
678
679 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
680
681 void mir_analyze_helper_terminate(compiler_context *ctx);
682 void mir_analyze_helper_requirements(compiler_context *ctx);
683
684 /* Final emission */
685
686 void emit_binary_bundle(compiler_context *ctx, midgard_block *block,
687 midgard_bundle *bundle, struct util_dynarray *emission,
688 int next_tag);
689
690 bool nir_fuse_io_16(nir_shader *shader);
691
692 bool midgard_nir_lod_errata(nir_shader *shader);
693
694 unsigned midgard_get_first_tag_from_block(compiler_context *ctx,
695 unsigned block_idx);
696
697 /* Optimizations */
698
699 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
700 bool midgard_opt_prop(compiler_context *ctx);
701 bool midgard_opt_combine_projection(compiler_context *ctx,
702 midgard_block *block);
703 bool midgard_opt_varying_projection(compiler_context *ctx,
704 midgard_block *block);
705 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
706 bool midgard_opt_dead_move_eliminate(compiler_context *ctx,
707 midgard_block *block);
708
709 #endif
710