1 /*
2 * Copyright (c) 2021, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_utilities_next.h
24 //! \brief This modules implements utilities which are shared by both the HW interface and the state heap interface.
25 //!
26 #ifndef __MHW_UTILITIES_NEXT_H__
27 #define __MHW_UTILITIES_NEXT_H__
28
29 #include <memory>
30 #include "mos_defs.h"
31 #include "mos_os.h"
32 #include "mos_util_debug.h"
33 #include "mhw_mmio.h"
34 #include "mos_os_hw.h"
35 #include "mos_os_specific.h"
36 #include "mos_resource_defs.h"
37 #include "mos_utilities.h"
38 struct _MHW_BATCH_BUFFER;
39
40 typedef struct _MHW_RCS_SURFACE_PARAMS MHW_RCS_SURFACE_PARAMS, * PMHW_RCS_SURFACE_PARAMS;
41 typedef struct _MHW_BATCH_BUFFER MHW_BATCH_BUFFER, * PMHW_BATCH_BUFFER;
42
43 #define MHW_CACHELINE_SIZE 64
44 #define MHW_PAGE_SIZE 0x1000
45
46 #define MHW_TIMEOUT_MS_DEFAULT 1000
47 #define MHW_EVENT_TIMEOUT_MS 5
48
49 #define MHW_WIDTH_IN_DW(w) ((w + 0x3) >> 2)
50
51 #define MHW_AVS_TBL_COEF_PREC 6 //!< Table coef precision (after decimal point
52 #define MHW_TABLE_PHASE_PREC 5
53 #define MHW_TABLE_PHASE_COUNT (1 << MHW_TABLE_PHASE_PREC)
54 #define MHW_SCALER_UV_WIN_SIZE 4
55 #define MHW_TBL_COEF_PREC 6
56
57 #define NUM_HW_POLYPHASE_TABLES 32 //!< must be the same as NUM_HW_POLYPHASE_TABLES_G9
58 #define NUM_POLYPHASE_TABLES 32
59 #define NUM_POLYPHASE_Y_ENTRIES 8
60 #define NUM_POLYPHASE_5x5_Y_ENTRIES 5
61 #define NUM_POLYPHASE_UV_ENTRIES 4
62
63 #define NUM_HW_POLYPHASE_TABLES_G8 17
64 #define POLYPHASE_Y_COEFFICIENT_TABLE_SIZE_G8 (NUM_POLYPHASE_Y_ENTRIES * NUM_HW_POLYPHASE_TABLES_G8 * sizeof(int32_t))
65 #define POLYPHASE_UV_COEFFICIENT_TABLE_SIZE_G8 (NUM_POLYPHASE_UV_ENTRIES * NUM_HW_POLYPHASE_TABLES_G8 * sizeof(int32_t))
66
67 #define NUM_HW_POLYPHASE_TABLES_G9 32
68 #define POLYPHASE_Y_COEFFICIENT_TABLE_SIZE_G9 (NUM_POLYPHASE_Y_ENTRIES * NUM_HW_POLYPHASE_TABLES_G9 * sizeof(int32_t))
69 #define POLYPHASE_UV_COEFFICIENT_TABLE_SIZE_G9 (NUM_POLYPHASE_UV_ENTRIES * NUM_HW_POLYPHASE_TABLES_G9 * sizeof(int32_t))
70
71 #define NUM_HW_POLYPHASE_TABLES_G10 32
72 #define POLYPHASE_Y_COEFFICIENT_TABLE_SIZE_G10 (NUM_POLYPHASE_Y_ENTRIES * NUM_HW_POLYPHASE_TABLES_G10 * sizeof(int32_t))
73 #define POLYPHASE_UV_COEFFICIENT_TABLE_SIZE_G10 (NUM_POLYPHASE_UV_ENTRIES * NUM_HW_POLYPHASE_TABLES_G10 * sizeof(int32_t))
74
75
76
77 // Calculates the number of bits between the startbit and the endbit (0 based).
78 #ifndef MHW_BITFIELD_RANGE
79 #define MHW_BITFIELD_RANGE( startbit, endbit ) ((endbit)-(startbit)+1)
80 #endif
81
82 #define _NAME_MERGE_(x, y) x ## y
83 #define _NAME_LABEL_(name, id) _NAME_MERGE_(name, id)
84 #define __CODEGEN_UNIQUE(name) _NAME_LABEL_(name, __LINE__)
85
86 #ifndef SIZE32
87 #define SIZE32( x ) ((uint32_t)( sizeof(x) / sizeof(uint32_t) ))
88 #endif // SIZE32
89
90 #ifndef OP_LENGTH
91 #define OP_LENGTH( x ) ((uint32_t)(x) - 2 )
92 #endif // OP_LENGTH
93
94 // Calculates the number of bits between the startbit and the endbit (0 based).
95 #ifndef BITFIELD_RANGE
96 #define BITFIELD_RANGE( startbit, endbit ) ((endbit)-(startbit)+1)
97 #endif
98
99 // Definition declared for clarity when creating structs.
100 #ifndef BITFIELD_BIT
101 #define BITFIELD_BIT( bit ) 1
102 #endif
103
104 #define MHW_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
105
106 //------------------------------------------------------------------------------
107 // Macros specific to MOS_CODEC_SUBCOMP_HW sub-comp
108 //------------------------------------------------------------------------------
109 #define MHW_ASSERT(_expr) \
110 MOS_ASSERT(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _expr)
111
112 #define MHW_ASSERTMESSAGE(_message, ...) \
113 MOS_ASSERTMESSAGE(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _message, ##__VA_ARGS__)
114
115 #define MHW_NORMALMESSAGE(_message, ...) \
116 MOS_NORMALMESSAGE(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _message, ##__VA_ARGS__)
117
118 #define MHW_VERBOSEMESSAGE(_message, ...) \
119 MOS_VERBOSEMESSAGE(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _message, ##__VA_ARGS__)
120
121 #define MHW_FUNCTION_ENTER \
122 MOS_FUNCTION_ENTER(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL)
123
124 #define MHW_FUNCTION_EXIT \
125 MOS_FUNCTION_EXIT(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, eStatus)
126
127 #define MHW_CHK_STATUS(_stmt) \
128 MOS_CHK_STATUS(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _stmt)
129
130 #define MHW_CHK_STATUS_RETURN(_stmt) \
131 MOS_CHK_STATUS_RETURN(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _stmt)
132
133 #define MHW_CHK_STATUS_MESSAGE(_stmt, _message, ...) \
134 MOS_CHK_STATUS_MESSAGE(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _stmt, _message, ##__VA_ARGS__)
135
136 #define MHW_CHK_NULL(_ptr) \
137 MOS_CHK_NULL(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _ptr)
138
139 #define MHW_CHK_NULL_NO_STATUS(_ptr) \
140 MOS_CHK_NULL_NO_STATUS(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _ptr)
141
142 #define MHW_CHK_NULL_NO_STATUS_RETURN(_ptr) \
143 MOS_CHK_NULL_NO_STATUS_RETURN(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _ptr)
144
145 #define MHW_CHK_COND(_condition, _message, ...) \
146 MOS_CHK_COND_RETURN(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, (_condition), (_message), ##__VA_ARGS__)
147
148 #define MHW_CHK_NULL_RETURN(_ptr) \
149 MOS_CHK_NULL_RETURN(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _ptr)
150
151 #define MHW_CHK_STATUS_RETURN(_stmt) \
152 MOS_CHK_STATUS_RETURN(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _stmt)
153
154 #define MHW_MI_CHK_STATUS(_stmt) \
155 MOS_CHK_STATUS_RETURN(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _stmt)
156
157 #define MHW_MI_CHK_STATUS_MESSAGE(_stmt, _message, ...) \
158 MOS_CHK_STATUS_MESSAGE_RETURN(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _stmt, _message, ##__VA_ARGS__)
159
160 #define MHW_MI_CHK_NULL(_ptr) \
161 MOS_CHK_NULL_RETURN(MOS_COMPONENT_HW, MOS_HW_SUBCOMP_ALL, _ptr)
162
163 enum GFX_OPCODE
164 {
165 GFXOP_PIPELINED = 0x0,
166 GFXOP_VEBOX = 0x4,
167 GFXOP_MFX_VEBOX_SFC = 0xA // Media MFX/VEBOX+SFC Mode
168 };
169
170 enum INSTRUCTION_PIPELINE
171 {
172 PIPE_COMMON = 0x0,
173 PIPE_SINGLE_DWORD = 0x1,
174 PIPE_COMMON_CTG = 0x1,
175 PIPE_MEDIA = 0x2,
176 PIPE_3D = 0x3
177 };
178
179 enum INSTRUCTION_TYPE
180 {
181 INSTRUCTION_MI = 0x0,
182 INSTRUCTION_2D = 0x2,
183 INSTRUCTION_GFX = 0x3
184 };
185
186 enum MHW_GFX3DSTATE_SURFACEFORMAT
187 {
188 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32A32_FLOAT = 0x000,
189 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32A32_SINT = 0x001,
190 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32A32_UINT = 0x002,
191 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32A32_UNORM = 0x003,
192 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32A32_SNORM = 0x004,
193 MHW_GFX3DSTATE_SURFACEFORMAT_R64G64_FLOAT = 0x005,
194 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32X32_FLOAT = 0x006,
195 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32A32_SSCALED = 0x007,
196 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32A32_USCALED = 0x008,
197 MHW_GFX3DSTATE_SURFACEFORMAT_R16B16_UNORM_SAMPLE_8X8 = 0x017,
198 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32_FLOAT = 0x040,
199 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32_SINT = 0x041,
200 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32_UINT = 0x042,
201 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32_UNORM = 0x043,
202 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32_SNORM = 0x044,
203 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32_SSCALED = 0x045,
204 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32B32_USCALED = 0x046,
205 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16A16_UNORM = 0x080,
206 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16A16_SNORM = 0x081,
207 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16A16_SINT = 0x082,
208 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16A16_UINT = 0x083,
209 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16A16_FLOAT = 0x084,
210 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32_FLOAT = 0x085,
211 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32_SINT = 0x086,
212 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32_UINT = 0x087,
213 MHW_GFX3DSTATE_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS = 0x088,
214 MHW_GFX3DSTATE_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT = 0x089,
215 MHW_GFX3DSTATE_SURFACEFORMAT_L32A32_FLOAT = 0x08A,
216 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32_UNORM = 0x08B,
217 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32_SNORM = 0x08C,
218 MHW_GFX3DSTATE_SURFACEFORMAT_R64_FLOAT = 0x08D,
219 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16X16_UNORM = 0x08E,
220 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16X16_FLOAT = 0x08F,
221 MHW_GFX3DSTATE_SURFACEFORMAT_A32X32_FLOAT = 0x090,
222 MHW_GFX3DSTATE_SURFACEFORMAT_L32X32_FLOAT = 0x091,
223 MHW_GFX3DSTATE_SURFACEFORMAT_I32X32_FLOAT = 0x092,
224 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16A16_SSCALED = 0x093,
225 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16A16_USCALED = 0x094,
226 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32_SSCALED = 0x095,
227 MHW_GFX3DSTATE_SURFACEFORMAT_R32G32_USCALED = 0x096,
228 MHW_GFX3DSTATE_SURFACEFORMAT_B8G8R8A8_UNORM = 0x0C0,
229 MHW_GFX3DSTATE_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB = 0x0C1,
230 MHW_GFX3DSTATE_SURFACEFORMAT_R10G10B10A2_UNORM = 0x0C2,
231 MHW_GFX3DSTATE_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB = 0x0C3,
232 MHW_GFX3DSTATE_SURFACEFORMAT_R10G10B10A2_UINT = 0x0C4,
233 MHW_GFX3DSTATE_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM = 0x0C5,
234 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_UNORM = 0x0C7,
235 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB = 0x0C8,
236 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_SNORM = 0x0C9,
237 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_SINT = 0x0CA,
238 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_UINT = 0x0CB,
239 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16_UNORM = 0x0CC,
240 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16_SNORM = 0x0CD,
241 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16_SINT = 0x0CE,
242 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16_UINT = 0x0CF,
243 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16_FLOAT = 0x0D0,
244 MHW_GFX3DSTATE_SURFACEFORMAT_B10G10R10A2_UNORM = 0x0D1,
245 MHW_GFX3DSTATE_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB = 0x0D2,
246 MHW_GFX3DSTATE_SURFACEFORMAT_R11G11B10_FLOAT = 0x0D3,
247 MHW_GFX3DSTATE_SURFACEFORMAT_R32_SINT = 0x0D6,
248 MHW_GFX3DSTATE_SURFACEFORMAT_R32_UINT = 0x0D7,
249 MHW_GFX3DSTATE_SURFACEFORMAT_R32_FLOAT = 0x0D8,
250 MHW_GFX3DSTATE_SURFACEFORMAT_R24_UNORM_X8_TYPELESS = 0x0D9,
251 MHW_GFX3DSTATE_SURFACEFORMAT_X24_TYPELESS_G8_UINT = 0x0DA,
252 MHW_GFX3DSTATE_SURFACEFORMAT_L16A16_UNORM = 0x0DF,
253 MHW_GFX3DSTATE_SURFACEFORMAT_I24X8_UNORM = 0x0E0,
254 MHW_GFX3DSTATE_SURFACEFORMAT_L24X8_UNORM = 0x0E1,
255 MHW_GFX3DSTATE_SURFACEFORMAT_A24X8_UNORM = 0x0E2,
256 MHW_GFX3DSTATE_SURFACEFORMAT_I32_FLOAT = 0x0E3,
257 MHW_GFX3DSTATE_SURFACEFORMAT_L32_FLOAT = 0x0E4,
258 MHW_GFX3DSTATE_SURFACEFORMAT_A32_FLOAT = 0x0E5,
259 MHW_GFX3DSTATE_SURFACEFORMAT_B8G8R8X8_UNORM = 0x0E9,
260 MHW_GFX3DSTATE_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB = 0x0EA,
261 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8X8_UNORM = 0x0EB,
262 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB = 0x0EC,
263 MHW_GFX3DSTATE_SURFACEFORMAT_R9G9B9E5_SHAREDEXP = 0x0ED,
264 MHW_GFX3DSTATE_SURFACEFORMAT_B10G10R10X2_UNORM = 0x0EE,
265 MHW_GFX3DSTATE_SURFACEFORMAT_L16A16_FLOAT = 0x0F0,
266 MHW_GFX3DSTATE_SURFACEFORMAT_R32_UNORM = 0x0F1,
267 MHW_GFX3DSTATE_SURFACEFORMAT_R32_SNORM = 0x0F2,
268 MHW_GFX3DSTATE_SURFACEFORMAT_R10G10B10X2_USCALED = 0x0F3,
269 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_SSCALED = 0x0F4,
270 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_USCALED = 0x0F5,
271 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16_SSCALED = 0x0F6,
272 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16_USCALED = 0x0F7,
273 MHW_GFX3DSTATE_SURFACEFORMAT_R32_SSCALED = 0x0F8,
274 MHW_GFX3DSTATE_SURFACEFORMAT_R32_USCALED = 0x0F9,
275 MHW_GFX3DSTATE_SURFACEFORMAT_R8B8G8A8_UNORM = 0x0FA,
276 MHW_GFX3DSTATE_SURFACEFORMAT_B5G6R5_UNORM = 0x100,
277 MHW_GFX3DSTATE_SURFACEFORMAT_B5G6R5_UNORM_SRGB = 0x101,
278 MHW_GFX3DSTATE_SURFACEFORMAT_B5G5R5A1_UNORM = 0x102,
279 MHW_GFX3DSTATE_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB = 0x103,
280 MHW_GFX3DSTATE_SURFACEFORMAT_B4G4R4A4_UNORM = 0x104,
281 MHW_GFX3DSTATE_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB = 0x105,
282 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8_UNORM = 0x106,
283 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8_SNORM = 0x107,
284 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8_SINT = 0x108,
285 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8_UINT = 0x109,
286 MHW_GFX3DSTATE_SURFACEFORMAT_R16_UNORM = 0x10A,
287 MHW_GFX3DSTATE_SURFACEFORMAT_R16_SNORM = 0x10B,
288 MHW_GFX3DSTATE_SURFACEFORMAT_R16_SINT = 0x10C,
289 MHW_GFX3DSTATE_SURFACEFORMAT_R16_UINT = 0x10D,
290 MHW_GFX3DSTATE_SURFACEFORMAT_R16_FLOAT = 0x10E,
291 MHW_GFX3DSTATE_SURFACEFORMAT_I16_UNORM = 0x111,
292 MHW_GFX3DSTATE_SURFACEFORMAT_L16_UNORM = 0x112,
293 MHW_GFX3DSTATE_SURFACEFORMAT_A16_UNORM = 0x113,
294 MHW_GFX3DSTATE_SURFACEFORMAT_L8A8_UNORM = 0x114,
295 MHW_GFX3DSTATE_SURFACEFORMAT_I16_FLOAT = 0x115,
296 MHW_GFX3DSTATE_SURFACEFORMAT_L16_FLOAT = 0x116,
297 MHW_GFX3DSTATE_SURFACEFORMAT_A16_FLOAT = 0x117,
298 MHW_GFX3DSTATE_SURFACEFORMAT_L8A8_UNORM_SRGB = 0x118,
299 MHW_GFX3DSTATE_SURFACEFORMAT_R5G5_SNORM_B6_UNORM = 0x119,
300 MHW_GFX3DSTATE_SURFACEFORMAT_B5G5R5X1_UNORM = 0x11A,
301 MHW_GFX3DSTATE_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB = 0x11B,
302 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8_SSCALED = 0x11C,
303 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8_USCALED = 0x11D,
304 MHW_GFX3DSTATE_SURFACEFORMAT_R16_SSCALED = 0x11E,
305 MHW_GFX3DSTATE_SURFACEFORMAT_R16_USCALED = 0x11F,
306 MHW_GFX3DSTATE_SURFACEFORMAT_P8A8_UNORM_PALETTE_0 = 0x122,
307 MHW_GFX3DSTATE_SURFACEFORMAT_P8A8_UNORM_PALETTE_1 = 0x123,
308 MHW_GFX3DSTATE_SURFACEFORMAT_R8_UNORM = 0x140,
309 MHW_GFX3DSTATE_SURFACEFORMAT_R8_SNORM = 0x141,
310 MHW_GFX3DSTATE_SURFACEFORMAT_R8_SINT = 0x142,
311 MHW_GFX3DSTATE_SURFACEFORMAT_R8_UINT = 0x143,
312 MHW_GFX3DSTATE_SURFACEFORMAT_A8_UNORM = 0x144,
313 MHW_GFX3DSTATE_SURFACEFORMAT_I8_UNORM = 0x145,
314 MHW_GFX3DSTATE_SURFACEFORMAT_L8_UNORM = 0x146,
315 MHW_GFX3DSTATE_SURFACEFORMAT_P4A4_UNORM_PALETTE_0 = 0x147,
316 MHW_GFX3DSTATE_SURFACEFORMAT_A4P4_UNORM_PALETTE_0 = 0x148,
317 MHW_GFX3DSTATE_SURFACEFORMAT_R8_SSCALED = 0x149,
318 MHW_GFX3DSTATE_SURFACEFORMAT_R8_USCALED = 0x14A,
319 MHW_GFX3DSTATE_SURFACEFORMAT_P8_UNORM_PALETTE_0 = 0x14B,
320 MHW_GFX3DSTATE_SURFACEFORMAT_L8_UNORM_SRGB = 0x14C,
321 MHW_GFX3DSTATE_SURFACEFORMAT_P8_UNORM_PALETTE_1 = 0x14D,
322 MHW_GFX3DSTATE_SURFACEFORMAT_P4A4_UNORM_PALETTE_1 = 0x14E,
323 MHW_GFX3DSTATE_SURFACEFORMAT_A4P4_UNORM_PALETTE_1 = 0x14F,
324 MHW_GFX3DSTATE_SURFACEFORMAT_DXT1_RGB_SRGB = 0x180,
325 MHW_GFX3DSTATE_SURFACEFORMAT_R1_UINT = 0x181,
326 MHW_GFX3DSTATE_SURFACEFORMAT_YCRCB_NORMAL = 0x182,
327 MHW_GFX3DSTATE_SURFACEFORMAT_YCRCB_SWAPUVY = 0x183,
328 MHW_GFX3DSTATE_SURFACEFORMAT_P2_UNORM_PALETTE_0 = 0x184,
329 MHW_GFX3DSTATE_SURFACEFORMAT_P2_UNORM_PALETTE_1 = 0x185,
330 MHW_GFX3DSTATE_SURFACEFORMAT_BC1_UNORM = 0x186,
331 MHW_GFX3DSTATE_SURFACEFORMAT_BC2_UNORM = 0x187,
332 MHW_GFX3DSTATE_SURFACEFORMAT_BC3_UNORM = 0x188,
333 MHW_GFX3DSTATE_SURFACEFORMAT_BC4_UNORM = 0x189,
334 MHW_GFX3DSTATE_SURFACEFORMAT_BC5_UNORM = 0x18A,
335 MHW_GFX3DSTATE_SURFACEFORMAT_BC1_UNORM_SRGB = 0x18B,
336 MHW_GFX3DSTATE_SURFACEFORMAT_BC2_UNORM_SRGB = 0x18C,
337 MHW_GFX3DSTATE_SURFACEFORMAT_BC3_UNORM_SRGB = 0x18D,
338 MHW_GFX3DSTATE_SURFACEFORMAT_MONO8 = 0x18E,
339 MHW_GFX3DSTATE_SURFACEFORMAT_YCRCB_SWAPUV = 0x18F,
340 MHW_GFX3DSTATE_SURFACEFORMAT_YCRCB_SWAPY = 0x190,
341 MHW_GFX3DSTATE_SURFACEFORMAT_DXT1_RGB = 0x191,
342 MHW_GFX3DSTATE_SURFACEFORMAT_FXT1 = 0x192,
343 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8_UNORM = 0x193,
344 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8_SNORM = 0x194,
345 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8_SSCALED = 0x195,
346 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8_USCALED = 0x196,
347 MHW_GFX3DSTATE_SURFACEFORMAT_R64G64B64A64_FLOAT = 0x197,
348 MHW_GFX3DSTATE_SURFACEFORMAT_R64G64B64_FLOAT = 0x198,
349 MHW_GFX3DSTATE_SURFACEFORMAT_BC4_SNORM = 0x199,
350 MHW_GFX3DSTATE_SURFACEFORMAT_BC5_SNORM = 0x19A,
351 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16_UNORM = 0x19C,
352 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16_SNORM = 0x19D,
353 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16_SSCALED = 0x19E,
354 MHW_GFX3DSTATE_SURFACEFORMAT_R16G16B16_USCALED = 0x19F,
355 MHW_GFX3DSTATE_SURFACEFORMAT_PLANAR_420_8 = 0x1A5,
356 MHW_GFX3DSTATE_SURFACEFORMAT_PLANAR_420_16 = 0x1A6,
357 MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8_UNORM_SRGB = 0x1A8,
358 MHW_GFX3DSTATE_SURFACEFORMAT_RAW = 0x1FF,
359 NUM_MHW_GFX3DSTATE_SURFACEFORMATS
360 };
361
362 enum MHW_MEDIASTATE_SURFACEFORMAT
363 {
364 MHW_MEDIASTATE_SURFACEFORMAT_YCRCB_NORMAL = 0,
365 MHW_MEDIASTATE_SURFACEFORMAT_YCRCB_SWAPUVY = 1,
366 MHW_MEDIASTATE_SURFACEFORMAT_YCRCB_SWAPUV = 2,
367 MHW_MEDIASTATE_SURFACEFORMAT_YCRCB_SWAPY = 3,
368 MHW_MEDIASTATE_SURFACEFORMAT_PLANAR_420_8 = 4,
369 MHW_MEDIASTATE_SURFACEFORMAT_PLANAR_411_8 = 5, // deinterlace only
370 MHW_MEDIASTATE_SURFACEFORMAT_PLANAR_422_8 = 6, // deinterlace only
371 MHW_MEDIASTATE_SURFACEFORMAT_STMM_DN_STATISTICS = 7, // deinterlace only
372 MHW_MEDIASTATE_SURFACEFORMAT_R10G10B10A2_UNORM = 8, // sample_8x8 only
373 MHW_MEDIASTATE_SURFACEFORMAT_R8G8B8A8_UNORM = 9, // sample_8x8 only
374 MHW_MEDIASTATE_SURFACEFORMAT_R8B8_UNORM = 10, // CrCb, sample_8x8 only
375 MHW_MEDIASTATE_SURFACEFORMAT_R8_UNORM = 11, // Cr/Cb, sample_8x8 only
376 MHW_MEDIASTATE_SURFACEFORMAT_Y8_UNORM = 12, // sample_8x8 only
377 MHW_MEDIASTATE_SURFACEFORMAT_A8Y8U8V8_UNORM = 13, // sample_8x8 only
378 MHW_MEDIASTATE_SURFACEFORMAT_B8G8R8A8_UNORM = 14, // sample_8x8 only
379 MHW_MEDIASTATE_SURFACEFORMAT_R16G16B16A16 = 15, // Sample_8x8 only
380 MHW_MEDIASTATE_SURFACEFORMAT_PLANAR_420_16 = 23, // Sample_8x8 only
381 MHW_MEDIASTATE_SURFACEFORMAT_R16B16_UNORM = 24, // Sample_8x8 only
382 MHW_MEDIASTATE_SURFACEFORMAT_R16_UNORM = 25, // Sample_8x8 only
383 MHW_MEDIASTATE_SURFACEFORMAT_Y16_UNORM = 26 // Sample_8x8 only
384 };
385
386 enum GFX3DSTATE_SURFACETYPE
387 {
388 GFX3DSTATE_SURFACETYPE_1D = 0,
389 GFX3DSTATE_SURFACETYPE_2D = 1,
390 GFX3DSTATE_SURFACETYPE_3D = 2,
391 GFX3DSTATE_SURFACETYPE_CUBE = 3,
392 GFX3DSTATE_SURFACETYPE_BUFFER = 4,
393 GFX3DSTATE_SURFACETYPE_SREBUF = 5, // Structured buffer surface.
394 GFX3DSTATE_SURFACETYPE_SCRATCH = 6, // Scratch space buffer.
395 GFX3DSTATE_SURFACETYPE_NULL = 7
396 };
397
398 enum SurfaceCacheabilityControl
399 {
400 surfaceCacheabilityControlBitsFromGtt = 0x0,
401 surfaceCacheabilityControlL3Cache = 0x1,
402 surfaceCacheabilityControlLLCCache = 0x2
403 };
404
405 enum GFX3DSTATE_MEDIA_BOUNDARY_PIXEL_MODE
406 {
407 GFX3DSTATE_BOUNDARY_NORMAL = 0x0,
408 GFX3DSTATE_BOUNDARY_PROGRESSIVE_FRAME = 0x2,
409 GFX3DSTATE_BOUNDARY_INTERLACED_FRAME = 0x3
410 };
411
412 enum TILED_RESOURCE_MODE_LEGACY
413 {
414 TRMODE_NONE = 0,
415 TRMODE_TILEYF = 1,
416 TRMODE_TILEYS = 2,
417 };
418
419 enum MEDIASTATE_SFC_PIPE_MODE
420 {
421 MEDIASTATE_SFC_PIPE_VD_TO_SFC = 0,
422 MEDIASTATE_SFC_PIPE_VE_TO_SFC = 1,
423 MEDIASTATE_SFC_PIPE_VE_TO_SFC_INTEGRAL = 4
424 };
425
426 enum MEDIASTATE_SFC_AVS_FILTER_MODE
427 {
428 MEDIASTATE_SFC_AVS_FILTER_5x5 = 0,
429 MEDIASTATE_SFC_AVS_FILTER_8x8 = 1,
430 MEDIASTATE_SFC_AVS_FILTER_BILINEAR = 2
431 };
432
433 enum MEDIASTATE_SFC_CHROMA_SUBSAMPLING_MODE
434 {
435 MEDIASTATE_SFC_CHROMA_SUBSAMPLING_400 = 0,
436 MEDIASTATE_SFC_CHROMA_SUBSAMPLING_420 = 1,
437 MEDIASTATE_SFC_CHROMA_SUBSAMPLING_422H = 2,
438 MEDIASTATE_SFC_CHROMA_SUBSAMPLING_444 = 4,
439 MEDIASTATE_SFC_CHROMA_SUBSAMPLING_411 = 5
440 };
441
442 enum MEDIASTATE_SFC_INPUT_ORDERING_MODE
443 {
444 MEDIASTATE_SFC_INPUT_ORDERING_VE_4x8 = 0,
445 MEDIASTATE_SFC_INPUT_ORDERING_VE_4x4 = 1,
446 MEDIASTATE_SFC_INPUT_ORDERING_VE_4x8_128pixel = 2,
447 MEDIASTATE_SFC_INPUT_ORDERING_VE_4x4_128pixel = 3,
448 MEDIASTATE_SFC_INPUT_ORDERING_VD_16x16_NOSHIFT = 0,
449 MEDIASTATE_SFC_INPUT_ORDERING_VD_16x16_SHIFT = 1,
450 MEDIASTATE_SFC_INPUT_ORDERING_VD_8x8_JPEG = 2,
451 MEDIASTATE_SFC_INPUT_ORDERING_VD_16x16_JPEG = 3,
452 MEDIASTATE_SFC_INPUT_ORDERING_VD_16x16_VP8 = 4
453 };
454
455 // SFC Pre-AVS Chroma Downsampling Mode
456 enum MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_MODE
457 {
458 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_DISABLED = 0x0,
459 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_444TO420 = 0x1,
460 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_444TO422 = 0x2,
461 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_422TO420 = 0x3
462 };
463
464 // SFC Pre-AVS Chroma Downsampling Coefficient -- Fractional Position of the Bilinear Filter
465 enum MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF
466 {
467 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF_0_OVER_8 = 0x0,
468 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF_1_OVER_8 = 0x1,
469 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF_2_OVER_8 = 0x2,
470 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF_3_OVER_8 = 0x3,
471 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF_4_OVER_8 = 0x4,
472 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF_5_OVER_8 = 0x5,
473 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF_6_OVER_8 = 0x6,
474 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF_7_OVER_8 = 0x7,
475 MEDIASTATE_SFC_CHROMA_DOWNSAMPLING_COEF_8_OVER_8 = 0x8
476 };
477
478 enum MEDIASTATE_VDIRECTION
479 {
480 MEDIASTATE_VDIRECTION_TOP_FIELD = 1,
481 MEDIASTATE_VDIRECTION_FULL_FRAME = 2,
482 MEDIASTATE_VDIRECTION_BOTTOM_FIELD = 3
483 };
484
485 typedef union _MHW_MEMORY_OBJECT_CONTROL_PARAMS
486 {
487 struct
488 {
489 uint32_t L3 : 1;
490 uint32_t CacheControl : 1;
491 uint32_t GFDT : 1;
492 uint32_t : 1;
493 uint32_t : 28;
494 } Gen7;
495 struct
496 {
497 uint32_t L3 : 1;
498 uint32_t CacheControl : 2;
499 uint32_t : 1;
500 uint32_t : 28;
501 } Gen7_5;
502 struct
503 {
504 uint32_t Age : 2;
505 uint32_t : 1;
506 uint32_t TargetCache : 2;
507 uint32_t CacheControl : 2;
508 uint32_t : 25;
509 } Gen8;
510 struct
511 {
512 uint32_t : 1;
513 uint32_t Index : 6;
514 uint32_t : 25;
515 } Gen9, Gen10, Gen11, Gen12, Gen12_5, Gen12_7;
516 uint32_t Value;
517 } MHW_MEMORY_OBJECT_CONTROL_PARAMS, * PMHW_MEMORY_OBJECT_CONTROL_PARAMS;
518
519 typedef struct _MHW_RENDER_PWR_CLK_STATE_PARAMS
520 {
521 union
522 {
523 struct
524 {
525 // 0010: 2 EUs
526 // 0100: 4 EUs
527 // 0110: 6 EUs
528 // 1000: 8 EUs
529 uint32_t EUmin : BITFIELD_RANGE(0, 3); // Minimum number of EUs to power (per subslice if multiple subslices enabled)
530 uint32_t EUmax : BITFIELD_RANGE(4, 7); // Maximum number of EUs to power (per subslice if multiple subslices enabled)
531 // To specify an exact number of subslices, set EUmax equal to EUmin
532
533 uint32_t SubSliceCount : BITFIELD_RANGE(8, 10);
534
535 uint32_t SSCountEn : BITFIELD_RANGE(11, 11);
536
537 uint32_t SliceCount : BITFIELD_RANGE(12, 17);
538
539 uint32_t SCountEn : BITFIELD_RANGE(18, 18);
540
541 uint32_t Reserved1 : BITFIELD_RANGE(19, 30);
542
543 // Main trigger: Power Clock State Enable
544 // 0: No specific power state set, no message/wait with PMunit
545 // 1: CSunit sends the contents of this register to PMunit each time it is written, Send contents of this register to PMunit, wait for Ack.
546 uint32_t PowerClkStateEn : BITFIELD_RANGE(31, 31);
547 };
548
549 uint32_t Data;
550 };
551
552 }MHW_RENDER_PWR_CLK_STATE_PARAMS;
553
554 struct _MHW_BATCH_BUFFER
555 {
556 MOS_RESOURCE OsResource;
557 int32_t iRemaining; //!< Remaining space in the BB
558 int32_t iSize; //!< Command buffer size
559 uint32_t count; //!< Actual batch count in this resource. If larger than 1, multiple buffer has equal size and resource size count * size.
560 int32_t iCurrent; //!< Current offset in CB
561 bool bLocked; //!< True if locked in memory (pData must be valid)
562 uint8_t* pData; //!< Pointer to BB data
563 #if (_DEBUG || _RELEASE_INTERNAL)
564 int32_t iLastCurrent; //!< Save offset in CB (for debug plug-in/out)
565 #endif
566
567 // User defined
568 bool bSecondLevel; // REMOVE REMOVE
569 uint32_t dwOffset; //!< Offset to the data in the OS resource
570
571 // Batch Buffer synchronization logic
572 bool bBusy; //!< Busy flag (clear when Sync Tag is reached)
573 uint32_t dwCmdBufId; //!< Command Buffer ID for the workload
574 PMHW_BATCH_BUFFER pNext; //!< Next BB in the sync list
575 PMHW_BATCH_BUFFER pPrev; //!< Prev BB in the sync list
576
577 // Batch Buffer Client Private Data
578 uint32_t dwSyncTag;
579 bool bMatch;
580 int32_t iPrivateType; //!< Indicates the BB client
581 int32_t iPrivateSize; //!< Size of the current render args
582 void* pPrivateData; //!< Pointer to private BB data
583 };
584
585 typedef struct _MHW_BATCH_BUFFER_LIST
586 {
587 PMHW_BATCH_BUFFER pHead; //!< First element in the list
588 PMHW_BATCH_BUFFER pTail; //!< Last element in the list
589 int32_t iCount; //!< Number of BBs in this list
590 uint32_t dwSize; //!< Total BB memory in this list
591 } MHW_BATCH_BUFFER_LIST, * PMHW_BATCH_BUFFER_LIST;
592
593 enum WRITE_FLAG
594 {
595 WRITE = 0x1,
596 WRITE_WA = 0x2,
597 };
598
599 typedef struct _MHW_MOCS_PARAMS
600 {
601 uint32_t* mocsTableIndex;
602 uint8_t bitFieldLow;
603 uint8_t bitFieldHigh;
604 } MHW_MOCS_PARAMS;
605
606 typedef struct _MHW_RESOURCE_PARAMS
607 {
608 PMOS_RESOURCE presResource;
609 uint32_t dwOffset;
610 uint32_t* pdwCmd;
611 uint32_t dwLocationInCmd;
612 uint32_t dwLsbNum;
613 uint32_t dwOffsetInSSH;
614
615 // Location of upper bound value relative to
616 // allocated resource address. The upper bound
617 // value will be set if this parameter is > zero
618 uint32_t dwUpperBoundLocationOffsetFromCmd;
619 uint32_t dwSize;
620
621 MOS_HW_COMMAND HwCommandType;
622 uint32_t dwSharedMocsOffset;
623 uint32_t bIsWritable;
624
625 // If the patching location does not start at bit 0 then the value to be patched needs to be shifted
626 uint32_t shiftAmount;
627 uint32_t shiftDirection;
628 MOS_PATCH_TYPE patchType;
629 MHW_MOCS_PARAMS mocsParams;
630 }MHW_RESOURCE_PARAMS, * PMHW_RESOURCE_PARAMS;
631
632 typedef struct _MHW_GENERIC_PROLOG_PARAMS
633 {
634 PMOS_INTERFACE pOsInterface;
635 void* pvMiInterface;
636 bool bMmcEnabled;
637 PMOS_RESOURCE presStoreData;
638 uint32_t dwStoreDataOffset;
639 uint32_t dwStoreDataValue;
640 } MHW_GENERIC_PROLOG_PARAMS, * PMHW_GENERIC_PROLOG_PARAMS;
641
InitMocsParams(MHW_RESOURCE_PARAMS & hwResourceParam,uint32_t * addr,uint8_t bitFieldLow,uint8_t bitFieldHigh)642 void inline InitMocsParams(
643 MHW_RESOURCE_PARAMS& hwResourceParam,
644 uint32_t* addr,
645 uint8_t bitFieldLow,
646 uint8_t bitFieldHigh)
647 {
648 hwResourceParam.mocsParams.mocsTableIndex = addr;
649 hwResourceParam.mocsParams.bitFieldLow = bitFieldLow;
650 hwResourceParam.mocsParams.bitFieldHigh = bitFieldHigh;
651 return;
652 }
653
654 MOS_STATUS Mhw_AddResourceToCmd_GfxAddress(
655 PMOS_INTERFACE pOsInterface,
656 PMOS_COMMAND_BUFFER pCmdBuffer,
657 PMHW_RESOURCE_PARAMS pParams);
658
659 MOS_STATUS Mhw_AddResourceToCmd_PatchList(
660 PMOS_INTERFACE pOsInterface,
661 PMOS_COMMAND_BUFFER pCmdBuffer,
662 PMHW_RESOURCE_PARAMS pParams);
663
664 MOS_STATUS Mhw_SurfaceFormatToType(
665 uint32_t dwForceSurfaceFormat,
666 PMOS_SURFACE psSurface,
667 uint32_t* pdwSurfaceType);
668
669 MOS_STATUS Mhw_SendGenericPrologCmdNext(
670 PMOS_COMMAND_BUFFER pCmdBuffer,
671 PMHW_GENERIC_PROLOG_PARAMS pParams,
672 std::shared_ptr<void> pMiItf,
673 MHW_MI_MMIOREGISTERS *pMmioReg = nullptr);
674
675 MOS_STATUS Mhw_SetNearestModeTable(
676 int32_t* iCoefs,
677 uint32_t dwPlane,
678 bool bBalancedFilter);
679
680 MOS_STATUS Mhw_CalcPolyphaseTablesY(
681 int32_t* iCoefs,
682 float fScaleFactor,
683 uint32_t dwPlane,
684 MOS_FORMAT srcFmt,
685 float fHPStrength,
686 bool bUse8x8Filter,
687 uint32_t dwHwPhase,
688 float fLanczosT);
689
690 MOS_STATUS Mhw_CalcPolyphaseTablesUV(
691 int32_t* piCoefs,
692 float fLanczosT,
693 float fInverseScaleFactor);
694
695 MOS_STATUS Mhw_CalcPolyphaseTablesUVOffset(
696 int32_t* piCoefs,
697 float fLanczosT,
698 float fInverseScaleFactor,
699 int32_t iUvPhaseOffset);
700
701 MOS_STATUS Mhw_AllocateBb(
702 PMOS_INTERFACE pOsInterface,
703 PMHW_BATCH_BUFFER pBatchBuffer,
704 PMHW_BATCH_BUFFER pBatchBufferList,
705 uint32_t dwSize,
706 uint32_t batchCount = 1,
707 bool notLockable = false,
708 bool inSystemMem = false);
709
710 MOS_STATUS Mhw_FreeBb(
711 PMOS_INTERFACE pOsInterface,
712 PMHW_BATCH_BUFFER pBatchBuffer,
713 PMHW_BATCH_BUFFER pBatchBufferList);
714
715 MOS_STATUS Mhw_LockBb(
716 PMOS_INTERFACE pOsInterface,
717 PMHW_BATCH_BUFFER pBatchBuffer);
718
719 MOS_STATUS Mhw_UnlockBb(
720 PMOS_INTERFACE pOsInterface,
721 PMHW_BATCH_BUFFER pBatchBuffer,
722 bool bResetBuffer);
723
724 uint32_t Mhw_ConvertToTRMode(
725 MOS_TILE_TYPE Type);
726
727 //*-----------------------------------------------------------------------------
728 //| Purpose: Function to add command to batch buffer
729 //| Also used to skip commands if pCmd provided is nullptr
730 //| Return: MOS_STATUS_SUCCESS if call succeeds
731 //*-----------------------------------------------------------------------------
Mhw_AddCommandBB(PMHW_BATCH_BUFFER pBatchBuffer,const void * pCmd,uint32_t dwCmdSize)732 static __inline MOS_STATUS Mhw_AddCommandBB(
733 PMHW_BATCH_BUFFER pBatchBuffer, // [in] Pointer to Batch Buffer
734 const void* pCmd, // [in] Command Pointer
735 uint32_t dwCmdSize) // [in] Size of command in bytes
736 {
737 uint8_t* pbBatchPtr;
738 uint32_t dwCmdSizeDwAligned;
739 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
740
741 //---------------------------------------------
742 MHW_CHK_NULL_RETURN(pBatchBuffer);
743 MHW_CHK_NULL_RETURN(pBatchBuffer->pData);
744 //---------------------------------------------
745
746 pbBatchPtr = pBatchBuffer->pData + pBatchBuffer->iCurrent;
747
748 dwCmdSizeDwAligned = MOS_ALIGN_CEIL(dwCmdSize, sizeof(uint32_t));
749
750 pBatchBuffer->iCurrent += dwCmdSizeDwAligned;
751
752 if (pCmd)
753 {
754 pBatchBuffer->iRemaining -= dwCmdSizeDwAligned;
755 if (pBatchBuffer->iRemaining < 0)
756 {
757 MHW_ASSERTMESSAGE("Unable to add command (no space).");
758 return MOS_STATUS_UNKNOWN;
759 }
760
761 eStatus = MOS_SecureMemcpy(pbBatchPtr, dwCmdSize, pCmd, dwCmdSize);
762 if (eStatus != MOS_STATUS_SUCCESS)
763 {
764 MHW_ASSERTMESSAGE("Failed to copy memory.");
765 return eStatus;
766 }
767 }
768
769 return eStatus;
770 }
771
772 //*-----------------------------------------------------------------------------
773 //| Purpose: Function to add command to batch buffer
774 //| Return: MOS_STATUS_SUCCESS if call succeeds
775 //*-----------------------------------------------------------------------------
Mhw_AddCommandCmdOrBB(PMOS_INTERFACE pOsInterface,void * pCmdBuffer,void * pBatchBuffer,const void * pCmd,uint32_t dwCmdSize)776 static __inline MOS_STATUS Mhw_AddCommandCmdOrBB(
777 PMOS_INTERFACE pOsInterface, // [in] Pointer to mos interface
778 void* pCmdBuffer, // [in] Pointer to Command Buffer
779 void* pBatchBuffer, // [in] Pointer to Batch Buffer
780 const void* pCmd, // [in] Command Pointer
781 uint32_t dwCmdSize) // [in] Size of command in bytes
782 {
783 if (pCmdBuffer)
784 {
785 MHW_CHK_NULL_RETURN(pOsInterface);
786 return pOsInterface->pfnAddCommand((PMOS_COMMAND_BUFFER)pCmdBuffer, pCmd, dwCmdSize);
787 }
788 else if (pBatchBuffer)
789 {
790 return (Mhw_AddCommandBB((PMHW_BATCH_BUFFER)pBatchBuffer, pCmd, dwCmdSize));
791 }
792 else
793 {
794 MHW_ASSERTMESSAGE("There is no valid command buffer or batch buffer.");
795 return MOS_STATUS_NULL_POINTER;
796 }
797 }
798
799 #endif // __MHW_UTILITIES_NEXT_H__
800