1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DRAMC_REGISTER_H_ 4 #define _DRAMC_REGISTER_H_ 5 6 #include <device/mmio.h> 7 #include <types.h> 8 #include <soc/addressmap.h> 9 10 struct dramc_no_regs_rk_counter { 11 uint32_t pre_standby_counter; 12 uint32_t pre_powerdown_counter; 13 uint32_t act_standby_counter; 14 uint32_t act_powerdown_counter; 15 }; 16 17 struct dramc_nao_regs_rk { 18 uint32_t dqsosc_status; 19 uint32_t dqsosc_delta; 20 uint32_t dqsosc_delta2; 21 uint32_t rsvd_1[1]; 22 uint32_t current_tx_setting1; 23 uint32_t current_tx_setting2; 24 uint32_t current_tx_setting3; 25 uint32_t current_tx_setting4; 26 uint32_t dummy_rd_data[4]; 27 uint32_t b0_stb_max_min_dly; 28 uint32_t b1_stb_max_min_dly; 29 uint32_t b2_stb_max_min_dly; 30 uint32_t b3_stb_max_min_dly; 31 uint32_t dqsiendly; 32 uint32_t dqsienuidly; 33 uint32_t dqsienuidly_p1; 34 uint32_t rsvd_2[1]; 35 uint32_t dqs_stbcaldec_cnt1; 36 uint32_t dqs_stbcaldec_cnt2; 37 uint32_t dqs_stbcalinc_cnt1; 38 uint32_t dqs_stbcalinc_cnt2; 39 uint32_t fine_tune_dq_cal; 40 uint32_t dqsg_retry_flag; 41 uint32_t fine_tune_dqm_cal; 42 uint32_t rsvd_3[1]; 43 uint32_t dqs0_stbcal_cnt; 44 uint32_t dqs1_stbcal_cnt; 45 uint32_t dqs2_stbcal_cnt; 46 uint32_t dqs3_stbcal_cnt; 47 uint32_t b01_stb_dbg_info[16]; 48 uint32_t b23_stb_dbg_info[16]; 49 }; 50 51 struct dramc_nao_regs { 52 uint32_t testmode; 53 uint32_t lbwdat0; 54 uint32_t lbwdat1; 55 uint32_t lbwdat2; 56 uint32_t lbwdat3; 57 uint32_t reserved0[3]; 58 uint32_t ckphchk; 59 uint32_t dmmonitor; 60 uint32_t reserved1[2]; 61 uint32_t testchip_dma1; 62 uint32_t reserved2[19]; 63 uint32_t misc_statusa; 64 uint32_t special_status; 65 uint32_t spcmdresp; 66 uint32_t mrr_status; 67 uint32_t mrr_status2; 68 uint32_t mrrdata0; 69 uint32_t mrrdata1; 70 uint32_t mrrdata2; 71 uint32_t mrrdata3; 72 uint32_t reserved3[1]; 73 uint32_t drs_status; 74 uint32_t reserved4[4]; 75 uint32_t jmeter_st; 76 uint32_t tcmdo1lat; 77 uint32_t rdqc_cmp; 78 uint32_t ckphchk_status; 79 uint32_t reserved5[16]; 80 uint32_t hwmrr_push2pop_cnt; 81 uint32_t hwmrr_status; 82 uint32_t hw_refrate_mon; 83 uint32_t reserved6[2]; 84 uint32_t testrpt; 85 uint32_t cmp_err; 86 uint32_t test_abit_status1; 87 uint32_t test_abit_status2; 88 uint32_t test_abit_status3; 89 uint32_t test_abit_status4; 90 uint32_t reserved7[6]; 91 uint32_t dqsdly0; 92 uint32_t dq_cal_max[8]; 93 uint32_t dqs_cal_min[8]; 94 uint32_t dqs_cal_max[8]; 95 uint32_t dqical0; 96 uint32_t dqical1; 97 uint32_t dqical2; 98 uint32_t dqical3; 99 uint32_t reserved8[15]; 100 uint32_t testchip_dma_status[34]; 101 uint32_t reserved9[30]; 102 uint32_t refresh_pop_counter; 103 uint32_t freerun_26m_counter; 104 uint32_t dramc_idle_counter; 105 uint32_t r2r_page_hit_counter; 106 uint32_t r2r_page_miss_counter; 107 uint32_t r2r_interbank_counter; 108 uint32_t r2w_page_hit_counter; 109 uint32_t r2w_page_miss_counter; 110 uint32_t r2w_interbank_counter; 111 uint32_t w2r_page_hit_counter; 112 uint32_t w2r_page_miss_counter; 113 uint32_t w2r_interbank_counter; 114 uint32_t w2w_page_hit_counter; 115 uint32_t w2w_page_miss_counter; 116 uint32_t w2w_interbank_counter; 117 struct dramc_no_regs_rk_counter rk_counter[3]; 118 uint32_t dq0_toggle_counter; 119 uint32_t dq1_toggle_counter; 120 uint32_t dq2_toggle_counter; 121 uint32_t dq3_toggle_counter; 122 uint32_t dq0_toggle_counter_r; 123 uint32_t dq1_toggle_counter_r; 124 uint32_t dq2_toggle_counter_r; 125 uint32_t dq3_toggle_counter_r; 126 uint32_t read_bytes_counter; 127 uint32_t write_bytes_counter; 128 uint32_t max_sref_req_to_ack_latency_counter; 129 uint32_t max_rk1_drs_long_req_to_ack_latency_counter; 130 uint32_t max_rk1_drs_req_to_ack_latency_counter; 131 uint32_t reserved10[8]; 132 uint32_t lat_counter_cmd[8]; 133 uint32_t lat_counter_aver; 134 uint32_t lat_counter_num; 135 uint32_t lat_counter_block_ale; 136 uint32_t reserved11[5]; 137 uint32_t dqssamplev; 138 uint32_t reserved12[1]; 139 uint32_t dqsgnwcnt[6]; 140 uint32_t toggle_cnt; 141 uint32_t dqs0_err_cnt; 142 uint32_t dq_err_cnt0; 143 uint32_t dqs1_err_cnt; 144 uint32_t dq_err_cnt1; 145 uint32_t dqs2_err_cnt; 146 uint32_t dq_err_cnt2; 147 uint32_t dqs3_err_cnt; 148 uint32_t dq_err_cnt3; 149 uint32_t reserved13[3]; 150 uint32_t iorgcnt; 151 uint32_t dqsg_retry_state; 152 uint32_t dqsg_retry_state1; 153 uint32_t reserved14[1]; 154 uint32_t impcal_status1; 155 uint32_t impcal_status2; 156 uint32_t dqdrv_status; 157 uint32_t cmddrv_status; 158 uint32_t cmddrv1; 159 uint32_t cmddrv2; 160 uint32_t reserved15[98]; 161 struct dramc_nao_regs_rk rk[3]; 162 uint32_t reserved25[192]; 163 uint32_t dvfs_dbg0; 164 uint32_t dvfs_dbg1; 165 uint32_t dramc_nao_regs_end; 166 }; 167 168 check_member(dramc_nao_regs, testmode, 0x0000); 169 check_member(dramc_nao_regs, cmddrv2, 0x0474); 170 171 struct dramc_ao_regs_rk { 172 uint32_t dqsosc; 173 uint32_t rsvd_1[5]; 174 uint32_t dummy_rd_wdata[4]; 175 uint32_t dummy_rd_adr; 176 uint32_t dummy_rd_bk; 177 uint32_t pre_tdqsck[12]; 178 uint32_t rsvd_2[40]; 179 }; 180 181 struct dramc_ao_regs_shu_rk { 182 uint32_t dqsctl; 183 uint32_t dqsien; 184 uint32_t dqscal; 185 uint32_t fine_tune; 186 uint32_t dqsosc; 187 uint32_t rsvd_1[2]; 188 uint32_t selph_odten0; 189 uint32_t selph_odten1; 190 uint32_t selph_dqsg0; 191 uint32_t selph_dqsg1; 192 uint32_t selph_dq[4]; 193 uint32_t rsvd_2[1]; 194 uint32_t dqs2dq_cal1; 195 uint32_t dqs2dq_cal2; 196 uint32_t dqs2dq_cal3; 197 uint32_t dqs2dq_cal4; 198 uint32_t dqs2dq_cal5; 199 uint32_t rsvd_3[43]; 200 }; 201 202 struct dramc_ao_regs { 203 uint32_t ddrconf0; 204 uint32_t dramctrl; 205 uint32_t misctl0; 206 uint32_t perfctl0; 207 uint32_t arbctl; 208 uint32_t reserved0[2]; 209 uint32_t rstmask; 210 uint32_t padctrl; 211 uint32_t ckectrl; 212 uint32_t drsctrl; 213 uint32_t reserved1[2]; 214 uint32_t rkcfg; 215 uint32_t dramc_pd_ctrl; 216 uint32_t clkar; 217 uint32_t clkctrl; 218 uint32_t selfref_hwsave_flag; 219 uint32_t srefctrl; 220 uint32_t refctrl0; 221 uint32_t refctrl1; 222 uint32_t refratre_filter; 223 uint32_t zqcs; 224 uint32_t mrs; 225 uint32_t spcmd; 226 uint32_t spcmdctrl; 227 uint32_t ppr_ctrl; 228 uint32_t mpc_option; 229 uint32_t refque_cnt; 230 uint32_t hw_mrr_fun; 231 uint32_t mrr_bit_mux1; 232 uint32_t mrr_bit_mux2; 233 uint32_t mrr_bit_mux3; 234 uint32_t mrr_bit_mux4; 235 uint32_t reserved2[1]; 236 uint32_t test2_5; 237 uint32_t test2_0; 238 uint32_t test2_1; 239 uint32_t test2_2; 240 uint32_t test2_3; 241 uint32_t test2_4; 242 uint32_t wdt_dbg_signal; 243 uint32_t reserved3[1]; 244 uint32_t lbtest; 245 uint32_t catraining1; 246 uint32_t catraining2; 247 uint32_t reserved4[1]; 248 uint32_t write_lev; 249 uint32_t mr_golden; 250 uint32_t slp4_testmode; 251 uint32_t dqsoscr; 252 uint32_t reserved5[1]; 253 uint32_t dummy_rd; 254 uint32_t shuctrl; 255 uint32_t shuctrl1; 256 uint32_t shuctrl2; 257 uint32_t shuctrl3; 258 uint32_t shustatus; 259 uint32_t reserved6[70]; 260 uint32_t stbcal; 261 uint32_t stbcal1; 262 uint32_t stbcal2; 263 uint32_t eyescan; 264 uint32_t dvfsdll; 265 uint32_t reserved7[1]; 266 uint32_t pre_tdqsck[4]; 267 uint32_t reserved8[1]; 268 uint32_t impcal; 269 uint32_t impedamce_ctrl1; 270 uint32_t impedamce_ctrl2; 271 uint32_t impedamce_ctrl3; 272 uint32_t impedamce_ctrl4; 273 uint32_t dramc_dbg_sel1; 274 uint32_t dramc_dbg_sel2; 275 uint32_t rsvd_10[46]; 276 struct dramc_ao_regs_rk rk[3]; 277 uint32_t rsvd_16[64]; 278 struct dramc_ao_regs_shu { 279 uint32_t rsvd0[64]; 280 uint32_t actim[7]; 281 uint32_t actim_xrt; 282 uint32_t ac_time_05t; 283 uint32_t ac_derating0; 284 uint32_t ac_derating1; 285 uint32_t rsvd1[1]; 286 uint32_t ac_derating_05t; 287 uint32_t rsvd2[3]; 288 uint32_t conf[4]; 289 uint32_t stbcal; 290 uint32_t dqsoscthrd; 291 uint32_t rankctl; 292 uint32_t ckectrl; 293 uint32_t odtctrl; 294 uint32_t impcal1; 295 uint32_t dqsosc_prd; 296 uint32_t dqsoscr; 297 uint32_t dqsoscr2; 298 uint32_t rodtenstb; 299 uint32_t pipe; 300 uint32_t test1; 301 uint32_t selph_ca1; 302 uint32_t selph_ca2; 303 uint32_t selph_ca3; 304 uint32_t selph_ca4; 305 uint32_t selph_ca5; 306 uint32_t selph_ca6; 307 uint32_t selph_ca7; 308 uint32_t selph_ca8; 309 uint32_t selph_dqs0; 310 uint32_t selph_dqs1; 311 uint32_t drving[6]; 312 uint32_t wodt; 313 uint32_t dqsg; 314 uint32_t scintv; 315 uint32_t misc; 316 uint32_t dqs2dq_tx; 317 uint32_t hwset_mr2; 318 uint32_t hwset_mr13; 319 uint32_t hwset_vrcg; 320 uint32_t rsvd3[72]; 321 union { 322 struct dramc_ao_regs_shu_rk rk[3]; 323 struct { 324 uint32_t rsvd_63[149]; 325 uint32_t dqsg_retry; 326 }; 327 }; 328 } shu[4]; 329 uint32_t dramc_ao_regs_end; 330 }; 331 332 check_member(dramc_ao_regs, ddrconf0, 0x0000); 333 check_member(dramc_ao_regs, shu[3].dqsg_retry, 0x1e54); 334 335 struct dramc_ddrphy_regs_misc_stberr_rk { 336 uint32_t r; 337 uint32_t f; 338 }; 339 340 struct dramc_ddrphy_regs_shu_rk { 341 struct { 342 uint32_t dq[8]; 343 uint32_t rsvd_20[12]; 344 } b[2]; 345 uint32_t ca_cmd[10]; 346 uint32_t rsvd_22[14]; 347 }; 348 349 struct dramc_ddrphy_ao_regs { 350 uint32_t pll1; 351 uint32_t pll2; 352 uint32_t pll3; 353 uint32_t pll4; 354 uint32_t pll5; 355 uint32_t pll6; 356 uint32_t pll7; 357 uint32_t pll8; 358 uint32_t pll9; 359 uint32_t pll10; 360 uint32_t pll11; 361 uint32_t pll12; 362 uint32_t pll13; 363 uint32_t pll14; 364 uint32_t pll15; 365 uint32_t pll16; 366 uint32_t reserved0[16]; 367 struct { 368 uint32_t dll_fine_tune[6]; 369 uint32_t dq[10]; 370 uint32_t _rsvd_0[4]; 371 uint32_t tx_mck; 372 uint32_t _rsvd_1[11]; 373 } b[2]; 374 uint32_t ca_dll_fine_tune[6]; 375 uint32_t ca_cmd[11]; 376 uint32_t rfu_0x1c4; 377 uint32_t rfu_0x1c8; 378 uint32_t rfu_0x1cc; 379 uint32_t ca_tx_mck; 380 uint32_t reserved3[11]; 381 uint32_t misc_extlb[24]; 382 uint32_t dvfs_emi_clk; 383 uint32_t misc_vref_ctrl; 384 uint32_t misc_imp_ctrl0; 385 uint32_t misc_imp_ctrl1; 386 uint32_t misc_shu_opt; 387 uint32_t misc_spm_ctrl0; 388 uint32_t misc_spm_ctrl1; 389 uint32_t misc_spm_ctrl2; 390 uint32_t misc_spm_ctrl3; 391 uint32_t misc_cg_ctrl0; 392 uint32_t misc_cg_ctrl1; 393 uint32_t misc_cg_ctrl2; 394 uint32_t misc_cg_ctrl3; 395 uint32_t misc_cg_ctrl4; 396 uint32_t misc_cg_ctrl5; 397 uint32_t misc_ctrl0; 398 uint32_t misc_ctrl1; 399 uint32_t misc_ctrl2; 400 uint32_t misc_ctrl3; 401 uint32_t misc_ctrl4; 402 uint32_t misc_ctrl5; 403 uint32_t misc_extlb_rx[21]; 404 uint32_t ckmux_sel; 405 uint32_t reserved4[129]; 406 uint32_t misc_stberr_rk0_r; 407 uint32_t misc_stberr_rk0_f; 408 uint32_t misc_stberr_rk1_r; 409 uint32_t misc_stberr_rk1_f; 410 uint32_t misc_stberr_rk2_r; 411 uint32_t misc_stberr_rk2_f; 412 uint32_t reserved5[46]; 413 uint32_t misc_rxdvs[3]; 414 uint32_t rfu_0x5ec; 415 uint32_t b0_rxdvs[2]; 416 uint32_t rfu_0x5f8; 417 uint32_t rfu_0x5fc; 418 union { 419 struct { 420 struct { 421 uint32_t rxdvs[8]; 422 uint32_t _rsvd[24]; 423 } b[2]; 424 uint32_t rxdvs[10]; 425 uint32_t _rsvd_b[54]; 426 } r[3]; 427 struct { 428 uint32_t rsvd_2[28]; 429 uint32_t b1_rxdvs[2]; 430 uint32_t rsvd_3[30]; 431 uint32_t ca_rxdvs0; 432 uint32_t ca_rxdvs1; 433 uint32_t rsvd_4[2]; 434 uint32_t r0_ca_rxdvs[10]; 435 }; 436 }; 437 438 struct ddrphy_ao_shu { 439 struct { 440 uint32_t dq[13]; 441 uint32_t dll[2]; 442 uint32_t rsvd_16[17]; 443 } b[2]; 444 uint32_t ca_cmd[13]; 445 uint32_t ca_dll[2]; 446 uint32_t rsvd_18[17]; 447 uint32_t pll[16]; 448 uint32_t rsvd_19[4]; 449 uint32_t pll20; 450 uint32_t pll21; 451 uint32_t rsvd_20[6]; 452 uint32_t misc0; 453 uint32_t rsvd_21[3]; 454 struct dramc_ddrphy_regs_shu_rk rk[3]; 455 } shu[4]; 456 }; 457 458 check_member(dramc_ddrphy_ao_regs, pll1, 0x0000); 459 check_member(dramc_ddrphy_ao_regs, shu[3].rk[2].ca_cmd[9], 0x1FC4); 460 461 struct dramc_ddrphy_nao_regs { 462 uint32_t misc_sta_extlb[3]; 463 uint32_t reserved0[29]; 464 uint32_t misc_dq_rxdly_trro[32]; 465 uint32_t misc_ca_rxdly_trro[32]; 466 uint32_t misc_dqo1; 467 uint32_t misc_cao1; 468 uint32_t misc_ad_rx_dq_o1; 469 uint32_t misc_ad_rx_cmd_o1; 470 uint32_t misc_phy_rgs_dq; 471 uint32_t misc_phy_rgs_cmd; 472 uint32_t misc_phy_stben_b[2]; 473 uint32_t misc_phy_rgs_stben_cmd; 474 uint32_t dramc_ddrphy_nao_regs_end; 475 }; 476 477 check_member(dramc_ddrphy_nao_regs, misc_sta_extlb[0], 0x0); 478 check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_stben_cmd, 0x01A0); 479 480 struct emi_regs { 481 uint32_t cona; 482 uint32_t reserved0[1]; 483 uint32_t conb; 484 uint32_t reserved1[1]; 485 uint32_t conc; 486 uint32_t reserved2[1]; 487 uint32_t cond; 488 uint32_t reserved3[1]; 489 uint32_t cone; 490 uint32_t reserved4[1]; 491 uint32_t conf; 492 uint32_t reserved5[1]; 493 uint32_t cong; 494 uint32_t reserved6[1]; 495 uint32_t conh; 496 uint32_t conh_2nd; 497 uint32_t coni; 498 uint32_t reserved7[1]; 499 uint32_t conj; 500 uint32_t reserved8[5]; 501 uint32_t conm; 502 uint32_t reserved9[1]; 503 uint32_t conn; 504 uint32_t reserved10[1]; 505 uint32_t cono; 506 uint32_t reserved11[1]; 507 uint32_t mdct; 508 uint32_t mdct_2nd; 509 uint32_t reserved12[20]; 510 uint32_t iocl; 511 uint32_t iocl_2nd; 512 uint32_t iocm; 513 uint32_t iocm_2nd; 514 uint32_t reserved13[2]; 515 uint32_t testb; 516 uint32_t reserved14[1]; 517 uint32_t testc; 518 uint32_t reserved15[1]; 519 uint32_t testd; 520 uint32_t reserved16[1]; 521 uint32_t arba; 522 uint32_t reserved17[1]; 523 uint32_t arbb; 524 uint32_t reserved18[1]; 525 uint32_t arbc; 526 uint32_t reserved19[1]; 527 uint32_t arbd; 528 uint32_t reserved20[1]; 529 uint32_t arbe; 530 uint32_t reserved21[1]; 531 uint32_t arbf; 532 uint32_t reserved22[1]; 533 uint32_t arbg; 534 uint32_t reserved23[1]; 535 uint32_t arbh; 536 uint32_t reserved24[1]; 537 uint32_t arbi; 538 uint32_t arbi_2nd; 539 uint32_t reserved25[2]; 540 uint32_t arbk; 541 uint32_t arbk_2nd; 542 uint32_t slct; 543 uint32_t reserved26[277]; 544 uint32_t bwct0; 545 uint32_t reserved27[59]; 546 uint32_t bwct0_2nd; 547 uint32_t reserved28[43]; 548 uint32_t ltct0_2nd; 549 uint32_t ltct1_2nd; 550 uint32_t ltct2_2nd; 551 uint32_t ltct3_2nd; 552 uint32_t reserved29[4]; 553 uint32_t bwct0_3rd; 554 uint32_t reserved30[3]; 555 uint32_t bwct0_4th; 556 uint32_t reserved31[11]; 557 uint32_t bwct0_5th; 558 uint32_t reserved32[19]; 559 uint32_t slva; 560 }; 561 562 check_member(emi_regs, cona, 0x0000); 563 check_member(emi_regs, bwct0_5th, 0x07B0); 564 565 struct chn_emi_regs { 566 uint32_t chn_cona; 567 uint32_t rsvd_1[1]; 568 uint32_t chn_conb; 569 uint32_t rsvd_2[1]; 570 uint32_t chn_conc; 571 uint32_t rsvd_3[1]; 572 uint32_t chn_mdct; 573 uint32_t rsvd_4[11]; 574 uint32_t chn_testb; 575 uint32_t rsvd_5[1]; 576 uint32_t chn_testc; 577 uint32_t rsvd_6[1]; 578 uint32_t chn_testd; 579 uint32_t rsvd_7[9]; 580 uint32_t chn_md_pre_mask; 581 uint32_t rsvd_8[1]; 582 uint32_t chn_md_pre_mask_shf; 583 uint32_t rsvd_9[45]; 584 uint32_t chn_arbi; 585 uint32_t chn_arbi_2nd; 586 uint32_t chn_arbj; 587 uint32_t chn_arbj_2nd; 588 uint32_t chn_arbk; 589 uint32_t chn_arbk_2nd; 590 uint32_t chn_slct; 591 uint32_t chn_arb_ref; 592 uint32_t rsvd_10[20]; 593 uint32_t chn_rkarb0; 594 uint32_t chn_rkarb1; 595 uint32_t chn_rkarb2; 596 uint32_t rsvd_11[144]; 597 uint32_t chn_eco3; 598 uint32_t rsvd_12[196]; 599 uint32_t chn_emi_shf0; 600 uint32_t chn_emi_regs_end; 601 602 }; 603 604 check_member(chn_emi_regs, chn_cona, 0x0000); 605 check_member(chn_emi_regs, chn_emi_shf0, 0x0710); 606 607 struct emi_mpu_regs { 608 uint32_t mpu_ctrl; 609 uint32_t rsvd[511]; 610 uint32_t mpu_ctrl_d[16]; 611 }; 612 613 check_member(emi_mpu_regs, mpu_ctrl, 0x0000); 614 check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800); 615 616 DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24) 617 DEFINE_BIT(SPCMDRESP_DQSOSCEN_RESPONSE, 10) 618 DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 1) 619 DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0) 620 DEFINE_BITFIELD(MRR_STATUS_MRR_REG, 15, 0) 621 622 DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22) 623 DEFINE_BIT(DDRCONF0_RDATRST, 0) 624 DEFINE_BIT(PERFCTL0_RWOFOEN, 4) 625 626 DEFINE_BITFIELD(RKCFG_TXRANK, 1, 0) 627 DEFINE_BIT(RKCFG_TXRANKFIX, 3) 628 DEFINE_BIT(RKCFG_DQSOSC2RK, 11) 629 630 DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3) 631 DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0) 632 633 DEFINE_BITFIELD(SHURK_DQSIEN_DQS0IEN, 6, 0) 634 DEFINE_BITFIELD(SHURK_DQSIEN_DQS1IEN, 14, 8) 635 DEFINE_BITFIELD(SHURK_DQSIEN_DQS2IEN, 22, 16) 636 DEFINE_BITFIELD(SHURK_DQSIEN_DQS3IEN, 30, 24) 637 638 DEFINE_BIT(REFCTRL0_REFDIS, 29) 639 DEFINE_BIT(REFCTRL0_PBREFEN, 18) 640 641 DEFINE_BIT(CKECTRL_CKEFIXON, 6) 642 DEFINE_BIT(CKECTRL_CKEFIXOFF, 7) 643 644 DEFINE_BITFIELD(MRS_MRSBG, 31, 30) 645 DEFINE_BITFIELD(MRS_MPCRK, 29, 28) 646 DEFINE_BITFIELD(MRS_MRRRK, 27, 26) 647 DEFINE_BITFIELD(MRS_MRSRK, 25, 24) 648 DEFINE_BITFIELD(MRS_MRSBA, 23, 21) 649 DEFINE_BITFIELD(MRS_MRSMA, 20, 8) 650 DEFINE_BITFIELD(MRS_MRSOP, 7, 0) 651 652 DEFINE_BIT(SPCMD_DQSOSCENEN, 10) 653 DEFINE_BIT(SPCMD_DQSGCNTRST, 9) 654 DEFINE_BIT(SPCMD_DQSGCNTEN, 8) 655 DEFINE_BIT(SPCMD_ZQLATEN, 6) 656 DEFINE_BIT(SPCMD_RDDQCEN, 7) 657 DEFINE_BIT(SPCMD_ZQCEN, 4) 658 DEFINE_BIT(SPCMD_MRREN, 1) 659 DEFINE_BIT(SPCMD_MRWEN, 0) 660 661 DEFINE_BIT(SPCMDCTRL_RDDQCDIS, 11) 662 663 DEFINE_BIT(MPC_OPTION_MPCRKEN, 17) 664 DEFINE_BIT(MPC_OPTION_MPC_BLOCKALE_OPT, 0) 665 666 DEFINE_BIT(DVFSDLL_R_BYPASS_1ST_DLL_SHU1, 1) 667 668 DEFINE_BITFIELD(MISC_CG_CTRL0_CLK_MEM_SEL, 5, 4) 669 670 DEFINE_BIT(DRAMCTRL_ADRDECEN_TARKMODE, 1) 671 672 DEFINE_BIT(TESTCHIP_DMA1_DMA_LP4MATAB_OPT, 12) 673 DEFINE_BITFIELD(TEST2_0_PAT0, 15, 8) 674 DEFINE_BITFIELD(TEST2_0_PAT1, 7, 0) 675 676 DEFINE_BITFIELD(TEST2_1_TEST2_BASE, 31, 4) 677 DEFINE_BITFIELD(TEST2_2_TEST2_OFF, 31, 4) 678 679 DEFINE_BIT(TEST2_3_TEST2W, 31) 680 DEFINE_BIT(TEST2_3_TEST2R, 30) 681 DEFINE_BIT(TEST2_3_TEST1, 29) 682 DEFINE_BIT(TEST2_3_TESTAUDPAT, 7) 683 DEFINE_BITFIELD(TEST2_3_TESTCNT, 3, 0) 684 685 DEFINE_BITFIELD(TEST2_4_TESTAGENTRKSEL, 30, 28) 686 DEFINE_BITFIELD(TEST2_4_TESTAGENTRK, 25, 24) 687 DEFINE_BIT(TEST2_4_TEST_REQ_LEN1, 17) 688 DEFINE_BIT(TEST2_4_TESTXTALKPAT, 16) 689 DEFINE_BIT(TEST2_4_TESTAUDMODE, 15) 690 DEFINE_BIT(TEST2_4_TESTAUDBITINV, 14) 691 DEFINE_BITFIELD(TEST2_4_TESTAUDINIT, 12, 8) 692 DEFINE_BIT(TEST2_4_TESTSSOXTALKPAT, 7) 693 DEFINE_BIT(TEST2_4_TESTSSOPAT, 6) 694 DEFINE_BITFIELD(TEST2_4_TESTAUDINC, 4, 0) 695 696 DEFINE_BITFIELD(MR_GOLDEN_MR15_GOLDEN, 15, 8) 697 DEFINE_BITFIELD(MR_GOLDEN_MR20_GOLDEN, 7, 0) 698 699 DEFINE_BIT(DUMMY_RD_DQSG_DMYWR_EN, 23) 700 DEFINE_BIT(DUMMY_RD_DQSG_DMYRD_EN, 22) 701 DEFINE_BIT(DUMMY_RD_SREF_DMYRD_EN, 21) 702 DEFINE_BIT(DUMMY_RD_DUMMY_RD_EN, 20) 703 DEFINE_BIT(DUMMY_RD_DMY_RD_DBG, 7) 704 DEFINE_BIT(DUMMY_RD_DMY_WR_DBG, 6) 705 706 DEFINE_BIT(STBCAL1_STBCNT_LATCH_EN, 11) 707 DEFINE_BIT(STBCAL1_STBENCMPEN, 10) 708 709 DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2R, 3, 0) 710 711 DEFINE_BITFIELD(SHU_CONF1_DATLAT_DSEL_PHY, 30, 26) 712 DEFINE_BITFIELD(SHU_CONF1_DATLAT_DSEL, 12, 8) 713 DEFINE_BITFIELD(SHU_CONF1_DATLAT, 4, 0) 714 715 DEFINE_BIT(SHU_PIPE_READ_START_EXTEND1, 31) 716 DEFINE_BIT(SHU_PIPE_DLE_LAST_EXTEND1, 30) 717 DEFINE_BIT(SHU_PIPE_READ_START_EXTEND2, 29) 718 DEFINE_BIT(SHU_PIPE_DLE_LAST_EXTEND2, 28) 719 DEFINE_BIT(SHU_PIPE_READ_START_EXTEND3, 27) 720 DEFINE_BIT(SHU_PIPE_DLE_LAST_EXTEND3, 26) 721 722 DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL_PHY, 31, 28) 723 DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24) 724 DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL, 23, 20) 725 726 DEFINE_BIT(SHU1_WODT_DBIWR, 29) 727 DEFINE_BIT(SHU_SCINTV_DQSOSCENDIS, 30) 728 DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_SHU_PITHRD, 23, 18) 729 DEFINE_BITFIELD(SHURK_DQSCTL_DQSINCTL, 3, 0) 730 DEFINE_BIT(RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 29) 731 DEFINE_BIT(RK0_DQSOSC_DQSOSCR_RK0EN, 30) 732 DEFINE_BIT(RK1_DQSOSC_DQSOSCR_RK1EN, 30) 733 734 DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_0, 4, 0) 735 DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_1, 9, 5) 736 DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_3, 19, 15) 737 DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_4, 24, 20) 738 DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6, 7, 3) 739 DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7, 12, 8) 740 741 DEFINE_BIT(PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 16) 742 DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_START, 18) 743 DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 19) 744 745 DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_FILT_PITHRD, 29, 24) 746 DEFINE_BITFIELD(SHU1_WODT_TXUPD_W2R_SEL, 16, 14) 747 DEFINE_BITFIELD(SHU1_WODT_TXUPD_SEL, 13, 12) 748 DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, 9, 0) 749 DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0) 750 DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7) 751 DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24) 752 DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31) 753 754 DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0, 11, 0) 755 DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0, 23, 12) 756 DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0, 31, 24) 757 DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8, 19, 16) 758 DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1, 31, 20) 759 DEFINE_BITFIELD(SHU_DQSOSCR2_DQSOSCENCNT, 8, 0) 760 761 DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12) 762 DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4) 763 DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0) 764 765 DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS1_GATED_P1, 14, 12) 766 DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED_P1, 6, 4) 767 DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED, 2, 0) 768 DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0, 15, 0) 769 DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16) 770 771 DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16) 772 DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16) 773 774 DEFINE_BIT(MISC_CTRL1_R_DMSTBENCMP_RK, 25) 775 DEFINE_BIT(MISC_CTRL1_R_DMARPIDQ_SW, 7) 776 DEFINE_BIT(MISC_CTRL1_R_DMPHYRST, 1) 777 778 DEFINE_BITFIELD(MISC_STBERR_RK_R_STBERR_RK_R, 15, 0) 779 DEFINE_BITFIELD(MISC_STBERR_RK_F_STBERR_RK_F, 15, 0) 780 781 DEFINE_BITFIELD(SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 5, 0) 782 783 DEFINE_BIT(SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0, 7) 784 DEFINE_BITFIELD(SHU1_B0_DQ7_R_DMRANKRXDVS, 3, 0) 785 786 DEFINE_BITFIELD(SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 14, 12) 787 788 DEFINE_BITFIELD(SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE, 11, 10) 789 790 DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0, 30, 24) 791 DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, 22, 16) 792 DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0, 13, 8) 793 DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0, 5, 0) 794 795 DEFINE_BITFIELD(FINE_TUNE_PBYTE, 29, 24) 796 DEFINE_BITFIELD(FINE_TUNE_DQM, 21, 16) 797 DEFINE_BITFIELD(FINE_TUNE_DQ, 13, 8) 798 799 DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 29, 24) 800 DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8) 801 DEFINE_BITFIELD(SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD, 13, 8) 802 DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0) 803 804 /* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK1) */ 805 DEFINE_BIT(PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 22) 806 DEFINE_BIT(PRE_TDQSCK1_TDQSCK_REG_DVFS, 25) 807 DEFINE_BIT(PRE_TDQSCK1_TDQSCK_PRECAL_HW, 26) 808 809 /* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK2) */ 810 DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3, 7, 0) 811 DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2, 15, 8) 812 DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1, 23, 16) 813 DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0, 31, 24) 814 815 /* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK3) */ 816 DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7, 7, 0) 817 DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6, 15, 8) 818 DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5, 23, 16) 819 DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4, 31, 24) 820 821 /* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK4) */ 822 DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11, 7, 0) 823 DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10, 15, 8) 824 DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9, 23, 16) 825 DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8, 31, 24) 826 827 /* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0) */ 828 DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1, 30, 28) 829 DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED, 26, 24) 830 DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1, 22, 20) 831 DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED, 18, 16) 832 DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12) 833 DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED, 10, 8) 834 DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4) 835 DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0) 836 837 /* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1) */ 838 DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1, 30, 28) 839 DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED, 26, 24) 840 DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1, 22, 20) 841 DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED, 18, 16) 842 DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1, 14, 12) 843 DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED, 10, 8) 844 DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1, 6, 4) 845 DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED, 2, 0) 846 847 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1) */ 848 DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0, 25, 19) 849 DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0, 18, 13) 850 DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0, 12, 6) 851 DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0, 5, 0) 852 853 /* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN) */ 854 DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS3IEN, 30, 24) 855 DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS2IEN, 22, 16) 856 DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS1IEN, 14, 8) 857 DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS0IEN, 6, 0) 858 859 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK3) */ 860 DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0, 17, 12) 861 DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0, 11, 6) 862 DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0, 5, 0) 863 864 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK2) */ 865 DEFINE_BITFIELD(RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0, 12, 6) 866 DEFINE_BITFIELD(RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0, 5, 0) 867 868 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK4) */ 869 DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0, 25, 19) 870 DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0, 18, 13) 871 DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R0, 12, 6) 872 DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0, 5, 0) 873 874 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK6) */ 875 DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0, 17, 12) 876 DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0, 11, 6) 877 DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0, 5, 0) 878 879 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK5) */ 880 DEFINE_BITFIELD(RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0, 12, 6) 881 DEFINE_BITFIELD(RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0, 5, 0) 882 883 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK7) */ 884 DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R0, 25, 19) 885 DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R0, 18, 13) 886 DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R0, 12, 6) 887 DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R0, 5, 0) 888 889 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK9) */ 890 DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R0, 17, 12) 891 DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R0, 11, 6) 892 DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R0, 5, 0) 893 894 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK8) */ 895 DEFINE_BITFIELD(RK0_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R0, 12, 6) 896 DEFINE_BITFIELD(RK0_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R0, 5, 0) 897 898 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK10) */ 899 DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R0, 25, 19) 900 DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R0, 18, 13) 901 DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R0, 12, 6) 902 DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R0, 5, 0) 903 904 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK12) */ 905 DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R0, 17, 12) 906 DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R0, 11, 6) 907 DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0, 5, 0) 908 909 /* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK11) */ 910 DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0, 12, 6) 911 DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0, 5, 0) 912 913 /* DRAMC_REG_MRR_BIT_MUX1 */ 914 DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT3_SEL, 28, 24) 915 DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT2_SEL, 20, 16) 916 DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT1_SEL, 12, 8) 917 DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT0_SEL, 4, 0) 918 919 /* DRAMC_REG_SHU_SELPH_CA7 */ 920 DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA5, 22, 20) 921 DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA4, 18, 16) 922 DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA3, 14, 12) 923 DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA2, 10, 8) 924 DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA1, 6, 4) 925 DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA0, 2, 0) 926 927 /* DRAMC_REG_MRR_BIT_MUX2 */ 928 DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT5_SEL, 12, 8) 929 DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT4_SEL, 4, 0) 930 931 /* DDRPHY_SHU1_R0_CA_CMD0 */ 932 DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY, 23, 20) 933 DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY, 19, 16) 934 DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY, 15, 12) 935 DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY, 11, 8) 936 DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY, 7, 4) 937 DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY, 3, 0) 938 939 /* DDRPHY_PLL2 */ 940 DEFINE_BIT(PLL2_RG_RCLRPLL_EN, 31) 941 942 /* DDRPHY_PLL1 */ 943 DEFINE_BIT(PLL1_RG_RPHYPLL_EN, 31) 944 945 /* DRAMC_REG_PADCTRL */ 946 DEFINE_BITFIELD(PADCTRL_FIXDQIEN, 19, 16) 947 948 /* SPM_POWER_ON_VAL0 */ 949 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DR_SHU_EN_PCM, 22) 950 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DPHY_RXDLY_TRACK_EN, 25) 951 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DDRPHY_FB_CK_EN_PCM, 16) 952 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_TX_TRACKING_DIS, 11) 953 DEFINE_BITFIELD(SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL_PCM, 31, 30) 954 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_PHYPLL2_SHU_EN_PCM, 27) 955 DEFINE_BIT(SPM_POWER_ON_VAL0_SC_PHYPLL1_SHU_EN_PCM, 26) 956 957 /* SPM_POWER_ON_VAL1 */ 958 DEFINE_BIT(SPM_POWER_ON_VAL1_SC_DR_SHORT_QUEUE_PCM, 31) 959 960 /* SPM_DRAMC_DPY_CLK_SW_CON */ 961 DEFINE_BITFIELD(DRAMC_DPY_CLK_SW_CON_SC_DMDRAMCSHU_ACK, 25, 24) 962 963 /* DRAMC_REG_DRAMC_PD_CTRL */ 964 DEFINE_BIT(DRAMC_PD_CTRL_DCMEN, 0) 965 DEFINE_BIT(DRAMC_PD_CTRL_PHYCLKDYNGEN, 30) 966 DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26) 967 968 /* DRAMC_REG_WRITE_LEV */ 969 DEFINE_BIT(WRITE_LEV_DQS_WLEV, 7) 970 DEFINE_BITFIELD(WRITE_LEV_DQSBX_G, 11, 8) 971 DEFINE_BITFIELD(WRITE_LEV_DQS_SEL, 19, 16) 972 DEFINE_BITFIELD(WRITE_LEV_DMVREFCA, 27, 20) 973 DEFINE_BIT(WRITE_LEV_WRITE_LEVEL_EN, 0) 974 DEFINE_BIT(WRITE_LEV_BYTEMODECBTEN, 3) 975 976 /* DRAMC_REG_STBCAL */ 977 DEFINE_BIT(STBCAL_DQSIENCG_NORMAL_EN, 29) 978 979 /* DDRPHY_B0_DQ5 */ 980 DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 17) 981 982 /* DDRPHY_B1_DQ5 */ 983 DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 17) 984 985 /* DDRPHY_B0_DQ3 */ 986 DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1) 987 988 /* DDRPHY_B1_DQ3 */ 989 DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1) 990 991 /* DDRPHY_CA_CMD5 */ 992 DEFINE_BIT(CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN, 17) 993 994 /* DDRPHY_CA_CMD3 */ 995 DEFINE_BIT(CA_CMD3_RG_RX_ARCMD_SMT_EN, 1) 996 997 struct dramc_channel_regs { 998 union { 999 struct dramc_ddrphy_ao_regs phy; 1000 uint8_t raw_ddrphy_ao_regs[0x2000]; 1001 }; 1002 1003 union { 1004 struct dramc_ao_regs ao; 1005 uint8_t raw_ao_regs[0x2000]; 1006 }; 1007 1008 union { 1009 struct dramc_nao_regs nao; 1010 uint8_t raw_nao_regs[0x1000]; 1011 }; 1012 1013 union { 1014 struct chn_emi_regs emi; 1015 uint8_t raw_emi_regs[0x1000]; 1016 }; 1017 1018 union { 1019 struct dramc_ddrphy_nao_regs phy_nao; 1020 uint8_t raw_ddrphy_nao_regs[0x2000]; 1021 }; 1022 }; 1023 1024 static struct dramc_channel_regs *const ch = (void *)DRAMC_CH_BASE; 1025 static struct emi_mpu_regs *const emi_mpu = (void *)EMI_MPU_BASE; 1026 1027 #endif /* _DRAMC_REGISTER_H_ */ 1028