1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7
8 #include "core.h"
9
10 enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20
21 struct rtw89_c2hreg_hdr {
22 u32 w0;
23 };
24
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30 struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35 } __packed;
36
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50 #define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)
51
52 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)
53 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)
54 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)
55 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)
56 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)
57 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)
58 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)
59 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_256 0x1
60 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024 0x2
61 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096 0x3
62 #define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)
63
64 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
65 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
66 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
67 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
68 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
69 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
70 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
71 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
72 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
73 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
74 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
75 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
76 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
77 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
78 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
79 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
80 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
81 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
82 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
83 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
84 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
85 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
86 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
87 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
88 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
89
90 struct rtw89_h2creg_hdr {
91 u32 w0;
92 };
93
94 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
95 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
96
97 struct rtw89_h2creg_sch_tx_en {
98 u32 w0;
99 u32 w1;
100 } __packed;
101
102 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
103 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
104 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
105
106 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
107
108 #define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)
109
110 #define RTW89_H2CREG_MAX 4
111 #define RTW89_C2HREG_MAX 4
112 #define RTW89_C2HREG_HDR_LEN 2
113 #define RTW89_H2CREG_HDR_LEN 2
114 #define RTW89_C2H_TIMEOUT 1000000
115 struct rtw89_mac_c2h_info {
116 u8 id;
117 u8 content_len;
118 union {
119 u32 c2hreg[RTW89_C2HREG_MAX];
120 struct rtw89_c2hreg_hdr hdr;
121 struct rtw89_c2hreg_phycap phycap;
122 } u;
123 };
124
125 struct rtw89_mac_h2c_info {
126 u8 id;
127 u8 content_len;
128 union {
129 u32 h2creg[RTW89_H2CREG_MAX];
130 struct rtw89_h2creg_hdr hdr;
131 struct rtw89_h2creg_sch_tx_en sch_tx_en;
132 } u;
133 };
134
135 enum rtw89_mac_h2c_type {
136 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
137 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
138 RTW89_FWCMD_H2CREG_FUNC_FWERR,
139 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
140 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
141 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
142 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
143 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
144 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
145 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
146 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
147 };
148
149 enum rtw89_mac_c2h_type {
150 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
151 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
152 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
153 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
154 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
155 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
156 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1 = 0xC,
157 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
158 };
159
160 enum rtw89_fw_c2h_category {
161 RTW89_C2H_CAT_TEST,
162 RTW89_C2H_CAT_MAC,
163 RTW89_C2H_CAT_OUTSRC,
164 };
165
166 enum rtw89_fw_log_level {
167 RTW89_FW_LOG_LEVEL_OFF,
168 RTW89_FW_LOG_LEVEL_CRT,
169 RTW89_FW_LOG_LEVEL_SER,
170 RTW89_FW_LOG_LEVEL_WARN,
171 RTW89_FW_LOG_LEVEL_LOUD,
172 RTW89_FW_LOG_LEVEL_TR,
173 };
174
175 enum rtw89_fw_log_path {
176 RTW89_FW_LOG_LEVEL_UART,
177 RTW89_FW_LOG_LEVEL_C2H,
178 RTW89_FW_LOG_LEVEL_SNI,
179 };
180
181 enum rtw89_fw_log_comp {
182 RTW89_FW_LOG_COMP_VER,
183 RTW89_FW_LOG_COMP_INIT,
184 RTW89_FW_LOG_COMP_TASK,
185 RTW89_FW_LOG_COMP_CNS,
186 RTW89_FW_LOG_COMP_H2C,
187 RTW89_FW_LOG_COMP_C2H,
188 RTW89_FW_LOG_COMP_TX,
189 RTW89_FW_LOG_COMP_RX,
190 RTW89_FW_LOG_COMP_IPSEC,
191 RTW89_FW_LOG_COMP_TIMER,
192 RTW89_FW_LOG_COMP_DBGPKT,
193 RTW89_FW_LOG_COMP_PS,
194 RTW89_FW_LOG_COMP_ERROR,
195 RTW89_FW_LOG_COMP_WOWLAN,
196 RTW89_FW_LOG_COMP_SECURE_BOOT,
197 RTW89_FW_LOG_COMP_BTC,
198 RTW89_FW_LOG_COMP_BB,
199 RTW89_FW_LOG_COMP_TWT,
200 RTW89_FW_LOG_COMP_RF,
201 RTW89_FW_LOG_COMP_MCC = 20,
202 RTW89_FW_LOG_COMP_SCAN = 28,
203 };
204
205 enum rtw89_pkt_offload_op {
206 RTW89_PKT_OFLD_OP_ADD,
207 RTW89_PKT_OFLD_OP_DEL,
208 RTW89_PKT_OFLD_OP_READ,
209
210 NUM_OF_RTW89_PKT_OFFLOAD_OP,
211 };
212
213 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
214 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
215
216 enum rtw89_scanofld_notify_reason {
217 RTW89_SCAN_DWELL_NOTIFY,
218 RTW89_SCAN_PRE_TX_NOTIFY,
219 RTW89_SCAN_POST_TX_NOTIFY,
220 RTW89_SCAN_ENTER_CH_NOTIFY,
221 RTW89_SCAN_LEAVE_CH_NOTIFY,
222 RTW89_SCAN_END_SCAN_NOTIFY,
223 RTW89_SCAN_REPORT_NOTIFY,
224 RTW89_SCAN_CHKPT_NOTIFY,
225 RTW89_SCAN_ENTER_OP_NOTIFY,
226 RTW89_SCAN_LEAVE_OP_NOTIFY,
227 };
228
229 enum rtw89_scanofld_status {
230 RTW89_SCAN_STATUS_NOTIFY,
231 RTW89_SCAN_STATUS_SUCCESS,
232 RTW89_SCAN_STATUS_FAIL,
233 };
234
235 enum rtw89_chan_type {
236 RTW89_CHAN_OPERATE = 0,
237 RTW89_CHAN_ACTIVE,
238 RTW89_CHAN_DFS,
239 };
240
241 enum rtw89_p2pps_action {
242 RTW89_P2P_ACT_INIT = 0,
243 RTW89_P2P_ACT_UPDATE = 1,
244 RTW89_P2P_ACT_REMOVE = 2,
245 RTW89_P2P_ACT_TERMINATE = 3,
246 };
247
248 #define RTW89_DEFAULT_CQM_HYST 4
249 #define RTW89_DEFAULT_CQM_THOLD -70
250
251 enum rtw89_bcn_fltr_offload_mode {
252 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
253 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
254 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
255 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
256
257 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
258 };
259
260 enum rtw89_bcn_fltr_type {
261 RTW89_BCN_FLTR_BEACON_LOSS,
262 RTW89_BCN_FLTR_RSSI,
263 RTW89_BCN_FLTR_NOTIFY,
264 };
265
266 enum rtw89_bcn_fltr_rssi_event {
267 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
268 RTW89_BCN_FLTR_RSSI_HIGH,
269 RTW89_BCN_FLTR_RSSI_LOW,
270 };
271
272 #define FWDL_SECTION_MAX_NUM 10
273 #define FWDL_SECTION_CHKSUM_LEN 8
274 #define FWDL_SECTION_PER_PKT_LEN 2020
275
276 struct rtw89_fw_hdr_section_info {
277 u8 redl;
278 const u8 *addr;
279 u32 len;
280 u32 len_override;
281 u32 dladdr;
282 u32 mssc;
283 u8 type;
284 bool ignore;
285 const u8 *key_addr;
286 u32 key_len;
287 u32 key_idx;
288 };
289
290 struct rtw89_fw_bin_info {
291 u8 section_num;
292 u32 hdr_len;
293 bool dynamic_hdr_en;
294 u32 dynamic_hdr_len;
295 u8 idmem_share_mode;
296 bool dsp_checksum;
297 bool secure_section_exist;
298 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
299 };
300
301 struct rtw89_fw_macid_pause_grp {
302 __le32 pause_grp[4];
303 __le32 mask_grp[4];
304 } __packed;
305
306 struct rtw89_fw_macid_pause_sleep_grp {
307 struct {
308 __le32 pause_grp[4];
309 __le32 pause_mask_grp[4];
310 __le32 sleep_grp[4];
311 __le32 sleep_mask_grp[4];
312 } __packed n[4];
313 } __packed;
314
315 #define RTW89_H2C_MAX_SIZE 2048
316 #define RTW89_CHANNEL_TIME 45
317 #define RTW89_CHANNEL_TIME_6G 20
318 #define RTW89_DFS_CHAN_TIME 105
319 #define RTW89_OFF_CHAN_TIME 100
320 #define RTW89_DWELL_TIME 20
321 #define RTW89_DWELL_TIME_6G 10
322 #define RTW89_SCAN_WIDTH 0
323 #define RTW89_SCANOFLD_MAX_SSID 8
324 #define RTW89_SCANOFLD_MAX_IE_LEN 512
325 #define RTW89_SCANOFLD_PKT_NONE 0xFF
326 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
327 #define RTW89_CHAN_INVALID 0xFF
328 #define RTW89_MAC_CHINFO_SIZE 28
329 #define RTW89_MAC_CHINFO_SIZE_BE 32
330 #define RTW89_SCAN_LIST_GUARD 4
331 #define RTW89_SCAN_LIST_LIMIT(size) \
332 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD)
333 #define RTW89_SCAN_LIST_LIMIT_AX RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE)
334 #define RTW89_SCAN_LIST_LIMIT_BE RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE_BE)
335
336 #define RTW89_BCN_LOSS_CNT 10
337
338 struct rtw89_mac_chinfo {
339 u8 period;
340 u8 dwell_time;
341 u8 central_ch;
342 u8 pri_ch;
343 u8 bw:3;
344 u8 notify_action:5;
345 u8 num_pkt:4;
346 u8 tx_pkt:1;
347 u8 pause_data:1;
348 u8 ch_band:2;
349 u8 probe_id;
350 u8 dfs_ch:1;
351 u8 tx_null:1;
352 u8 rand_seq_num:1;
353 u8 cfg_tx_pwr:1;
354 u8 rsvd0: 4;
355 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
356 u16 tx_pwr_idx;
357 u8 rsvd1;
358 struct list_head list;
359 bool is_psc;
360 };
361
362 struct rtw89_mac_chinfo_be {
363 u8 period;
364 u8 dwell_time;
365 u8 central_ch;
366 u8 pri_ch;
367 u8 bw:3;
368 u8 ch_band:2;
369 u8 dfs_ch:1;
370 u8 pause_data:1;
371 u8 tx_null:1;
372 u8 rand_seq_num:1;
373 u8 notify_action:5;
374 u8 probe_id;
375 u8 leave_crit;
376 u8 chkpt_timer;
377 u8 leave_time;
378 u8 leave_th;
379 u16 tx_pkt_ctrl;
380 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
381 u8 sw_def;
382 u16 fw_probe0_ssids;
383 u16 fw_probe0_shortssids;
384 u16 fw_probe0_bssids;
385
386 struct list_head list;
387 bool is_psc;
388 };
389
390 struct rtw89_pktofld_info {
391 struct list_head list;
392 u8 id;
393 bool wildcard_6ghz;
394
395 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */
396 u8 ssid[IEEE80211_MAX_SSID_LEN];
397 u8 ssid_len;
398 u8 bssid[ETH_ALEN];
399 u16 channel_6ghz;
400 bool cancel;
401 };
402
403 struct rtw89_h2c_ra {
404 __le32 w0;
405 __le32 w1;
406 __le32 w2;
407 __le32 w3;
408 } __packed;
409
410 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
411 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
412 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
413 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
414 #define RTW89_H2C_RA_W0_DCM BIT(16)
415 #define RTW89_H2C_RA_W0_ER BIT(17)
416 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
417 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
418 #define RTW89_H2C_RA_W0_SGI BIT(21)
419 #define RTW89_H2C_RA_W0_LDPC BIT(22)
420 #define RTW89_H2C_RA_W0_STBC BIT(23)
421 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
422 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
423 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
424 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
425 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
426 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
427 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
428 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
429 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
430 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
431 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
432 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
433 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
434 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
435 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
436 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
437 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
438
439 struct rtw89_h2c_ra_v1 {
440 struct rtw89_h2c_ra v0;
441 __le32 w4;
442 __le32 w5;
443 } __packed;
444
445 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
446 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
447 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
448 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
449
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)450 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
451 {
452 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
453 }
454
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)455 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
456 {
457 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
458 }
459
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)460 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
461 {
462 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
463 }
464
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)465 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
466 {
467 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
468 }
469
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)470 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
471 {
472 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
473 }
474
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)475 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
476 {
477 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
478 }
479
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)480 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
481 {
482 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
483 }
484
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)485 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
486 {
487 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
488 }
489
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)490 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
491 {
492 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
493 }
494
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)495 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
496 {
497 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
498 }
499
RTW89_SET_EDCA_SEL(void * cmd,u32 val)500 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
501 {
502 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
503 }
504
RTW89_SET_EDCA_BAND(void * cmd,u32 val)505 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
506 {
507 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
508 }
509
RTW89_SET_EDCA_WMM(void * cmd,u32 val)510 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
511 {
512 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
513 }
514
RTW89_SET_EDCA_AC(void * cmd,u32 val)515 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
516 {
517 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
518 }
519
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)520 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
521 {
522 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
523 }
524 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
525 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
526 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
527 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
528
529 #define FWDL_SECURITY_SECTION_TYPE 9
530 #define FWDL_SECURITY_SIGLEN 512
531 #define FWDL_SECURITY_CHKSUM_LEN 8
532
533 struct rtw89_fw_dynhdr_sec {
534 __le32 w0;
535 u8 content[];
536 } __packed;
537
538 struct rtw89_fw_dynhdr_hdr {
539 __le32 hdr_len;
540 __le32 setcion_count;
541 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
542 } __packed;
543
544 struct rtw89_fw_hdr_section {
545 __le32 w0;
546 __le32 w1;
547 __le32 w2;
548 __le32 w3;
549 } __packed;
550
551 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
552 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
553 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
554 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
555 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
556 #define FWSECTION_HDR_W1_REDL BIT(29)
557 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
558
559 struct rtw89_fw_hdr {
560 __le32 w0;
561 __le32 w1;
562 __le32 w2;
563 __le32 w3;
564 __le32 w4;
565 __le32 w5;
566 __le32 w6;
567 __le32 w7;
568 struct rtw89_fw_hdr_section sections[];
569 /* struct rtw89_fw_dynhdr_hdr (optional) */
570 } __packed;
571
572 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
573 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
574 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
575 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
576 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
577 #define FW_HDR_W3_LEN GENMASK(23, 16)
578 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
579 #define FW_HDR_W4_MONTH GENMASK(7, 0)
580 #define FW_HDR_W4_DATE GENMASK(15, 8)
581 #define FW_HDR_W4_HOUR GENMASK(23, 16)
582 #define FW_HDR_W4_MIN GENMASK(31, 24)
583 #define FW_HDR_W5_YEAR GENMASK(31, 0)
584 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
585 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
586 #define FW_HDR_W7_DYN_HDR BIT(16)
587 #define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
588 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
589
590 struct rtw89_fw_hdr_section_v1 {
591 __le32 w0;
592 __le32 w1;
593 __le32 w2;
594 __le32 w3;
595 } __packed;
596
597 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
598 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
599 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
600 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
601 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
602 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
603 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
604 #define FORMATTED_MSSC 0xFF
605 #define FORMATTED_MSSC_MASK GENMASK(7, 0)
606 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
607
608 struct rtw89_fw_hdr_v1 {
609 __le32 w0;
610 __le32 w1;
611 __le32 w2;
612 __le32 w3;
613 __le32 w4;
614 __le32 w5;
615 __le32 w6;
616 __le32 w7;
617 __le32 w8;
618 __le32 w9;
619 __le32 w10;
620 __le32 w11;
621 struct rtw89_fw_hdr_section_v1 sections[];
622 } __packed;
623
624 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
625 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
626 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
627 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
628 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
629 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
630 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
631 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
632 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
633 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
634 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
635 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
636 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
637 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
638 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
639 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
640 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
641 #define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
642
643 enum rtw89_fw_mss_pool_rmp_tbl_type {
644 MSS_POOL_RMP_TBL_BITMASK = 0x0,
645 MSS_POOL_RMP_TBL_RECORD = 0x1,
646 };
647
648 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
649
650 struct rtw89_fw_mss_pool_hdr {
651 u8 signature[8]; /* equal to mss_signature[] */
652 __le32 rmp_tbl_offset;
653 __le32 key_raw_offset;
654 u8 defen;
655 u8 rsvd[3];
656 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
657 u8 mssdev_max;
658 __le16 keypair_num;
659 __le16 msscust_max;
660 __le16 msskey_num_max;
661 __le32 rsvd3;
662 u8 rmp_tbl[];
663 } __packed;
664
665 union rtw89_fw_section_mssc_content {
666 struct {
667 u8 pad[58];
668 __le32 v;
669 } __packed sb_sel_ver;
670 struct {
671 u8 pad[60];
672 __le16 v;
673 } __packed key_sign_len;
674 } __packed;
675
SET_CTRL_INFO_MACID(void * table,u32 val)676 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
677 {
678 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
679 }
680
SET_CTRL_INFO_OPERATION(void * table,u32 val)681 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
682 {
683 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
684 }
685 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)686 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
687 {
688 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
689 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
690 GENMASK(8, 0));
691 }
692 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)693 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
694 {
695 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
696 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
697 BIT(9));
698 }
699 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)700 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
701 {
702 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
703 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
704 GENMASK(11, 10));
705 }
706 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)707 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
708 {
709 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
710 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
711 GENMASK(14, 12));
712 }
713 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)714 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
715 {
716 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
717 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
718 BIT(15));
719 }
720 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)721 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
722 {
723 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
724 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
725 GENMASK(19, 16));
726 }
727 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)728 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
729 {
730 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
731 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
732 BIT(20));
733 }
734 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)735 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
736 {
737 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
738 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
739 BIT(21));
740 }
741 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)742 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
743 {
744 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
745 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
746 BIT(22));
747 }
748 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)749 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
750 {
751 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
752 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
753 BIT(23));
754 }
755 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)756 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
757 {
758 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
759 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
760 BIT(25));
761 }
762 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)763 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
764 {
765 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
766 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
767 BIT(26));
768 }
769 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)770 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
771 {
772 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
773 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
774 BIT(27));
775 }
776 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)777 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
778 {
779 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
780 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
781 GENMASK(31, 28));
782 }
783 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)784 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
785 {
786 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
787 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
788 GENMASK(8, 0));
789 }
790 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)791 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
792 {
793 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
794 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
795 BIT(9));
796 }
797 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)798 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
799 {
800 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
801 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
802 BIT(10));
803 }
804 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)805 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
806 {
807 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
808 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
809 BIT(11));
810 }
811 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)812 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
813 {
814 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
815 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
816 GENMASK(15, 12));
817 }
818 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)819 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
820 {
821 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
822 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
823 GENMASK(24, 16));
824 }
825 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)826 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
827 {
828 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
829 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
830 BIT(27));
831 }
832 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)833 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
834 {
835 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
836 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
837 GENMASK(31, 28));
838 }
839 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)840 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
841 {
842 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
843 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
844 GENMASK(5, 0));
845 }
846 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)847 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
848 {
849 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
850 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
851 BIT(6));
852 }
853 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)854 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
855 {
856 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
857 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
858 BIT(7));
859 }
860 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)861 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
862 {
863 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
864 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
865 BIT(8));
866 }
867 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)868 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
869 {
870 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
871 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
872 BIT(9));
873 }
874 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)875 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
876 {
877 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
878 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
879 GENMASK(11, 10));
880 }
881 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)882 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
883 {
884 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
885 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
886 BIT(12));
887 }
888 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)889 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
890 {
891 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
892 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
893 GENMASK(14, 13));
894 }
895 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)896 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
897 {
898 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
899 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
900 GENMASK(26, 16));
901 }
902 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)903 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
904 {
905 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
906 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
907 BIT(27));
908 }
909 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)910 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
911 {
912 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
913 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
914 GENMASK(31, 28));
915 }
916 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)917 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
918 {
919 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
920 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
921 GENMASK(7, 0));
922 }
923 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)924 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
925 {
926 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
927 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
928 GENMASK(9, 8));
929 }
930 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)931 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
932 {
933 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
934 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
935 GENMASK(18, 16));
936 }
937 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)938 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
939 {
940 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
941 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
942 GENMASK(21, 19));
943 }
944 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)945 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
946 {
947 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
948 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
949 GENMASK(24, 22));
950 }
951 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)952 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
953 {
954 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
955 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
956 GENMASK(27, 25));
957 }
958 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)959 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
960 {
961 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
962 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
963 GENMASK(31, 28));
964 }
965 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)966 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
967 {
968 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
969 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
970 GENMASK(2, 0));
971 }
972 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)973 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
974 {
975 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
976 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
977 BIT(3));
978 }
979 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)980 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
981 {
982 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
983 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
984 GENMASK(7, 4));
985 }
986 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)987 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
988 {
989 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
990 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
991 BIT(8));
992 }
993 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)994 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
995 {
996 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
997 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
998 GENMASK(11, 9));
999 }
1000 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)1001 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
1002 {
1003 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
1004 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
1005 BIT(12));
1006 }
1007 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)1008 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
1009 {
1010 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
1011 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
1012 BIT(13));
1013 }
1014 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)1015 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
1016 {
1017 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
1018 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
1019 BIT(14));
1020 }
1021 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)1022 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
1023 {
1024 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1025 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1026 BIT(15));
1027 }
1028 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)1029 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1030 {
1031 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1032 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1033 BIT(16));
1034 }
1035 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)1036 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1037 {
1038 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1039 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1040 BIT(17));
1041 }
1042 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)1043 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1044 {
1045 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1046 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1047 BIT(18));
1048 }
1049 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)1050 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1051 {
1052 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1053 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1054 BIT(19));
1055 }
1056 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)1057 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1058 {
1059 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1060 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1061 BIT(20));
1062 }
1063 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)1064 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1065 {
1066 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1067 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1068 BIT(21));
1069 }
1070 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)1071 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1072 {
1073 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1074 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1075 BIT(27));
1076 }
1077 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)1078 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1079 {
1080 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1081 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1082 GENMASK(31, 28));
1083 }
1084 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)1085 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1086 {
1087 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1088 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1089 GENMASK(8, 0));
1090 }
1091 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)1092 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1093 {
1094 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1095 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1096 BIT(12));
1097 }
1098 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)1099 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1100 {
1101 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1102 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1103 BIT(13));
1104 }
1105 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)1106 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1107 {
1108 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1109 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1110 GENMASK(19, 16));
1111 }
1112 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)1113 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1114 {
1115 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1116 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1117 GENMASK(21, 20));
1118 }
1119 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)1120 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1121 {
1122 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1123 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1124 GENMASK(23, 22));
1125 }
1126 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)1127 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1128 {
1129 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1130 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1131 GENMASK(25, 24));
1132 }
1133 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)1134 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1135 {
1136 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1137 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1138 GENMASK(27, 26));
1139 }
1140 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)1141 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1142 {
1143 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1144 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1145 BIT(28));
1146 }
1147 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)1148 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1149 {
1150 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1151 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1152 BIT(29));
1153 }
1154 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)1155 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1156 {
1157 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1158 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1159 BIT(30));
1160 }
1161 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1162 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1163 {
1164 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1165 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1166 BIT(31));
1167 }
1168
1169 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1170 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1171 {
1172 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1173 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1174 GENMASK(1, 0));
1175 }
1176
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1177 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1178 {
1179 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1180 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1181 GENMASK(3, 2));
1182 }
1183
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1184 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1185 {
1186 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1187 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1188 GENMASK(5, 4));
1189 }
1190
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1191 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1192 {
1193 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1194 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1195 GENMASK(7, 6));
1196 }
1197
1198 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1199 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1200 {
1201 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1202 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1203 GENMASK(7, 0));
1204 }
1205 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1206 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1207 {
1208 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1209 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1210 GENMASK(16, 8));
1211 }
1212 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1213 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1214 {
1215 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1216 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1217 BIT(17));
1218 }
1219 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1220 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1221 {
1222 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1223 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1224 GENMASK(19, 18));
1225 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1226 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1227 {
1228 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1229 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1230 GENMASK(21, 20));
1231 }
1232
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1233 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1234 {
1235 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1236 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1237 GENMASK(23, 22));
1238 }
1239 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1240 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1241 {
1242 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1243 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1244 GENMASK(27, 24));
1245 }
1246
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1247 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1248 {
1249 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1250 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1251 GENMASK(31, 30));
1252 }
1253 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1254 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1255 {
1256 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1257 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1258 GENMASK(2, 0));
1259 }
1260 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1261 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1262 {
1263 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1264 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1265 GENMASK(5, 3));
1266 }
1267 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1268 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1269 {
1270 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1271 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1272 GENMASK(7, 6));
1273 }
1274 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1275 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1276 {
1277 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1278 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1279 GENMASK(9, 8));
1280 }
1281 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1282 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1283 {
1284 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1285 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1286 GENMASK(11, 10));
1287 }
1288 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1289 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1290 {
1291 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1292 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1293 BIT(12));
1294 }
1295 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1296 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1297 {
1298 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1299 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1300 BIT(13));
1301 }
1302 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1303 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1304 {
1305 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1306 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1307 BIT(14));
1308 }
1309 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1310 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1311 {
1312 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1313 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1314 BIT(15));
1315 }
1316 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1317 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1318 {
1319 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1320 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1321 GENMASK(24, 16));
1322 }
1323 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1324 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1325 {
1326 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1327 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1328 GENMASK(27, 25));
1329 }
1330
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1331 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1332 {
1333 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1334 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1335 GENMASK(29, 28));
1336 }
1337
1338 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1339 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1340 {
1341 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1342 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1343 GENMASK(31, 30));
1344 }
1345
1346 struct rtw89_h2c_cctlinfo_ud_g7 {
1347 __le32 c0;
1348 __le32 w0;
1349 __le32 w1;
1350 __le32 w2;
1351 __le32 w3;
1352 __le32 w4;
1353 __le32 w5;
1354 __le32 w6;
1355 __le32 w7;
1356 __le32 w8;
1357 __le32 w9;
1358 __le32 w10;
1359 __le32 w11;
1360 __le32 w12;
1361 __le32 w13;
1362 __le32 w14;
1363 __le32 w15;
1364 __le32 m0;
1365 __le32 m1;
1366 __le32 m2;
1367 __le32 m3;
1368 __le32 m4;
1369 __le32 m5;
1370 __le32 m6;
1371 __le32 m7;
1372 __le32 m8;
1373 __le32 m9;
1374 __le32 m10;
1375 __le32 m11;
1376 __le32 m12;
1377 __le32 m13;
1378 __le32 m14;
1379 __le32 m15;
1380 } __packed;
1381
1382 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1383 #define CCTLINFO_G7_C0_OP BIT(7)
1384
1385 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1386 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1387 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1388 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1389 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1390 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1391 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1392 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1393 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1394 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1395 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1396 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1397 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1398 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1399 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1400 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1401 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1402 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1403 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1404 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1405 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1406 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1407 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1408 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1409 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1410 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1411 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1412 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1413 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1414 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1415 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1416 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1417 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1418 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1419 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1420 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1421 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1422 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1423 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1424 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1425 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1426 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1427 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1428 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1429 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1430 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1431 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1432 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1433 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1434 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1435 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1436 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1437 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1438 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1439 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1440 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1441 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1442 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1443 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1444 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1445 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1446 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1447 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1448 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1449 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1450 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1451 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1452 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1453 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1454 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1455 #define CCTLINFO_G7_W6_ULDL BIT(31)
1456 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1457 #define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1458 #define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1459 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1460 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1461 #define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1462 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1463 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1464 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1465 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1466 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1467 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1468 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1469 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1470 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1471 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1472 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1473 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1474 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1475 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1476 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1477 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1478 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1479 /* W9~13 are reserved */
1480 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1481 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1482 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1483 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1484 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1485 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1486 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1487 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1488
1489 struct rtw89_h2c_bcn_upd {
1490 __le32 w0;
1491 __le32 w1;
1492 __le32 w2;
1493 } __packed;
1494
1495 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1496 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1497 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1498 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1499 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1500 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1501 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1502 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1503 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1504 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1505 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1506 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1507 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1508 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1509 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1510 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1511 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1512 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1513 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1514 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1515
1516 struct rtw89_h2c_bcn_upd_be {
1517 __le32 w0;
1518 __le32 w1;
1519 __le32 w2;
1520 __le32 w3;
1521 __le32 w4;
1522 __le32 w5;
1523 __le32 w6;
1524 __le32 w7;
1525 __le32 w8;
1526 __le32 w9;
1527 __le32 w10;
1528 __le32 w11;
1529 __le32 w12;
1530 __le32 w13;
1531 __le32 w14;
1532 __le32 w15;
1533 __le32 w16;
1534 __le32 w17;
1535 __le32 w18;
1536 __le32 w19;
1537 __le32 w20;
1538 __le32 w21;
1539 __le32 w22;
1540 __le32 w23;
1541 __le32 w24;
1542 __le32 w25;
1543 __le32 w26;
1544 __le32 w27;
1545 __le32 w28;
1546 __le32 w29;
1547 } __packed;
1548
1549 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1550 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1551 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1552 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1553 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1554 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1555 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1556 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1557 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1558 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1559 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1560 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1561 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1562 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1563 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1564 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1565 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1566 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1567 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1568 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1569 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1570 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1571 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1572 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1573 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1574 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1575 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1576 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1577 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1578 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1579 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1580 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1581
SET_FWROLE_MAINTAIN_MACID(void * h2c,u32 val)1582 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1583 {
1584 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1585 }
1586
SET_FWROLE_MAINTAIN_SELF_ROLE(void * h2c,u32 val)1587 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1588 {
1589 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1590 }
1591
SET_FWROLE_MAINTAIN_UPD_MODE(void * h2c,u32 val)1592 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1593 {
1594 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1595 }
1596
SET_FWROLE_MAINTAIN_WIFI_ROLE(void * h2c,u32 val)1597 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1598 {
1599 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1600 }
1601
1602 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1603 RTW89_FW_N_AC_STA = 0,
1604 RTW89_FW_AX_STA = 1,
1605 RTW89_FW_BE_STA = 2,
1606 };
1607
1608 struct rtw89_h2c_join {
1609 __le32 w0;
1610 } __packed;
1611
1612 struct rtw89_h2c_join_v1 {
1613 __le32 w0;
1614 __le32 w1;
1615 __le32 w2;
1616 } __packed;
1617
1618 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1619 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1620 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1621 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1622 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1623 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1624 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1625 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1626 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1627 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1628 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1629 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1630 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1631 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1632 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1633 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1634 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1635 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1636 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1637 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1638 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1639 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1640 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1641 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1642
1643 struct rtw89_h2c_notify_dbcc {
1644 __le32 w0;
1645 } __packed;
1646
1647 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1648
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1649 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1650 {
1651 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1652 }
1653
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1654 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1655 {
1656 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1657 }
1658
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1659 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1660 {
1661 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1662 }
1663
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1664 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1665 {
1666 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1667 }
1668
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1669 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1670 {
1671 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1672 }
1673
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1674 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1675 {
1676 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1677 }
1678
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1679 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1680 {
1681 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1682 }
1683
SET_LOG_CFG_PATH(void * h2c,u32 val)1684 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1685 {
1686 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1687 }
1688
SET_LOG_CFG_COMP(void * h2c,u32 val)1689 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1690 {
1691 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1692 }
1693
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1694 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1695 {
1696 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1697 }
1698
1699 struct rtw89_h2c_ba_cam {
1700 __le32 w0;
1701 __le32 w1;
1702 } __packed;
1703
1704 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1705 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1706 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1707 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1708 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1709 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1710 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1711 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1712 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1713 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1714 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1715
1716 struct rtw89_h2c_ba_cam_v1 {
1717 __le32 w0;
1718 __le32 w1;
1719 } __packed;
1720
1721 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1722 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1723 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1724 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1725 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1726 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1727 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1728 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1729 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1730 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1731 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1732
1733 struct rtw89_h2c_ba_cam_init {
1734 __le32 w0;
1735 } __packed;
1736
1737 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1738 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1739 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1740
SET_LPS_PARM_MACID(void * h2c,u32 val)1741 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1742 {
1743 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1744 }
1745
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1746 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1747 {
1748 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1749 }
1750
SET_LPS_PARM_RLBM(void * h2c,u32 val)1751 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1752 {
1753 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1754 }
1755
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1756 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1757 {
1758 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1759 }
1760
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1761 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1762 {
1763 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1764 }
1765
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1766 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1767 {
1768 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1769 }
1770
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1771 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1772 {
1773 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1774 }
1775
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1776 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1777 {
1778 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1779 }
1780
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)1781 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1782 {
1783 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1784 }
1785
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)1786 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1787 {
1788 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1789 }
1790
1791 struct rtw89_h2c_lps_ch_info {
1792 struct {
1793 u8 pri_ch;
1794 u8 central_ch;
1795 u8 bw;
1796 u8 band;
1797 } __packed info[2];
1798
1799 __le32 mlo_dbcc_mode_lps;
1800 } __packed;
1801
1802 struct rtw89_h2c_lps_ml_cmn_info {
1803 u8 fmt_id;
1804 u8 rsvd0[3];
1805 __le32 mlo_dbcc_mode;
1806 u8 central_ch[RTW89_PHY_MAX];
1807 u8 pri_ch[RTW89_PHY_MAX];
1808 u8 bw[RTW89_PHY_MAX];
1809 u8 band[RTW89_PHY_MAX];
1810 u8 bcn_rate_type[RTW89_PHY_MAX];
1811 u8 rsvd1[2];
1812 __le16 tia_gain[RTW89_PHY_MAX][TIA_GAIN_NUM];
1813 u8 lna_gain[RTW89_PHY_MAX][LNA_GAIN_NUM];
1814 u8 rsvd2[2];
1815 } __packed;
1816
RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void * cmd,u32 val)1817 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1818 {
1819 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1820 }
1821
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)1822 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1823 {
1824 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1825 }
1826
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)1827 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1828 {
1829 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1830 }
1831
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)1832 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1833 {
1834 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1835 }
1836
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)1837 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1838 {
1839 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1840 }
1841
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)1842 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1843 {
1844 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1845 }
1846
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)1847 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1848 {
1849 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1850 }
1851
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void * cmd,u32 val)1852 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1853 {
1854 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1855 }
1856
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void * cmd,u32 val)1857 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1858 {
1859 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1860 }
1861
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void * cmd,u32 val)1862 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1863 {
1864 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1865 }
1866
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void * cmd,u32 val)1867 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1868 {
1869 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1870 }
1871
RTW89_SET_KEEP_ALIVE_ENABLE(void * h2c,u32 val)1872 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1873 {
1874 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1875 }
1876
RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void * h2c,u32 val)1877 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1878 {
1879 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1880 }
1881
RTW89_SET_KEEP_ALIVE_PERIOD(void * h2c,u32 val)1882 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1883 {
1884 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1885 }
1886
RTW89_SET_KEEP_ALIVE_MACID(void * h2c,u32 val)1887 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1888 {
1889 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1890 }
1891
RTW89_SET_DISCONNECT_DETECT_ENABLE(void * h2c,u32 val)1892 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1893 {
1894 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1895 }
1896
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void * h2c,u32 val)1897 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1898 {
1899 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1900 }
1901
RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void * h2c,u32 val)1902 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1903 {
1904 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1905 }
1906
RTW89_SET_DISCONNECT_DETECT_MAC_ID(void * h2c,u32 val)1907 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1908 {
1909 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1910 }
1911
RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void * h2c,u32 val)1912 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1913 {
1914 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1915 }
1916
RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void * h2c,u32 val)1917 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1918 {
1919 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1920 }
1921
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void * h2c,u32 val)1922 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1923 {
1924 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1925 }
1926
1927 struct rtw89_h2c_wow_global {
1928 __le32 w0;
1929 struct rtw89_wow_key_info key_info;
1930 } __packed;
1931
1932 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1933 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1934 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1935 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1936 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
1937 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
1938 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1939
1940 #define RTW89_MAX_SUPPORT_NL_NUM 16
1941 struct rtw89_h2c_cfg_nlo {
1942 __le32 w0;
1943 u8 nlo_cnt;
1944 u8 rsvd[3];
1945 __le32 patterncheck;
1946 __le32 rsvd1;
1947 __le32 rsvd2;
1948 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM];
1949 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM];
1950 u8 rsvd3[24];
1951 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN];
1952 } __packed;
1953
1954 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
1955 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
1956 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
1957
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void * h2c,u32 val)1958 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
1959 {
1960 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1961 }
1962
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void * h2c,u32 val)1963 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
1964 {
1965 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1966 }
1967
RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void * h2c,u32 val)1968 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
1969 {
1970 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1971 }
1972
RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void * h2c,u32 val)1973 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
1974 {
1975 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1976 }
1977
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void * h2c,u32 val)1978 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
1979 {
1980 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
1981 }
1982
RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void * h2c,u32 val)1983 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
1984 {
1985 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
1986 }
1987
RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void * h2c,u32 val)1988 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
1989 {
1990 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
1991 }
1992
RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void * h2c,u32 val)1993 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
1994 {
1995 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
1996 }
1997
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void * h2c,u32 val)1998 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
1999 {
2000 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2001 }
2002
RTW89_SET_WOW_CAM_UPD_R_W(void * h2c,u32 val)2003 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2004 {
2005 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2006 }
2007
RTW89_SET_WOW_CAM_UPD_IDX(void * h2c,u32 val)2008 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2009 {
2010 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2011 }
2012
RTW89_SET_WOW_CAM_UPD_WKFM1(void * h2c,u32 val)2013 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2014 {
2015 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2016 }
2017
RTW89_SET_WOW_CAM_UPD_WKFM2(void * h2c,u32 val)2018 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2019 {
2020 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2021 }
2022
RTW89_SET_WOW_CAM_UPD_WKFM3(void * h2c,u32 val)2023 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2024 {
2025 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2026 }
2027
RTW89_SET_WOW_CAM_UPD_WKFM4(void * h2c,u32 val)2028 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2029 {
2030 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2031 }
2032
RTW89_SET_WOW_CAM_UPD_CRC(void * h2c,u32 val)2033 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2034 {
2035 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2036 }
2037
RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void * h2c,u32 val)2038 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2039 {
2040 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2041 }
2042
RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void * h2c,u32 val)2043 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2044 {
2045 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2046 }
2047
RTW89_SET_WOW_CAM_UPD_UC(void * h2c,u32 val)2048 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2049 {
2050 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2051 }
2052
RTW89_SET_WOW_CAM_UPD_MC(void * h2c,u32 val)2053 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2054 {
2055 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2056 }
2057
RTW89_SET_WOW_CAM_UPD_BC(void * h2c,u32 val)2058 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2059 {
2060 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2061 }
2062
RTW89_SET_WOW_CAM_UPD_VALID(void * h2c,u32 val)2063 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2064 {
2065 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2066 }
2067
2068 struct rtw89_h2c_wow_gtk_ofld {
2069 __le32 w0;
2070 __le32 w1;
2071 struct rtw89_wow_gtk_info gtk_info;
2072 } __packed;
2073
2074 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2075 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2076 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2077 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2078 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2079 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2080 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2081 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2082 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2083 #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2084
2085 struct rtw89_h2c_arp_offload {
2086 __le32 w0;
2087 __le32 w1;
2088 } __packed;
2089
2090 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2091 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2092 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2093 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2094 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2095
2096 enum rtw89_btc_btf_h2c_class {
2097 BTFC_SET = 0x10,
2098 BTFC_GET = 0x11,
2099 BTFC_FW_EVENT = 0x12,
2100 };
2101
2102 enum rtw89_btc_btf_set {
2103 SET_REPORT_EN = 0x0,
2104 SET_SLOT_TABLE,
2105 SET_MREG_TABLE,
2106 SET_CX_POLICY,
2107 SET_GPIO_DBG,
2108 SET_DRV_INFO,
2109 SET_DRV_EVENT,
2110 SET_BT_WREG_ADDR,
2111 SET_BT_WREG_VAL,
2112 SET_BT_RREG_ADDR,
2113 SET_BT_WL_CH_INFO,
2114 SET_BT_INFO_REPORT,
2115 SET_BT_IGNORE_WLAN_ACT,
2116 SET_BT_TX_PWR,
2117 SET_BT_LNA_CONSTRAIN,
2118 SET_BT_QUERY_DEV_LIST,
2119 SET_BT_QUERY_DEV_INFO,
2120 SET_BT_PSD_REPORT,
2121 SET_H2C_TEST,
2122 SET_IOFLD_RF,
2123 SET_IOFLD_BB,
2124 SET_IOFLD_MAC,
2125 SET_IOFLD_SCBD,
2126 SET_H2C_MACRO,
2127 SET_MAX1,
2128 };
2129
2130 enum rtw89_btc_cxdrvinfo {
2131 CXDRVINFO_INIT = 0,
2132 CXDRVINFO_ROLE,
2133 CXDRVINFO_DBCC,
2134 CXDRVINFO_SMAP,
2135 CXDRVINFO_RFK,
2136 CXDRVINFO_RUN,
2137 CXDRVINFO_CTRL,
2138 CXDRVINFO_SCAN,
2139 CXDRVINFO_TRX, /* WL traffic to WL fw */
2140 CXDRVINFO_TXPWR,
2141 CXDRVINFO_FDDT,
2142 CXDRVINFO_MLO,
2143 CXDRVINFO_OSI,
2144 CXDRVINFO_MAX,
2145 };
2146
2147 enum rtw89_scan_mode {
2148 RTW89_SCAN_IMMEDIATE,
2149 RTW89_SCAN_DELAY,
2150 };
2151
2152 enum rtw89_scan_type {
2153 RTW89_SCAN_ONCE,
2154 RTW89_SCAN_NORMAL,
2155 RTW89_SCAN_NORMAL_SLOW,
2156 RTW89_SCAN_SEAMLESS,
2157 RTW89_SCAN_MAX,
2158 };
2159
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)2160 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2161 {
2162 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2163 }
2164
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)2165 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2166 {
2167 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2168 }
2169
2170 struct rtw89_h2c_cxhdr {
2171 u8 type;
2172 u8 len;
2173 } __packed;
2174
2175 struct rtw89_h2c_cxhdr_v7 {
2176 u8 type;
2177 u8 ver;
2178 u8 len;
2179 } __packed;
2180
2181 struct rtw89_h2c_cxctrl_v7 {
2182 struct rtw89_h2c_cxhdr_v7 hdr;
2183 struct rtw89_btc_ctrl_v7 ctrl;
2184 } __packed;
2185
2186 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2187 #define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2188
2189 struct rtw89_btc_wl_role_info_v7_u8 {
2190 u8 connect_cnt;
2191 u8 link_mode;
2192 u8 link_mode_chg;
2193 u8 p2p_2g;
2194
2195 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
2196 } __packed;
2197
2198 struct rtw89_btc_wl_role_info_v7_u32 {
2199 __le32 role_map;
2200 __le32 mrole_type;
2201 __le32 mrole_noa_duration;
2202 __le32 dbcc_en;
2203 __le32 dbcc_chg;
2204 __le32 dbcc_2g_phy;
2205 } __packed;
2206
2207 struct rtw89_h2c_cxrole_v7 {
2208 struct rtw89_h2c_cxhdr_v7 hdr;
2209 struct rtw89_btc_wl_role_info_v7_u8 _u8;
2210 struct rtw89_btc_wl_role_info_v7_u32 _u32;
2211 } __packed;
2212
2213 struct rtw89_btc_wl_role_info_v8_u8 {
2214 u8 connect_cnt;
2215 u8 link_mode;
2216 u8 link_mode_chg;
2217 u8 p2p_2g;
2218
2219 u8 pta_req_band;
2220 u8 dbcc_en;
2221 u8 dbcc_chg;
2222 u8 dbcc_2g_phy;
2223
2224 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
2225 } __packed;
2226
2227 struct rtw89_btc_wl_role_info_v8_u32 {
2228 __le32 role_map;
2229 __le32 mrole_type;
2230 __le32 mrole_noa_duration;
2231 } __packed;
2232
2233 struct rtw89_h2c_cxrole_v8 {
2234 struct rtw89_h2c_cxhdr_v7 hdr;
2235 struct rtw89_btc_wl_role_info_v8_u8 _u8;
2236 struct rtw89_btc_wl_role_info_v8_u32 _u32;
2237 } __packed;
2238
2239 struct rtw89_h2c_cxinit {
2240 struct rtw89_h2c_cxhdr hdr;
2241 u8 ant_type;
2242 u8 ant_num;
2243 u8 ant_iso;
2244 u8 ant_info;
2245 u8 mod_rfe;
2246 u8 mod_cv;
2247 u8 mod_info;
2248 u8 mod_adie_kt;
2249 u8 wl_gch;
2250 u8 info;
2251 u8 rsvd;
2252 u8 rsvd1;
2253 } __packed;
2254
2255 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2256 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2257 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2258 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2259
2260 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2261 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2262 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2263 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2264
2265 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2266 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2267 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2268 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2269 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2270
2271 struct rtw89_h2c_cxinit_v7 {
2272 struct rtw89_h2c_cxhdr_v7 hdr;
2273 struct rtw89_btc_init_info_v7 init;
2274 } __packed;
2275
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2276 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2277 {
2278 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2279 }
2280
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2281 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2282 {
2283 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2284 }
2285
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2286 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2287 {
2288 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2289 }
2290
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2291 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2292 {
2293 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2294 }
2295
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2296 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2297 {
2298 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2299 }
2300
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2301 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2302 {
2303 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2304 }
2305
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2306 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2307 {
2308 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2309 }
2310
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2311 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2312 {
2313 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2314 }
2315
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2316 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2317 {
2318 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2319 }
2320
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2321 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2322 {
2323 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2324 }
2325
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2326 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2327 {
2328 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2329 }
2330
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2331 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2332 {
2333 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2334 }
2335
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2336 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2337 {
2338 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2339 }
2340
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2341 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2342 {
2343 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2344 }
2345
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2346 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2347 {
2348 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2349 }
2350
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2351 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2352 {
2353 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2354 }
2355
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2356 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2357 {
2358 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2359 }
2360
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2361 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2362 {
2363 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2364 }
2365
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2366 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2367 {
2368 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2369 }
2370
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2371 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2372 {
2373 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2374 }
2375
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2376 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2377 {
2378 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2379 }
2380
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2381 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2382 {
2383 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2384 }
2385
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2386 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2387 {
2388 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2389 }
2390
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2391 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2392 {
2393 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2394 }
2395
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2396 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2397 {
2398 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2399 }
2400
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2401 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2402 {
2403 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2404 }
2405
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2406 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2407 {
2408 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2409 }
2410
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2411 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2412 {
2413 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2414 }
2415
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void * cmd,u8 val,int n,u8 offset)2416 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2417 {
2418 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2419 }
2420
RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void * cmd,u8 val,int n,u8 offset)2421 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2422 {
2423 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2424 }
2425
RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void * cmd,u8 val,int n,u8 offset)2426 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2427 {
2428 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2429 }
2430
RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void * cmd,u8 val,int n,u8 offset)2431 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2432 {
2433 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2434 }
2435
RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void * cmd,u8 val,int n,u8 offset)2436 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2437 {
2438 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2439 }
2440
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void * cmd,u8 val,int n,u8 offset)2441 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2442 {
2443 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2444 }
2445
RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void * cmd,u8 val,int n,u8 offset)2446 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2447 {
2448 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2449 }
2450
RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void * cmd,u8 val,int n,u8 offset)2451 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2452 {
2453 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2454 }
2455
RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void * cmd,u8 val,int n,u8 offset)2456 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2457 {
2458 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2459 }
2460
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void * cmd,u32 val,int n,u8 offset)2461 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2462 {
2463 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2464 }
2465
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2466 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2467 {
2468 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2469 }
2470
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2471 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2472 {
2473 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2474 }
2475
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2476 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2477 {
2478 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2479 }
2480
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2481 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2482 {
2483 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2484 }
2485
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2486 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2487 {
2488 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2489 }
2490
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2491 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2492 {
2493 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2494 }
2495
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2496 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2497 {
2498 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2499 }
2500
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2501 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2502 {
2503 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2504 }
2505
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2506 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2507 {
2508 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2509 }
2510
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2511 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2512 {
2513 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2514 }
2515
RTW89_SET_FWCMD_CXTRX_TXLV(void * cmd,u8 val)2516 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2517 {
2518 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2519 }
2520
RTW89_SET_FWCMD_CXTRX_RXLV(void * cmd,u8 val)2521 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2522 {
2523 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2524 }
2525
RTW89_SET_FWCMD_CXTRX_WLRSSI(void * cmd,u8 val)2526 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2527 {
2528 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2529 }
2530
RTW89_SET_FWCMD_CXTRX_BTRSSI(void * cmd,u8 val)2531 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2532 {
2533 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2534 }
2535
RTW89_SET_FWCMD_CXTRX_TXPWR(void * cmd,s8 val)2536 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2537 {
2538 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2539 }
2540
RTW89_SET_FWCMD_CXTRX_RXGAIN(void * cmd,s8 val)2541 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2542 {
2543 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2544 }
2545
RTW89_SET_FWCMD_CXTRX_BTTXPWR(void * cmd,s8 val)2546 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2547 {
2548 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2549 }
2550
RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void * cmd,s8 val)2551 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2552 {
2553 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2554 }
2555
RTW89_SET_FWCMD_CXTRX_CN(void * cmd,u8 val)2556 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2557 {
2558 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2559 }
2560
RTW89_SET_FWCMD_CXTRX_NHM(void * cmd,s8 val)2561 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2562 {
2563 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2564 }
2565
RTW89_SET_FWCMD_CXTRX_BTPROFILE(void * cmd,u8 val)2566 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2567 {
2568 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2569 }
2570
RTW89_SET_FWCMD_CXTRX_RSVD2(void * cmd,u8 val)2571 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2572 {
2573 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2574 }
2575
RTW89_SET_FWCMD_CXTRX_TXRATE(void * cmd,u16 val)2576 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2577 {
2578 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2579 }
2580
RTW89_SET_FWCMD_CXTRX_RXRATE(void * cmd,u16 val)2581 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2582 {
2583 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2584 }
2585
RTW89_SET_FWCMD_CXTRX_TXTP(void * cmd,u32 val)2586 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2587 {
2588 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2589 }
2590
RTW89_SET_FWCMD_CXTRX_RXTP(void * cmd,u32 val)2591 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2592 {
2593 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2594 }
2595
RTW89_SET_FWCMD_CXTRX_RXERRRA(void * cmd,u32 val)2596 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2597 {
2598 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2599 }
2600
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2601 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2602 {
2603 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2604 }
2605
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2606 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2607 {
2608 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2609 }
2610
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2611 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2612 {
2613 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2614 }
2615
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2616 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2617 {
2618 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2619 }
2620
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2621 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2622 {
2623 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2624 }
2625
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2626 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2627 {
2628 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2629 }
2630
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2631 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2632 {
2633 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2634 }
2635
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2636 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2637 {
2638 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2639 }
2640
2641 struct rtw89_h2c_chinfo_elem {
2642 __le32 w0;
2643 __le32 w1;
2644 __le32 w2;
2645 __le32 w3;
2646 __le32 w4;
2647 __le32 w5;
2648 __le32 w6;
2649 } __packed;
2650
2651 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2652 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2653 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2654 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2655 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2656 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2657 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2658 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2659 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2660 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2661 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2662 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2663 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2664 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2665 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2666 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2667 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2668 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2669 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2670 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2671 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2672 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2673 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2674 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2675
2676 struct rtw89_h2c_chinfo_elem_be {
2677 __le32 w0;
2678 __le32 w1;
2679 __le32 w2;
2680 __le32 w3;
2681 __le32 w4;
2682 __le32 w5;
2683 __le32 w6;
2684 __le32 w7;
2685 } __packed;
2686
2687 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2688 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2689 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2690 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2691 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2692 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2693 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2694 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2695 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2696 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2697 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2698 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2699 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2700 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2701 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2702 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2703 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2704 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2705 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2706 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2707 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2708 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2709 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2710 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2711 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2712 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2713 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2714 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2715 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2716 #define RTW89_H2C_CHINFO_BE_W7_PERIOD_V1 GENMASK(15, 0)
2717
2718 struct rtw89_h2c_chinfo {
2719 u8 ch_num;
2720 u8 elem_size;
2721 u8 arg;
2722 u8 rsvd0;
2723 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2724 } __packed;
2725
2726 struct rtw89_h2c_chinfo_be {
2727 u8 ch_num;
2728 u8 elem_size;
2729 u8 arg;
2730 u8 rsvd0;
2731 struct rtw89_h2c_chinfo_elem_be elem[] __counted_by(ch_num);
2732 } __packed;
2733
2734 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2735 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2736
2737 struct rtw89_h2c_scanofld {
2738 __le32 w0;
2739 __le32 w1;
2740 __le32 w2;
2741 __le32 tsf_high;
2742 __le32 tsf_low;
2743 __le32 w5;
2744 __le32 w6;
2745 } __packed;
2746
2747 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2748 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2749 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2750 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2751 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2752 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2753 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2754 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2755 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2756 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2757 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2758 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2759 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2760 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2761 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2762 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2763 #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
2764 #define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
2765
2766 struct rtw89_h2c_scanofld_be_macc_role {
2767 __le32 w0;
2768 } __packed;
2769
2770 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2771 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2772 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2773 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2774
2775 struct rtw89_h2c_scanofld_be_opch {
2776 __le32 w0;
2777 __le32 w1;
2778 __le32 w2;
2779 __le32 w3;
2780 __le32 w4;
2781 } __packed;
2782
2783 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
2784 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2785 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
2786 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
2787 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2788 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2789 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2790 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2791 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2792 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
2793 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2794 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2795 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2796 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2797 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2798 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2799 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2800 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2801 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2802 #define RTW89_H2C_SCANOFLD_BE_OPCH_W4_DURATION_V1 GENMASK(15, 0)
2803
2804 struct rtw89_h2c_scanofld_be {
2805 __le32 w0;
2806 __le32 w1;
2807 __le32 w2;
2808 __le32 w3;
2809 __le32 w4;
2810 __le32 w5;
2811 __le32 w6;
2812 __le32 w7;
2813 __le32 w8;
2814 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */
2815 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */
2816 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */
2817 } __packed;
2818
2819 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
2820 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
2821 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
2822 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2823 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2824 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2825 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2826 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
2827 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2828 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2829 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2830 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2831 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
2832 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2833 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2834 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2835 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2836 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2837 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2838 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2839 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2840 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2841 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2842 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2843 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2844 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
2845 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
2846 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
2847 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
2848 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
2849 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
2850
2851 struct rtw89_h2c_fwips {
2852 __le32 w0;
2853 } __packed;
2854
2855 #define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
2856 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2857
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)2858 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2859 {
2860 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2861 }
2862
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)2863 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2864 {
2865 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2866 }
2867
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)2868 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2869 {
2870 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2871 }
2872
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)2873 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2874 {
2875 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2876 }
2877
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)2878 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2879 {
2880 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2881 }
2882
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)2883 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2884 {
2885 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2886 }
2887
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)2888 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2889 {
2890 *((__le32 *)cmd + 1) = val;
2891 }
2892
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)2893 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2894 {
2895 *((__le32 *)cmd + 2) = val;
2896 }
2897
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)2898 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2899 {
2900 *((__le32 *)cmd + 3) = val;
2901 }
2902
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)2903 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2904 {
2905 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2906 }
2907
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)2908 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2909 {
2910 u8 ctwnd;
2911
2912 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2913 return;
2914 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2915 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2916 }
2917
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)2918 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2919 {
2920 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2921 }
2922
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)2923 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2924 {
2925 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2926 }
2927
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)2928 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2929 {
2930 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2931 }
2932
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)2933 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2934 {
2935 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2936 }
2937
2938 enum rtw89_fw_mcc_c2h_rpt_cfg {
2939 RTW89_FW_MCC_C2H_RPT_OFF = 0,
2940 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
2941 RTW89_FW_MCC_C2H_RPT_ALL = 2,
2942 };
2943
2944 struct rtw89_fw_mcc_add_req {
2945 u8 macid;
2946 u8 central_ch_seg0;
2947 u8 central_ch_seg1;
2948 u8 primary_ch;
2949 enum rtw89_bandwidth bandwidth: 4;
2950 u32 group: 2;
2951 u32 c2h_rpt: 2;
2952 u32 dis_tx_null: 1;
2953 u32 dis_sw_retry: 1;
2954 u32 in_curr_ch: 1;
2955 u32 sw_retry_count: 3;
2956 u32 tx_null_early: 4;
2957 u32 btc_in_2g: 1;
2958 u32 pta_en: 1;
2959 u32 rfk_by_pass: 1;
2960 u32 ch_band_type: 2;
2961 u32 rsvd0: 9;
2962 u32 duration;
2963 u8 courtesy_en;
2964 u8 courtesy_num;
2965 u8 courtesy_target;
2966 u8 rsvd1;
2967 };
2968
RTW89_SET_FWCMD_ADD_MCC_MACID(void * cmd,u32 val)2969 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2970 {
2971 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2972 }
2973
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void * cmd,u32 val)2974 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2975 {
2976 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2977 }
2978
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void * cmd,u32 val)2979 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2980 {
2981 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2982 }
2983
RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void * cmd,u32 val)2984 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2985 {
2986 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2987 }
2988
RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void * cmd,u32 val)2989 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2990 {
2991 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2992 }
2993
RTW89_SET_FWCMD_ADD_MCC_GROUP(void * cmd,u32 val)2994 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2995 {
2996 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2997 }
2998
RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void * cmd,u32 val)2999 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
3000 {
3001 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
3002 }
3003
RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void * cmd,u32 val)3004 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
3005 {
3006 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
3007 }
3008
RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void * cmd,u32 val)3009 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
3010 {
3011 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
3012 }
3013
RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void * cmd,u32 val)3014 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
3015 {
3016 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
3017 }
3018
RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void * cmd,u32 val)3019 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
3020 {
3021 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
3022 }
3023
RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void * cmd,u32 val)3024 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
3025 {
3026 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
3027 }
3028
RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void * cmd,u32 val)3029 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
3030 {
3031 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
3032 }
3033
RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void * cmd,u32 val)3034 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
3035 {
3036 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
3037 }
3038
RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void * cmd,u32 val)3039 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
3040 {
3041 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
3042 }
3043
RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void * cmd,u32 val)3044 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
3045 {
3046 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
3047 }
3048
RTW89_SET_FWCMD_ADD_MCC_DURATION(void * cmd,u32 val)3049 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3050 {
3051 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3052 }
3053
RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void * cmd,u32 val)3054 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3055 {
3056 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3057 }
3058
RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void * cmd,u32 val)3059 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3060 {
3061 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3062 }
3063
RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void * cmd,u32 val)3064 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3065 {
3066 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3067 }
3068
3069 enum rtw89_fw_mcc_old_group_actions {
3070 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3071 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3072 };
3073
3074 struct rtw89_fw_mcc_start_req {
3075 u32 group: 2;
3076 u32 btc_in_group: 1;
3077 u32 old_group_action: 2;
3078 u32 old_group: 2;
3079 u32 rsvd0: 9;
3080 u32 notify_cnt: 3;
3081 u32 rsvd1: 2;
3082 u32 notify_rxdbg_en: 1;
3083 u32 rsvd2: 2;
3084 u32 macid: 8;
3085 u32 tsf_low;
3086 u32 tsf_high;
3087 };
3088
RTW89_SET_FWCMD_START_MCC_GROUP(void * cmd,u32 val)3089 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3090 {
3091 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3092 }
3093
RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void * cmd,u32 val)3094 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3095 {
3096 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3097 }
3098
RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void * cmd,u32 val)3099 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3100 {
3101 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3102 }
3103
RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void * cmd,u32 val)3104 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3105 {
3106 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3107 }
3108
RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void * cmd,u32 val)3109 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3110 {
3111 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3112 }
3113
RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void * cmd,u32 val)3114 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3115 {
3116 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3117 }
3118
RTW89_SET_FWCMD_START_MCC_MACID(void * cmd,u32 val)3119 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3120 {
3121 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3122 }
3123
RTW89_SET_FWCMD_START_MCC_TSF_LOW(void * cmd,u32 val)3124 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3125 {
3126 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3127 }
3128
RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void * cmd,u32 val)3129 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3130 {
3131 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3132 }
3133
RTW89_SET_FWCMD_STOP_MCC_MACID(void * cmd,u32 val)3134 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3135 {
3136 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3137 }
3138
RTW89_SET_FWCMD_STOP_MCC_GROUP(void * cmd,u32 val)3139 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3140 {
3141 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3142 }
3143
RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void * cmd,u32 val)3144 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3145 {
3146 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3147 }
3148
RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void * cmd,u32 val)3149 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3150 {
3151 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3152 }
3153
RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void * cmd,u32 val)3154 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3155 {
3156 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3157 }
3158
RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void * cmd,u32 val)3159 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3160 {
3161 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3162 }
3163
3164 struct rtw89_fw_mcc_tsf_req {
3165 u8 group: 2;
3166 u8 rsvd0: 6;
3167 u8 macid_x;
3168 u8 macid_y;
3169 u8 rsvd1;
3170 };
3171
RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void * cmd,u32 val)3172 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3173 {
3174 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3175 }
3176
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void * cmd,u32 val)3177 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3178 {
3179 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3180 }
3181
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void * cmd,u32 val)3182 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3183 {
3184 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3185 }
3186
RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void * cmd,u32 val)3187 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3188 {
3189 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3190 }
3191
RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void * cmd,u32 val)3192 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3193 {
3194 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3195 }
3196
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void * cmd,u32 val)3197 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3198 {
3199 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3200 }
3201
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void * cmd,u8 * bitmap,u8 len)3202 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3203 u8 *bitmap, u8 len)
3204 {
3205 memcpy((__le32 *)cmd + 1, bitmap, len);
3206 }
3207
RTW89_SET_FWCMD_MCC_SYNC_GROUP(void * cmd,u32 val)3208 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3209 {
3210 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3211 }
3212
RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void * cmd,u32 val)3213 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3214 {
3215 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3216 }
3217
RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void * cmd,u32 val)3218 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3219 {
3220 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3221 }
3222
RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void * cmd,u32 val)3223 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3224 {
3225 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3226 }
3227
3228 struct rtw89_fw_mcc_duration {
3229 u32 group: 2;
3230 u32 btc_in_group: 1;
3231 u32 rsvd0: 5;
3232 u32 start_macid: 8;
3233 u32 macid_x: 8;
3234 u32 macid_y: 8;
3235 u32 start_tsf_low;
3236 u32 start_tsf_high;
3237 u32 duration_x;
3238 u32 duration_y;
3239 };
3240
RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void * cmd,u32 val)3241 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3242 {
3243 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3244 }
3245
3246 static
RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void * cmd,u32 val)3247 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3248 {
3249 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3250 }
3251
3252 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void * cmd,u32 val)3253 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3254 {
3255 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3256 }
3257
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void * cmd,u32 val)3258 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3259 {
3260 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3261 }
3262
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void * cmd,u32 val)3263 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3264 {
3265 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3266 }
3267
3268 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void * cmd,u32 val)3269 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3270 {
3271 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3272 }
3273
3274 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void * cmd,u32 val)3275 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3276 {
3277 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3278 }
3279
3280 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void * cmd,u32 val)3281 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3282 {
3283 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3284 }
3285
3286 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void * cmd,u32 val)3287 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3288 {
3289 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3290 }
3291
3292 enum rtw89_h2c_mrc_sch_types {
3293 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3294 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3295 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3296 };
3297
3298 enum rtw89_h2c_mrc_role_types {
3299 RTW89_H2C_MRC_ROLE_WIFI = 0,
3300 RTW89_H2C_MRC_ROLE_BT = 1,
3301 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3302 };
3303
3304 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3305 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3306
3307 struct rtw89_fw_mrc_add_slot_arg {
3308 u16 duration; /* unit: TU */
3309 bool courtesy_en;
3310 u8 courtesy_period;
3311 u8 courtesy_target; /* slot idx */
3312
3313 unsigned int role_num;
3314 struct {
3315 enum rtw89_h2c_mrc_role_types role_type;
3316 bool is_master;
3317 bool en_tx_null;
3318 enum rtw89_band band;
3319 enum rtw89_bandwidth bw;
3320 u8 macid;
3321 u8 central_ch;
3322 u8 primary_ch;
3323 u8 null_early; /* unit: TU */
3324
3325 /* if MLD, for macid: [0, chip::support_mld_num)
3326 * otherwise, for macid: [0, 32)
3327 */
3328 u32 macid_main_bitmap;
3329 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3330 u32 macid_paired_bitmap;
3331 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3332 };
3333
3334 struct rtw89_fw_mrc_add_arg {
3335 u8 sch_idx;
3336 enum rtw89_h2c_mrc_sch_types sch_type;
3337 bool btc_in_sch;
3338
3339 unsigned int slot_num;
3340 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3341 };
3342
3343 struct rtw89_h2c_mrc_add_role {
3344 __le32 w0;
3345 __le32 w1;
3346 __le32 w2;
3347 __le32 macid_main_bitmap;
3348 __le32 macid_paired_bitmap;
3349 } __packed;
3350
3351 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3352 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3353 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3354 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3355 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3356 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3357 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3358 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3359 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3360 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3361 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3362 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3363 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3364 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3365 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3366 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3367
3368 struct rtw89_h2c_mrc_add_slot {
3369 __le32 w0;
3370 __le32 w1;
3371 struct rtw89_h2c_mrc_add_role roles[];
3372 } __packed;
3373
3374 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3375 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3376 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3377 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3378 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3379
3380 struct rtw89_h2c_mrc_add {
3381 __le32 w0;
3382 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3383 * are other flexible array inside it. We cannot access them correctly
3384 * through this struct. So, in case misusing, we don't really declare
3385 * it here.
3386 */
3387 } __packed;
3388
3389 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3390 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3391 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3392 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3393
3394 enum rtw89_h2c_mrc_start_actions {
3395 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3396 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3397 };
3398
3399 struct rtw89_fw_mrc_start_arg {
3400 u8 sch_idx;
3401 u8 old_sch_idx;
3402 u64 start_tsf;
3403 enum rtw89_h2c_mrc_start_actions action;
3404 };
3405
3406 struct rtw89_h2c_mrc_start {
3407 __le32 w0;
3408 __le32 start_tsf_low;
3409 __le32 start_tsf_high;
3410 } __packed;
3411
3412 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3413 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3414 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3415
3416 struct rtw89_h2c_mrc_del {
3417 __le32 w0;
3418 } __packed;
3419
3420 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3421 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3422 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3423 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3424 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3425 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3426
3427 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3428
3429 struct rtw89_fw_mrc_req_tsf_arg {
3430 unsigned int num;
3431 struct {
3432 u8 band;
3433 u8 port;
3434 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3435 };
3436
3437 struct rtw89_h2c_mrc_req_tsf {
3438 u8 req_tsf_num;
3439 u8 infos[] __counted_by(req_tsf_num);
3440 } __packed;
3441
3442 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3443 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3444
3445 enum rtw89_h2c_mrc_upd_bitmap_actions {
3446 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3447 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3448 };
3449
3450 struct rtw89_fw_mrc_upd_bitmap_arg {
3451 u8 sch_idx;
3452 u8 macid;
3453 u8 client_macid;
3454 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3455 };
3456
3457 struct rtw89_h2c_mrc_upd_bitmap {
3458 __le32 w0;
3459 __le32 w1;
3460 } __packed;
3461
3462 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3463 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3464 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3465 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3466
3467 struct rtw89_fw_mrc_sync_arg {
3468 u8 offset; /* unit: TU */
3469 struct {
3470 u8 band;
3471 u8 port;
3472 } src, dest;
3473 };
3474
3475 struct rtw89_h2c_mrc_sync {
3476 __le32 w0;
3477 __le32 w1;
3478 } __packed;
3479
3480 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3481 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3482 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3483 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3484 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3485 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3486
3487 struct rtw89_fw_mrc_upd_duration_arg {
3488 u8 sch_idx;
3489 u64 start_tsf;
3490
3491 unsigned int slot_num;
3492 struct {
3493 u8 slot_idx;
3494 u16 duration; /* unit: TU */
3495 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3496 };
3497
3498 struct rtw89_h2c_mrc_upd_duration {
3499 __le32 w0;
3500 __le32 start_tsf_low;
3501 __le32 start_tsf_high;
3502 __le32 slots[];
3503 } __packed;
3504
3505 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3506 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3507 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3508 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3509 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3510
3511 struct rtw89_h2c_wow_aoac {
3512 __le32 w0;
3513 } __packed;
3514
3515 struct rtw89_h2c_ap_info {
3516 __le32 w0;
3517 } __packed;
3518
3519 #define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0)
3520
3521 #define RTW89_C2H_HEADER_LEN 8
3522
3523 struct rtw89_c2h_hdr {
3524 __le32 w0;
3525 __le32 w1;
3526 } __packed;
3527
3528 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3529 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3530 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3531 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3532
3533 struct rtw89_fw_c2h_attr {
3534 u8 category;
3535 u8 class;
3536 u8 func;
3537 u16 len;
3538 };
3539
RTW89_SKB_C2H_CB(struct sk_buff * skb)3540 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3541 {
3542 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3543
3544 return (struct rtw89_fw_c2h_attr *)skb->cb;
3545 }
3546
3547 struct rtw89_c2h_done_ack {
3548 __le32 w0;
3549 __le32 w1;
3550 __le32 w2;
3551 } __packed;
3552
3553 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3554 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3555 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3556 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3557 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3558
3559 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3560 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3561 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3562 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3563 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3564 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3565 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3566 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3567
3568 struct rtw89_fw_c2h_log_fmt {
3569 __le16 signature;
3570 u8 feature;
3571 u8 syntax;
3572 __le32 fmt_id;
3573 u8 file_num;
3574 __le16 line_num;
3575 u8 argc;
3576 union {
3577 DECLARE_FLEX_ARRAY(u8, raw);
3578 DECLARE_FLEX_ARRAY(__le32, argv);
3579 } __packed u;
3580 } __packed;
3581
3582 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3583 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3584 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3585 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3586 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3587
3588 struct rtw89_c2h_mac_bcnfltr_rpt {
3589 __le32 w0;
3590 __le32 w1;
3591 __le32 w2;
3592 } __packed;
3593
3594 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3595 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3596 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3597 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3598
3599 struct rtw89_c2h_ra_rpt {
3600 struct rtw89_c2h_hdr hdr;
3601 __le32 w2;
3602 __le32 w3;
3603 } __packed;
3604
3605 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3606 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3607 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3608 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3609 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3610 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3611 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3612 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3613 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3614
3615 /* For WiFi 6 chips:
3616 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3617 * HT-new: [6:5]: NA, [4:0]: MCS
3618 * For WiFi 7 chips (V1):
3619 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3620 */
3621 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3622 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3623 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3624 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3625 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3626 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3627 FIELD_PREP(GENMASK(2, 0), mcs))
3628
3629 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3630 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3631 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3632 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3633 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3634 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3635
3636 struct rtw89_c2h_scanofld {
3637 __le32 w0;
3638 __le32 w1;
3639 __le32 w2;
3640 __le32 w3;
3641 __le32 w4;
3642 __le32 w5;
3643 __le32 w6;
3644 __le32 w7;
3645 __le32 w8;
3646 } __packed;
3647
3648 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3649 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3650 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3651 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3652 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3653 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3654 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3655 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3656 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3657 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3658 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3659 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3660 #define RTW89_C2H_SCANOFLD_W8_PERIOD_V1 GENMASK(15, 0)
3661 #define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16)
3662
3663 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3664 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3665 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3666 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3667
3668 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3669 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3670 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3671 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3672 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3673 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3674
3675 struct rtw89_mac_mcc_tsf_rpt {
3676 u32 macid_x;
3677 u32 macid_y;
3678 u32 tsf_x_low;
3679 u32 tsf_x_high;
3680 u32 tsf_y_low;
3681 u32 tsf_y_high;
3682 };
3683
3684 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3685
3686 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3687 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3688 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3689 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3690 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3691 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3692 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3693 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3694 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3695 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3696 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3697 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3698 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3699 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3700
3701 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3702 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3703 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3704 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3705 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3706 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3707 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3708 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3709 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3710 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3711
3712 struct rtw89_mac_mrc_tsf_rpt {
3713 unsigned int num;
3714 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3715 };
3716
3717 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3718
3719 struct rtw89_c2h_mrc_tsf_rpt_info {
3720 __le32 tsf_low;
3721 __le32 tsf_high;
3722 } __packed;
3723
3724 struct rtw89_c2h_mrc_tsf_rpt {
3725 struct rtw89_c2h_hdr hdr;
3726 __le32 w2;
3727 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
3728 } __packed;
3729
3730 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3731
3732 struct rtw89_c2h_mrc_status_rpt {
3733 struct rtw89_c2h_hdr hdr;
3734 __le32 w2;
3735 __le32 tsf_low;
3736 __le32 tsf_high;
3737 } __packed;
3738
3739 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
3740 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3741
3742 struct rtw89_c2h_pkt_ofld_rsp {
3743 __le32 w0;
3744 __le32 w1;
3745 __le32 w2;
3746 } __packed;
3747
3748 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3749 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3750 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3751
3752 struct rtw89_c2h_tx_duty_rpt {
3753 struct rtw89_c2h_hdr c2h_hdr;
3754 __le32 w2;
3755 } __packed;
3756
3757 #define RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR GENMASK(2, 0)
3758
3759 struct rtw89_c2h_wow_aoac_report {
3760 struct rtw89_c2h_hdr c2h_hdr;
3761 u8 rpt_ver;
3762 u8 sec_type;
3763 u8 key_idx;
3764 u8 pattern_idx;
3765 u8 rekey_ok;
3766 u8 rsvd1[3];
3767 u8 ptk_tx_iv[8];
3768 u8 eapol_key_replay_count[8];
3769 u8 gtk[32];
3770 u8 ptk_rx_iv[8];
3771 u8 gtk_rx_iv[4][8];
3772 __le64 igtk_key_id;
3773 __le64 igtk_ipn;
3774 u8 igtk[32];
3775 u8 csa_pri_ch;
3776 u8 csa_bw_ch_offset;
3777 u8 csa_ch_band_chsw_failed;
3778 u8 csa_rsvd1;
3779 } __packed;
3780
3781 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3782
3783 struct rtw89_c2h_pwr_int_notify {
3784 struct rtw89_c2h_hdr hdr;
3785 __le32 w2;
3786 } __packed;
3787
3788 #define RTW89_C2H_PWR_INT_NOTIFY_W2_MACID GENMASK(15, 0)
3789 #define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16)
3790
3791 struct rtw89_h2c_tx_duty {
3792 __le32 w0;
3793 __le32 w1;
3794 } __packed;
3795
3796 #define RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK GENMASK(15, 0)
3797 #define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)
3798 #define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
3799
3800 struct rtw89_h2c_bcnfltr {
3801 __le32 w0;
3802 } __packed;
3803
3804 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3805 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3806 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3807 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3808 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3809 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3810 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3811 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3812
3813 struct rtw89_h2c_ofld_rssi {
3814 __le32 w0;
3815 __le32 w1;
3816 } __packed;
3817
3818 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3819 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3820 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3821
3822 struct rtw89_h2c_ofld {
3823 __le32 w0;
3824 } __packed;
3825
3826 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3827 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3828 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3829
3830 #define RTW89_MFW_SIG 0xFF
3831
3832 struct rtw89_mfw_info {
3833 u8 cv;
3834 u8 type; /* enum rtw89_fw_type */
3835 u8 mp;
3836 u8 rsvd;
3837 __le32 shift;
3838 __le32 size;
3839 u8 rsvd2[4];
3840 } __packed;
3841
3842 struct rtw89_mfw_hdr {
3843 u8 sig; /* RTW89_MFW_SIG */
3844 u8 fw_nr;
3845 u8 rsvd0[2];
3846 struct {
3847 u8 major;
3848 u8 minor;
3849 u8 sub;
3850 u8 idx;
3851 } ver;
3852 u8 rsvd1[8];
3853 struct rtw89_mfw_info info[];
3854 } __packed;
3855
3856 struct rtw89_fw_logsuit_hdr {
3857 __le32 rsvd;
3858 __le32 count;
3859 __le32 ids[];
3860 } __packed;
3861
3862 #define RTW89_FW_ELEMENT_ALIGN 16
3863
3864 enum rtw89_fw_element_id {
3865 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3866 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3867 RTW89_FW_ELEMENT_ID_BB_REG = 2,
3868 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3869 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3870 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3871 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3872 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3873 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3874 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
3875 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
3876 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
3877 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3878 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
3879 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
3880 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
3881 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3882 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
3883 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
3884 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
3885
3886 RTW89_FW_ELEMENT_ID_NUM,
3887 };
3888
3889 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \
3890 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3891 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3892 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3893 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3894 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3895 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3896 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3897
3898 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
3899 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \
3900 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3901 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
3902
3903 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \
3904 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3905 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3906 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3907 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3908 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3909 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
3910
3911 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3912 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3913 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3914 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3915 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3916 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3917 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
3918
3919 struct __rtw89_fw_txpwr_element {
3920 u8 rsvd0;
3921 u8 rsvd1;
3922 u8 rfe_type;
3923 u8 ent_sz;
3924 __le32 num_ents;
3925 u8 content[];
3926 } __packed;
3927
3928 enum rtw89_fw_txpwr_trk_type {
3929 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
3930 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
3931 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
3932 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
3933 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
3934 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
3935
3936 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
3937 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
3938 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
3939 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
3940 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
3941 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
3942
3943 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
3944 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
3945 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
3946 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
3947 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
3948 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
3949 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
3950 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
3951 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
3952 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
3953
3954 RTW89_FW_TXPWR_TRK_TYPE_NR,
3955 };
3956
3957 struct rtw89_fw_txpwr_track_cfg {
3958 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
3959 };
3960
3961 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
3962 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
3963 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
3964 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
3965 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
3966 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
3967 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
3968 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
3969 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
3970 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
3971 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
3972 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
3973 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
3974 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
3975 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
3976 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
3977 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
3978 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
3979 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
3980
3981 struct rtw89_fw_element_hdr {
3982 __le32 id; /* enum rtw89_fw_element_id */
3983 __le32 size; /* exclude header size */
3984 u8 ver[4];
3985 __le32 rsvd0;
3986 __le32 rsvd1;
3987 __le32 rsvd2;
3988 union {
3989 struct {
3990 u8 priv[8];
3991 u8 contents[];
3992 } __packed common;
3993 struct {
3994 u8 idx;
3995 u8 rsvd[7];
3996 struct {
3997 __le32 addr;
3998 __le32 data;
3999 } __packed regs[];
4000 } __packed reg2;
4001 struct {
4002 u8 cv;
4003 u8 priv[7];
4004 u8 contents[];
4005 } __packed bbmcu;
4006 struct {
4007 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
4008 __le32 rsvd;
4009 s8 contents[][DELTA_SWINGIDX_SIZE];
4010 } __packed txpwr_trk;
4011 struct {
4012 u8 nr;
4013 u8 rsvd[3];
4014 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
4015 u8 rsvd1[3];
4016 __le16 offset[];
4017 } __packed rfk_log_fmt;
4018 struct __rtw89_fw_txpwr_element txpwr;
4019 } __packed u;
4020 } __packed;
4021
4022 struct fwcmd_hdr {
4023 __le32 hdr0;
4024 __le32 hdr1;
4025 };
4026
4027 union rtw89_compat_fw_hdr {
4028 struct rtw89_mfw_hdr mfw_hdr;
4029 struct rtw89_fw_hdr fw_hdr;
4030 };
4031
rtw89_compat_fw_hdr_ver_code(const void * fw_buf)4032 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
4033 {
4034 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
4035
4036 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
4037 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
4038 else
4039 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
4040 }
4041
rtw89_fw_get_filename(char * buf,size_t size,const char * fw_basename,int fw_format)4042 static inline void rtw89_fw_get_filename(char *buf, size_t size,
4043 const char *fw_basename, int fw_format)
4044 {
4045 if (fw_format <= 0)
4046 snprintf(buf, size, "%s.bin", fw_basename);
4047 else
4048 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
4049 }
4050
4051 #define RTW89_H2C_RF_PAGE_SIZE 500
4052 #define RTW89_H2C_RF_PAGE_NUM 3
4053 struct rtw89_fw_h2c_rf_reg_info {
4054 enum rtw89_rf_path rf_path;
4055 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
4056 u16 curr_idx;
4057 };
4058
4059 #define H2C_SEC_CAM_LEN 24
4060
4061 #define H2C_HEADER_LEN 8
4062 #define H2C_HDR_CAT GENMASK(1, 0)
4063 #define H2C_HDR_CLASS GENMASK(7, 2)
4064 #define H2C_HDR_FUNC GENMASK(15, 8)
4065 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
4066 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4067 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
4068 #define H2C_HDR_REC_ACK BIT(14)
4069 #define H2C_HDR_DONE_ACK BIT(15)
4070
4071 #define FWCMD_TYPE_H2C 0
4072
4073 #define H2C_CAT_TEST 0x0
4074
4075 /* CLASS 5 - FW STATUS TEST */
4076 #define H2C_CL_FW_STATUS_TEST 0x5
4077 #define H2C_FUNC_CPU_EXCEPTION 0x1
4078
4079 #define H2C_CAT_MAC 0x1
4080
4081 /* CLASS 0 - FW INFO */
4082 #define H2C_CL_FW_INFO 0x0
4083 #define H2C_FUNC_LOG_CFG 0x0
4084 #define H2C_FUNC_MAC_GENERAL_PKT 0x1
4085
4086 /* CLASS 1 - WOW */
4087 #define H2C_CL_MAC_WOW 0x1
4088 enum rtw89_wow_h2c_func {
4089 H2C_FUNC_KEEP_ALIVE = 0x0,
4090 H2C_FUNC_DISCONNECT_DETECT = 0x1,
4091 H2C_FUNC_WOW_GLOBAL = 0x2,
4092 H2C_FUNC_GTK_OFLD = 0x3,
4093 H2C_FUNC_ARP_OFLD = 0x4,
4094 H2C_FUNC_NLO = 0x7,
4095 H2C_FUNC_WAKEUP_CTRL = 0x8,
4096 H2C_FUNC_WOW_CAM_UPD = 0xC,
4097 H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4098
4099 NUM_OF_RTW89_WOW_H2C_FUNC,
4100 };
4101
4102 #define RTW89_WOW_WAIT_COND(tag, func) \
4103 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func))
4104
4105 #define RTW89_WOW_WAIT_COND_AOAC \
4106 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ)
4107
4108 /* CLASS 2 - PS */
4109 #define H2C_CL_MAC_PS 0x2
4110 enum rtw89_ps_h2c_func {
4111 H2C_FUNC_MAC_LPS_PARM = 0x0,
4112 H2C_FUNC_P2P_ACT = 0x1,
4113 H2C_FUNC_IPS_CFG = 0x3,
4114
4115 NUM_OF_RTW89_PS_H2C_FUNC,
4116 };
4117
4118 #define RTW89_PS_WAIT_COND(tag, func) \
4119 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func))
4120
4121 #define RTW89_PS_WAIT_COND_IPS_CFG \
4122 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG)
4123
4124 /* CLASS 3 - FW download */
4125 #define H2C_CL_MAC_FWDL 0x3
4126 #define H2C_FUNC_MAC_FWHDR_DL 0x0
4127
4128 /* CLASS 5 - Frame Exchange */
4129 #define H2C_CL_MAC_FR_EXCHG 0x5
4130 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4131 #define H2C_FUNC_MAC_BCN_UPD 0x5
4132 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4133 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4134 #define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4135 #define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4136 #define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4137
4138 /* CLASS 6 - Address CAM */
4139 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4140 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4141
4142 /* CLASS 8 - Media Status Report */
4143 #define H2C_CL_MAC_MEDIA_RPT 0x8
4144 #define H2C_FUNC_MAC_JOININFO 0x0
4145 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4146 #define H2C_FUNC_NOTIFY_DBCC 0x5
4147
4148 /* CLASS 9 - FW offload */
4149 #define H2C_CL_MAC_FW_OFLD 0x9
4150 enum rtw89_fw_ofld_h2c_func {
4151 H2C_FUNC_PACKET_OFLD = 0x1,
4152 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4153 H2C_FUNC_USR_EDCA = 0xF,
4154 H2C_FUNC_TSF32_TOGL = 0x10,
4155 H2C_FUNC_OFLD_CFG = 0x14,
4156 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4157 H2C_FUNC_SCANOFLD = 0x17,
4158 H2C_FUNC_TX_DUTY = 0x18,
4159 H2C_FUNC_PKT_DROP = 0x1b,
4160 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4161 H2C_FUNC_OFLD_RSSI = 0x1f,
4162 H2C_FUNC_OFLD_TP = 0x20,
4163 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4164 H2C_FUNC_SCANOFLD_BE = 0x2c,
4165
4166 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4167 };
4168
4169 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4170 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4171
4172 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4173 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4174 H2C_FUNC_PACKET_OFLD)
4175
4176 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4177
4178 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4179 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4180 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4181 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4182
4183
4184 /* CLASS 10 - Security CAM */
4185 #define H2C_CL_MAC_SEC_CAM 0xa
4186 #define H2C_FUNC_MAC_SEC_UPD 0x1
4187
4188 /* CLASS 12 - BA CAM */
4189 #define H2C_CL_BA_CAM 0xc
4190 #define H2C_FUNC_MAC_BA_CAM 0x0
4191 #define H2C_FUNC_MAC_BA_CAM_V1 0x1
4192 #define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4193
4194 /* CLASS 14 - MCC */
4195 #define H2C_CL_MCC 0xe
4196 enum rtw89_mcc_h2c_func {
4197 H2C_FUNC_ADD_MCC = 0x0,
4198 H2C_FUNC_START_MCC = 0x1,
4199 H2C_FUNC_STOP_MCC = 0x2,
4200 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4201 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4202 H2C_FUNC_MCC_REQ_TSF = 0x5,
4203 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4204 H2C_FUNC_MCC_SYNC = 0x7,
4205 H2C_FUNC_MCC_SET_DURATION = 0x8,
4206
4207 NUM_OF_RTW89_MCC_H2C_FUNC,
4208 };
4209
4210 #define RTW89_MCC_WAIT_COND(group, func) \
4211 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4212
4213 /* CLASS 24 - MRC */
4214 #define H2C_CL_MRC 0x18
4215 enum rtw89_mrc_h2c_func {
4216 H2C_FUNC_MRC_REQ_TSF = 0x0,
4217 H2C_FUNC_ADD_MRC = 0x1,
4218 H2C_FUNC_START_MRC = 0x2,
4219 H2C_FUNC_DEL_MRC = 0x3,
4220 H2C_FUNC_MRC_SYNC = 0x4,
4221 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4222 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4223
4224 NUM_OF_RTW89_MRC_H2C_FUNC,
4225 };
4226
4227 /* can consider MRC's sch_idx as MCC's group */
4228 #define RTW89_MRC_WAIT_COND(sch_idx, func) \
4229 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4230
4231 #define RTW89_MRC_WAIT_COND_REQ_TSF \
4232 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4233
4234 /* CLASS 36 - AP */
4235 #define H2C_CL_AP 0x24
4236 #define H2C_FUNC_AP_INFO 0x0
4237
4238 #define H2C_CAT_OUTSRC 0x2
4239
4240 #define H2C_CL_OUTSRC_RA 0x1
4241 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4242
4243 #define H2C_CL_OUTSRC_DM 0x2
4244 #define H2C_FUNC_FW_LPS_CH_INFO 0xb
4245 #define H2C_FUNC_FW_LPS_ML_CMN_INFO 0xe
4246
4247 #define H2C_CL_OUTSRC_RF_REG_A 0x8
4248 #define H2C_CL_OUTSRC_RF_REG_B 0x9
4249 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4250 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4251 #define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4252
4253 enum rtw89_rfk_offload_h2c_func {
4254 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4255 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4256 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4257 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4258 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4259 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4260 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4261 };
4262
4263 struct rtw89_fw_h2c_rf_get_mccch {
4264 __le32 ch_0;
4265 __le32 ch_1;
4266 __le32 band_0;
4267 __le32 band_1;
4268 __le32 current_channel;
4269 __le32 current_band_type;
4270 } __packed;
4271
4272 #define NUM_OF_RTW89_FW_RFK_PATH 2
4273 #define NUM_OF_RTW89_FW_RFK_TBL 3
4274
4275 struct rtw89_fw_h2c_rfk_pre_info_common {
4276 struct {
4277 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4278 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4279 } __packed dbcc;
4280
4281 __le32 mlo_mode;
4282 struct {
4283 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4284 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4285 } __packed tbl;
4286
4287 __le32 phy_idx;
4288 } __packed;
4289
4290 struct rtw89_fw_h2c_rfk_pre_info_v0 {
4291 struct rtw89_fw_h2c_rfk_pre_info_common common;
4292
4293 __le32 cur_band;
4294 __le32 cur_bw;
4295 __le32 cur_center_ch;
4296
4297 __le32 ktbl_sel0;
4298 __le32 ktbl_sel1;
4299 __le32 rfmod0;
4300 __le32 rfmod1;
4301
4302 __le32 mlo_1_1;
4303 __le32 rfe_type;
4304 __le32 drv_mode;
4305
4306 struct {
4307 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4308 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4309 } __packed mlo;
4310 } __packed;
4311
4312 struct rtw89_fw_h2c_rfk_pre_info_v1 {
4313 struct rtw89_fw_h2c_rfk_pre_info_common common;
4314 __le32 mlo_1_1;
4315 } __packed;
4316
4317 struct rtw89_fw_h2c_rfk_pre_info {
4318 struct rtw89_fw_h2c_rfk_pre_info_v1 base_v1;
4319 __le32 cur_bandwidth[NUM_OF_RTW89_FW_RFK_PATH];
4320 } __packed;
4321
4322 struct rtw89_h2c_rf_tssi {
4323 __le16 len;
4324 u8 phy;
4325 u8 ch;
4326 u8 bw;
4327 u8 band;
4328 u8 hwtx_en;
4329 u8 cv;
4330 s8 curr_tssi_cck_de[2];
4331 s8 curr_tssi_cck_de_20m[2];
4332 s8 curr_tssi_cck_de_40m[2];
4333 s8 curr_tssi_efuse_cck_de[2];
4334 s8 curr_tssi_ofdm_de[2];
4335 s8 curr_tssi_ofdm_de_20m[2];
4336 s8 curr_tssi_ofdm_de_40m[2];
4337 s8 curr_tssi_ofdm_de_80m[2];
4338 s8 curr_tssi_ofdm_de_160m[2];
4339 s8 curr_tssi_ofdm_de_320m[2];
4340 s8 curr_tssi_efuse_ofdm_de[2];
4341 s8 curr_tssi_ofdm_de_diff_20m[2];
4342 s8 curr_tssi_ofdm_de_diff_80m[2];
4343 s8 curr_tssi_ofdm_de_diff_160m[2];
4344 s8 curr_tssi_ofdm_de_diff_320m[2];
4345 s8 curr_tssi_trim_de[2];
4346 u8 pg_thermal[2];
4347 u8 ftable[2][128];
4348 u8 tssi_mode;
4349 } __packed;
4350
4351 struct rtw89_h2c_rf_iqk {
4352 __le32 phy_idx;
4353 __le32 dbcc;
4354 } __packed;
4355
4356 struct rtw89_h2c_rf_dpk {
4357 u8 len;
4358 u8 phy;
4359 u8 dpk_enable;
4360 u8 kpath;
4361 u8 cur_band;
4362 u8 cur_bw;
4363 u8 cur_ch;
4364 u8 dpk_dbg_en;
4365 } __packed;
4366
4367 struct rtw89_h2c_rf_txgapk {
4368 u8 len;
4369 u8 ktype;
4370 u8 phy;
4371 u8 kpath;
4372 u8 band;
4373 u8 bw;
4374 u8 ch;
4375 u8 cv;
4376 } __packed;
4377
4378 struct rtw89_h2c_rf_dack {
4379 __le32 len;
4380 __le32 phy;
4381 __le32 type;
4382 } __packed;
4383
4384 struct rtw89_h2c_rf_rxdck_v0 {
4385 u8 len;
4386 u8 phy;
4387 u8 is_afe;
4388 u8 kpath;
4389 u8 cur_band;
4390 u8 cur_bw;
4391 u8 cur_ch;
4392 u8 rxdck_dbg_en;
4393 } __packed;
4394
4395 struct rtw89_h2c_rf_rxdck {
4396 struct rtw89_h2c_rf_rxdck_v0 v0;
4397 u8 is_chl_k;
4398 } __packed;
4399
4400 enum rtw89_rf_log_type {
4401 RTW89_RF_RUN_LOG = 0,
4402 RTW89_RF_RPT_LOG = 1,
4403 };
4404
4405 struct rtw89_c2h_rf_log_hdr {
4406 u8 type; /* enum rtw89_rf_log_type */
4407 __le16 len;
4408 u8 content[];
4409 } __packed;
4410
4411 struct rtw89_c2h_rf_run_log {
4412 __le32 fmt_idx;
4413 __le32 arg[4];
4414 } __packed;
4415
4416 struct rtw89_c2h_rf_iqk_rpt_log {
4417 bool iqk_tx_fail[2];
4418 bool iqk_rx_fail[2];
4419 bool is_iqk_init;
4420 bool is_reload;
4421 bool is_wb_txiqk[2];
4422 bool is_wb_rxiqk[2];
4423 bool is_nbiqk;
4424 bool txiqk_en;
4425 bool rxiqk_en;
4426 bool lok_en;
4427 bool iqk_xym_en;
4428 bool iqk_sram_en;
4429 bool iqk_fft_en;
4430 bool is_fw_iqk;
4431 bool is_iqk_enable;
4432 bool iqk_cfir_en;
4433 bool thermal_rek_en;
4434 u8 iqk_band[2];
4435 u8 iqk_ch[2];
4436 u8 iqk_bw[2];
4437 u8 iqk_times;
4438 u8 version;
4439 u8 phy;
4440 u8 fwk_status;
4441 u8 rsvd;
4442 __le32 reload_cnt;
4443 __le32 iqk_fail_cnt;
4444 __le32 lok_idac[2];
4445 __le32 lok_vbuf[2];
4446 __le32 rftxgain[2][4];
4447 __le32 rfrxgain[2][4];
4448 __le32 tx_xym[2][4];
4449 __le32 rx_xym[2][4];
4450 } __packed;
4451
4452 struct rtw89_c2h_rf_dpk_rpt_log {
4453 u8 ver;
4454 u8 idx[2];
4455 u8 band[2];
4456 u8 bw[2];
4457 u8 ch[2];
4458 u8 path_ok[2];
4459 u8 txagc[2];
4460 u8 ther[2];
4461 u8 gs[2];
4462 u8 dc_i[4];
4463 u8 dc_q[4];
4464 u8 corr_val[2];
4465 u8 corr_idx[2];
4466 u8 is_timeout[2];
4467 u8 rxbb_ov[2];
4468 u8 rsvd;
4469 } __packed;
4470
4471 struct rtw89_c2h_rf_dack_rpt_log {
4472 u8 fwdack_ver;
4473 u8 fwdack_info_ver;
4474 u8 msbk_d[2][2][16];
4475 u8 dadck_d[2][2];
4476 u8 cdack_d[2][2][2];
4477 u8 addck2_hd[2][2][2];
4478 u8 addck2_ld[2][2][2];
4479 u8 adgaink_d[2][2];
4480 u8 biask_hd[2][2];
4481 u8 biask_ld[2][2];
4482 u8 addck_timeout;
4483 u8 cdack_timeout;
4484 u8 dadck_timeout;
4485 u8 msbk_timeout;
4486 u8 adgaink_timeout;
4487 u8 wbadcdck_timeout;
4488 u8 drck_timeout;
4489 u8 dack_fail;
4490 u8 wbdck_d[2];
4491 u8 rck_d;
4492 } __packed;
4493
4494 struct rtw89_c2h_rf_rxdck_rpt_log {
4495 u8 ver;
4496 u8 band[2];
4497 u8 bw[2];
4498 u8 ch[2];
4499 u8 timeout[2];
4500 } __packed;
4501
4502 struct rtw89_c2h_rf_tssi_rpt_log {
4503 s8 alignment_power[2][2][4];
4504 u8 alignment_power_cw_h[2][2][4];
4505 u8 alignment_power_cw_l[2][2][4];
4506 u8 tssi_alimk_state[2][2];
4507 u8 default_txagc_offset[2][2];
4508 } __packed;
4509
4510 struct rtw89_c2h_rf_txgapk_rpt_log {
4511 __le32 r0x8010[2];
4512 __le32 chk_cnt;
4513 u8 track_d[2][17];
4514 u8 power_d[2][17];
4515 u8 is_txgapk_ok;
4516 u8 chk_id;
4517 u8 ver;
4518 u8 rsv1;
4519 } __packed;
4520
4521 struct rtw89_c2h_rfk_report {
4522 struct rtw89_c2h_hdr hdr;
4523 u8 state; /* enum rtw89_rfk_report_state */
4524 u8 version;
4525 } __packed;
4526
4527 #define RTW89_FW_RSVD_PLE_SIZE 0x800
4528
4529 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
4530 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
4531 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
4532
4533 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4534 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
4535
4536 #define FWDL_WAIT_CNT 400000
4537
4538 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
4539 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
4540 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
4541 const struct firmware *
4542 rtw89_early_fw_feature_recognize(struct device *device,
4543 const struct rtw89_chip_info *chip,
4544 struct rtw89_fw_info *early_fw,
4545 int *used_fw_format);
4546 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
4547 bool include_bb);
4548 void rtw89_load_firmware_work(struct work_struct *work);
4549 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
4550 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
4551 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
4552 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
4553 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4554 u8 type, u8 cat, u8 class, u8 func,
4555 bool rack, bool dack, u32 len);
4556 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4557 struct rtw89_vif_link *rtwvif_link,
4558 struct rtw89_sta_link *rtwsta_link);
4559 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4560 struct rtw89_vif_link *rtwvif_link,
4561 struct rtw89_sta_link *rtwsta_link);
4562 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4563 struct rtw89_vif_link *rtwvif_link,
4564 struct rtw89_sta_link *rtwsta_link);
4565 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4566 struct rtw89_vif_link *rtwvif_link,
4567 struct rtw89_sta_link *rtwsta_link);
4568 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4569 struct rtw89_vif_link *rtwvif_link,
4570 struct rtw89_sta_link *rtwsta_link);
4571 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4572 struct rtw89_vif_link *rtwvif_link,
4573 struct rtw89_sta_link *rtwsta_link);
4574 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4575 struct rtw89_sta_link *rtwsta_link);
4576 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4577 struct rtw89_sta_link *rtwsta_link);
4578 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
4579 struct rtw89_vif_link *rtwvif_link);
4580 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
4581 struct rtw89_vif_link *rtwvif_link);
4582 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif,
4583 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr);
4584 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4585 struct rtw89_vif_link *rtwvif_link,
4586 struct rtw89_sta_link *rtwsta_link);
4587 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4588 struct rtw89_vif_link *rtwvif_link,
4589 struct rtw89_sta_link *rtwsta_link);
4590 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
4591 void rtw89_fw_c2h_work(struct work_struct *work);
4592 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
4593 struct rtw89_vif_link *rtwvif_link,
4594 struct rtw89_sta_link *rtwsta_link,
4595 enum rtw89_upd_mode upd_mode);
4596 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4597 struct rtw89_sta_link *rtwsta_link, bool dis_conn);
4598 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
4599 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
4600 bool pause);
4601 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4602 u8 ac, u32 val);
4603 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
4604 int rtw89_fw_h2c_tx_duty(struct rtw89_dev *rtwdev, u8 lv);
4605 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
4606 struct rtw89_vif_link *rtwvif_link,
4607 bool connect);
4608 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
4609 struct rtw89_rx_phy_ppdu *phy_ppdu);
4610 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
4611 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
4612 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
4613 int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
4614 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
4615 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
4616 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
4617 int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type);
4618 int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
4619 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
4620 int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
4621 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
4622 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
4623 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
4624 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
4625 struct sk_buff *skb_ofld);
4626 int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev,
4627 struct rtw89_scan_option *opt,
4628 struct rtw89_vif_link *vif,
4629 bool wowlan);
4630 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
4631 struct rtw89_scan_option *opt,
4632 struct rtw89_vif_link *vif,
4633 bool wowlan);
4634 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
4635 struct rtw89_fw_h2c_rf_reg_info *info,
4636 u16 len, u8 page);
4637 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
4638 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
4639 enum rtw89_phy_idx phy_idx);
4640 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4641 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode);
4642 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4643 const struct rtw89_chan *chan);
4644 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4645 const struct rtw89_chan *chan);
4646 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4647 const struct rtw89_chan *chan);
4648 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4649 const struct rtw89_chan *chan);
4650 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4651 const struct rtw89_chan *chan, bool is_chl_k);
4652 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
4653 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
4654 bool rack, bool dack);
4655 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
4656 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
4657 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4658 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4659 u8 macid);
4660 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
4661 struct rtw89_vif_link *rtwvif_link,
4662 bool notify_fw);
4663 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
4664 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev,
4665 struct rtw89_vif_link *rtwvif_link,
4666 struct rtw89_sta_link *rtwsta_link,
4667 bool valid, struct ieee80211_ampdu_params *params);
4668 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev,
4669 struct rtw89_vif_link *rtwvif_link,
4670 struct rtw89_sta_link *rtwsta_link,
4671 bool valid, struct ieee80211_ampdu_params *params);
4672 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
4673 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
4674 u8 offset, u8 mac_idx);
4675
4676 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
4677 struct rtw89_lps_parm *lps_param);
4678 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
4679 int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev,
4680 struct rtw89_vif *rtwvif);
4681 int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4682 bool enable);
4683 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
4684 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
4685 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
4686 struct rtw89_mac_h2c_info *h2c_info,
4687 struct rtw89_mac_c2h_info *c2h_info);
4688 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
4689 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
4690 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
4691 struct rtw89_vif_link *rtwvif_link,
4692 struct ieee80211_scan_request *scan_req);
4693 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev,
4694 struct rtw89_vif_link *rtwvif_link,
4695 bool aborted);
4696 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev,
4697 struct rtw89_vif_link *rtwvif_link,
4698 bool enable);
4699 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev,
4700 struct rtw89_vif_link *rtwvif_link);
4701 int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4702 struct rtw89_vif_link *rtwvif_link, bool connected);
4703 int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4704 struct rtw89_vif_link *rtwvif_link);
4705 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4706 struct rtw89_vif_link *rtwvif_link, bool connected);
4707 int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4708 struct rtw89_vif_link *rtwvif_link);
4709 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
4710 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
4711 const struct rtw89_pkt_drop_params *params);
4712 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev,
4713 struct rtw89_vif_link *rtwvif_link,
4714 struct ieee80211_bss_conf *bss_conf,
4715 struct ieee80211_p2p_noa_desc *desc,
4716 u8 act, u8 noa_id);
4717 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev,
4718 struct rtw89_vif_link *rtwvif_link,
4719 bool en);
4720 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4721 bool enable);
4722 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4723 struct rtw89_vif_link *rtwvif_link, bool enable);
4724 int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4725 bool enable);
4726 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4727 bool enable);
4728 int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
4729 struct rtw89_vif_link *rtwvif_link, bool enable);
4730 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
4731 struct rtw89_vif_link *rtwvif_link, bool enable);
4732 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4733 bool enable);
4734 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4735 struct rtw89_vif_link *rtwvif_link, bool enable);
4736 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
4737 struct rtw89_wow_cam_info *cam_info);
4738 int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
4739 struct rtw89_vif_link *rtwvif_link,
4740 bool enable);
4741 int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
4742 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
4743 const struct rtw89_fw_mcc_add_req *p);
4744 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
4745 const struct rtw89_fw_mcc_start_req *p);
4746 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4747 bool prev_groups);
4748 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
4749 bool prev_groups);
4750 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
4751 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
4752 const struct rtw89_fw_mcc_tsf_req *req,
4753 struct rtw89_mac_mcc_tsf_rpt *rpt);
4754 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4755 u8 *bitmap);
4756 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
4757 u8 target, u8 offset);
4758 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
4759 const struct rtw89_fw_mcc_duration *p);
4760 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
4761 const struct rtw89_fw_mrc_add_arg *arg);
4762 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
4763 const struct rtw89_fw_mrc_start_arg *arg);
4764 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx);
4765 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
4766 const struct rtw89_fw_mrc_req_tsf_arg *arg,
4767 struct rtw89_mac_mrc_tsf_rpt *rpt);
4768 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
4769 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
4770 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
4771 const struct rtw89_fw_mrc_sync_arg *arg);
4772 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
4773 const struct rtw89_fw_mrc_upd_duration_arg *arg);
4774 int rtw89_fw_h2c_ap_info_refcount(struct rtw89_dev *rtwdev, bool en);
4775
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)4776 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
4777 {
4778 const struct rtw89_chip_info *chip = rtwdev->chip;
4779
4780 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
4781 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
4782 }
4783
rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4784 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4785 struct rtw89_vif_link *rtwvif_link,
4786 struct rtw89_sta_link *rtwsta_link)
4787 {
4788 const struct rtw89_chip_info *chip = rtwdev->chip;
4789
4790 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4791 }
4792
rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4793 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
4794 struct rtw89_vif_link *rtwvif_link,
4795 struct rtw89_sta_link *rtwsta_link)
4796 {
4797 const struct rtw89_chip_info *chip = rtwdev->chip;
4798
4799 if (chip->ops->h2c_default_dmac_tbl)
4800 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4801
4802 return 0;
4803 }
4804
rtw89_chip_h2c_update_beacon(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4805 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
4806 struct rtw89_vif_link *rtwvif_link)
4807 {
4808 const struct rtw89_chip_info *chip = rtwdev->chip;
4809
4810 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link);
4811 }
4812
rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4813 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4814 struct rtw89_vif_link *rtwvif_link,
4815 struct rtw89_sta_link *rtwsta_link)
4816 {
4817 const struct rtw89_chip_info *chip = rtwdev->chip;
4818
4819 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4820 }
4821
4822 static inline
rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4823 int rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev *rtwdev,
4824 struct rtw89_vif_link *rtwvif_link,
4825 struct rtw89_sta_link *rtwsta_link)
4826 {
4827 const struct rtw89_chip_info *chip = rtwdev->chip;
4828
4829 if (chip->ops->h2c_ampdu_cmac_tbl)
4830 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link,
4831 rtwsta_link);
4832
4833 return 0;
4834 }
4835
rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4836 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
4837 struct rtw89_vif *rtwvif,
4838 struct rtw89_sta *rtwsta)
4839 {
4840 struct rtw89_vif_link *rtwvif_link;
4841 struct rtw89_sta_link *rtwsta_link;
4842 unsigned int link_id;
4843 int ret;
4844
4845 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
4846 rtwvif_link = rtwsta_link->rtwvif_link;
4847 ret = rtw89_chip_h2c_ampdu_link_cmac_tbl(rtwdev, rtwvif_link,
4848 rtwsta_link);
4849 if (ret)
4850 return ret;
4851 }
4852
4853 return 0;
4854 }
4855
4856 static inline
rtw89_chip_h2c_ba_cam(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool valid,struct ieee80211_ampdu_params * params)4857 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4858 bool valid, struct ieee80211_ampdu_params *params)
4859 {
4860 const struct rtw89_chip_info *chip = rtwdev->chip;
4861 struct rtw89_vif_link *rtwvif_link;
4862 struct rtw89_sta_link *rtwsta_link;
4863 unsigned int link_id;
4864 int ret;
4865
4866 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
4867 rtwvif_link = rtwsta_link->rtwvif_link;
4868 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link,
4869 valid, params);
4870 if (ret)
4871 return ret;
4872 }
4873
4874 return 0;
4875 }
4876
4877 /* must consider compatibility; don't insert new in the mid */
4878 struct rtw89_fw_txpwr_byrate_entry {
4879 u8 band;
4880 u8 nss;
4881 u8 rs;
4882 u8 shf;
4883 u8 len;
4884 __le32 data;
4885 u8 bw;
4886 u8 ofdma;
4887 } __packed;
4888
4889 /* must consider compatibility; don't insert new in the mid */
4890 struct rtw89_fw_txpwr_lmt_2ghz_entry {
4891 u8 bw;
4892 u8 nt;
4893 u8 rs;
4894 u8 bf;
4895 u8 regd;
4896 u8 ch_idx;
4897 s8 v;
4898 } __packed;
4899
4900 /* must consider compatibility; don't insert new in the mid */
4901 struct rtw89_fw_txpwr_lmt_5ghz_entry {
4902 u8 bw;
4903 u8 nt;
4904 u8 rs;
4905 u8 bf;
4906 u8 regd;
4907 u8 ch_idx;
4908 s8 v;
4909 } __packed;
4910
4911 /* must consider compatibility; don't insert new in the mid */
4912 struct rtw89_fw_txpwr_lmt_6ghz_entry {
4913 u8 bw;
4914 u8 nt;
4915 u8 rs;
4916 u8 bf;
4917 u8 regd;
4918 u8 reg_6ghz_power;
4919 u8 ch_idx;
4920 s8 v;
4921 } __packed;
4922
4923 /* must consider compatibility; don't insert new in the mid */
4924 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
4925 u8 ru;
4926 u8 nt;
4927 u8 regd;
4928 u8 ch_idx;
4929 s8 v;
4930 } __packed;
4931
4932 /* must consider compatibility; don't insert new in the mid */
4933 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
4934 u8 ru;
4935 u8 nt;
4936 u8 regd;
4937 u8 ch_idx;
4938 s8 v;
4939 } __packed;
4940
4941 /* must consider compatibility; don't insert new in the mid */
4942 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
4943 u8 ru;
4944 u8 nt;
4945 u8 regd;
4946 u8 reg_6ghz_power;
4947 u8 ch_idx;
4948 s8 v;
4949 } __packed;
4950
4951 /* must consider compatibility; don't insert new in the mid */
4952 struct rtw89_fw_tx_shape_lmt_entry {
4953 u8 band;
4954 u8 tx_shape_rs;
4955 u8 regd;
4956 u8 v;
4957 } __packed;
4958
4959 /* must consider compatibility; don't insert new in the mid */
4960 struct rtw89_fw_tx_shape_lmt_ru_entry {
4961 u8 band;
4962 u8 regd;
4963 u8 v;
4964 } __packed;
4965
4966 const struct rtw89_rfe_parms *
4967 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
4968 const struct rtw89_rfe_parms *init);
4969
4970 enum rtw89_wow_wakeup_ver {
4971 RTW89_WOW_REASON_V0,
4972 RTW89_WOW_REASON_V1,
4973 RTW89_WOW_REASON_NUM,
4974 };
4975
4976 #endif
4977