1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <device/mmio.h>
5 #include <console/console.h>
6 #include <delay.h>
7 #include <soc/dsi.h>
8 #include <timer.h>
9
mtk_dsi_configure_mipi_tx(u32 data_rate,u32 lanes)10 void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
11 {
12 u32 txdiv0, txdiv1;
13 u64 pcw;
14 u32 reg;
15 int i;
16
17 reg = read32(&mipi_tx0->dsi_bg_con);
18
19 reg = (reg & (~RG_DSI_V02_SEL)) | (4 << 20);
20 reg = (reg & (~RG_DSI_V032_SEL)) | (4 << 17);
21 reg = (reg & (~RG_DSI_V04_SEL)) | (4 << 14);
22 reg = (reg & (~RG_DSI_V072_SEL)) | (4 << 11);
23 reg = (reg & (~RG_DSI_V10_SEL)) | (4 << 8);
24 reg = (reg & (~RG_DSI_V12_SEL)) | (4 << 5);
25 reg |= RG_DSI_BG_CKEN;
26 reg |= RG_DSI_BG_CORE_EN;
27 write32(&mipi_tx0->dsi_bg_con, reg);
28 udelay(30);
29
30 clrsetbits32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE,
31 8 << 4 | RG_DSI_LNT_HS_BIAS_EN);
32
33 setbits32(&mipi_tx0->dsi_con,
34 RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN);
35
36 clrsetbits32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN,
37 RG_DSI_MPPLL_SDM_PWR_ON);
38
39 clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
40
41 if (data_rate > 500 * MHz) {
42 txdiv0 = 0;
43 txdiv1 = 0;
44 } else if (data_rate >= 250 * MHz) {
45 txdiv0 = 1;
46 txdiv1 = 0;
47 } else if (data_rate >= 125 * MHz) {
48 txdiv0 = 2;
49 txdiv1 = 0;
50 } else if (data_rate >= 62 * MHz) {
51 txdiv0 = 2;
52 txdiv1 = 1;
53 } else {
54 /* MIN = 50 */
55 assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
56 txdiv0 = 2;
57 txdiv1 = 2;
58 }
59
60 clrsetbits32(&mipi_tx0->dsi_pll_con0,
61 RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 |
62 RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3);
63
64 /**
65 * PLL PCW config
66 * PCW bit 24~30 = integer part of pcw
67 * PCW bit 0~23 = fractional part of pcw
68 * pcw = data_Rate*4*txdiv/(Ref_clk*2);
69 * Post DIV =4, so need data_Rate*4
70 * Ref_clk is 26MHz
71 */
72 pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24;
73 pcw /= 13 * MHz;
74 write32(&mipi_tx0->dsi_pll_con2, pcw);
75
76 setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);
77
78 setbits32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN);
79
80 for (i = 0; i < lanes; i++)
81 setbits32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN);
82
83 setbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
84
85 udelay(40);
86
87 clrbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
88 clrbits32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
89 }
90
mtk_dsi_reset(void)91 void mtk_dsi_reset(void)
92 {
93 setbits32(&dsi0->dsi_con_ctrl, 3);
94 clrbits32(&dsi0->dsi_con_ctrl, 1);
95 }
96
mtk_dsi_override_phy_timing(struct mtk_phy_timing * timing)97 void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
98 {
99 int lpx = 5;
100 timing->lpx = lpx;
101 timing->da_hs_prepare = 6;
102 timing->da_hs_zero = 10;
103 timing->da_hs_trail = 8;
104
105 timing->ta_go = 4 * lpx;
106 timing->ta_sure = 3 * lpx / 2;
107 timing->ta_get = 5 * lpx;
108 timing->da_hs_exit = 7;
109
110 timing->da_hs_sync = 0;
111 timing->clk_hs_exit = 2 * lpx;
112
113 timing->d_phy = 12;
114 }
115
mtk_dsi_pin_drv_ctrl(void)116 void mtk_dsi_pin_drv_ctrl(void)
117 {
118 struct stopwatch sw;
119 uint32_t pwr_ack;
120
121 setbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
122
123 stopwatch_init_usecs_expire(&sw, 1000);
124
125 do {
126 if (stopwatch_expired(&sw)) {
127 printk(BIOS_ERR, "enable lvdstx_power failed!!!\n");
128 return;
129 }
130 pwr_ack = read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK;
131 } while (pwr_ack == 0);
132
133 clrbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN);
134 }
135