1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <string.h>
4 #include <assert.h>
5 #include <console/console.h>
6 #include <delay.h>
7 #include <timer.h>
8 #include <symbols.h>
9 #include <device/mmio.h>
10 #include <soc/i2c.h>
11 #include <soc/i2c_common.h>
12 #include <device/i2c_simple.h>
13
14 const struct i2c_spec_values standard_mode_spec = {
15 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
16 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
17 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
18 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
19 };
20
21 const struct i2c_spec_values fast_mode_spec = {
22 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
23 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
24 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
25 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
26 };
27
28 const struct i2c_spec_values fast_mode_plus_spec = {
29 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
30 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
31 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
32 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
33 };
34
mtk_i2c_dump_more_info(struct mt_i2c_regs * regs)35 __weak void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
36 {
37 /* do nothing */
38 }
39
mtk_i2c_config_timing(struct mt_i2c_regs * regs,struct mtk_i2c * bus_ctrl)40 __weak void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
41 {
42 /* do nothing */
43 }
44
mtk_i2c_get_spec(uint32_t speed)45 const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed)
46 {
47 if (speed <= I2C_SPEED_STANDARD)
48 return &standard_mode_spec;
49 else if (speed <= I2C_SPEED_FAST)
50 return &fast_mode_spec;
51 else
52 return &fast_mode_plus_spec;
53 }
54
i2c_hw_reset(uint8_t bus)55 static inline void i2c_hw_reset(uint8_t bus)
56 {
57 struct mt_i2c_regs *regs;
58 struct mt_i2c_dma_regs *dma_regs;
59
60 regs = mtk_i2c_bus_controller[bus].i2c_regs;
61 dma_regs = mtk_i2c_bus_controller[bus].i2c_dma_regs;
62
63 if (mtk_i2c_bus_controller[bus].mt_i2c_flag == I2C_APDMA_ASYNC) {
64 write32(&dma_regs->dma_rst, I2C_DMA_WARM_RST);
65 udelay(10);
66 write32(&dma_regs->dma_rst, I2C_DMA_CLR_FLAG);
67 udelay(10);
68 write32(&dma_regs->dma_rst,
69 I2C_DMA_HARD_RST | I2C_DMA_HANDSHAKE_RST);
70 write32(®s->softreset, I2C_SOFT_RST | I2C_HANDSHAKE_RST);
71 udelay(10);
72 write32(&dma_regs->dma_rst, I2C_DMA_CLR_FLAG);
73 write32(®s->softreset, I2C_CLR_FLAG);
74 } else {
75 write32(®s->softreset, I2C_SOFT_RST);
76 write32(&dma_regs->dma_rst, I2C_DMA_WARM_RST);
77 udelay(50);
78 write32(&dma_regs->dma_rst, I2C_DMA_HARD_RST);
79 udelay(50);
80 write32(&dma_regs->dma_rst, I2C_DMA_CLR_FLAG);
81 udelay(50);
82 }
83 }
84
mtk_i2c_dump_info(struct mt_i2c_regs * regs)85 static inline void mtk_i2c_dump_info(struct mt_i2c_regs *regs)
86 {
87 printk(BIOS_DEBUG, "I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\n"
88 "INTR_STAT %x\nCONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\n"
89 "DELAY_LEN %x\nTIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\n"
90 "HS %x\nDEBUGSTAT %x\nEXT_CONF %x\n",
91 read32(®s->slave_addr),
92 read32(®s->intr_mask),
93 read32(®s->intr_stat),
94 read32(®s->control),
95 read32(®s->transfer_len),
96 read32(®s->transac_len),
97 read32(®s->delay_len),
98 read32(®s->timing),
99 read32(®s->start),
100 read32(®s->fifo_stat),
101 read32(®s->io_config),
102 read32(®s->hs),
103 read32(®s->debug_stat),
104 read32(®s->ext_conf));
105
106 mtk_i2c_dump_more_info(regs);
107 }
108
mtk_i2c_transfer(uint8_t bus,struct i2c_msg * seg,enum i2c_modes mode)109 static int mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg,
110 enum i2c_modes mode)
111 {
112 int ret = I2C_OK;
113 uint16_t status;
114 uint16_t dma_sync = 0;
115 uint32_t time_out_val = 0;
116 uint8_t addr;
117 uint32_t write_len = 0;
118 uint32_t read_len = 0;
119 uint8_t *write_buffer = NULL;
120 uint8_t *read_buffer = NULL;
121 struct mt_i2c_regs *regs;
122 struct mt_i2c_dma_regs *dma_regs;
123 struct stopwatch sw;
124
125 regs = mtk_i2c_bus_controller[bus].i2c_regs;
126 dma_regs = mtk_i2c_bus_controller[bus].i2c_dma_regs;
127
128 addr = seg[0].slave;
129
130 if (mtk_i2c_bus_controller[bus].mt_i2c_flag == I2C_APDMA_ASYNC) {
131 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
132 if (mode == I2C_WRITE_READ_MODE)
133 dma_sync |= I2C_DMA_DIR_CHANGE;
134 }
135
136 switch (mode) {
137 case I2C_WRITE_MODE:
138 assert(seg[0].len > 0 && seg[0].len <= 255);
139 write_len = seg[0].len;
140 write_buffer = seg[0].buf;
141 break;
142
143 case I2C_READ_MODE:
144 assert(seg[0].len > 0 && seg[0].len <= 255);
145 read_len = seg[0].len;
146 read_buffer = seg[0].buf;
147 break;
148
149 /* Must use special write-then-read mode for repeated starts. */
150 case I2C_WRITE_READ_MODE:
151 assert(seg[0].len > 0 && seg[0].len <= 255);
152 assert(seg[1].len > 0 && seg[1].len <= 255);
153 write_len = seg[0].len;
154 read_len = seg[1].len;
155 write_buffer = seg[0].buf;
156 read_buffer = seg[1].buf;
157 break;
158 }
159
160 /* Clear interrupt status */
161 write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR |
162 I2C_HS_NACKERR);
163
164 write32(®s->fifo_addr_clr, 0x1);
165
166 /* Enable interrupt */
167 write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR |
168 I2C_TRANSAC_COMP);
169
170 switch (mode) {
171 case I2C_WRITE_MODE:
172 memcpy(_dma_coherent, write_buffer, write_len);
173
174 /* control registers */
175 write32(®s->control, ASYNC_MODE | DMAACK_EN |
176 ACK_ERR_DET_EN | DMA_EN | CLK_EXT |
177 REPEATED_START_FLAG);
178
179 /* Set transfer and transaction len */
180 write32(®s->transac_len, 1);
181 write32(®s->transfer_len, write_len);
182
183 /* set i2c write slave address*/
184 write32(®s->slave_addr, addr << 1);
185
186 /* Prepare buffer data to start transfer */
187 write32(&dma_regs->dma_con, I2C_DMA_CON_TX | dma_sync);
188 write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent);
189 write32(&dma_regs->dma_tx_len, write_len);
190 break;
191
192 case I2C_READ_MODE:
193 /* control registers */
194 write32(®s->control, ASYNC_MODE | DMAACK_EN |
195 ACK_ERR_DET_EN | DMA_EN | CLK_EXT |
196 REPEATED_START_FLAG);
197
198 /* Set transfer and transaction len */
199 write32(®s->transac_len, 1);
200 write32(®s->transfer_len, read_len);
201
202 /* set i2c read slave address*/
203 write32(®s->slave_addr, (addr << 1 | 0x1));
204
205 /* Prepare buffer data to start transfer */
206 write32(&dma_regs->dma_con, I2C_DMA_CON_RX | dma_sync);
207 write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent);
208 write32(&dma_regs->dma_rx_len, read_len);
209 break;
210
211 case I2C_WRITE_READ_MODE:
212 memcpy(_dma_coherent, write_buffer, write_len);
213
214 /* control registers */
215 write32(®s->control, ASYNC_MODE | DMAACK_EN |
216 DIR_CHG | ACK_ERR_DET_EN | DMA_EN |
217 CLK_EXT | REPEATED_START_FLAG);
218
219 /* Set transfer and transaction len */
220 write32(®s->transfer_len, write_len);
221 write32(®s->transfer_aux_len, read_len);
222 write32(®s->transac_len, 2);
223
224 /* set i2c write slave address*/
225 write32(®s->slave_addr, addr << 1);
226
227 /* Prepare buffer data to start transfer */
228 write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG | dma_sync);
229 write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent);
230 write32(&dma_regs->dma_tx_len, write_len);
231 write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent);
232 write32(&dma_regs->dma_rx_len, read_len);
233 break;
234 }
235
236 write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG);
237 write32(&dma_regs->dma_en, I2C_DMA_START_EN);
238
239 /* start transfer transaction */
240 write32(®s->start, 0x1);
241
242 stopwatch_init_usecs_expire(&sw, CONFIG_I2C_TRANSFER_TIMEOUT_US);
243
244 /* polling mode : see if transaction complete */
245 while (1) {
246 status = read32(®s->intr_stat);
247 if (status & I2C_HS_NACKERR) {
248 ret = I2C_TRANSFER_FAIL_HS_NACKERR;
249 printk(BIOS_ERR, "[i2c%d] transfer NACK error\n", bus);
250 mtk_i2c_dump_info(regs);
251 break;
252 } else if (status & I2C_ACKERR) {
253 ret = I2C_TRANSFER_FAIL_ACKERR;
254 printk(BIOS_ERR, "[i2c%d] transfer ACK error\n", bus);
255 mtk_i2c_dump_info(regs);
256 break;
257 } else if (status & I2C_TRANSAC_COMP) {
258 ret = I2C_OK;
259 memcpy(read_buffer, _dma_coherent, read_len);
260 break;
261 }
262
263 if (stopwatch_expired(&sw)) {
264 ret = I2C_TRANSFER_FAIL_TIMEOUT;
265 printk(BIOS_ERR, "[i2c%d] transfer timeout:%d\n", bus,
266 time_out_val);
267 mtk_i2c_dump_info(regs);
268 break;
269 }
270 }
271
272 write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR |
273 I2C_HS_NACKERR);
274
275 /* clear bit mask */
276 write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR |
277 I2C_TRANSAC_COMP);
278
279 /* reset the i2c controller for next i2c transfer. */
280 i2c_hw_reset(bus);
281
282 return ret;
283 }
284
mtk_i2c_should_combine(struct i2c_msg * seg,int left_count)285 static bool mtk_i2c_should_combine(struct i2c_msg *seg, int left_count)
286 {
287 return (left_count >= 2 &&
288 !(seg[0].flags & I2C_M_RD) &&
289 (seg[1].flags & I2C_M_RD) &&
290 seg[0].slave == seg[1].slave);
291 }
292
mtk_i2c_max_step_cnt(uint32_t target_speed)293 static int mtk_i2c_max_step_cnt(uint32_t target_speed)
294 {
295 if (target_speed > I2C_SPEED_FAST_PLUS)
296 return MAX_HS_STEP_CNT_DIV;
297 else
298 return MAX_STEP_CNT_DIV;
299 }
300
platform_i2c_transfer(unsigned int bus,struct i2c_msg * segments,int seg_count)301 int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
302 int seg_count)
303 {
304 int ret;
305 int i;
306 int mode;
307
308 for (i = 0; i < seg_count; i++) {
309 if (mtk_i2c_should_combine(&segments[i], seg_count - i)) {
310 mode = I2C_WRITE_READ_MODE;
311 } else {
312 mode = (segments[i].flags & I2C_M_RD) ?
313 I2C_READ_MODE : I2C_WRITE_MODE;
314 }
315
316 ret = mtk_i2c_transfer(bus, &segments[i], mode);
317 if (ret < 0)
318 return ret;
319
320 if (mode == I2C_WRITE_READ_MODE)
321 i++;
322 }
323
324 return 0;
325 }
326
327 /*
328 * Check and calculate i2c ac-timing.
329 *
330 * Hardware design:
331 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
332 * xxx_cnt_div = spec->min_xxx_ns / sample_ns
333 *
334 * The calculation of sample_ns is rounded down;
335 * otherwise xxx_cnt_div would be greater than the smallest spec.
336 * The sda_timing is chosen as the middle value between
337 * the largest and smallest.
338 */
mtk_i2c_check_ac_timing(uint8_t bus,uint32_t clk_src,uint32_t check_speed,uint32_t step_cnt,uint32_t sample_cnt)339 int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src,
340 uint32_t check_speed,
341 uint32_t step_cnt,
342 uint32_t sample_cnt)
343 {
344 const struct i2c_spec_values *spec;
345 uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
346 uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100;
347 uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src;
348 struct mtk_i2c_ac_timing *ac_timing;
349
350 spec = mtk_i2c_get_spec(check_speed);
351
352 clk_ns = NSECS_PER_SEC / clk_src;
353
354 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
355 if (su_sta_cnt > max_sta_cnt)
356 return -1;
357
358 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
359 max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
360 if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) {
361 if (low_cnt > step_cnt) {
362 high_cnt = 2 * step_cnt - low_cnt;
363 } else {
364 high_cnt = step_cnt;
365 low_cnt = step_cnt;
366 }
367 } else {
368 return -2;
369 }
370
371 sda_max = spec->max_hd_dat_ns / sample_ns;
372 if (sda_max > low_cnt)
373 sda_max = 0;
374
375 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
376 if (sda_min < low_cnt)
377 sda_min = 0;
378
379 if (sda_min > sda_max)
380 return -3;
381
382 ac_timing = &mtk_i2c_bus_controller[bus].ac_timing;
383 if (check_speed > I2C_SPEED_FAST_PLUS) {
384 ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8);
385 ac_timing->ltiming &= ~GENMASK(15, 9);
386 ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9);
387 ac_timing->ext &= ~GENMASK(7, 1);
388 ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0);
389 } else {
390 ac_timing->htiming = (sample_cnt << 8) | (high_cnt);
391 ac_timing->ltiming = (sample_cnt << 6) | (low_cnt);
392 ac_timing->ext = (su_sta_cnt << 8) | (1 << 0);
393 }
394
395 return 0;
396 }
397
398 /*
399 * Calculate i2c port speed.
400 *
401 * Hardware design:
402 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
403 * clock_div: fixed in hardware, but may be various in different SoCs
404 *
405 * To calculate sample_cnt and step_cnt, we pick the highest bus frequency
406 * that is still no larger than i2c->speed_hz.
407 */
mtk_i2c_calculate_speed(uint8_t bus,uint32_t clk_src,uint32_t target_speed,uint32_t * timing_step_cnt,uint32_t * timing_sample_cnt)408 int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
409 uint32_t target_speed,
410 uint32_t *timing_step_cnt,
411 uint32_t *timing_sample_cnt)
412 {
413 uint32_t step_cnt;
414 uint32_t sample_cnt;
415 uint32_t max_step_cnt;
416 uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV;
417 uint32_t base_step_cnt;
418 uint32_t opt_div;
419 uint32_t best_mul;
420 uint32_t cnt_mul;
421 uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div;
422 int32_t clock_div_constraint = 0;
423 int success = 0;
424
425 if (target_speed > I2C_SPEED_HIGH)
426 target_speed = I2C_SPEED_HIGH;
427
428 max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
429 base_step_cnt = max_step_cnt;
430
431 /* Find the best combination */
432 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
433 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
434
435 /* Search for the best pair (sample_cnt, step_cnt) with
436 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
437 * 0 < step_cnt < max_step_cnt
438 * sample_cnt * step_cnt >= opt_div
439 * optimizing for sample_cnt * step_cnt being minimal
440 */
441 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
442 if (sample_cnt == 1) {
443 if (clk_div != 0)
444 clock_div_constraint = 1;
445 else
446 clock_div_constraint = 0;
447 } else {
448 if (clk_div > 1)
449 clock_div_constraint = 1;
450 else if (clk_div == 0)
451 clock_div_constraint = -1;
452 else
453 clock_div_constraint = 0;
454 }
455
456 step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt);
457 if (step_cnt > max_step_cnt)
458 continue;
459
460 cnt_mul = step_cnt * sample_cnt;
461 if (cnt_mul >= best_mul)
462 continue;
463
464 if (mtk_i2c_check_ac_timing(bus, clk_src,
465 target_speed, step_cnt - 1,
466 sample_cnt - 1))
467 continue;
468
469 success = 1;
470 best_mul = cnt_mul;
471 base_sample_cnt = sample_cnt;
472 base_step_cnt = step_cnt;
473 if (best_mul == opt_div + clock_div_constraint)
474 break;
475 }
476
477 if (!success)
478 return -1;
479
480 sample_cnt = base_sample_cnt;
481 step_cnt = base_step_cnt;
482
483 if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) >
484 target_speed)
485 return -1;
486
487 *timing_step_cnt = step_cnt - 1;
488 *timing_sample_cnt = sample_cnt - 1;
489
490 return 0;
491 }
492
mtk_i2c_speed_init(uint8_t bus,uint32_t speed)493 void mtk_i2c_speed_init(uint8_t bus, uint32_t speed)
494 {
495 uint32_t max_clk_div = MAX_CLOCK_DIV;
496 uint32_t clk_src, clk_div, step_cnt, sample_cnt;
497 uint32_t l_step_cnt, l_sample_cnt;
498 struct mtk_i2c *bus_ctrl;
499
500 if (bus >= I2C_BUS_NUMBER) {
501 printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus);
502 return;
503 }
504
505 bus_ctrl = &mtk_i2c_bus_controller[bus];
506
507 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
508 clk_src = I2C_CLK_HZ / clk_div;
509 bus_ctrl->ac_timing.inter_clk_div = clk_div - 1;
510
511 if (speed > I2C_SPEED_FAST_PLUS) {
512 /* Set master code speed register */
513 if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST,
514 &l_step_cnt, &l_sample_cnt))
515 continue;
516
517 /* Set the high speed mode register */
518 if (mtk_i2c_calculate_speed(bus, clk_src, speed,
519 &step_cnt, &sample_cnt))
520 continue;
521
522 bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1);
523 } else {
524 if (mtk_i2c_calculate_speed(bus, clk_src, speed,
525 &l_step_cnt, &l_sample_cnt))
526 continue;
527
528 /* Disable the high speed transaction */
529 bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE;
530 }
531
532 break;
533 }
534
535 if (clk_div > max_clk_div) {
536 printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus);
537 return;
538 }
539
540 /* Init i2c bus timing register. */
541 mtk_i2c_config_timing(bus_ctrl->i2c_regs, bus_ctrl);
542 }
543