1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 * SPDX-License-Identifier: MIT
5 *
6 * based in part on anv driver which is:
7 * Copyright © 2015 Intel Corporation
8 */
9
10 #ifndef TU_PIPELINE_H
11 #define TU_PIPELINE_H
12
13 #include "tu_common.h"
14
15 #include "tu_cs.h"
16 #include "tu_descriptor_set.h"
17 #include "tu_shader.h"
18 #include "tu_suballoc.h"
19
20 enum tu_dynamic_state
21 {
22 TU_DYNAMIC_STATE_VIEWPORT,
23 TU_DYNAMIC_STATE_SCISSOR,
24 TU_DYNAMIC_STATE_RAST,
25 TU_DYNAMIC_STATE_DEPTH_BIAS,
26 TU_DYNAMIC_STATE_BLEND_CONSTANTS,
27 TU_DYNAMIC_STATE_DS,
28 TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
29 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
30 TU_DYNAMIC_STATE_VB_STRIDE,
31 TU_DYNAMIC_STATE_BLEND,
32 TU_DYNAMIC_STATE_VERTEX_INPUT,
33 TU_DYNAMIC_STATE_PATCH_CONTROL_POINTS,
34 TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM,
35 TU_DYNAMIC_STATE_COUNT,
36 };
37
38 struct cache_entry;
39
40 struct tu_lrz_blend
41 {
42 bool valid;
43 bool reads_dest;
44 };
45
46 struct tu_bandwidth
47 {
48 uint32_t color_bandwidth_per_sample;
49 uint32_t depth_cpp_per_sample;
50 uint32_t stencil_cpp_per_sample;
51 bool valid;
52 };
53
54 struct tu_nir_shaders
55 {
56 struct vk_pipeline_cache_object base;
57
58 /* This is optional, and is only filled out when a library pipeline is
59 * compiled with RETAIN_LINK_TIME_OPTIMIZATION_INFO.
60 */
61 nir_shader *nir[MESA_SHADER_STAGES];
62 };
63
64 extern const struct vk_pipeline_cache_object_ops tu_nir_shaders_ops;
65
66 static bool inline
tu6_shared_constants_enable(const struct tu_pipeline_layout * layout,const struct ir3_compiler * compiler)67 tu6_shared_constants_enable(const struct tu_pipeline_layout *layout,
68 const struct ir3_compiler *compiler)
69 {
70 return layout->push_constant_size > 0 &&
71 layout->push_constant_size <= (compiler->shared_consts_size * 16);
72 }
73
74 enum ir3_push_consts_type
75 tu_push_consts_type(const struct tu_pipeline_layout *layout,
76 const struct ir3_compiler *compiler);
77
78 struct tu_program_descriptor_linkage
79 {
80 struct ir3_const_state const_state;
81
82 uint32_t constlen;
83
84 struct tu_const_state tu_const_state;
85 };
86
87 struct tu_program_state
88 {
89 struct tu_draw_state config_state;
90 struct tu_draw_state vs_state, vs_binning_state;
91 struct tu_draw_state hs_state;
92 struct tu_draw_state ds_state;
93 struct tu_draw_state gs_state, gs_binning_state;
94 struct tu_draw_state vpc_state;
95 struct tu_draw_state fs_state;
96
97 struct tu_push_constant_range shared_consts;
98
99 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
100
101 unsigned dynamic_descriptor_offsets[MAX_SETS];
102
103 bool per_view_viewport;
104 };
105
106 struct tu_pipeline_executable {
107 gl_shader_stage stage;
108
109 struct ir3_info stats;
110 bool is_binning;
111
112 char *nir_from_spirv;
113 char *nir_final;
114 char *disasm;
115 };
116
117 enum tu_pipeline_type {
118 TU_PIPELINE_GRAPHICS,
119 TU_PIPELINE_GRAPHICS_LIB,
120 TU_PIPELINE_COMPUTE,
121 };
122
123 struct tu_pipeline
124 {
125 struct vk_object_base base;
126 enum tu_pipeline_type type;
127
128 struct tu_cs cs;
129 struct tu_suballoc_bo bo;
130
131 VkShaderStageFlags active_stages;
132 uint32_t active_desc_sets;
133
134 /* mask of enabled dynamic states
135 * if BIT(i) is set, pipeline->dynamic_state[i] is used
136 */
137 uint32_t set_state_mask;
138 struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
139
140 BITSET_DECLARE(static_state_mask, MESA_VK_DYNAMIC_GRAPHICS_STATE_ENUM_MAX);
141
142 struct {
143 bool raster_order_attachment_access;
144 } ds;
145
146 /* Misc. info from the fragment output interface state that is used
147 * elsewhere.
148 */
149 struct {
150 bool raster_order_attachment_access;
151 } output;
152
153 /* In other words - framebuffer fetch support */
154 struct {
155 /* If the pipeline sets SINGLE_PRIM_MODE for sysmem. */
156 bool sysmem_single_prim_mode;
157 struct tu_draw_state state_gmem;
158 } prim_order;
159
160 /* draw states for the pipeline */
161 struct tu_draw_state load_state;
162
163 struct tu_shader *shaders[MESA_SHADER_STAGES];
164
165 struct tu_program_state program;
166
167 struct tu_lrz_blend lrz_blend;
168 struct tu_bandwidth bandwidth;
169
170 void *executables_mem_ctx;
171 /* tu_pipeline_executable */
172 struct util_dynarray executables;
173 };
174
175 struct tu_graphics_lib_pipeline {
176 struct tu_pipeline base;
177
178 VkGraphicsPipelineLibraryFlagsEXT state;
179
180 struct vk_graphics_pipeline_state graphics_state;
181
182 /* For vk_graphics_pipeline_state */
183 void *state_data;
184
185 struct tu_nir_shaders *nir_shaders;
186 struct {
187 nir_shader *nir;
188 struct tu_shader_key key;
189 } shaders[MESA_SHADER_FRAGMENT + 1];
190
191 /* Used to stitch together an overall layout for the final pipeline. */
192 struct tu_descriptor_set_layout *layouts[MAX_SETS];
193 unsigned num_sets;
194 unsigned push_constant_size;
195 bool independent_sets;
196 };
197
198 struct tu_graphics_pipeline {
199 struct tu_pipeline base;
200
201 struct vk_dynamic_graphics_state dynamic_state;
202
203 /* Only used if the sample locations are static but the enable is dynamic.
204 * Otherwise we should be able to precompile the draw state.
205 */
206 struct vk_sample_locations_state sample_locations;
207
208 VkImageAspectFlags feedback_loops;
209 bool feedback_loop_may_involve_textures;
210 };
211
212 struct tu_compute_pipeline {
213 struct tu_pipeline base;
214
215 uint32_t local_size[3];
216 uint32_t instrlen;
217 };
218
219 VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, base, VkPipeline,
220 VK_OBJECT_TYPE_PIPELINE)
221
222 #define TU_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
223 static inline struct tu_##pipe_type##_pipeline * \
224 tu_pipeline_to_##pipe_type(struct tu_pipeline *pipeline) \
225 { \
226 assert(pipeline->type == pipe_enum); \
227 return (struct tu_##pipe_type##_pipeline *) pipeline; \
228 }
229
230 TU_DECL_PIPELINE_DOWNCAST(graphics, TU_PIPELINE_GRAPHICS)
231 TU_DECL_PIPELINE_DOWNCAST(graphics_lib, TU_PIPELINE_GRAPHICS_LIB)
232 TU_DECL_PIPELINE_DOWNCAST(compute, TU_PIPELINE_COMPUTE)
233
234 VkOffset2D tu_fdm_per_bin_offset(VkExtent2D frag_area, VkRect2D bin);
235
236 template <chip CHIP>
237 uint32_t tu_emit_draw_state(struct tu_cmd_buffer *cmd);
238
239 struct tu_pvtmem_config {
240 uint64_t iova;
241 uint32_t per_fiber_size;
242 uint32_t per_sp_size;
243 bool per_wave;
244 };
245
246 template <chip CHIP>
247 void
248 tu6_emit_xs_config(struct tu_cs *cs,
249 gl_shader_stage stage,
250 const struct ir3_shader_variant *xs);
251
252 template <chip CHIP>
253 void
254 tu6_emit_shared_consts_enable(struct tu_cs *cs, bool shared_consts_enable);
255
256 template <chip CHIP>
257 void
258 tu6_emit_vpc(struct tu_cs *cs,
259 const struct ir3_shader_variant *vs,
260 const struct ir3_shader_variant *hs,
261 const struct ir3_shader_variant *ds,
262 const struct ir3_shader_variant *gs,
263 const struct ir3_shader_variant *fs);
264
265 void
266 tu_fill_render_pass_state(struct vk_render_pass_state *rp,
267 const struct tu_render_pass *pass,
268 const struct tu_subpass *subpass);
269
270 #endif /* TU_PIPELINE_H */
271