1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /*
4 * Designware High-Definition Multimedia Interface (HDMI) driveG
5 */
6
7 #include <device/mmio.h>
8 #include <console/console.h>
9 #include <delay.h>
10 #include <edid.h>
11 #include <gpio.h>
12 #include <stdint.h>
13 #include <soc/addressmap.h>
14 #include <soc/hdmi.h>
15 #include <soc/grf.h>
16 #include <soc/vop.h>
17 #include <timer.h>
18
19 #include "chip.h"
20
21 #define AUDIO_SAMPLERATE_DEFAULT (48*KHz)
22
23 #define hdmi_debug(x...) do { if (0) printk(BIOS_DEBUG, x); } while (0)
24
25 struct rk3288_hdmi_regs * const hdmi_regs = (void *)HDMI_TX_BASE;
26
27 struct tmds_n_cts {
28 u32 tmds;
29 u32 cts;
30 u32 n;
31 };
32
33 static const struct tmds_n_cts n_cts_table[] = {
34 {
35 .tmds = 25175, .n = 6144, .cts = 25175,
36 }, {
37 .tmds = 25200, .n = 6144, .cts = 25200,
38 }, {
39 .tmds = 27000, .n = 6144, .cts = 27000,
40 }, {
41 .tmds = 27027, .n = 6144, .cts = 27027,
42 }, {
43 .tmds = 40000, .n = 6144, .cts = 40000,
44 }, {
45 .tmds = 54000, .n = 6144, .cts = 54000,
46 }, {
47 .tmds = 54054, .n = 6144, .cts = 54054,
48 }, {
49 .tmds = 65000, .n = 6144, .cts = 65000,
50 }, {
51 .tmds = 74176, .n = 11648, .cts = 140625,
52 }, {
53 .tmds = 74250, .n = 6144, .cts = 74250,
54 }, {
55 .tmds = 83500, .n = 6144, .cts = 83500,
56 }, {
57 .tmds = 106500, .n = 6144, .cts = 106500,
58 }, {
59 .tmds = 108000, .n = 6144, .cts = 108000,
60 }, {
61 .tmds = 148352, .n = 5824, .cts = 140625,
62 }, {
63 .tmds = 148500, .n = 6144, .cts = 148500,
64 }, {
65 .tmds = 297000, .n = 5120, .cts = 247500,
66 }
67 };
68
69 struct hdmi_mpll_config {
70 u64 mpixelclock;
71 /* Mode of Operation and PLL Dividers Control Register */
72 u32 cpce;
73 /* PLL Gmp Control Register */
74 u32 gmp;
75 /* PLL Current COntrol Register */
76 u32 curr;
77 };
78
79 struct hdmi_phy_config {
80 u64 mpixelclock;
81 u32 sym_ctr; /* clock symbol and transmitter control */
82 u32 term; /* transmission termination value */
83 u32 vlev_ctr; /* voltage level control */
84 };
85
86 static const struct hdmi_phy_config rockchip_phy_config[] = {
87 {
88 .mpixelclock = 74250,
89 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
90 }, {
91 .mpixelclock = 148500,
92 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
93 }, {
94 .mpixelclock = 297000,
95 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
96 }, {
97 .mpixelclock = ~0ul,
98 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
99 }
100 };
101
102 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
103 {
104 .mpixelclock = 40000,
105 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
106 }, {
107 .mpixelclock = 65000,
108 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
109 }, {
110 .mpixelclock = 66000,
111 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
112 }, {
113 .mpixelclock = 83500,
114 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
115 }, {
116 .mpixelclock = 146250,
117 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
118 }, {
119 .mpixelclock = 148500,
120 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
121 }, {
122 .mpixelclock = ~0ul,
123 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
124 }
125 };
126
127 static const u32 csc_coeff_default[3][4] = {
128 { 0x2000, 0x0000, 0x0000, 0x0000 },
129 { 0x0000, 0x2000, 0x0000, 0x0000 },
130 { 0x0000, 0x0000, 0x2000, 0x0000 }
131 };
132
hdmi_set_clock_regenerator(u32 n,u32 cts)133 static void hdmi_set_clock_regenerator(u32 n, u32 cts)
134 {
135 u8 cts3;
136 u8 n3;
137
138 /* first set ncts_atomic_write (if present) */
139 n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
140 write32(&hdmi_regs->aud_n3, n3);
141
142 /* set cts_manual (if present) */
143 cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
144
145 cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
146 cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
147
148 /* write cts values; cts3 must be written first */
149 write32(&hdmi_regs->aud_cts3, cts3);
150 write32(&hdmi_regs->aud_cts2, (cts >> 8) & 0xff);
151 write32(&hdmi_regs->aud_cts1, cts & 0xff);
152
153 /* write n values; n1 must be written last */
154 n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
155 write32(&hdmi_regs->aud_n3, n3);
156 write32(&hdmi_regs->aud_n2, (n >> 8) & 0xff);
157 write32(&hdmi_regs->aud_n1, n & 0xff);
158
159 write32(&hdmi_regs->aud_inputclkfs, HDMI_AUD_INPUTCLKFS_128);
160 }
161
hdmi_lookup_n_cts(u32 pixel_clk)162 static int hdmi_lookup_n_cts(u32 pixel_clk)
163 {
164 int i;
165
166 for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
167 if (pixel_clk <= n_cts_table[i].tmds)
168 break;
169
170 if (i >= ARRAY_SIZE(n_cts_table))
171 return -1;
172
173 return i;
174 }
175
hdmi_audio_set_samplerate(u32 pixel_clk)176 static void hdmi_audio_set_samplerate(u32 pixel_clk)
177 {
178 u32 clk_n, clk_cts;
179 int index;
180
181 index = hdmi_lookup_n_cts(pixel_clk);
182 if (index == -1) {
183 hdmi_debug("audio not supported for pixel clk %d\n", pixel_clk);
184 return;
185 }
186
187 clk_n = n_cts_table[index].n;
188 clk_cts = n_cts_table[index].cts;
189 hdmi_set_clock_regenerator(clk_n, clk_cts);
190 }
191
192 /*
193 * this submodule is responsible for the video data synchronization.
194 * for example, for rgb 4:4:4 input, the data map is defined as
195 * pin{47~40} <==> r[7:0]
196 * pin{31~24} <==> g[7:0]
197 * pin{15~8} <==> b[7:0]
198 */
hdmi_video_sample(void)199 static void hdmi_video_sample(void)
200 {
201 u32 color_format = 0x01;
202 u8 val;
203
204 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
205 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
206 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
207
208 write32(&hdmi_regs->tx_invid0, val);
209
210 /* enable tx stuffing: when de is inactive, fix the output data to 0 */
211 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
212 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
213 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
214 write32(&hdmi_regs->tx_instuffing, val);
215 write32(&hdmi_regs->tx_gydata0, 0x0);
216 write32(&hdmi_regs->tx_gydata1, 0x0);
217 write32(&hdmi_regs->tx_rcrdata0, 0x0);
218 write32(&hdmi_regs->tx_rcrdata1, 0x0);
219 write32(&hdmi_regs->tx_bcbdata0, 0x0);
220 write32(&hdmi_regs->tx_bcbdata1, 0x0);
221 }
222
hdmi_update_csc_coeffs(void)223 static void hdmi_update_csc_coeffs(void)
224 {
225 u32 i, j;
226 u32 csc_scale = 1;
227
228 /* the csc registers are sequential, alternating msb then lsb */
229 for (i = 0; i < ARRAY_SIZE(csc_coeff_default); i++) {
230 for (j = 0; j < ARRAY_SIZE(csc_coeff_default[0]); j++) {
231 u32 coeff = csc_coeff_default[i][j];
232 write32(&hdmi_regs->csc_coef[i][j].msb, coeff >> 8);
233 write32(&hdmi_regs->csc_coef[i][j].lsb, coeff & 0xff);
234 }
235 }
236
237 clrsetbits32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
238 csc_scale);
239 }
240
hdmi_video_csc(void)241 static void hdmi_video_csc(void)
242 {
243 u32 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
244 u32 interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
245
246 /* configure the csc registers */
247 write32(&hdmi_regs->csc_cfg, interpolation);
248 clrsetbits32(&hdmi_regs->csc_scale,
249 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth);
250
251 hdmi_update_csc_coeffs();
252 }
253
hdmi_video_packetize(void)254 static void hdmi_video_packetize(void)
255 {
256 u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
257 u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
258 u32 color_depth = 0;
259 u8 val, vp_conf;
260
261 /* set the packetizer registers */
262 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
263 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
264 ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
265 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
266 write32(&hdmi_regs->vp_pr_cd, val);
267
268 clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK,
269 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
270
271 /* data from pixel repeater block */
272 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
273 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
274
275 clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK |
276 HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
277
278 clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
279 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
280
281 write32(&hdmi_regs->vp_remap, remap_size);
282
283 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
284 HDMI_VP_CONF_PP_EN_DISABLE |
285 HDMI_VP_CONF_YCC422_EN_DISABLE;
286
287 clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK |
288 HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
289 vp_conf);
290
291 clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK |
292 HDMI_VP_STUFF_YCC422_STUFFING_MASK,
293 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
294 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
295
296 clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
297 output_select);
298 }
299
hdmi_phy_test_clear(u8 bit)300 static inline void hdmi_phy_test_clear(u8 bit)
301 {
302 clrsetbits32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
303 bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
304 }
305
hdmi_phy_wait_i2c_done(u32 msec)306 static int hdmi_phy_wait_i2c_done(u32 msec)
307 {
308 struct stopwatch phyi2c_done;
309 u32 val;
310
311 stopwatch_init_msecs_expire(&phyi2c_done, msec);
312 do {
313 val = read32(&hdmi_regs->ih_i2cmphy_stat0);
314 if (val & 0x3) {
315 write32(&hdmi_regs->ih_i2cmphy_stat0, val);
316 return 0;
317 }
318
319 udelay(100);
320 } while (!stopwatch_expired(&phyi2c_done));
321
322 return 1;
323 }
324
hdmi_phy_i2c_write(u16 data,u8 addr)325 static void hdmi_phy_i2c_write(u16 data, u8 addr)
326 {
327 write32(&hdmi_regs->ih_i2cmphy_stat0, 0xff);
328 write32(&hdmi_regs->phy_i2cm_address_addr, addr);
329 write32(&hdmi_regs->phy_i2cm_datao_1_addr, (u8)(data >> 8));
330 write32(&hdmi_regs->phy_i2cm_datao_0_addr, (u8)(data >> 0));
331 write32(&hdmi_regs->phy_i2cm_operation_addr,
332 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE);
333
334 hdmi_phy_wait_i2c_done(1000);
335 }
336
hdmi_phy_enable_power(u8 enable)337 static void hdmi_phy_enable_power(u8 enable)
338 {
339 clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK,
340 enable << HDMI_PHY_CONF0_PDZ_OFFSET);
341 }
342
hdmi_phy_enable_tmds(u8 enable)343 static void hdmi_phy_enable_tmds(u8 enable)
344 {
345 clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK,
346 enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
347 }
348
hdmi_phy_enable_spare(u8 enable)349 static void hdmi_phy_enable_spare(u8 enable)
350 {
351 clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK,
352 enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
353 }
354
hdmi_phy_gen2_pddq(u8 enable)355 static void hdmi_phy_gen2_pddq(u8 enable)
356 {
357 clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
358 enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
359 }
360
hdmi_phy_gen2_txpwron(u8 enable)361 static void hdmi_phy_gen2_txpwron(u8 enable)
362 {
363 clrsetbits32(&hdmi_regs->phy_conf0,
364 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
365 enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
366 }
367
hdmi_phy_sel_data_en_pol(u8 enable)368 static void hdmi_phy_sel_data_en_pol(u8 enable)
369 {
370 clrsetbits32(&hdmi_regs->phy_conf0,
371 HDMI_PHY_CONF0_SELDATAENPOL_MASK,
372 enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
373 }
374
hdmi_phy_sel_interface_control(u8 enable)375 static void hdmi_phy_sel_interface_control(u8 enable)
376 {
377 clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK,
378 enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
379 }
380
hdmi_phy_configure(u32 mpixelclock)381 static int hdmi_phy_configure(u32 mpixelclock)
382 {
383 struct stopwatch pll_ready;
384 u8 i, val;
385
386 write32(&hdmi_regs->mc_flowctrl,
387 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS);
388
389 /* gen2 tx power off */
390 hdmi_phy_gen2_txpwron(0);
391
392 /* gen2 pddq */
393 hdmi_phy_gen2_pddq(1);
394
395 /* phy reset */
396 write32(&hdmi_regs->mc_phyrstz, HDMI_MC_PHYRSTZ_DEASSERT);
397 write32(&hdmi_regs->mc_phyrstz, HDMI_MC_PHYRSTZ_ASSERT);
398 write32(&hdmi_regs->mc_heacphy_rst, HDMI_MC_HEACPHY_RST_ASSERT);
399
400 hdmi_phy_test_clear(1);
401 write32(&hdmi_regs->phy_i2cm_slave_addr,
402 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
403 hdmi_phy_test_clear(0);
404
405 /* pll/mpll cfg - always match on final entry */
406 for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++)
407 if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock)
408 break;
409
410 hdmi_phy_i2c_write(rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
411 hdmi_phy_i2c_write(rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
412 hdmi_phy_i2c_write(rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL);
413
414 hdmi_phy_i2c_write(0x0000, PHY_PLLPHBYCTRL);
415 hdmi_phy_i2c_write(0x0006, PHY_PLLCLKBISTPHASE);
416
417 for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++)
418 if (mpixelclock <= rockchip_phy_config[i].mpixelclock)
419 break;
420
421 /*
422 * resistance term 133ohm cfg
423 * preemp cgf 0.00
424 * tx/ck lvl 10
425 */
426 hdmi_phy_i2c_write(rockchip_phy_config[i].term, PHY_TXTERM);
427 hdmi_phy_i2c_write(rockchip_phy_config[i].sym_ctr, PHY_CKSYMTXCTRL);
428 hdmi_phy_i2c_write(rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL);
429
430 /* remove clk term */
431 hdmi_phy_i2c_write(0x8000, PHY_CKCALCTRL);
432
433 hdmi_phy_enable_power(1);
434
435 /* toggle tmds enable */
436 hdmi_phy_enable_tmds(0);
437 hdmi_phy_enable_tmds(1);
438
439 /* gen2 tx power on */
440 hdmi_phy_gen2_txpwron(1);
441 hdmi_phy_gen2_pddq(0);
442
443 hdmi_phy_enable_spare(1);
444
445 /* wait for phy pll lock */
446 stopwatch_init_msecs_expire(&pll_ready, 5);
447 do {
448 val = read32(&hdmi_regs->phy_stat0);
449 if (!(val & HDMI_PHY_TX_PHY_LOCK))
450 return 0;
451
452 udelay(100);
453 } while (!stopwatch_expired(&pll_ready));
454
455 return -1;
456 }
457
hdmi_phy_init(u32 mpixelclock)458 static int hdmi_phy_init(u32 mpixelclock)
459 {
460 int i, ret;
461
462 /* hdmi phy spec says to do the phy initialization sequence twice */
463 for (i = 0; i < 2; i++) {
464 hdmi_phy_sel_data_en_pol(1);
465 hdmi_phy_sel_interface_control(0);
466 hdmi_phy_enable_tmds(0);
467 hdmi_phy_enable_power(0);
468
469 /* enable csc */
470 ret = hdmi_phy_configure(mpixelclock);
471 if (ret) {
472 hdmi_debug("hdmi phy config failure %d\n", ret);
473 return ret;
474 }
475 }
476
477 return 0;
478 }
479
hdmi_av_composer(const struct edid * edid)480 static void hdmi_av_composer(const struct edid *edid)
481 {
482 u8 mdataenablepolarity = 1;
483 u8 inv_val;
484
485 /* set up hdmi_fc_invidconf */
486 inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
487
488 inv_val |= ((edid->mode.pvsync == '+') ?
489 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
490 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
491
492 inv_val |= ((edid->mode.phsync == '+') ?
493 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
494 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
495
496 inv_val |= (mdataenablepolarity ?
497 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
498 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
499
500 inv_val |= (edid->hdmi_monitor_detected ?
501 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
502 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
503
504 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
505
506 inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
507
508 write32(&hdmi_regs->fc_invidconf, inv_val);
509
510 /* set up horizontal active pixel width */
511 write32(&hdmi_regs->fc_inhactv1, edid->mode.ha >> 8);
512 write32(&hdmi_regs->fc_inhactv0, edid->mode.ha);
513
514 /* set up vertical active lines */
515 write32(&hdmi_regs->fc_invactv1, edid->mode.va >> 8);
516 write32(&hdmi_regs->fc_invactv0, edid->mode.va);
517
518 /* set up horizontal blanking pixel region width */
519 write32(&hdmi_regs->fc_inhblank1, edid->mode.hbl >> 8);
520 write32(&hdmi_regs->fc_inhblank0, edid->mode.hbl);
521
522 /* set up vertical blanking pixel region width */
523 write32(&hdmi_regs->fc_invblank, edid->mode.vbl);
524
525 /* set up hsync active edge delay width (in pixel clks) */
526 write32(&hdmi_regs->fc_hsyncindelay1, edid->mode.hso >> 8);
527 write32(&hdmi_regs->fc_hsyncindelay0, edid->mode.hso);
528
529 /* set up vsync active edge delay (in lines) */
530 write32(&hdmi_regs->fc_vsyncindelay, edid->mode.vso);
531
532 /* set up hsync active pulse width (in pixel clks) */
533 write32(&hdmi_regs->fc_hsyncinwidth1, edid->mode.hspw >> 8);
534 write32(&hdmi_regs->fc_hsyncinwidth0, edid->mode.hspw);
535
536 /* set up vsync active edge delay (in lines) */
537 write32(&hdmi_regs->fc_vsyncinwidth, edid->mode.vspw);
538 }
539
540 /* hdmi initialization step b.4 */
hdmi_enable_video_path(void)541 static void hdmi_enable_video_path(void)
542 {
543 u8 clkdis;
544
545 /* control period minimum duration */
546 write32(&hdmi_regs->fc_ctrldur, 12);
547 write32(&hdmi_regs->fc_exctrldur, 32);
548 write32(&hdmi_regs->fc_exctrlspac, 1);
549
550 /* set to fill tmds data channels */
551 write32(&hdmi_regs->fc_ch0pream, 0x0b);
552 write32(&hdmi_regs->fc_ch1pream, 0x16);
553 write32(&hdmi_regs->fc_ch2pream, 0x21);
554
555 /* enable pixel clock and tmds data path */
556 clkdis = 0x7f;
557 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
558 write32(&hdmi_regs->mc_clkdis, clkdis);
559
560 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
561 write32(&hdmi_regs->mc_clkdis, clkdis);
562
563 clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
564 write32(&hdmi_regs->mc_clkdis, clkdis);
565 }
566
567 /* workaround to clear the overflow condition */
hdmi_clear_overflow(void)568 static void hdmi_clear_overflow(void)
569 {
570 u8 val, count;
571
572 /* tmds software reset */
573 write32(&hdmi_regs->mc_swrstz, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ);
574
575 val = read32(&hdmi_regs->fc_invidconf);
576
577 for (count = 0; count < 4; count++)
578 write32(&hdmi_regs->fc_invidconf, val);
579 }
580
hdmi_audio_set_format(void)581 static void hdmi_audio_set_format(void)
582 {
583 write32(&hdmi_regs->aud_conf0,
584 HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0);
585
586 write32(&hdmi_regs->aud_conf1,
587 HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
588 HDMI_AUD_CONF1_I2S_WIDTH_16BIT);
589
590 write32(&hdmi_regs->aud_conf2, 0x00);
591 }
592
hdmi_audio_fifo_reset(void)593 static void hdmi_audio_fifo_reset(void)
594 {
595 write32(&hdmi_regs->mc_swrstz, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ);
596 write32(&hdmi_regs->aud_conf0, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST);
597
598 write32(&hdmi_regs->aud_int, 0x00);
599 write32(&hdmi_regs->aud_int1, 0x00);
600 }
601
hdmi_setup(const struct edid * edid)602 static int hdmi_setup(const struct edid *edid)
603 {
604 int ret;
605
606 hdmi_debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
607 edid->mode.pixel_clock, edid->mode.ha, edid->mode.va);
608
609 hdmi_av_composer(edid);
610
611 ret = hdmi_phy_init(edid->mode.pixel_clock);
612 if (ret)
613 return ret;
614
615 hdmi_enable_video_path();
616
617 hdmi_audio_fifo_reset();
618 hdmi_audio_set_format();
619 hdmi_audio_set_samplerate(edid->mode.pixel_clock);
620
621 hdmi_video_packetize();
622 hdmi_video_csc();
623 hdmi_video_sample();
624
625 hdmi_clear_overflow();
626
627 return 0;
628 }
629
hdmi_init_interrupt(void)630 static void hdmi_init_interrupt(void)
631 {
632 u8 ih_mute;
633
634 /*
635 * boot up defaults are:
636 * hdmi_ih_mute = 0x03 (disabled)
637 * hdmi_ih_mute_* = 0x00 (enabled)
638 *
639 * disable top level interrupt bits in hdmi block
640 */
641 ih_mute = read32(&hdmi_regs->ih_mute) |
642 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
643 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
644
645 write32(&hdmi_regs->ih_mute, ih_mute);
646
647 /* enable i2c master done irq */
648 write32(&hdmi_regs->i2cm_int, ~0x04);
649
650 /* enable i2c client nack % arbitration error irq */
651 write32(&hdmi_regs->i2cm_ctlint, ~0x44);
652
653 /* enable phy i2cm done irq */
654 write32(&hdmi_regs->phy_i2cm_int_addr, HDMI_PHY_I2CM_INT_ADDR_DONE_POL);
655
656 /* enable phy i2cm nack & arbitration error irq */
657 write32(&hdmi_regs->phy_i2cm_ctlint_addr,
658 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
659 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL);
660
661 /* enable cable hot plug irq */
662 write32(&hdmi_regs->phy_mask0, (u8)~HDMI_PHY_HPD);
663
664 /* clear hotplug interrupts */
665 write32(&hdmi_regs->ih_phy_stat0, HDMI_IH_PHY_STAT0_HPD);
666 }
667
hdmi_get_plug_in_status(void)668 static u8 hdmi_get_plug_in_status(void)
669 {
670 u8 val = read32(&hdmi_regs->phy_stat0) & HDMI_PHY_HPD;
671
672 return !!(val);
673 }
674
hdmi_wait_for_hpd(void)675 static int hdmi_wait_for_hpd(void)
676 {
677 struct stopwatch hpd;
678
679 stopwatch_init_msecs_expire(&hpd, 30000);
680 do {
681 if (hdmi_get_plug_in_status())
682 return 0;
683 udelay(100);
684 } while (!stopwatch_expired(&hpd));
685
686 return -1;
687 }
688
hdmi_ddc_wait_i2c_done(int msec)689 static int hdmi_ddc_wait_i2c_done(int msec)
690 {
691 struct stopwatch ddci2c_done;
692 u32 val;
693
694 stopwatch_init_msecs_expire(&ddci2c_done, msec);
695 do {
696 val = read32(&hdmi_regs->ih_i2cm_stat0);
697 if (val & 0x2) {
698 write32(&hdmi_regs->ih_i2cm_stat0, val);
699 return 0;
700 }
701
702 udelay(100);
703 } while (!stopwatch_expired(&ddci2c_done));
704
705 return 1;
706 }
707
hdmi_ddc_reset(void)708 static void hdmi_ddc_reset(void)
709 {
710 clrsetbits32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ,
711 HDMI_I2CM_SOFTRSTZ);
712 }
713
hdmi_read_edid(int block,u8 * buff)714 static int hdmi_read_edid(int block, u8 *buff)
715 {
716 int shift = (block % 2) * 0x80;
717 int edid_read_err = 0;
718 u32 trytime = 5;
719 u32 n, j, val;
720
721 /* set ddc i2c clk which derived from ddc_clk to 100kHz */
722 write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a);
723 write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d);
724 clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,
725 HDMI_I2CM_DIV_STD_MODE);
726
727 write32(&hdmi_regs->i2cm_slave, HDMI_I2CM_SLAVE_DDC_ADDR);
728 write32(&hdmi_regs->i2cm_segaddr, HDMI_I2CM_SEGADDR_DDC);
729 write32(&hdmi_regs->i2cm_segptr, block >> 1);
730
731 while (trytime--) {
732 edid_read_err = 0;
733
734 for (n = 0; n < HDMI_EDID_BLOCK_SIZE/8; n++) {
735 write32(&hdmi_regs->i2cmess, shift + 8 * n);
736
737 if (block == 0)
738 clrsetbits32(&hdmi_regs->i2cm_operation,
739 HDMI_I2CM_OPT_RD8,
740 HDMI_I2CM_OPT_RD8);
741 else
742 clrsetbits32(&hdmi_regs->i2cm_operation,
743 HDMI_I2CM_OPT_RD8_EXT,
744 HDMI_I2CM_OPT_RD8_EXT);
745
746 if (hdmi_ddc_wait_i2c_done(10)) {
747 hdmi_ddc_reset();
748 edid_read_err = 1;
749 break;
750 }
751
752 for (j = 0; j < 8; j++) {
753 val = read32(&hdmi_regs->i2cm_buf0 + j);
754 buff[8 * n + j] = val;
755 }
756 }
757
758 if (!edid_read_err)
759 break;
760 }
761
762 return edid_read_err;
763 }
764
rk_hdmi_get_edid(struct edid * edid)765 int rk_hdmi_get_edid(struct edid *edid)
766 {
767 u8 edid_buf[HDMI_EDID_BLOCK_SIZE * 2];
768 u32 edid_size = HDMI_EDID_BLOCK_SIZE;
769 gpio_t hdmi_i2c_sda = GPIO(7, C, 3);
770 gpio_t hdmi_i2c_scl = GPIO(7, C, 4);
771 int ret;
772
773 /* If SDA is low, try to clock once to fix it */
774 gpio_input_pullup(hdmi_i2c_sda);
775 if (gpio_get(hdmi_i2c_sda) == 0) {
776 gpio_output(hdmi_i2c_scl, 0);
777 udelay(1000);
778 gpio_input_pullup(hdmi_i2c_scl);
779 udelay(1000);
780 }
781
782 /* HDMI I2C */
783 write32(&rk3288_grf->iomux_i2c5sda, IOMUX_HDMI_EDP_I2C_SDA);
784 write32(&rk3288_grf->iomux_i2c5scl, IOMUX_HDMI_EDP_I2C_SCL);
785
786 ret = hdmi_read_edid(0, edid_buf);
787 if (ret) {
788 hdmi_debug("failed to read edid.\n");
789 return -1;
790 }
791
792 if (edid_buf[0x7e] != 0) {
793 hdmi_read_edid(1, edid_buf + HDMI_EDID_BLOCK_SIZE);
794 edid_size += HDMI_EDID_BLOCK_SIZE;
795 }
796
797 /* Assume usage of HDMI implies an external display in which case
798 * we should be lenient about errors that the EDID decoder finds. */
799 if (decode_edid(edid_buf, edid_size, edid) != EDID_CONFORMANT)
800 hdmi_debug("failed to decode edid.\n");
801
802 /* Try 480p for best compatibility. */
803 if (set_display_mode(edid, EDID_MODE_640x480_60Hz))
804 hdmi_debug("failed to set mode to 640x480@60Hz\n");
805
806 return 0;
807 }
808
rk_hdmi_enable(const struct edid * edid)809 int rk_hdmi_enable(const struct edid *edid)
810 {
811 hdmi_setup(edid);
812
813 return 0;
814 }
815
rk_hdmi_init(u32 vop_id)816 int rk_hdmi_init(u32 vop_id)
817 {
818 int ret;
819 u32 val;
820
821 /* hdmi source select hdmi controller */
822 write32(&rk3288_grf->soc_con6, RK_SETBITS(1 << 15));
823
824 /* hdmi data from vop id */
825 val = (vop_id == 1) ? RK_SETBITS(1 << 4) : RK_CLRBITS(1 << 4);
826 write32(&rk3288_grf->soc_con6, val);
827
828 ret = hdmi_wait_for_hpd();
829 if (ret < 0) {
830 hdmi_debug("hdmi can not get hpd signal\n");
831 return -1;
832 }
833
834 hdmi_init_interrupt();
835
836 hdmi_debug("hdmi init success\n");
837
838 return 0;
839 }
840