1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * SPDX-License-Identifier: MIT
9 */
10
11 #ifndef RADV_IMAGE_H
12 #define RADV_IMAGE_H
13
14 #include "ac_surface.h"
15
16 #include "radv_device.h"
17 #include "radv_physical_device.h"
18 #include "radv_radeon_winsys.h"
19
20 #include "vk_format.h"
21 #include "vk_image.h"
22
23 static const VkImageUsageFlags RADV_IMAGE_USAGE_WRITE_BITS =
24 VK_IMAGE_USAGE_TRANSFER_DST_BIT | VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT |
25 VK_IMAGE_USAGE_STORAGE_BIT;
26
27 struct radv_image_plane {
28 VkFormat format;
29 struct radeon_surf surface;
30 };
31
32 struct radv_image_binding {
33 /* Set when bound */
34 struct radeon_winsys_bo *bo;
35 VkDeviceSize offset;
36 uint64_t bo_va;
37 uint64_t range;
38 };
39
40 struct radv_image {
41 struct vk_image vk;
42
43 VkDeviceSize size;
44 uint32_t alignment;
45
46 unsigned queue_family_mask;
47 bool exclusive;
48 bool shareable;
49 bool l2_coherent;
50 bool dcc_sign_reinterpret;
51 bool support_comp_to_single;
52
53 struct radv_image_binding bindings[3];
54 bool tc_compatible_cmask;
55
56 uint64_t clear_value_offset;
57 uint64_t fce_pred_offset;
58 uint64_t dcc_pred_offset;
59
60 /*
61 * Metadata for the TC-compat zrange workaround. If the 32-bit value
62 * stored at this offset is UINT_MAX, the driver will emit
63 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
64 * SET_CONTEXT_REG packet.
65 */
66 uint64_t tc_compat_zrange_offset;
67
68 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
69 VkDeviceMemory owned_memory;
70
71 unsigned plane_count;
72 bool disjoint;
73 struct radv_image_plane planes[0];
74 };
75
76 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image, vk.base, VkImage, VK_OBJECT_TYPE_IMAGE)
77
78 static inline uint64_t
radv_image_get_va(const struct radv_image * image,uint32_t bind_idx)79 radv_image_get_va(const struct radv_image *image, uint32_t bind_idx)
80 {
81 return radv_buffer_get_va(image->bindings[bind_idx].bo) + image->bindings[bind_idx].offset;
82 }
83
84 static inline bool
radv_image_extent_compare(const struct radv_image * image,const VkExtent3D * extent)85 radv_image_extent_compare(const struct radv_image *image, const VkExtent3D *extent)
86 {
87 if (extent->width != image->vk.extent.width || extent->height != image->vk.extent.height ||
88 extent->depth != image->vk.extent.depth)
89 return false;
90 return true;
91 }
92
93 /**
94 * Return whether the image has CMASK metadata for color surfaces.
95 */
96 static inline bool
radv_image_has_cmask(const struct radv_image * image)97 radv_image_has_cmask(const struct radv_image *image)
98 {
99 return image->planes[0].surface.cmask_offset;
100 }
101
102 /**
103 * Return whether the image has FMASK metadata for color surfaces.
104 */
105 static inline bool
radv_image_has_fmask(const struct radv_image * image)106 radv_image_has_fmask(const struct radv_image *image)
107 {
108 return image->planes[0].surface.fmask_offset;
109 }
110
111 /**
112 * Return whether the image has DCC metadata for color surfaces.
113 */
114 static inline bool
radv_image_has_dcc(const struct radv_image * image)115 radv_image_has_dcc(const struct radv_image *image)
116 {
117 return !(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) && image->planes[0].surface.meta_offset;
118 }
119
120 /**
121 * Return whether the image is TC-compatible CMASK.
122 */
123 static inline bool
radv_image_is_tc_compat_cmask(const struct radv_image * image)124 radv_image_is_tc_compat_cmask(const struct radv_image *image)
125 {
126 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
127 }
128
129 /**
130 * Return whether DCC metadata is enabled for a level.
131 */
132 static inline bool
radv_dcc_enabled(const struct radv_image * image,unsigned level)133 radv_dcc_enabled(const struct radv_image *image, unsigned level)
134 {
135 return radv_image_has_dcc(image) && level < image->planes[0].surface.num_meta_levels;
136 }
137
138 /**
139 * Return whether the image has CB metadata.
140 */
141 static inline bool
radv_image_has_CB_metadata(const struct radv_image * image)142 radv_image_has_CB_metadata(const struct radv_image *image)
143 {
144 return radv_image_has_cmask(image) || radv_image_has_fmask(image) || radv_image_has_dcc(image);
145 }
146
147 /**
148 * Return whether the image has HTILE metadata for depth surfaces.
149 */
150 static inline bool
radv_image_has_htile(const struct radv_image * image)151 radv_image_has_htile(const struct radv_image *image)
152 {
153 return image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER && image->planes[0].surface.meta_size;
154 }
155
156 /**
157 * Return whether the image has VRS HTILE metadata for depth surfaces
158 */
159 static inline bool
radv_image_has_vrs_htile(const struct radv_device * device,const struct radv_image * image)160 radv_image_has_vrs_htile(const struct radv_device *device, const struct radv_image *image)
161 {
162 const struct radv_physical_device *pdev = radv_device_physical(device);
163 const enum amd_gfx_level gfx_level = pdev->info.gfx_level;
164
165 /* Any depth buffer can potentially use VRS on GFX10.3. */
166 return gfx_level == GFX10_3 && device->vk.enabled_features.attachmentFragmentShadingRate &&
167 radv_image_has_htile(image) && (image->vk.usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT);
168 }
169
170 /**
171 * Return whether HTILE metadata is enabled for a level.
172 */
173 static inline bool
radv_htile_enabled(const struct radv_image * image,unsigned level)174 radv_htile_enabled(const struct radv_image *image, unsigned level)
175 {
176 return radv_image_has_htile(image) && level < image->planes[0].surface.num_meta_levels;
177 }
178
179 /**
180 * Return whether the image is TC-compatible HTILE.
181 */
182 static inline bool
radv_image_is_tc_compat_htile(const struct radv_image * image)183 radv_image_is_tc_compat_htile(const struct radv_image *image)
184 {
185 return radv_image_has_htile(image) && (image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE);
186 }
187
188 /**
189 * Return whether the entire HTILE buffer can be used for depth in order to
190 * improve HiZ Z-Range precision.
191 */
192 static inline bool
radv_image_tile_stencil_disabled(const struct radv_device * device,const struct radv_image * image)193 radv_image_tile_stencil_disabled(const struct radv_device *device, const struct radv_image *image)
194 {
195 const struct radv_physical_device *pdev = radv_device_physical(device);
196
197 if (pdev->info.gfx_level >= GFX9) {
198 return !vk_format_has_stencil(image->vk.format) && !radv_image_has_vrs_htile(device, image);
199 } else {
200 /* Due to a hw bug, TILE_STENCIL_DISABLE must be set to 0 for
201 * the TC-compat ZRANGE issue even if no stencil is used.
202 */
203 return !vk_format_has_stencil(image->vk.format) && !radv_image_is_tc_compat_htile(image);
204 }
205 }
206
207 static inline bool
radv_image_has_clear_value(const struct radv_image * image)208 radv_image_has_clear_value(const struct radv_image *image)
209 {
210 return image->clear_value_offset != 0;
211 }
212
213 static inline uint64_t
radv_image_get_fast_clear_va(const struct radv_image * image,uint32_t base_level)214 radv_image_get_fast_clear_va(const struct radv_image *image, uint32_t base_level)
215 {
216 assert(radv_image_has_clear_value(image));
217
218 uint64_t va = radv_image_get_va(image, 0);
219 va += image->clear_value_offset + base_level * 8;
220 return va;
221 }
222
223 static inline uint64_t
radv_image_get_fce_pred_va(const struct radv_image * image,uint32_t base_level)224 radv_image_get_fce_pred_va(const struct radv_image *image, uint32_t base_level)
225 {
226 assert(image->fce_pred_offset != 0);
227
228 uint64_t va = radv_image_get_va(image, 0);
229 va += image->fce_pred_offset + base_level * 8;
230 return va;
231 }
232
233 static inline uint64_t
radv_image_get_dcc_pred_va(const struct radv_image * image,uint32_t base_level)234 radv_image_get_dcc_pred_va(const struct radv_image *image, uint32_t base_level)
235 {
236 assert(image->dcc_pred_offset != 0);
237
238 uint64_t va = radv_image_get_va(image, 0);
239 va += image->dcc_pred_offset + base_level * 8;
240 return va;
241 }
242
243 static inline uint64_t
radv_get_tc_compat_zrange_va(const struct radv_image * image,uint32_t base_level)244 radv_get_tc_compat_zrange_va(const struct radv_image *image, uint32_t base_level)
245 {
246 assert(image->tc_compat_zrange_offset != 0);
247
248 uint64_t va = radv_image_get_va(image, 0);
249 va += image->tc_compat_zrange_offset + base_level * 4;
250 return va;
251 }
252
253 static inline uint64_t
radv_get_ds_clear_value_va(const struct radv_image * image,uint32_t base_level)254 radv_get_ds_clear_value_va(const struct radv_image *image, uint32_t base_level)
255 {
256 assert(radv_image_has_clear_value(image));
257
258 uint64_t va = radv_image_get_va(image, 0);
259 va += image->clear_value_offset + base_level * 8;
260 return va;
261 }
262
263 static inline uint32_t
radv_get_htile_initial_value(const struct radv_device * device,const struct radv_image * image)264 radv_get_htile_initial_value(const struct radv_device *device, const struct radv_image *image)
265 {
266 uint32_t initial_value;
267
268 if (radv_image_tile_stencil_disabled(device, image)) {
269 /* Z only (no stencil):
270 *
271 * |31 18|17 4|3 0|
272 * +---------+---------+-------+
273 * | Max Z | Min Z | ZMask |
274 */
275 initial_value = 0xfffc000f;
276 } else {
277 /* Z and stencil:
278 *
279 * |31 12|11 10|9 8|7 6|5 4|3 0|
280 * +-----------+-----+------+-----+-----+-------+
281 * | Z Range | | SMem | SR1 | SR0 | ZMask |
282 *
283 * SR0/SR1 contains the stencil test results. Initializing
284 * SR0/SR1 to 0x3 means the stencil test result is unknown.
285 *
286 * Z, stencil and 4 bit VRS encoding:
287 * |31 12|11 10|9 8|7 6|5 4|3 0|
288 * +-----------+------------+------+------------+-----+-------+
289 * | Z Range | VRS y-rate | SMem | VRS x-rate | SR0 | ZMask |
290 */
291 if (radv_image_has_vrs_htile(device, image)) {
292 /* Initialize the VRS x-rate value at 0, so the hw interprets it as 1 sample. */
293 initial_value = 0xfffff33f;
294 } else {
295 initial_value = 0xfffff3ff;
296 }
297 }
298
299 return initial_value;
300 }
301
302 static inline bool
radv_image_get_iterate256(const struct radv_device * device,struct radv_image * image)303 radv_image_get_iterate256(const struct radv_device *device, struct radv_image *image)
304 {
305 const struct radv_physical_device *pdev = radv_device_physical(device);
306
307 /* ITERATE_256 is required for depth or stencil MSAA images that are TC-compatible HTILE. */
308 return pdev->info.gfx_level >= GFX10 && radv_image_is_tc_compat_htile(image) && image->vk.samples > 1;
309 }
310
311 bool radv_are_formats_dcc_compatible(const struct radv_physical_device *pdev, const void *pNext, VkFormat format,
312 VkImageCreateFlags flags, bool *sign_reinterpret);
313
314 bool radv_image_use_dcc_image_stores(const struct radv_device *device, const struct radv_image *image);
315
316 bool radv_image_use_dcc_predication(const struct radv_device *device, const struct radv_image *image);
317
318 void radv_compose_swizzle(const struct util_format_description *desc, const VkComponentMapping *mapping,
319 enum pipe_swizzle swizzle[4]);
320
321 void radv_init_metadata(struct radv_device *device, struct radv_image *image, struct radeon_bo_metadata *metadata);
322
323 void radv_image_override_offset_stride(struct radv_device *device, struct radv_image *image, uint64_t offset,
324 uint32_t stride);
325
326 bool radv_image_can_fast_clear(const struct radv_device *device, const struct radv_image *image);
327
328 struct ac_surf_info radv_get_ac_surf_info(struct radv_device *device, const struct radv_image *image);
329
330 struct radv_image_create_info {
331 const VkImageCreateInfo *vk_info;
332 bool scanout;
333 bool no_metadata_planes;
334 bool prime_blit_src;
335 const struct radeon_bo_metadata *bo_metadata;
336 };
337
338 VkResult radv_image_create_layout(struct radv_device *device, struct radv_image_create_info create_info,
339 const struct VkImageDrmFormatModifierExplicitCreateInfoEXT *mod_info,
340 const struct VkVideoProfileListInfoKHR *profile_list, struct radv_image *image);
341
342 VkResult radv_image_create(VkDevice _device, const struct radv_image_create_info *info,
343 const VkAllocationCallbacks *alloc, VkImage *pImage, bool is_internal);
344
345 unsigned radv_plane_from_aspect(VkImageAspectFlags mask);
346
347 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
348
349 /* Whether the image has a htile that is known consistent with the contents of
350 * the image and is allowed to be in compressed form.
351 *
352 * If this is false reads that don't use the htile should be able to return
353 * correct results.
354 */
355 bool radv_layout_is_htile_compressed(const struct radv_device *device, const struct radv_image *image,
356 VkImageLayout layout, unsigned queue_mask);
357
358 bool radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_image *image, unsigned level,
359 VkImageLayout layout, unsigned queue_mask);
360
361 bool radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_image *image, unsigned level,
362 VkImageLayout layout, unsigned queue_mask);
363
364 enum radv_fmask_compression {
365 RADV_FMASK_COMPRESSION_NONE,
366 RADV_FMASK_COMPRESSION_PARTIAL,
367 RADV_FMASK_COMPRESSION_FULL,
368 };
369
370 enum radv_fmask_compression radv_layout_fmask_compression(const struct radv_device *device,
371 const struct radv_image *image, VkImageLayout layout,
372 unsigned queue_mask);
373
374 unsigned radv_image_queue_family_mask(const struct radv_image *image, enum radv_queue_family family,
375 enum radv_queue_family queue_family);
376
377 bool radv_image_is_renderable(const struct radv_device *device, const struct radv_image *image);
378
379 #endif /* RADV_IMAGE_H */
380