1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_QUALCOMM_COMMON_CLOCK_H__ 4 #define __SOC_QUALCOMM_COMMON_CLOCK_H__ 5 6 #define QCOM_CLOCK_DIV(div) (2 * div - 1) 7 8 /* Root Clock Generator */ 9 struct clock_rcg { 10 u32 rcg_cmd; 11 u32 rcg_cfg; 12 }; 13 14 /* Root Clock Generator with MND */ 15 struct clock_rcg_mnd { 16 struct clock_rcg clock; 17 u32 m; 18 u32 n; 19 u32 d_2; 20 }; 21 22 /* DFS controlled Root Clock Generator */ 23 struct clock_rcg_dfsr { 24 u32 cmd_dfsr; 25 u8 _res0[0x20 - 0x1c]; 26 u32 perf_dfsr[8]; 27 u8 _res1[0x60 - 0x40]; 28 u32 perf_m_dfsr[8]; 29 u8 _res2[0xa0 - 0x80]; 30 u32 perf_n_dfsr[8]; 31 u8 _res3[0xe0 - 0xc0]; 32 u32 perf_d_dfsr[8]; 33 u8 _res4[0x130 - 0x100]; 34 }; 35 36 /* Clock Frequency Table */ 37 struct clock_freq_config { 38 uint32_t hz; 39 uint8_t src; 40 uint8_t div; 41 uint16_t m; 42 uint16_t n; 43 uint16_t d_2; 44 }; 45 46 struct qupv3_clock { 47 u32 cbcr; 48 struct clock_rcg_mnd clk; 49 struct clock_rcg_dfsr dfsr_clk; 50 }; 51 52 /* PLL Configuration */ 53 struct alpha_pll_reg_val_config { 54 void *reg_mode; 55 u32 mode_val; 56 void *reg_l; 57 u32 l_val; 58 void *reg_cal_l; 59 u32 cal_l_val; 60 void *reg_user_ctl; 61 u32 user_ctl_val; 62 void *reg_user_ctl_hi; 63 u32 user_ctl_hi_val; 64 void *reg_user_ctl_hi1; 65 u32 user_ctl_hi1_val; 66 void *reg_config_ctl; 67 u32 config_ctl_val; 68 void *reg_config_ctl_hi; 69 u32 config_ctl_hi_val; 70 void *reg_config_ctl_hi1; 71 u32 config_ctl_hi1_val; 72 void *reg_alpha; 73 u32 alpha_val; 74 void *reg_opmode; 75 void *reg_apcs_pll_br_en; 76 bool fsm_enable; 77 }; 78 79 enum clk_ctl_gpll_user_ctl { 80 PLL_PLLOUT_MAIN_SHFT = 0, 81 PLL_PLLOUT_EVEN_SHFT = 1, 82 PLL_PLLOUT_ODD_SHFT = 2, 83 PLL_POST_DIV_EVEN_SHFT = 8, 84 PLL_POST_DIV_ODD_SHFT = 12, 85 PLL_PLLOUT_EVEN_BMSK = 0x2, 86 }; 87 88 enum gpll_mode { 89 PLL_LOCK_DET_BMSK = 0x80000000, 90 PLL_BYPASSNL_BMSK = 0x2, 91 PLL_OUTCTRL_BMSK = 0x1, 92 PLL_USERCTL_BMSK = 0xF, 93 PLL_STANDBY_MODE = 0, 94 PLL_RUN_MODE = 1, 95 PLL_OPMODE_SHFT = 0, 96 PLL_OUTCTRL_SHFT = 0, 97 PLL_BYPASSNL_SHFT = 1, 98 PLL_RESET_SHFT = 2, 99 PLL_RESET_N_SHFT = 2, 100 PLL_FSM_EN_SHFT = 20, 101 }; 102 103 enum clk_ctl_cfg_rcgr { 104 CLK_CTL_CFG_SRC_DIV_SHFT = 0, 105 CLK_CTL_CFG_SRC_SEL_SHFT = 8, 106 CLK_CTL_CFG_MODE_SHFT = 12, 107 }; 108 109 enum clk_ctl_cmd_rcgr { 110 CLK_CTL_CMD_UPDATE_SHFT = 0, 111 }; 112 113 enum clk_ctl_cbcr { 114 CLK_CTL_EN_SHFT = 0, 115 CLK_CTL_OFF_SHFT = 31, 116 CLK_CTL_EN_BMSK = 0x1, 117 CLK_CTL_OFF_BMSK = 0x80000000, 118 }; 119 120 enum clk_ctl_rcg_mnd { 121 RCG_MODE_DUAL_EDGE = 2, 122 CLK_CTL_RCG_MND_SHFT = 0, 123 CLK_CTL_RCG_MND_BMSK = 0xFFFF, 124 }; 125 126 enum clk_ctl_bcr { 127 CLK_CTL_BCR_BLK_SHFT = 0, 128 CLK_CTL_BCR_BLK_BMSK = 0x1, 129 }; 130 131 enum clk_ctl_dfsr { 132 CLK_CTL_CMD_DFSR_SHFT = 0, 133 CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15, 134 CLK_CTL_CMD_DFSR_BMSK = 0x1, 135 }; 136 137 #define GDSC_ENABLE_BIT 0 138 139 enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, 140 uint32_t vote_bit); 141 142 enum cb_err clock_enable(void *cbcr_addr); 143 144 enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr); 145 146 void clock_reset_bcr(void *bcr_addr, bool assert); 147 148 /* 149 * clock_configure(): Configure the clock at the given clock speed (hz). If hz 150 * does not match any entries in the clk_cfg array, will throw and error and die(). 151 * 152 * @param clk struct clock_rcg pointer (root clock generator) 153 * @param clk_cfg Array with possible clock configurations 154 * @param hz frequency of clock to set 155 * @param num_perfs size of clock array 156 */ 157 enum cb_err clock_configure(struct clock_rcg *clk, struct clock_freq_config *clk_cfg, 158 uint32_t hz, uint32_t num_perfs); 159 160 void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg, 161 uint32_t num_perfs); 162 163 enum cb_err clock_configure_enable_gpll(struct alpha_pll_reg_val_config *cfg, 164 bool enable, int br_enable); 165 enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg); 166 167 enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg); 168 169 struct aoss { 170 u8 _res0[0x50020]; 171 u32 aoss_cc_reset_status; 172 u8 _res1[0x5002c - 0x50024]; 173 u32 aoss_cc_apcs_misc; 174 }; 175 check_member(aoss, aoss_cc_reset_status, 0x50020); 176 check_member(aoss, aoss_cc_apcs_misc, 0x5002c); 177 178 struct shrm { 179 u32 shrm_sproc_ctrl; 180 }; 181 182 void clock_reset_subsystem(u32 *misc, u32 shft); 183 184 #endif 185