1 /*
2  * Copyright (c) 2014 Travis Geiselbrecht
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining
5  * a copy of this software and associated documentation files
6  * (the "Software"), to deal in the Software without restriction,
7  * including without limitation the rights to use, copy, modify, merge,
8  * publish, distribute, sublicense, and/or sell copies of the Software,
9  * and to permit persons to whom the Software is furnished to do so,
10  * subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be
13  * included in all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19  * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #include <dev/cache/pl310.h>
24 
25 #include <assert.h>
26 #include <trace.h>
27 #include <err.h>
28 #include <reg.h>
29 #include <stdlib.h>
30 #include <arch.h>
31 #include <arch/arm/mmu.h>
32 #include <dev/cache/pl310_config.h>
33 #include <lk/init.h>
34 
35 /* configuration of the pl310 comes from #define space */
36 #ifndef PL310_BASE
37 #error need to define PL310_BASE
38 #endif
39 
40 #define LOCAL_TRACE 0
41 
42 #define PL310_REG(reg) (*REG32(PL310_BASE + (reg)))
43 
44 /* registers */
45 #define REG0_CACHE_ID              0x000
46 #define REG0_CACHE_TYPE            0x004
47 #define REG1_CONTROL               0x100
48 #define REG1_AUX_CONTROL           0x104
49 #define REG1_TAG_RAM_CONTROL       0x108
50 #define REG1_DATA_RAM_CONTROL      0x10c
51 #define REG2_EV_COUNTER_CTRL       0x200
52 #define REG2_EV_COUNTER1_CFG       0x204
53 #define REG2_EV_COUNTER0_CFG       0x208
54 #define REG2_EV_COUNTER1           0x20c
55 #define REG2_EV_COUNTER0           0x210
56 #define REG2_INT_MASK              0x214
57 #define REG2_INT_MASK_STATUS       0x218
58 #define REG2_INT_RAW_STATUS        0x21c
59 #define REG2_INT_CLEAR             0x220
60 #define REG7_CACHE_SYNC            0x730
61 #define REG7_INV_PA                0x770
62 #define REG7_INV_WAY               0x77c
63 #define REG7_CLEAN_PA              0x7b0
64 #define REG7_CLEAN_INDEX           0x7b8
65 #define REG7_CLEAN_WAY             0x7bc
66 #define REG7_CLEAN_INV_PA          0x7f0
67 #define REG7_CLEAN_INV_INDEX       0x7f8
68 #define REG7_CLEAN_INV_WAY         0x7fc
69 #define REG9_D_LOCKDOWN0           0x900
70 #define REG9_I_LOCKDOWN0           0x904
71 #define REG9_D_LOCKDOWN1           0x908
72 #define REG9_I_LOCKDOWN1           0x90c
73 #define REG9_D_LOCKDOWN2           0x910
74 #define REG9_I_LOCKDOWN2           0x914
75 #define REG9_D_LOCKDOWN3           0x918
76 #define REG9_I_LOCKDOWN3           0x91c
77 #define REG9_D_LOCKDOWN4           0x920
78 #define REG9_I_LOCKDOWN4           0x924
79 #define REG9_D_LOCKDOWN5           0x928
80 #define REG9_I_LOCKDOWN5           0x92c
81 #define REG9_D_LOCKDOWN6           0x930
82 #define REG9_I_LOCKDOWN6           0x934
83 #define REG9_D_LOCKDOWN7           0x938
84 #define REG9_I_LOCKDOWN7           0x93c
85 #define REG9_LOCK_LINE_EN          0x950
86 #define REG9_UNLOCK_WAY            0x954
87 #define REG12_ADDR_FILTERING_START 0xc00
88 #define REG12_ADDR_FILTERING_END   0xc04
89 #define REG15_DEBUG_CTRL           0xf40
90 #define REG15_PREFETCH_CTRL        0xf60
91 #define REG15_POWER_CTRL           0xf80
92 
pl310_enabled(void)93 static inline bool pl310_enabled(void)
94 {
95     return !!(PL310_REG(REG1_CONTROL) & 1);
96 }
97 
pl310_init(uint level)98 static void pl310_init(uint level)
99 {
100     /* make sure it's already disabled */
101     DEBUG_ASSERT(!pl310_enabled());
102 
103     /* set tag and data ram latency */
104     PL310_REG(REG1_TAG_RAM_CONTROL) = PL310_TAG_RAM_LATENCY;
105     PL310_REG(REG1_DATA_RAM_CONTROL) = PL310_DATA_RAM_LATENCY;
106 
107     /* configure */
108     /* early BRESP enable, instruction/data prefetch, exclusive cache, full line of zero */
109     PL310_REG(REG1_AUX_CONTROL) |= (1<<30)|(1<<29)|(1<<28)|(1<<12)|(1<<0);
110 
111     /* flush all the ways */
112     PL310_REG(REG7_INV_WAY) = 0xffff;
113 }
114 
115 /* run just before arch_early_init so the L2 is ready to go when
116  * the arch code starts up the caching system.
117  */
118 LK_INIT_HOOK(pl310_init, pl310_init, LK_INIT_LEVEL_ARCH_EARLY - 1);
119 
pl310_set_enable(bool enable)120 status_t pl310_set_enable(bool enable)
121 {
122     LTRACEF("enable %d\n", enable);
123 
124     if (enable) {
125         if ((PL310_REG(REG1_CONTROL) & 1) == 0) {
126             /* if disabled */
127             pl310_invalidate();
128             PL310_REG(REG1_CONTROL) = 1;
129         }
130     } else {
131         if ((PL310_REG(REG1_CONTROL) & 1) == 1) {
132             /* if enabled */
133             pl310_flush_invalidate();
134             PL310_REG(REG1_CONTROL) = 0;
135             /* this seems to not always latch on the first try */
136             while (PL310_REG(REG1_CONTROL) & 1) {
137                 PL310_REG(REG1_CONTROL) = 0;
138             }
139         }
140     }
141 
142     return NO_ERROR;
143 }
144 
pl310_invalidate(void)145 void pl310_invalidate(void)
146 {
147     if (unlikely(!pl310_enabled()))
148         return;
149     PL310_REG(REG7_INV_WAY) = 0xffff;
150     while (PL310_REG(REG7_INV_WAY) != 0)
151         ;
152 }
153 
pl310_flush_invalidate(void)154 void pl310_flush_invalidate(void)
155 {
156     if (unlikely(!pl310_enabled()))
157         return;
158     PL310_REG(REG7_CLEAN_INV_WAY) = 0xffff;
159     while (PL310_REG(REG7_CLEAN_INV_WAY) != 0)
160         ;
161 }
162 
pl310_sync_range(void)163 void pl310_sync_range(void)
164 {
165     if (unlikely(!pl310_enabled()))
166         return;
167 
168     PL310_REG(REG7_CACHE_SYNC) = 1;
169 }
170 
171 #define PL310_LOOP_BODY(reg) \
172     if (unlikely(!pl310_enabled())) \
173         return; \
174  \
175     addr_t pa = 0; \
176     uint32_t last_pa_page = 1; \
177     addr_t last_va = start + len; \
178     start &= ~(CACHE_LINE - 1); \
179     while (start < last_va) { \
180         if (unlikely(pa / PAGE_SIZE != last_pa_page)) { \
181             /* get the physical address */ \
182             if (unlikely(arm_vtop(start, &pa))) \
183                 return; \
184             last_pa_page = pa / PAGE_SIZE; \
185         } \
186         PL310_REG(reg) = pa; \
187  \
188         pa += CACHE_LINE; \
189         start += CACHE_LINE; \
190     } \
191 \
192     PL310_REG(REG7_CACHE_SYNC) = 1;
193 
pl310_clean_range(addr_t start,size_t len)194 void pl310_clean_range(addr_t start, size_t len)
195 {
196     LTRACEF("start 0x%lx, len %zd\n", start, len);
197     PL310_LOOP_BODY(REG7_CLEAN_PA);
198 }
199 
pl310_clean_invalidate_range(addr_t start,size_t len)200 void pl310_clean_invalidate_range(addr_t start, size_t len)
201 {
202     LTRACEF("start 0x%lx, len %zd\n", start, len);
203     PL310_LOOP_BODY(REG7_CLEAN_INV_PA);
204 }
205 
pl310_invalidate_range(addr_t start,size_t len)206 void pl310_invalidate_range(addr_t start, size_t len)
207 {
208     LTRACEF("start 0x%lx, len %zd\n", start, len);
209     PL310_LOOP_BODY(REG7_INV_PA);
210 }
211 
pl310_pin_cache_range(addr_t start,size_t len)212 void pl310_pin_cache_range(addr_t start, size_t len)
213 {
214     len = round_up(len, CACHE_LINE);
215 
216     arch_disable_ints();
217 
218     arch_clean_invalidate_cache_range(start, len);
219 
220     PL310_REG(REG9_LOCK_LINE_EN) = 1;
221     DSB;
222 
223     while (len > 0) {
224         asm volatile("pld [%0]" :: "r"(start) : "memory");
225         start += CACHE_LINE;
226         len -= CACHE_LINE;
227     }
228 
229     DSB;
230     PL310_REG(REG9_LOCK_LINE_EN) = 0;
231 
232     arch_enable_ints();
233 }
234 
235