1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <amdblocks/biosram.h>
4 #include <amdblocks/ioapic.h>
5
6 #include "Porting.h"
7 #include "AGESA.h"
8
9 #include <device/device.h>
10 #include <northbridge/amd/agesa/state_machine.h>
11 #include <northbridge/amd/agesa/agesa_helper.h>
12 #include <northbridge/amd/nb_common.h>
13
platform_BeforeInitReset(struct sysinfo * cb,AMD_RESET_PARAMS * Reset)14 void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
15 {
16 }
17
platform_BeforeInitEarly(struct sysinfo * cb,AMD_EARLY_PARAMS * Early)18 void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
19 {
20 Early->GnbConfig.PsppPolicy = PsppDisabled;
21 }
22
platform_BeforeInitPost(struct sysinfo * cb,AMD_POST_PARAMS * Post)23 void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
24 {
25 Post->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE;
26 Post->MemConfig.UmaSize = 0;
27 Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24);
28 }
29
platform_AfterInitPost(struct sysinfo * cb,AMD_POST_PARAMS * Post)30 void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
31 {
32 /* If UMA is enabled we currently have it below TOP_MEM as well.
33 * UMA may or may not be cacheable, so Sub4GCacheTop could be
34 * higher than UmaBase. With UMA_NONE we see UmaBase==0. */
35 if (Post->MemConfig.UmaBase)
36 backup_top_of_low_cacheable(Post->MemConfig.UmaBase << 16);
37 else
38 backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop);
39 }
40
platform_BeforeInitEnv(struct sysinfo * cb,AMD_ENV_PARAMS * Env)41 void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
42 {
43 EmptyHeap();
44 }
45
platform_AfterInitEnv(struct sysinfo * cb,AMD_ENV_PARAMS * Env)46 void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
47 {
48 }
49
platform_BeforeInitMid(struct sysinfo * cb,AMD_MID_PARAMS * Mid)50 void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid)
51 {
52 amd_initcpuio();
53
54 /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
55 Mid->GnbMidConfiguration.iGpuVgaMode = 0;
56 Mid->GnbMidConfiguration.GnbIoapicAddress = IO_APIC2_ADDR;
57 }
58
platform_BeforeInitLate(struct sysinfo * cb,AMD_LATE_PARAMS * Late)59 void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
60 {
61 const struct device *iommu_dev = pcidev_on_root(0, 2);
62
63 if (iommu_dev && iommu_dev->enabled) {
64 /* According to AGESA headers these must be set to sane values
65 * when IOMMU build config is enabled otherwise AGESA will skip
66 * it during IOMMU init and IVRS generation.
67 */
68 Late->GnbLateConfiguration.GnbIoapicId = GNB_IOAPIC_ID;
69 Late->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID;
70 }
71
72 /* Make binaryPI use \_SB_ as processor object scope in PSTATE SSDT */
73 Late->PlatformConfig.ProcessorScopeInSb = true;
74
75 /* Code for creating CDIT requires hop count table. If it is not
76 * present AGESA_ERROR is returned, which confuses users. CDIT is not
77 * written to the ACPI tables anyway. */
78 Late->PlatformConfig.UserOptionCdit = 0;
79 }
80
platform_AfterInitLate(struct sysinfo * cb,AMD_LATE_PARAMS * Late)81 void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
82 {
83 }
84
platform_BeforeInitResume(struct sysinfo * cb,AMD_RESUME_PARAMS * Resume)85 void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
86 {
87 }
88
platform_AfterInitResume(struct sysinfo * cb,AMD_RESUME_PARAMS * Resume)89 void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
90 {
91 }
92
platform_BeforeS3LateRestore(struct sysinfo * cb,AMD_S3LATE_PARAMS * S3Late)93 void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
94 {
95 }
96
platform_AfterS3LateRestore(struct sysinfo * cb,AMD_S3LATE_PARAMS * S3Late)97 void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
98 {
99 amd_initcpuio();
100 }
101
platform_AfterS3Save(struct sysinfo * cb,AMD_S3SAVE_PARAMS * S3Save)102 void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save)
103 {
104 }
105