1 /*
2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch.h>
8 #include <arch_features.h>
9 #include <arch_helpers.h>
10 #include <lib/extensions/pmuv3.h>
11
init_mdcr_el2_hpmn(u_register_t mdcr_el2)12 static u_register_t init_mdcr_el2_hpmn(u_register_t mdcr_el2)
13 {
14 /*
15 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't
16 * throw anyone off who expects this to be sensible.
17 */
18 mdcr_el2 &= ~MDCR_EL2_HPMN_MASK;
19 mdcr_el2 |= ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & PMCR_EL0_N_MASK);
20
21 return mdcr_el2;
22 }
23
pmuv3_enable(cpu_context_t * ctx)24 void pmuv3_enable(cpu_context_t *ctx)
25 {
26 #if CTX_INCLUDE_EL2_REGS
27 u_register_t mdcr_el2_val;
28
29 mdcr_el2_val = read_el2_ctx_common(get_el2_sysregs_ctx(ctx), mdcr_el2);
30 mdcr_el2_val = init_mdcr_el2_hpmn(mdcr_el2_val);
31 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), mdcr_el2, mdcr_el2_val);
32 #endif /* CTX_INCLUDE_EL2_REGS */
33 }
34
mtpmu_disable_el3(u_register_t mdcr_el3)35 static u_register_t mtpmu_disable_el3(u_register_t mdcr_el3)
36 {
37 if (!is_feat_mtpmu_supported()) {
38 return mdcr_el3;
39 }
40
41 /*
42 * MDCR_EL3.MTPME = 0
43 * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>_EL0.MT is
44 * zero.
45 */
46 mdcr_el3 &= ~MDCR_MTPME_BIT;
47
48 return mdcr_el3;
49 }
50
pmuv3_init_el3(void)51 void pmuv3_init_el3(void)
52 {
53 u_register_t mdcr_el3 = read_mdcr_el3();
54
55 /* ---------------------------------------------------------------------
56 * Initialise MDCR_EL3, setting all fields rather than relying on hw.
57 * Some fields are architecturally UNKNOWN on reset.
58 *
59 * MDCR_EL3.MPMX: Set to zero to not affect event counters (when
60 * SPME = 0).
61 *
62 * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
63 * prohibited in EL3. This bit is RES0 in versions of the
64 * architecture with FEAT_PMUv3p7 not implemented.
65 *
66 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
67 * prohibited in Secure state. This bit is RES0 in versions of the
68 * architecture with FEAT_PMUv3p5 not implemented.
69 *
70 * MDCR_EL3.SPME: Set to zero so that event counting is prohibited in
71 * Secure state (and explicitly EL3 with later revisions). If ARMv8.2
72 * Debug is not implemented this bit does not have any effect on the
73 * counters unless there is support for the implementation defined
74 * authentication interface ExternalSecureNoninvasiveDebugEnabled().
75 *
76 * The SPME/MPMX combination is a little tricky. Below is a small
77 * summary if another combination is ever needed:
78 * SPME | MPMX | secure world | EL3
79 * -------------------------------------
80 * 0 | 0 | disabled | disabled
81 * 1 | 0 | enabled | enabled
82 * 0 | 1 | enabled | disabled
83 * 1 | 1 | enabled | disabled only for counters 0 to
84 * MDCR_EL2.HPMN - 1. Enabled for the rest
85 *
86 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
87 * accesses to all Performance Monitors registers do not trap to EL3.
88 */
89 mdcr_el3 = (mdcr_el3 | MDCR_SCCD_BIT | MDCR_MCCD_BIT) &
90 ~(MDCR_MPMX_BIT | MDCR_SPME_BIT | MDCR_TPM_BIT);
91 mdcr_el3 = mtpmu_disable_el3(mdcr_el3);
92 write_mdcr_el3(mdcr_el3);
93
94 /* ---------------------------------------------------------------------
95 * Initialise PMCR_EL0 setting all fields rather than relying
96 * on hw. Some fields are architecturally UNKNOWN on reset.
97 *
98 * PMCR_EL0.DP: Set to one so that the cycle counter,
99 * PMCCNTR_EL0 does not count when event counting is prohibited.
100 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not
101 * available
102 *
103 * PMCR_EL0.X: Set to zero to disable export of events.
104 *
105 * PMCR_EL0.C: Set to one to reset PMCCNTR_EL0 to zero.
106 *
107 * PMCR_EL0.P: Set to one to reset each event counter PMEVCNTR<n>_EL0 to
108 * zero.
109 *
110 * PMCR_EL0.E: Set to zero to disable cycle and event counters.
111 * ---------------------------------------------------------------------
112 */
113 write_pmcr_el0((read_pmcr_el0() | PMCR_EL0_DP_BIT | PMCR_EL0_C_BIT |
114 PMCR_EL0_P_BIT) & ~(PMCR_EL0_X_BIT | PMCR_EL0_E_BIT));
115 }
116
mtpmu_disable_el2(u_register_t mdcr_el2)117 static u_register_t mtpmu_disable_el2(u_register_t mdcr_el2)
118 {
119 if (!is_feat_mtpmu_supported()) {
120 return mdcr_el2;
121 }
122
123 /*
124 * MDCR_EL2.MTPME = 0
125 * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>_EL0.MT is
126 * zero.
127 */
128 mdcr_el2 &= ~MDCR_EL2_MTPME;
129
130 return mdcr_el2;
131 }
132
pmuv3_init_el2_unused(void)133 void pmuv3_init_el2_unused(void)
134 {
135 u_register_t mdcr_el2 = read_mdcr_el2();
136
137 /*
138 * Initialise MDCR_EL2, setting all fields rather than
139 * relying on hw. Some fields are architecturally
140 * UNKNOWN on reset.
141 *
142 * MDCR_EL2.HLP: Set to one so that event counter overflow, that is
143 * recorded in PMOVSCLR_EL0[0-30], occurs on the increment that changes
144 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is implemented.
145 * This bit is RES0 in versions of the architecture earlier than
146 * ARMv8.5, setting it to 1 doesn't have any effect on them.
147 *
148 * MDCR_EL2.HCCD: Set to one to prohibit cycle counting at EL2. This bit
149 * is RES0 in versions of the architecture with FEAT_PMUv3p5 not
150 * implemented.
151 *
152 * MDCR_EL2.HPMD: Set to one so that event counting is
153 * prohibited at EL2 for counter n < MDCR_EL2.HPMN. This bit is RES0
154 * in versions of the architecture with FEAT_PMUv3p1 not implemented.
155 *
156 * MDCR_EL2.HPME: Set to zero to disable event counters for counters
157 * n >= MDCR_EL2.HPMN.
158 *
159 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
160 * EL1 accesses to all Performance Monitors registers
161 * are not trapped to EL2.
162 *
163 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
164 * and EL1 accesses to the PMCR_EL0 or PMCR are not
165 * trapped to EL2.
166 */
167 mdcr_el2 = (mdcr_el2 | MDCR_EL2_HLP_BIT | MDCR_EL2_HPMD_BIT |
168 MDCR_EL2_HCCD_BIT) &
169 ~(MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | MDCR_EL2_TPMCR_BIT);
170 mdcr_el2 = init_mdcr_el2_hpmn(mdcr_el2);
171 mdcr_el2 = mtpmu_disable_el2(mdcr_el2);
172 write_mdcr_el2(mdcr_el2);
173 }
174