xref: /aosp_15_r20/external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-bgx.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1 #ifndef __BDK_CSRS_BGX_H__
2 #define __BDK_CSRS_BGX_H__
3 /* This file is auto-generated. Do not edit */
4 
5 /***********************license start***************
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43 
44 
45 /**
46  * @file
47  *
48  * Configuration and status register (CSR) address and type definitions for
49  * Cavium BGX.
50  *
51  * This file is auto generated. Do not edit.
52  *
53  */
54 
55 /**
56  * Enumeration bgx_bar_e
57  *
58  * BGX Base Address Register Enumeration
59  * Enumerates the base address registers.
60  */
61 #define BDK_BGX_BAR_E_BGXX_PF_BAR0(a) (0x87e0e0000000ll + 0x1000000ll * (a))
62 #define BDK_BGX_BAR_E_BGXX_PF_BAR0_SIZE 0x400000ull
63 #define BDK_BGX_BAR_E_BGXX_PF_BAR4(a) (0x87e0e0400000ll + 0x1000000ll * (a))
64 #define BDK_BGX_BAR_E_BGXX_PF_BAR4_SIZE 0x400000ull
65 
66 /**
67  * Enumeration bgx_int_vec_e
68  *
69  * BGX MSI-X Vector Enumeration
70  * Enumeration the MSI-X interrupt vectors.
71  */
72 #define BDK_BGX_INT_VEC_E_CMRX_INT(a) (0 + 7 * (a))
73 #define BDK_BGX_INT_VEC_E_CMR_MEM_INT (0x1c)
74 #define BDK_BGX_INT_VEC_E_GMPX_GMI_RX_INT(a) (5 + 7 * (a))
75 #define BDK_BGX_INT_VEC_E_GMPX_GMI_TX_INT(a) (6 + 7 * (a))
76 #define BDK_BGX_INT_VEC_E_GMPX_PCS_INT(a) (4 + 7 * (a))
77 #define BDK_BGX_INT_VEC_E_SMUX_RX_INT(a) (2 + 7 * (a))
78 #define BDK_BGX_INT_VEC_E_SMUX_TX_INT(a) (3 + 7 * (a))
79 #define BDK_BGX_INT_VEC_E_SPUX_INT(a) (1 + 7 * (a))
80 #define BDK_BGX_INT_VEC_E_SPU_MEM_INT (0x1d)
81 
82 /**
83  * Enumeration bgx_lmac_types_e
84  *
85  * BGX LMAC Type Enumeration
86  * Enumerates the LMAC Types that BGX supports.
87  */
88 #define BDK_BGX_LMAC_TYPES_E_FORTYG_R (4)
89 #define BDK_BGX_LMAC_TYPES_E_QSGMII (6)
90 #define BDK_BGX_LMAC_TYPES_E_RGMII (5)
91 #define BDK_BGX_LMAC_TYPES_E_RXAUI (2)
92 #define BDK_BGX_LMAC_TYPES_E_SGMII (0)
93 #define BDK_BGX_LMAC_TYPES_E_TENG_R (3)
94 #define BDK_BGX_LMAC_TYPES_E_XAUI (1)
95 
96 /**
97  * Enumeration bgx_opcode_e
98  *
99  * INTERNAL: BGX Error Opcode Enumeration
100  *
101  * Enumerates the error opcodes created by BGX and presented to NCSI/TNS/NIC.
102  */
103 #define BDK_BGX_OPCODE_E_RE_FCS (7)
104 #define BDK_BGX_OPCODE_E_RE_FCS_RCV (8)
105 #define BDK_BGX_OPCODE_E_RE_JABBER (2)
106 #define BDK_BGX_OPCODE_E_RE_NONE (0)
107 #define BDK_BGX_OPCODE_E_RE_PARTIAL (1)
108 #define BDK_BGX_OPCODE_E_RE_RX_CTL (0xb)
109 #define BDK_BGX_OPCODE_E_RE_SKIP (0xc)
110 #define BDK_BGX_OPCODE_E_RE_TERMINATE (9)
111 
112 /**
113  * Enumeration bgx_spu_br_train_cst_e
114  *
115  * BGX Training Coefficient Status Enumeration
116  * 2-bit status for each coefficient as defined in 802.3-2008, Table 72-5.
117  */
118 #define BDK_BGX_SPU_BR_TRAIN_CST_E_MAXIMUM (3)
119 #define BDK_BGX_SPU_BR_TRAIN_CST_E_MINIMUM (2)
120 #define BDK_BGX_SPU_BR_TRAIN_CST_E_NOT_UPDATED (0)
121 #define BDK_BGX_SPU_BR_TRAIN_CST_E_UPDATED (1)
122 
123 /**
124  * Enumeration bgx_spu_br_train_cup_e
125  *
126  * BGX Training Coefficient Enumeration
127  * 2-bit command for each coefficient as defined in 802.3-2008, Table 72-4.
128  */
129 #define BDK_BGX_SPU_BR_TRAIN_CUP_E_DECREMENT (1)
130 #define BDK_BGX_SPU_BR_TRAIN_CUP_E_HOLD (0)
131 #define BDK_BGX_SPU_BR_TRAIN_CUP_E_INCREMENT (2)
132 #define BDK_BGX_SPU_BR_TRAIN_CUP_E_RSV_CMD (3)
133 
134 /**
135  * Structure bgx_spu_br_lane_train_status_s
136  *
137  * BGX Lane Training Status Structure
138  * This is the group of lane status bits for a single lane in the BASE-R PMD status register
139  * (MDIO address 1.151) as defined in 802.3ba-2010, Table 45-55.
140  */
141 union bdk_bgx_spu_br_lane_train_status_s
142 {
143     uint32_t u;
144     struct bdk_bgx_spu_br_lane_train_status_s_s
145     {
146 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
147         uint32_t reserved_4_31         : 28;
148         uint32_t training_failure      : 1;  /**< [  3:  3] Link training failure. */
149         uint32_t training              : 1;  /**< [  2:  2] Link training state.
150                                                                  0 = Training in progress.
151                                                                  1 = Training has completed. */
152         uint32_t frame_lock            : 1;  /**< [  1:  1] Frame lock status. Set when training frame delineation has been detected. */
153         uint32_t rx_trained            : 1;  /**< [  0:  0] Receiver trained status.
154                                                                  0 = Receiver training.
155                                                                  1 = Receiver trained and ready to receive data for the lane. */
156 #else /* Word 0 - Little Endian */
157         uint32_t rx_trained            : 1;  /**< [  0:  0] Receiver trained status.
158                                                                  0 = Receiver training.
159                                                                  1 = Receiver trained and ready to receive data for the lane. */
160         uint32_t frame_lock            : 1;  /**< [  1:  1] Frame lock status. Set when training frame delineation has been detected. */
161         uint32_t training              : 1;  /**< [  2:  2] Link training state.
162                                                                  0 = Training in progress.
163                                                                  1 = Training has completed. */
164         uint32_t training_failure      : 1;  /**< [  3:  3] Link training failure. */
165         uint32_t reserved_4_31         : 28;
166 #endif /* Word 0 - End */
167     } s;
168     /* struct bdk_bgx_spu_br_lane_train_status_s_s cn; */
169 };
170 
171 /**
172  * Structure bgx_spu_br_train_cup_s
173  *
174  * BGX Lane Training Coeffiecient Structure
175  * This is the coefficient update field of the BASE-R link training packet as defined in
176  * 802.3-2008, Table 72-4.
177  */
178 union bdk_bgx_spu_br_train_cup_s
179 {
180     uint32_t u;
181     struct bdk_bgx_spu_br_train_cup_s_s
182     {
183 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
184         uint32_t reserved_14_31        : 18;
185         uint32_t preset                : 1;  /**< [ 13: 13] Preset. Set to indicate that all TX coefficients be set to a state where equalization is
186                                                                  turned off, i.e. the precursor (k = -1) and postcursor (k = +1) coefficients should be set
187                                                                  to 0 and the main
188                                                                  (k = 0) coefficient should be set to its maximum value. */
189         uint32_t init                  : 1;  /**< [ 12: 12] Initialize. Set to indicate that the TX coefficients should be set to meet the conditions
190                                                                  defined in 802.3-2008 sub-clause 72.6.10.4.2. */
191         uint32_t reserved_6_11         : 6;
192         uint32_t post_cup              : 2;  /**< [  5:  4] Post-cursor (k = +1) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
193                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
194         uint32_t main_cup              : 2;  /**< [  3:  2] Main (k = 0) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
195                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
196         uint32_t pre_cup               : 2;  /**< [  1:  0] Pre-cursor (k = -1) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
197                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
198 #else /* Word 0 - Little Endian */
199         uint32_t pre_cup               : 2;  /**< [  1:  0] Pre-cursor (k = -1) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
200                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
201         uint32_t main_cup              : 2;  /**< [  3:  2] Main (k = 0) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
202                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
203         uint32_t post_cup              : 2;  /**< [  5:  4] Post-cursor (k = +1) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
204                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
205         uint32_t reserved_6_11         : 6;
206         uint32_t init                  : 1;  /**< [ 12: 12] Initialize. Set to indicate that the TX coefficients should be set to meet the conditions
207                                                                  defined in 802.3-2008 sub-clause 72.6.10.4.2. */
208         uint32_t preset                : 1;  /**< [ 13: 13] Preset. Set to indicate that all TX coefficients be set to a state where equalization is
209                                                                  turned off, i.e. the precursor (k = -1) and postcursor (k = +1) coefficients should be set
210                                                                  to 0 and the main
211                                                                  (k = 0) coefficient should be set to its maximum value. */
212         uint32_t reserved_14_31        : 18;
213 #endif /* Word 0 - End */
214     } s;
215     struct bdk_bgx_spu_br_train_cup_s_cn
216     {
217 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
218         uint32_t reserved_16_31        : 16;
219         uint32_t reserved_14_15        : 2;
220         uint32_t preset                : 1;  /**< [ 13: 13] Preset. Set to indicate that all TX coefficients be set to a state where equalization is
221                                                                  turned off, i.e. the precursor (k = -1) and postcursor (k = +1) coefficients should be set
222                                                                  to 0 and the main
223                                                                  (k = 0) coefficient should be set to its maximum value. */
224         uint32_t init                  : 1;  /**< [ 12: 12] Initialize. Set to indicate that the TX coefficients should be set to meet the conditions
225                                                                  defined in 802.3-2008 sub-clause 72.6.10.4.2. */
226         uint32_t reserved_6_11         : 6;
227         uint32_t post_cup              : 2;  /**< [  5:  4] Post-cursor (k = +1) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
228                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
229         uint32_t main_cup              : 2;  /**< [  3:  2] Main (k = 0) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
230                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
231         uint32_t pre_cup               : 2;  /**< [  1:  0] Pre-cursor (k = -1) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
232                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
233 #else /* Word 0 - Little Endian */
234         uint32_t pre_cup               : 2;  /**< [  1:  0] Pre-cursor (k = -1) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
235                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
236         uint32_t main_cup              : 2;  /**< [  3:  2] Main (k = 0) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
237                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
238         uint32_t post_cup              : 2;  /**< [  5:  4] Post-cursor (k = +1) coefficient update. Valid when PRESET = INIT = 0. Enumerated by
239                                                                  BGX_SPU_BR_TRAIN_CUP_E. */
240         uint32_t reserved_6_11         : 6;
241         uint32_t init                  : 1;  /**< [ 12: 12] Initialize. Set to indicate that the TX coefficients should be set to meet the conditions
242                                                                  defined in 802.3-2008 sub-clause 72.6.10.4.2. */
243         uint32_t preset                : 1;  /**< [ 13: 13] Preset. Set to indicate that all TX coefficients be set to a state where equalization is
244                                                                  turned off, i.e. the precursor (k = -1) and postcursor (k = +1) coefficients should be set
245                                                                  to 0 and the main
246                                                                  (k = 0) coefficient should be set to its maximum value. */
247         uint32_t reserved_14_15        : 2;
248         uint32_t reserved_16_31        : 16;
249 #endif /* Word 0 - End */
250     } cn;
251 };
252 
253 /**
254  * Structure bgx_spu_br_train_rep_s
255  *
256  * BGX Training Report Structure
257  * This is the status report field of the BASE-R link training packet as defined in 802.3-2008,
258  * Table 72-5.
259  */
260 union bdk_bgx_spu_br_train_rep_s
261 {
262     uint32_t u;
263     struct bdk_bgx_spu_br_train_rep_s_s
264     {
265 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
266         uint32_t reserved_16_31        : 16;
267         uint32_t rx_ready              : 1;  /**< [ 15: 15] Receiver ready. Set to indicate that the local receiver has determined that training is
268                                                                  complete and is prepared to receive data. */
269         uint32_t reserved_6_14         : 9;
270         uint32_t post_cst              : 2;  /**< [  5:  4] Post-cursor (k = +1) coefficient status. Valid when PRESET = INIT = 0. Enumerated by
271                                                                  BGX_SPU_BR_TRAIN_CST_E. */
272         uint32_t main_cst              : 2;  /**< [  3:  2] Main (k = 0) coefficient status. Valid when PRESET = INIT = 0. Enumerated by
273                                                                  BGX_SPU_BR_TRAIN_CST_E. */
274         uint32_t pre_cst               : 2;  /**< [  1:  0] Pre-cursor (k = -1) coefficient status. Valid when PRESET = INIT = 0. Enumerated by
275                                                                  BGX_SPU_BR_TRAIN_CST_E. */
276 #else /* Word 0 - Little Endian */
277         uint32_t pre_cst               : 2;  /**< [  1:  0] Pre-cursor (k = -1) coefficient status. Valid when PRESET = INIT = 0. Enumerated by
278                                                                  BGX_SPU_BR_TRAIN_CST_E. */
279         uint32_t main_cst              : 2;  /**< [  3:  2] Main (k = 0) coefficient status. Valid when PRESET = INIT = 0. Enumerated by
280                                                                  BGX_SPU_BR_TRAIN_CST_E. */
281         uint32_t post_cst              : 2;  /**< [  5:  4] Post-cursor (k = +1) coefficient status. Valid when PRESET = INIT = 0. Enumerated by
282                                                                  BGX_SPU_BR_TRAIN_CST_E. */
283         uint32_t reserved_6_14         : 9;
284         uint32_t rx_ready              : 1;  /**< [ 15: 15] Receiver ready. Set to indicate that the local receiver has determined that training is
285                                                                  complete and is prepared to receive data. */
286         uint32_t reserved_16_31        : 16;
287 #endif /* Word 0 - End */
288     } s;
289     /* struct bdk_bgx_spu_br_train_rep_s_s cn; */
290 };
291 
292 /**
293  * Structure bgx_spu_sds_cu_s
294  *
295  * INTERNAL: BGX Training Coeffiecient Structure
296  *
297  * This structure is similar to BGX_SPU_BR_TRAIN_CUP_S format, but with reserved fields removed
298  * and [RCVR_READY] field added.
299  */
300 union bdk_bgx_spu_sds_cu_s
301 {
302     uint32_t u;
303     struct bdk_bgx_spu_sds_cu_s_s
304     {
305 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
306         uint32_t reserved_9_31         : 23;
307         uint32_t rcvr_ready            : 1;  /**< [  8:  8] See BGX_SPU_BR_TRAIN_REP_S[RX_READY]. */
308         uint32_t preset                : 1;  /**< [  7:  7] See BGX_SPU_BR_TRAIN_CUP_S[PRESET]. */
309         uint32_t initialize            : 1;  /**< [  6:  6] See BGX_SPU_BR_TRAIN_CUP_S[INIT]. */
310         uint32_t post_cu               : 2;  /**< [  5:  4] See BGX_SPU_BR_TRAIN_CUP_S[POST_CUP]. */
311         uint32_t main_cu               : 2;  /**< [  3:  2] See BGX_SPU_BR_TRAIN_CUP_S[MAIN_CUP]. */
312         uint32_t pre_cu                : 2;  /**< [  1:  0] See BGX_SPU_BR_TRAIN_CUP_S[PRE_CUP]. */
313 #else /* Word 0 - Little Endian */
314         uint32_t pre_cu                : 2;  /**< [  1:  0] See BGX_SPU_BR_TRAIN_CUP_S[PRE_CUP]. */
315         uint32_t main_cu               : 2;  /**< [  3:  2] See BGX_SPU_BR_TRAIN_CUP_S[MAIN_CUP]. */
316         uint32_t post_cu               : 2;  /**< [  5:  4] See BGX_SPU_BR_TRAIN_CUP_S[POST_CUP]. */
317         uint32_t initialize            : 1;  /**< [  6:  6] See BGX_SPU_BR_TRAIN_CUP_S[INIT]. */
318         uint32_t preset                : 1;  /**< [  7:  7] See BGX_SPU_BR_TRAIN_CUP_S[PRESET]. */
319         uint32_t rcvr_ready            : 1;  /**< [  8:  8] See BGX_SPU_BR_TRAIN_REP_S[RX_READY]. */
320         uint32_t reserved_9_31         : 23;
321 #endif /* Word 0 - End */
322     } s;
323     /* struct bdk_bgx_spu_sds_cu_s_s cn; */
324 };
325 
326 /**
327  * Structure bgx_spu_sds_skew_status_s
328  *
329  * BGX Skew Status Structure
330  * Provides receive skew information detected for a physical SerDes lane when it is assigned to a
331  * multilane LMAC/LPCS. Contents are valid when RX deskew is done for the associated LMAC/LPCS.
332  */
333 union bdk_bgx_spu_sds_skew_status_s
334 {
335     uint32_t u;
336     struct bdk_bgx_spu_sds_skew_status_s_s
337     {
338 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
339         uint32_t reserved_25_31        : 7;
340         uint32_t lane_skew             : 5;  /**< [ 24: 20] Lane skew. The SerDes lane's receive skew/delay in number of code-groups (BASE-X) or
341                                                                  blocks (40GBASE-R) relative to the earliest (least delayed) lane of the LMAC/LPCS. */
342         uint32_t reserved_18_19        : 2;
343         uint32_t am_lane_id            : 2;  /**< [ 17: 16] Alignment Marker ID. Valid for 40GBASE-R only. This is the PCS lane number of the
344                                                                  alignment marker received on the SerDes lane. */
345         uint32_t reserved_12_15        : 4;
346         uint32_t am_timestamp          : 12; /**< [ 11:  0] Alignment marker PTP timestamp. Valid for 40GBASE-R only. Contains the lower 12 bits of
347                                                                  the PTP timestamp of the alignment marker received on the SerDes lane during align/skew
348                                                                  detection. */
349 #else /* Word 0 - Little Endian */
350         uint32_t am_timestamp          : 12; /**< [ 11:  0] Alignment marker PTP timestamp. Valid for 40GBASE-R only. Contains the lower 12 bits of
351                                                                  the PTP timestamp of the alignment marker received on the SerDes lane during align/skew
352                                                                  detection. */
353         uint32_t reserved_12_15        : 4;
354         uint32_t am_lane_id            : 2;  /**< [ 17: 16] Alignment Marker ID. Valid for 40GBASE-R only. This is the PCS lane number of the
355                                                                  alignment marker received on the SerDes lane. */
356         uint32_t reserved_18_19        : 2;
357         uint32_t lane_skew             : 5;  /**< [ 24: 20] Lane skew. The SerDes lane's receive skew/delay in number of code-groups (BASE-X) or
358                                                                  blocks (40GBASE-R) relative to the earliest (least delayed) lane of the LMAC/LPCS. */
359         uint32_t reserved_25_31        : 7;
360 #endif /* Word 0 - End */
361     } s;
362     /* struct bdk_bgx_spu_sds_skew_status_s_s cn; */
363 };
364 
365 /**
366  * Structure bgx_spu_sds_sr_s
367  *
368  * INTERNAL: BGX Lane Training Coefficient Structure
369  *
370  * Similar to BGX_SPU_BR_TRAIN_REP_S format, but with reserved and RX_READY fields removed.
371  */
372 union bdk_bgx_spu_sds_sr_s
373 {
374     uint32_t u;
375     struct bdk_bgx_spu_sds_sr_s_s
376     {
377 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
378         uint32_t reserved_6_31         : 26;
379         uint32_t post_status           : 2;  /**< [  5:  4] See BGX_SPU_BR_TRAIN_REP_S[POST_CST]. */
380         uint32_t main_status           : 2;  /**< [  3:  2] See BGX_SPU_BR_TRAIN_REP_S[MAIN_CST]. */
381         uint32_t pre_status            : 2;  /**< [  1:  0] See BGX_SPU_BR_TRAIN_REP_S[PRE_CST]. */
382 #else /* Word 0 - Little Endian */
383         uint32_t pre_status            : 2;  /**< [  1:  0] See BGX_SPU_BR_TRAIN_REP_S[PRE_CST]. */
384         uint32_t main_status           : 2;  /**< [  3:  2] See BGX_SPU_BR_TRAIN_REP_S[MAIN_CST]. */
385         uint32_t post_status           : 2;  /**< [  5:  4] See BGX_SPU_BR_TRAIN_REP_S[POST_CST]. */
386         uint32_t reserved_6_31         : 26;
387 #endif /* Word 0 - End */
388     } s;
389     /* struct bdk_bgx_spu_sds_sr_s_s cn; */
390 };
391 
392 /**
393  * Register (RSL) bgx#_cmr#_config
394  *
395  * BGX CMR Configuration Registers
396  * Logical MAC/PCS configuration registers; one per LMAC. The maximum number of LMACs (and
397  * maximum LMAC ID) that can be enabled by these registers is limited by
398  * BGX()_CMR_RX_LMACS[LMACS] and BGX()_CMR_TX_LMACS[LMACS]. When multiple LMACs are
399  * enabled, they must be configured with the same [LMAC_TYPE] value.
400  *
401  * Internal:
402  * \<pre\>
403  * Typical configurations:
404  *   ---------------------------------------------------------------------------
405  *   Configuration           LMACS  Register             [ENABLE]    [LMAC_TYPE]
406  *   ---------------------------------------------------------------------------
407  *   1x40GBASE-R4            1      BGXn_CMR0_CONFIG     1           4
408  *                                  BGXn_CMR1_CONFIG     0           --
409  *                                  BGXn_CMR2_CONFIG     0           --
410  *                                  BGXn_CMR3_CONFIG     0           --
411  *   ---------------------------------------------------------------------------
412  *   4x10GBASE-R             4      BGXn_CMR0_CONFIG     1           3
413  *                                  BGXn_CMR1_CONFIG     1           3
414  *                                  BGXn_CMR2_CONFIG     1           3
415  *                                  BGXn_CMR3_CONFIG     1           3
416  *   ---------------------------------------------------------------------------
417  *   2xRXAUI                 2      BGXn_CMR0_CONFIG     1           2
418  *                                  BGXn_CMR1_CONFIG     1           2
419  *                                  BGXn_CMR2_CONFIG     0           --
420  *                                  BGXn_CMR3_CONFIG     0           --
421  *   ---------------------------------------------------------------------------
422  *   1x10GBASE-X/XAUI/DXAUI  1      BGXn_CMR0_CONFIG     1           1
423  *                                  BGXn_CMR1_CONFIG     0           --
424  *                                  BGXn_CMR2_CONFIG     0           --
425  *                                  BGXn_CMR3_CONFIG     0           --
426  *   ---------------------------------------------------------------------------
427  *   4xSGMII/1000BASE-X      4      BGXn_CMR0_CONFIG     1           0
428  *                                  BGXn_CMR1_CONFIG     1           0
429  *                                  BGXn_CMR2_CONFIG     1           0
430  *                                  BGXn_CMR3_CONFIG     1           0
431  *   ---------------------------------------------------------------------------
432  * \</pre\>
433  */
434 union bdk_bgxx_cmrx_config
435 {
436     uint64_t u;
437     struct bdk_bgxx_cmrx_config_s
438     {
439 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
440         uint64_t reserved_18_63        : 46;
441         uint64_t p2x_select            : 1;  /**< [ 17: 17](R/W) Selects interior side P2X interface over which the LMAC will communicate:
442                                                                  \<pre\>
443                                                                    [P2X_SELECT]      Name      Connected block
444                                                                    -------------------------------------------
445                                                                    0                 P2X0      NIC
446                                                                    1                 P2X1      PKO
447                                                                  \</pre\> */
448         uint64_t x2p_select            : 1;  /**< [ 16: 16](R/W) Selects interior side X2P interface over which the LMAC will communicate:
449                                                                  \<pre\>
450                                                                    [X2P_SELECT]      Name      Connected block
451                                                                    -------------------------------------------
452                                                                    0                 X2P0      NIC
453                                                                    1                 X2P1      PKI
454                                                                  \</pre\> */
455         uint64_t enable                : 1;  /**< [ 15: 15](R/W) Logical MAC/PCS enable. This is the master enable for the LMAC. When clear, all the
456                                                                  dedicated BGX context state for the LMAC (state machines, FIFOs, counters, etc.) is reset,
457                                                                  and LMAC access to shared BGX resources (data path, SerDes lanes) is disabled.
458 
459                                                                  When set, LMAC operation is enabled, including link bring-up, synchronization, and
460                                                                  transmit/receive of idles and fault sequences. Note that configuration registers for an
461                                                                  LMAC are not reset when this bit is clear, allowing software to program them before
462                                                                  setting this bit to enable the LMAC. This bit together with [LMAC_TYPE] is also used to
463                                                                  enable the clocking to the GMP and/or blocks of the Super path (SMU and SPU). CMR clocking
464                                                                  is enabled when any of the paths are enabled. */
465         uint64_t data_pkt_rx_en        : 1;  /**< [ 14: 14](R/W) Data packet receive enable. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 1, the reception of
466                                                                  data
467                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 0, the MAC
468                                                                  layer
469                                                                  drops received data and flow-control packets. */
470         uint64_t data_pkt_tx_en        : 1;  /**< [ 13: 13](R/W) Data packet transmit enable. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 1, the transmission
471                                                                  of
472                                                                  data
473                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 0, the MAC
474                                                                  layer
475                                                                  suppresses the transmission of new data and packets for the LMAC. */
476         uint64_t int_beat_gen          : 1;  /**< [ 12: 12](R/W) Internal beat generation. This bit is used for debug/test purposes and should be clear
477                                                                  during normal operation. When set, the LMAC's PCS layer ignores RXVALID and
478                                                                  TXREADY/TXCREDIT from the associated SerDes lanes, internally generates fake (idle)
479                                                                  RXVALID and TXCREDIT pulses, and suppresses transmission to the SerDes. */
480         uint64_t mix_en                : 1;  /**< [ 11: 11](R/W) Must be 0. */
481         uint64_t lmac_type             : 3;  /**< [ 10:  8](R/W) Logical MAC/PCS/prt type:
482 
483                                                                  \<pre\>
484                                                                    LMAC_TYPE  Name       Description            NUM_PCS_LANES
485                                                                    ----------------------------------------------------------
486                                                                    0x0        SGMII      SGMII/1000BASE-X             1
487                                                                    0x1        XAUI       10GBASE-X/XAUI or DXAUI      4
488                                                                    0x2        RXAUI      Reduced XAUI                 2
489                                                                    0x3        10G_R      10GBASE-R                    1
490                                                                    0x4        40G_R      40GBASE-R                    4
491                                                                    0x5        --         Reserved                     -
492                                                                    0x6        QSGMII     QSGMII                       1
493                                                                    Other      --         Reserved                     -
494                                                                  \</pre\>
495 
496                                                                  NUM_PCS_LANES specifies the number of PCS lanes that are valid for
497                                                                  each type. Each valid PCS lane is mapped to a physical SerDes lane
498                                                                  based on the programming of [LANE_TO_SDS].
499 
500                                                                  This field must be programmed to its final value before [ENABLE] is set, and must not
501                                                                  be changed when [ENABLE] = 1. */
502         uint64_t lane_to_sds           : 8;  /**< [  7:  0](R/W) PCS lane-to-SerDes mapping.
503                                                                  This is an array of 2-bit values that map each logical PCS lane to a
504                                                                  physical SerDes lane, as follows:
505 
506                                                                  \<pre\>
507                                                                    Bits    Description            Reset value
508                                                                    ------------------------------------------
509                                                                    \<7:6\>   PCS Lane 3 SerDes ID       0x3
510                                                                    \<5:4\>   PCS Lane 2 SerDes ID       0x2
511                                                                    \<3:2\>   PCS Lane 1 SerDes ID       0x1
512                                                                    \<1:0\>   PCS Lane 0 SerDes ID       0x0
513                                                                  \</pre\>
514 
515                                                                  PCS lanes 0 through NUM_PCS_LANES-1 are valid, where NUM_PCS_LANES is a function of the
516                                                                  logical MAC/PCS type (see [LMAC_TYPE]). For example, when [LMAC_TYPE] = SGMII,
517                                                                  then NUM_PCS_LANES = 1, PCS lane 0 is valid and the associated physical SerDes lanes
518                                                                  are selected by bits \<1:0\>.
519 
520                                                                  For 40GBASE-R ([LMAC_TYPE] = 40G_R), all four PCS lanes are valid, and the PCS lane IDs
521                                                                  determine the block distribution order and associated alignment markers on the transmit
522                                                                  side. This is not necessarily the order in which PCS lanes receive data because 802.3
523                                                                  allows multilane BASE-R receive lanes to be reordered. When a lane (called service
524                                                                  interface in 802.3ba-2010) has achieved alignment marker lock on the receive side (i.e.
525                                                                  the associated BGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), then the actual
526                                                                  detected RX PCS lane number is recorded in the corresponding
527                                                                  BGX()_SPU()_BR_LANE_MAP[LNx_MAPPING].
528 
529                                                                  For QSGMII, [LANE_TO_SDS]\<1:0\> for LMAC 0 selects the physical SerDes lane shared by four
530                                                                  LMACs, and [LANE_TO_SDS]\<1:0\> must be unique for each of the four LMACs.
531 
532                                                                  This field must be programmed to its final value before [ENABLE] is set, and
533                                                                  must not be changed when [ENABLE] = 1. */
534 #else /* Word 0 - Little Endian */
535         uint64_t lane_to_sds           : 8;  /**< [  7:  0](R/W) PCS lane-to-SerDes mapping.
536                                                                  This is an array of 2-bit values that map each logical PCS lane to a
537                                                                  physical SerDes lane, as follows:
538 
539                                                                  \<pre\>
540                                                                    Bits    Description            Reset value
541                                                                    ------------------------------------------
542                                                                    \<7:6\>   PCS Lane 3 SerDes ID       0x3
543                                                                    \<5:4\>   PCS Lane 2 SerDes ID       0x2
544                                                                    \<3:2\>   PCS Lane 1 SerDes ID       0x1
545                                                                    \<1:0\>   PCS Lane 0 SerDes ID       0x0
546                                                                  \</pre\>
547 
548                                                                  PCS lanes 0 through NUM_PCS_LANES-1 are valid, where NUM_PCS_LANES is a function of the
549                                                                  logical MAC/PCS type (see [LMAC_TYPE]). For example, when [LMAC_TYPE] = SGMII,
550                                                                  then NUM_PCS_LANES = 1, PCS lane 0 is valid and the associated physical SerDes lanes
551                                                                  are selected by bits \<1:0\>.
552 
553                                                                  For 40GBASE-R ([LMAC_TYPE] = 40G_R), all four PCS lanes are valid, and the PCS lane IDs
554                                                                  determine the block distribution order and associated alignment markers on the transmit
555                                                                  side. This is not necessarily the order in which PCS lanes receive data because 802.3
556                                                                  allows multilane BASE-R receive lanes to be reordered. When a lane (called service
557                                                                  interface in 802.3ba-2010) has achieved alignment marker lock on the receive side (i.e.
558                                                                  the associated BGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), then the actual
559                                                                  detected RX PCS lane number is recorded in the corresponding
560                                                                  BGX()_SPU()_BR_LANE_MAP[LNx_MAPPING].
561 
562                                                                  For QSGMII, [LANE_TO_SDS]\<1:0\> for LMAC 0 selects the physical SerDes lane shared by four
563                                                                  LMACs, and [LANE_TO_SDS]\<1:0\> must be unique for each of the four LMACs.
564 
565                                                                  This field must be programmed to its final value before [ENABLE] is set, and
566                                                                  must not be changed when [ENABLE] = 1. */
567         uint64_t lmac_type             : 3;  /**< [ 10:  8](R/W) Logical MAC/PCS/prt type:
568 
569                                                                  \<pre\>
570                                                                    LMAC_TYPE  Name       Description            NUM_PCS_LANES
571                                                                    ----------------------------------------------------------
572                                                                    0x0        SGMII      SGMII/1000BASE-X             1
573                                                                    0x1        XAUI       10GBASE-X/XAUI or DXAUI      4
574                                                                    0x2        RXAUI      Reduced XAUI                 2
575                                                                    0x3        10G_R      10GBASE-R                    1
576                                                                    0x4        40G_R      40GBASE-R                    4
577                                                                    0x5        --         Reserved                     -
578                                                                    0x6        QSGMII     QSGMII                       1
579                                                                    Other      --         Reserved                     -
580                                                                  \</pre\>
581 
582                                                                  NUM_PCS_LANES specifies the number of PCS lanes that are valid for
583                                                                  each type. Each valid PCS lane is mapped to a physical SerDes lane
584                                                                  based on the programming of [LANE_TO_SDS].
585 
586                                                                  This field must be programmed to its final value before [ENABLE] is set, and must not
587                                                                  be changed when [ENABLE] = 1. */
588         uint64_t mix_en                : 1;  /**< [ 11: 11](R/W) Must be 0. */
589         uint64_t int_beat_gen          : 1;  /**< [ 12: 12](R/W) Internal beat generation. This bit is used for debug/test purposes and should be clear
590                                                                  during normal operation. When set, the LMAC's PCS layer ignores RXVALID and
591                                                                  TXREADY/TXCREDIT from the associated SerDes lanes, internally generates fake (idle)
592                                                                  RXVALID and TXCREDIT pulses, and suppresses transmission to the SerDes. */
593         uint64_t data_pkt_tx_en        : 1;  /**< [ 13: 13](R/W) Data packet transmit enable. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 1, the transmission
594                                                                  of
595                                                                  data
596                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 0, the MAC
597                                                                  layer
598                                                                  suppresses the transmission of new data and packets for the LMAC. */
599         uint64_t data_pkt_rx_en        : 1;  /**< [ 14: 14](R/W) Data packet receive enable. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 1, the reception of
600                                                                  data
601                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 0, the MAC
602                                                                  layer
603                                                                  drops received data and flow-control packets. */
604         uint64_t enable                : 1;  /**< [ 15: 15](R/W) Logical MAC/PCS enable. This is the master enable for the LMAC. When clear, all the
605                                                                  dedicated BGX context state for the LMAC (state machines, FIFOs, counters, etc.) is reset,
606                                                                  and LMAC access to shared BGX resources (data path, SerDes lanes) is disabled.
607 
608                                                                  When set, LMAC operation is enabled, including link bring-up, synchronization, and
609                                                                  transmit/receive of idles and fault sequences. Note that configuration registers for an
610                                                                  LMAC are not reset when this bit is clear, allowing software to program them before
611                                                                  setting this bit to enable the LMAC. This bit together with [LMAC_TYPE] is also used to
612                                                                  enable the clocking to the GMP and/or blocks of the Super path (SMU and SPU). CMR clocking
613                                                                  is enabled when any of the paths are enabled. */
614         uint64_t x2p_select            : 1;  /**< [ 16: 16](R/W) Selects interior side X2P interface over which the LMAC will communicate:
615                                                                  \<pre\>
616                                                                    [X2P_SELECT]      Name      Connected block
617                                                                    -------------------------------------------
618                                                                    0                 X2P0      NIC
619                                                                    1                 X2P1      PKI
620                                                                  \</pre\> */
621         uint64_t p2x_select            : 1;  /**< [ 17: 17](R/W) Selects interior side P2X interface over which the LMAC will communicate:
622                                                                  \<pre\>
623                                                                    [P2X_SELECT]      Name      Connected block
624                                                                    -------------------------------------------
625                                                                    0                 P2X0      NIC
626                                                                    1                 P2X1      PKO
627                                                                  \</pre\> */
628         uint64_t reserved_18_63        : 46;
629 #endif /* Word 0 - End */
630     } s;
631     struct bdk_bgxx_cmrx_config_cn81xx
632     {
633 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
634         uint64_t reserved_18_63        : 46;
635         uint64_t p2x_select            : 1;  /**< [ 17: 17](R/W) Selects interior side P2X interface over which the LMAC will communicate:
636                                                                  \<pre\>
637                                                                    [P2X_SELECT]      Name      Connected block
638                                                                    -------------------------------------------
639                                                                    0                 P2X0      NIC
640                                                                    1                 P2X1      Reserved
641                                                                  \</pre\> */
642         uint64_t x2p_select            : 1;  /**< [ 16: 16](R/W) Selects interior side X2P interface over which the LMAC will communicate:
643                                                                  \<pre\>
644                                                                    [X2P_SELECT]      Name      Connected block
645                                                                    -------------------------------------------
646                                                                    0                 X2P0      NIC
647                                                                    1                 X2P1      Reserved
648                                                                  \</pre\> */
649         uint64_t enable                : 1;  /**< [ 15: 15](R/W) Logical MAC/PCS enable. This is the master enable for the LMAC. When clear, all the
650                                                                  dedicated BGX context state for the LMAC (state machines, FIFOs, counters, etc.) is reset,
651                                                                  and LMAC access to shared BGX resources (data path, SerDes lanes) is disabled.
652 
653                                                                  When set, LMAC operation is enabled, including link bring-up, synchronization, and
654                                                                  transmit/receive of idles and fault sequences. Note that configuration registers for an
655                                                                  LMAC are not reset when this bit is clear, allowing software to program them before
656                                                                  setting this bit to enable the LMAC. This bit together with [LMAC_TYPE] is also used to
657                                                                  enable the clocking to the GMP and/or blocks of the Super path (SMU and SPU). CMR clocking
658                                                                  is enabled when any of the paths are enabled. */
659         uint64_t data_pkt_rx_en        : 1;  /**< [ 14: 14](R/W) Data packet receive enable. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 1, the reception of
660                                                                  data
661                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 0, the MAC
662                                                                  layer
663                                                                  drops received data and flow-control packets. */
664         uint64_t data_pkt_tx_en        : 1;  /**< [ 13: 13](R/W) Data packet transmit enable. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 1, the transmission
665                                                                  of
666                                                                  data
667                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 0, the MAC
668                                                                  layer
669                                                                  suppresses the transmission of new data and packets for the LMAC. */
670         uint64_t int_beat_gen          : 1;  /**< [ 12: 12](R/W) Internal beat generation. This bit is used for debug/test purposes and should be clear
671                                                                  during normal operation. When set, the LMAC's PCS layer ignores RXVALID and
672                                                                  TXREADY/TXCREDIT from the associated SerDes lanes, internally generates fake (idle)
673                                                                  RXVALID and TXCREDIT pulses, and suppresses transmission to the SerDes. */
674         uint64_t mix_en                : 1;  /**< [ 11: 11](R/W) Must be 0. */
675         uint64_t lmac_type             : 3;  /**< [ 10:  8](R/W) Logical MAC/PCS/prt type:
676 
677                                                                  \<pre\>
678                                                                    LMAC_TYPE  Name       Description            NUM_PCS_LANES
679                                                                    ----------------------------------------------------------
680                                                                    0x0        SGMII      SGMII/1000BASE-X             1
681                                                                    0x1        XAUI       10GBASE-X/XAUI or DXAUI      4
682                                                                    0x2        RXAUI      Reduced XAUI                 2
683                                                                    0x3        10G_R      10GBASE-R                    1
684                                                                    0x4        40G_R      40GBASE-R                    4
685                                                                    0x5        --         Reserved                     -
686                                                                    0x6        QSGMII     QSGMII                       1
687                                                                    Other      --         Reserved                     -
688                                                                  \</pre\>
689 
690                                                                  NUM_PCS_LANES specifies the number of PCS lanes that are valid for
691                                                                  each type. Each valid PCS lane is mapped to a physical SerDes lane
692                                                                  based on the programming of [LANE_TO_SDS].
693 
694                                                                  This field must be programmed to its final value before [ENABLE] is set, and must not
695                                                                  be changed when [ENABLE] = 1. */
696         uint64_t lane_to_sds           : 8;  /**< [  7:  0](R/W) PCS lane-to-SerDes mapping.
697                                                                  This is an array of 2-bit values that map each logical PCS lane to a
698                                                                  physical SerDes lane, as follows:
699 
700                                                                  \<pre\>
701                                                                    Bits    Description            Reset value
702                                                                    ------------------------------------------
703                                                                    \<7:6\>   PCS Lane 3 SerDes ID       0x3
704                                                                    \<5:4\>   PCS Lane 2 SerDes ID       0x2
705                                                                    \<3:2\>   PCS Lane 1 SerDes ID       0x1
706                                                                    \<1:0\>   PCS Lane 0 SerDes ID       0x0
707                                                                  \</pre\>
708 
709                                                                  PCS lanes 0 through NUM_PCS_LANES-1 are valid, where NUM_PCS_LANES is a function of the
710                                                                  logical MAC/PCS type (see [LMAC_TYPE]). For example, when [LMAC_TYPE] = SGMII,
711                                                                  then NUM_PCS_LANES = 1, PCS lane 0 is valid and the associated physical SerDes lanes
712                                                                  are selected by bits \<1:0\>.
713 
714                                                                  For 40GBASE-R ([LMAC_TYPE] = 40G_R), all four PCS lanes are valid, and the PCS lane IDs
715                                                                  determine the block distribution order and associated alignment markers on the transmit
716                                                                  side. This is not necessarily the order in which PCS lanes receive data because 802.3
717                                                                  allows multilane BASE-R receive lanes to be reordered. When a lane (called service
718                                                                  interface in 802.3ba-2010) has achieved alignment marker lock on the receive side (i.e.
719                                                                  the associated BGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), then the actual
720                                                                  detected RX PCS lane number is recorded in the corresponding
721                                                                  BGX()_SPU()_BR_LANE_MAP[LNx_MAPPING].
722 
723                                                                  For QSGMII, [LANE_TO_SDS]\<1:0\> for LMAC 0 selects the physical SerDes lane shared by four
724                                                                  LMACs, and [LANE_TO_SDS]\<1:0\> must be unique for each of the four LMACs.
725 
726                                                                  This field must be programmed to its final value before [ENABLE] is set, and
727                                                                  must not be changed when [ENABLE] = 1. */
728 #else /* Word 0 - Little Endian */
729         uint64_t lane_to_sds           : 8;  /**< [  7:  0](R/W) PCS lane-to-SerDes mapping.
730                                                                  This is an array of 2-bit values that map each logical PCS lane to a
731                                                                  physical SerDes lane, as follows:
732 
733                                                                  \<pre\>
734                                                                    Bits    Description            Reset value
735                                                                    ------------------------------------------
736                                                                    \<7:6\>   PCS Lane 3 SerDes ID       0x3
737                                                                    \<5:4\>   PCS Lane 2 SerDes ID       0x2
738                                                                    \<3:2\>   PCS Lane 1 SerDes ID       0x1
739                                                                    \<1:0\>   PCS Lane 0 SerDes ID       0x0
740                                                                  \</pre\>
741 
742                                                                  PCS lanes 0 through NUM_PCS_LANES-1 are valid, where NUM_PCS_LANES is a function of the
743                                                                  logical MAC/PCS type (see [LMAC_TYPE]). For example, when [LMAC_TYPE] = SGMII,
744                                                                  then NUM_PCS_LANES = 1, PCS lane 0 is valid and the associated physical SerDes lanes
745                                                                  are selected by bits \<1:0\>.
746 
747                                                                  For 40GBASE-R ([LMAC_TYPE] = 40G_R), all four PCS lanes are valid, and the PCS lane IDs
748                                                                  determine the block distribution order and associated alignment markers on the transmit
749                                                                  side. This is not necessarily the order in which PCS lanes receive data because 802.3
750                                                                  allows multilane BASE-R receive lanes to be reordered. When a lane (called service
751                                                                  interface in 802.3ba-2010) has achieved alignment marker lock on the receive side (i.e.
752                                                                  the associated BGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), then the actual
753                                                                  detected RX PCS lane number is recorded in the corresponding
754                                                                  BGX()_SPU()_BR_LANE_MAP[LNx_MAPPING].
755 
756                                                                  For QSGMII, [LANE_TO_SDS]\<1:0\> for LMAC 0 selects the physical SerDes lane shared by four
757                                                                  LMACs, and [LANE_TO_SDS]\<1:0\> must be unique for each of the four LMACs.
758 
759                                                                  This field must be programmed to its final value before [ENABLE] is set, and
760                                                                  must not be changed when [ENABLE] = 1. */
761         uint64_t lmac_type             : 3;  /**< [ 10:  8](R/W) Logical MAC/PCS/prt type:
762 
763                                                                  \<pre\>
764                                                                    LMAC_TYPE  Name       Description            NUM_PCS_LANES
765                                                                    ----------------------------------------------------------
766                                                                    0x0        SGMII      SGMII/1000BASE-X             1
767                                                                    0x1        XAUI       10GBASE-X/XAUI or DXAUI      4
768                                                                    0x2        RXAUI      Reduced XAUI                 2
769                                                                    0x3        10G_R      10GBASE-R                    1
770                                                                    0x4        40G_R      40GBASE-R                    4
771                                                                    0x5        --         Reserved                     -
772                                                                    0x6        QSGMII     QSGMII                       1
773                                                                    Other      --         Reserved                     -
774                                                                  \</pre\>
775 
776                                                                  NUM_PCS_LANES specifies the number of PCS lanes that are valid for
777                                                                  each type. Each valid PCS lane is mapped to a physical SerDes lane
778                                                                  based on the programming of [LANE_TO_SDS].
779 
780                                                                  This field must be programmed to its final value before [ENABLE] is set, and must not
781                                                                  be changed when [ENABLE] = 1. */
782         uint64_t mix_en                : 1;  /**< [ 11: 11](R/W) Must be 0. */
783         uint64_t int_beat_gen          : 1;  /**< [ 12: 12](R/W) Internal beat generation. This bit is used for debug/test purposes and should be clear
784                                                                  during normal operation. When set, the LMAC's PCS layer ignores RXVALID and
785                                                                  TXREADY/TXCREDIT from the associated SerDes lanes, internally generates fake (idle)
786                                                                  RXVALID and TXCREDIT pulses, and suppresses transmission to the SerDes. */
787         uint64_t data_pkt_tx_en        : 1;  /**< [ 13: 13](R/W) Data packet transmit enable. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 1, the transmission
788                                                                  of
789                                                                  data
790                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 0, the MAC
791                                                                  layer
792                                                                  suppresses the transmission of new data and packets for the LMAC. */
793         uint64_t data_pkt_rx_en        : 1;  /**< [ 14: 14](R/W) Data packet receive enable. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 1, the reception of
794                                                                  data
795                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 0, the MAC
796                                                                  layer
797                                                                  drops received data and flow-control packets. */
798         uint64_t enable                : 1;  /**< [ 15: 15](R/W) Logical MAC/PCS enable. This is the master enable for the LMAC. When clear, all the
799                                                                  dedicated BGX context state for the LMAC (state machines, FIFOs, counters, etc.) is reset,
800                                                                  and LMAC access to shared BGX resources (data path, SerDes lanes) is disabled.
801 
802                                                                  When set, LMAC operation is enabled, including link bring-up, synchronization, and
803                                                                  transmit/receive of idles and fault sequences. Note that configuration registers for an
804                                                                  LMAC are not reset when this bit is clear, allowing software to program them before
805                                                                  setting this bit to enable the LMAC. This bit together with [LMAC_TYPE] is also used to
806                                                                  enable the clocking to the GMP and/or blocks of the Super path (SMU and SPU). CMR clocking
807                                                                  is enabled when any of the paths are enabled. */
808         uint64_t x2p_select            : 1;  /**< [ 16: 16](R/W) Selects interior side X2P interface over which the LMAC will communicate:
809                                                                  \<pre\>
810                                                                    [X2P_SELECT]      Name      Connected block
811                                                                    -------------------------------------------
812                                                                    0                 X2P0      NIC
813                                                                    1                 X2P1      Reserved
814                                                                  \</pre\> */
815         uint64_t p2x_select            : 1;  /**< [ 17: 17](R/W) Selects interior side P2X interface over which the LMAC will communicate:
816                                                                  \<pre\>
817                                                                    [P2X_SELECT]      Name      Connected block
818                                                                    -------------------------------------------
819                                                                    0                 P2X0      NIC
820                                                                    1                 P2X1      Reserved
821                                                                  \</pre\> */
822         uint64_t reserved_18_63        : 46;
823 #endif /* Word 0 - End */
824     } cn81xx;
825     struct bdk_bgxx_cmrx_config_cn88xx
826     {
827 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
828         uint64_t reserved_16_63        : 48;
829         uint64_t enable                : 1;  /**< [ 15: 15](R/W) Logical MAC/PCS enable. This is the master enable for the LMAC. When clear, all the
830                                                                  dedicated BGX context state for the LMAC (state machines, FIFOs, counters, etc.) is reset,
831                                                                  and LMAC access to shared BGX resources (SMU/SPU data path, SerDes lanes) is disabled.
832 
833                                                                  When set, LMAC operation is enabled, including link bring-up, synchronization, and
834                                                                  transmit/receive of idles and fault sequences. Note that configuration registers for an
835                                                                  LMAC are not reset when this bit is clear, allowing software to program them before
836                                                                  setting this bit to enable the LMAC. This bit together with [LMAC_TYPE] is also used to
837                                                                  enable the clocking to the GMP and/or blocks of the Super path (SMU and SPU). CMR clocking
838                                                                  is enabled when any of the paths are enabled. */
839         uint64_t data_pkt_rx_en        : 1;  /**< [ 14: 14](R/W) Data packet receive enable. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 1, the reception of
840                                                                  data
841                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 0, the MAC
842                                                                  layer
843                                                                  drops received data and flow-control packets. */
844         uint64_t data_pkt_tx_en        : 1;  /**< [ 13: 13](R/W) Data packet transmit enable. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 1, the transmission
845                                                                  of
846                                                                  data
847                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 0, the MAC
848                                                                  layer
849                                                                  suppresses the transmission of new data and packets for the LMAC. */
850         uint64_t int_beat_gen          : 1;  /**< [ 12: 12](R/W) Internal beat generation. This bit is used for debug/test purposes and should be clear
851                                                                  during normal operation. When set, the LMAC's PCS layer ignores RXVALID and
852                                                                  TXREADY/TXCREDIT from the associated SerDes lanes, internally generates fake (idle)
853                                                                  RXVALID and TXCREDIT pulses, and suppresses transmission to the SerDes. */
854         uint64_t mix_en                : 1;  /**< [ 11: 11](R/W) Must be 0. */
855         uint64_t lmac_type             : 3;  /**< [ 10:  8](R/W) Logical MAC/PCS/prt type:
856 
857                                                                  \<pre\>
858                                                                    LMAC_TYPE  Name       Description            NUM_PCS_LANES
859                                                                    ----------------------------------------------------------
860                                                                    0x0        SGMII      SGMII/1000BASE-X             1
861                                                                    0x1        XAUI       10GBASE-X/XAUI or DXAUI      4
862                                                                    0x2        RXAUI      Reduced XAUI                 2
863                                                                    0x3        10G_R      10GBASE-R                    1
864                                                                    0x4        40G_R      40GBASE-R                    4
865                                                                    Other      --         Reserved                     -
866                                                                  \</pre\>
867 
868                                                                  NUM_PCS_LANES specifies the number of PCS lanes that are valid for
869                                                                  each type. Each valid PCS lane is mapped to a physical SerDes lane
870                                                                  based on the programming of [LANE_TO_SDS].
871 
872                                                                  This field must be programmed to its final value before [ENABLE] is set, and must not
873                                                                  be changed when [ENABLE] = 1. */
874         uint64_t lane_to_sds           : 8;  /**< [  7:  0](R/W) PCS lane-to-SerDes mapping.
875                                                                  This is an array of 2-bit values that map each logical PCS lane to a
876                                                                  physical SerDes lane, as follows:
877 
878                                                                  \<pre\>
879                                                                    Bits    Description            Reset value
880                                                                    ------------------------------------------
881                                                                    \<7:6\>   PCS Lane 3 SerDes ID       0x3
882                                                                    \<5:4\>   PCS Lane 2 SerDes ID       0x2
883                                                                    \<3:2\>   PCS Lane 1 SerDes ID       0x1
884                                                                    \<1:0\>   PCS Lane 0 SerDes ID       0x0
885                                                                  \</pre\>
886 
887                                                                  PCS lanes 0 through NUM_PCS_LANES-1 are valid, where NUM_PCS_LANES is a function of the
888                                                                  logical MAC/PCS type (see [LMAC_TYPE]). For example, when [LMAC_TYPE] = SGMII,
889                                                                  then NUM_PCS_LANES = 1, PCS lane 0 is valid and the associated physical SerDes lanes
890                                                                  are selected by bits \<1:0\>.
891 
892                                                                  For 40GBASE-R ([LMAC_TYPE] = 40G_R), all four PCS lanes are valid, and the PCS lane IDs
893                                                                  determine the block distribution order and associated alignment markers on the transmit
894                                                                  side. This is not necessarily the order in which PCS lanes receive data because 802.3
895                                                                  allows multilane BASE-R receive lanes to be reordered. When a lane (called service
896                                                                  interface in 802.3ba-2010) has achieved alignment marker lock on the receive side (i.e.
897                                                                  the associated BGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), then the actual
898                                                                  detected RX PCS lane number is recorded in the corresponding
899                                                                  BGX()_SPU()_BR_LANE_MAP[LNx_MAPPING].
900 
901                                                                  This field must be programmed to its final value before [ENABLE] is set, and must not
902                                                                  be changed when [ENABLE] = 1. */
903 #else /* Word 0 - Little Endian */
904         uint64_t lane_to_sds           : 8;  /**< [  7:  0](R/W) PCS lane-to-SerDes mapping.
905                                                                  This is an array of 2-bit values that map each logical PCS lane to a
906                                                                  physical SerDes lane, as follows:
907 
908                                                                  \<pre\>
909                                                                    Bits    Description            Reset value
910                                                                    ------------------------------------------
911                                                                    \<7:6\>   PCS Lane 3 SerDes ID       0x3
912                                                                    \<5:4\>   PCS Lane 2 SerDes ID       0x2
913                                                                    \<3:2\>   PCS Lane 1 SerDes ID       0x1
914                                                                    \<1:0\>   PCS Lane 0 SerDes ID       0x0
915                                                                  \</pre\>
916 
917                                                                  PCS lanes 0 through NUM_PCS_LANES-1 are valid, where NUM_PCS_LANES is a function of the
918                                                                  logical MAC/PCS type (see [LMAC_TYPE]). For example, when [LMAC_TYPE] = SGMII,
919                                                                  then NUM_PCS_LANES = 1, PCS lane 0 is valid and the associated physical SerDes lanes
920                                                                  are selected by bits \<1:0\>.
921 
922                                                                  For 40GBASE-R ([LMAC_TYPE] = 40G_R), all four PCS lanes are valid, and the PCS lane IDs
923                                                                  determine the block distribution order and associated alignment markers on the transmit
924                                                                  side. This is not necessarily the order in which PCS lanes receive data because 802.3
925                                                                  allows multilane BASE-R receive lanes to be reordered. When a lane (called service
926                                                                  interface in 802.3ba-2010) has achieved alignment marker lock on the receive side (i.e.
927                                                                  the associated BGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), then the actual
928                                                                  detected RX PCS lane number is recorded in the corresponding
929                                                                  BGX()_SPU()_BR_LANE_MAP[LNx_MAPPING].
930 
931                                                                  This field must be programmed to its final value before [ENABLE] is set, and must not
932                                                                  be changed when [ENABLE] = 1. */
933         uint64_t lmac_type             : 3;  /**< [ 10:  8](R/W) Logical MAC/PCS/prt type:
934 
935                                                                  \<pre\>
936                                                                    LMAC_TYPE  Name       Description            NUM_PCS_LANES
937                                                                    ----------------------------------------------------------
938                                                                    0x0        SGMII      SGMII/1000BASE-X             1
939                                                                    0x1        XAUI       10GBASE-X/XAUI or DXAUI      4
940                                                                    0x2        RXAUI      Reduced XAUI                 2
941                                                                    0x3        10G_R      10GBASE-R                    1
942                                                                    0x4        40G_R      40GBASE-R                    4
943                                                                    Other      --         Reserved                     -
944                                                                  \</pre\>
945 
946                                                                  NUM_PCS_LANES specifies the number of PCS lanes that are valid for
947                                                                  each type. Each valid PCS lane is mapped to a physical SerDes lane
948                                                                  based on the programming of [LANE_TO_SDS].
949 
950                                                                  This field must be programmed to its final value before [ENABLE] is set, and must not
951                                                                  be changed when [ENABLE] = 1. */
952         uint64_t mix_en                : 1;  /**< [ 11: 11](R/W) Must be 0. */
953         uint64_t int_beat_gen          : 1;  /**< [ 12: 12](R/W) Internal beat generation. This bit is used for debug/test purposes and should be clear
954                                                                  during normal operation. When set, the LMAC's PCS layer ignores RXVALID and
955                                                                  TXREADY/TXCREDIT from the associated SerDes lanes, internally generates fake (idle)
956                                                                  RXVALID and TXCREDIT pulses, and suppresses transmission to the SerDes. */
957         uint64_t data_pkt_tx_en        : 1;  /**< [ 13: 13](R/W) Data packet transmit enable. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 1, the transmission
958                                                                  of
959                                                                  data
960                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_TX_EN] = 0, the MAC
961                                                                  layer
962                                                                  suppresses the transmission of new data and packets for the LMAC. */
963         uint64_t data_pkt_rx_en        : 1;  /**< [ 14: 14](R/W) Data packet receive enable. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 1, the reception of
964                                                                  data
965                                                                  packets is enabled in the MAC layer. When [ENABLE] = 1 and [DATA_PKT_RX_EN] = 0, the MAC
966                                                                  layer
967                                                                  drops received data and flow-control packets. */
968         uint64_t enable                : 1;  /**< [ 15: 15](R/W) Logical MAC/PCS enable. This is the master enable for the LMAC. When clear, all the
969                                                                  dedicated BGX context state for the LMAC (state machines, FIFOs, counters, etc.) is reset,
970                                                                  and LMAC access to shared BGX resources (SMU/SPU data path, SerDes lanes) is disabled.
971 
972                                                                  When set, LMAC operation is enabled, including link bring-up, synchronization, and
973                                                                  transmit/receive of idles and fault sequences. Note that configuration registers for an
974                                                                  LMAC are not reset when this bit is clear, allowing software to program them before
975                                                                  setting this bit to enable the LMAC. This bit together with [LMAC_TYPE] is also used to
976                                                                  enable the clocking to the GMP and/or blocks of the Super path (SMU and SPU). CMR clocking
977                                                                  is enabled when any of the paths are enabled. */
978         uint64_t reserved_16_63        : 48;
979 #endif /* Word 0 - End */
980     } cn88xx;
981     /* struct bdk_bgxx_cmrx_config_s cn83xx; */
982 };
983 typedef union bdk_bgxx_cmrx_config bdk_bgxx_cmrx_config_t;
984 
985 static inline uint64_t BDK_BGXX_CMRX_CONFIG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_CONFIG(unsigned long a,unsigned long b)986 static inline uint64_t BDK_BGXX_CMRX_CONFIG(unsigned long a, unsigned long b)
987 {
988     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
989         return 0x87e0e0000000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
990     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
991         return 0x87e0e0000000ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
992     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
993         return 0x87e0e0000000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
994     __bdk_csr_fatal("BGXX_CMRX_CONFIG", 2, a, b, 0, 0);
995 }
996 
997 #define typedef_BDK_BGXX_CMRX_CONFIG(a,b) bdk_bgxx_cmrx_config_t
998 #define bustype_BDK_BGXX_CMRX_CONFIG(a,b) BDK_CSR_TYPE_RSL
999 #define basename_BDK_BGXX_CMRX_CONFIG(a,b) "BGXX_CMRX_CONFIG"
1000 #define device_bar_BDK_BGXX_CMRX_CONFIG(a,b) 0x0 /* PF_BAR0 */
1001 #define busnum_BDK_BGXX_CMRX_CONFIG(a,b) (a)
1002 #define arguments_BDK_BGXX_CMRX_CONFIG(a,b) (a),(b),-1,-1
1003 
1004 /**
1005  * Register (RSL) bgx#_cmr#_int
1006  *
1007  * BGX CMR Interrupt Register
1008  */
1009 union bdk_bgxx_cmrx_int
1010 {
1011     uint64_t u;
1012     struct bdk_bgxx_cmrx_int_s
1013     {
1014 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1015         uint64_t reserved_4_63         : 60;
1016         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) TX channel out-of-range from NIC interface.
1017                                                                  Reported on this LMAC for ids in the range of LMAC_ID+4, LMAC_ID+8 and LMAC_ID+12.
1018                                                                  Reported regardless of LMAC enable or P2X_SELECT association for this LMAC. */
1019         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reserved. */
1020         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) RX overflow. */
1021         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) RX PAUSE packet was dropped due to full RXB FIFO or during partner reset. */
1022 #else /* Word 0 - Little Endian */
1023         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) RX PAUSE packet was dropped due to full RXB FIFO or during partner reset. */
1024         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) RX overflow. */
1025         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reserved. */
1026         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) TX channel out-of-range from NIC interface.
1027                                                                  Reported on this LMAC for ids in the range of LMAC_ID+4, LMAC_ID+8 and LMAC_ID+12.
1028                                                                  Reported regardless of LMAC enable or P2X_SELECT association for this LMAC. */
1029         uint64_t reserved_4_63         : 60;
1030 #endif /* Word 0 - End */
1031     } s;
1032     struct bdk_bgxx_cmrx_int_cn81xx
1033     {
1034 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1035         uint64_t reserved_4_63         : 60;
1036         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) TX channel out-of-range from NIC interface. */
1037         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reserved. */
1038         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) RX overflow. */
1039         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) RX PAUSE packet was dropped due to full RXB FIFO or during partner reset. */
1040 #else /* Word 0 - Little Endian */
1041         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) RX PAUSE packet was dropped due to full RXB FIFO or during partner reset. */
1042         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) RX overflow. */
1043         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reserved. */
1044         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) TX channel out-of-range from NIC interface. */
1045         uint64_t reserved_4_63         : 60;
1046 #endif /* Word 0 - End */
1047     } cn81xx;
1048     struct bdk_bgxx_cmrx_int_cn88xx
1049     {
1050 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1051         uint64_t reserved_3_63         : 61;
1052         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) TX channel out-of-range from TNS/NIC interface. */
1053         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) RX overflow. */
1054         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) RX PAUSE packet was dropped due to full RXB FIFO or during partner reset. */
1055 #else /* Word 0 - Little Endian */
1056         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) RX PAUSE packet was dropped due to full RXB FIFO or during partner reset. */
1057         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) RX overflow. */
1058         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) TX channel out-of-range from TNS/NIC interface. */
1059         uint64_t reserved_3_63         : 61;
1060 #endif /* Word 0 - End */
1061     } cn88xx;
1062     struct bdk_bgxx_cmrx_int_cn83xx
1063     {
1064 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1065         uint64_t reserved_4_63         : 60;
1066         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) TX channel out-of-range from NIC interface.
1067                                                                  Reported on this LMAC for ids in the range of LMAC_ID+4, LMAC_ID+8 and LMAC_ID+12.
1068                                                                  Reported regardless of LMAC enable or P2X_SELECT association for this LMAC. */
1069         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) TX channel out-of-range from PKO interface.
1070                                                                  Reported on this LMAC for ids in the range of LMAC_ID+4, LMAC_ID+8 and LMAC_ID+12.
1071                                                                  Reported regardless of LMAC enable or P2X_SELECT association for this LMAC. */
1072         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) RX overflow. */
1073         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) RX PAUSE packet was dropped due to full RXB FIFO or during partner reset. */
1074 #else /* Word 0 - Little Endian */
1075         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) RX PAUSE packet was dropped due to full RXB FIFO or during partner reset. */
1076         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) RX overflow. */
1077         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) TX channel out-of-range from PKO interface.
1078                                                                  Reported on this LMAC for ids in the range of LMAC_ID+4, LMAC_ID+8 and LMAC_ID+12.
1079                                                                  Reported regardless of LMAC enable or P2X_SELECT association for this LMAC. */
1080         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) TX channel out-of-range from NIC interface.
1081                                                                  Reported on this LMAC for ids in the range of LMAC_ID+4, LMAC_ID+8 and LMAC_ID+12.
1082                                                                  Reported regardless of LMAC enable or P2X_SELECT association for this LMAC. */
1083         uint64_t reserved_4_63         : 60;
1084 #endif /* Word 0 - End */
1085     } cn83xx;
1086 };
1087 typedef union bdk_bgxx_cmrx_int bdk_bgxx_cmrx_int_t;
1088 
1089 static inline uint64_t BDK_BGXX_CMRX_INT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_INT(unsigned long a,unsigned long b)1090 static inline uint64_t BDK_BGXX_CMRX_INT(unsigned long a, unsigned long b)
1091 {
1092     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1093         return 0x87e0e0000040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1094     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1095         return 0x87e0e0000040ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1096     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1097         return 0x87e0e0000040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1098     __bdk_csr_fatal("BGXX_CMRX_INT", 2, a, b, 0, 0);
1099 }
1100 
1101 #define typedef_BDK_BGXX_CMRX_INT(a,b) bdk_bgxx_cmrx_int_t
1102 #define bustype_BDK_BGXX_CMRX_INT(a,b) BDK_CSR_TYPE_RSL
1103 #define basename_BDK_BGXX_CMRX_INT(a,b) "BGXX_CMRX_INT"
1104 #define device_bar_BDK_BGXX_CMRX_INT(a,b) 0x0 /* PF_BAR0 */
1105 #define busnum_BDK_BGXX_CMRX_INT(a,b) (a)
1106 #define arguments_BDK_BGXX_CMRX_INT(a,b) (a),(b),-1,-1
1107 
1108 /**
1109  * Register (RSL) bgx#_cmr#_int_ena_w1c
1110  *
1111  * BGX CMR Interrupt Enable Clear Register
1112  * This register clears interrupt enable bits.
1113  */
1114 union bdk_bgxx_cmrx_int_ena_w1c
1115 {
1116     uint64_t u;
1117     struct bdk_bgxx_cmrx_int_ena_w1c_s
1118     {
1119 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1120         uint64_t reserved_4_63         : 60;
1121         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1122         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1123         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1124         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1125 #else /* Word 0 - Little Endian */
1126         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1127         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1128         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1129         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1130         uint64_t reserved_4_63         : 60;
1131 #endif /* Word 0 - End */
1132     } s;
1133     struct bdk_bgxx_cmrx_int_ena_w1c_cn81xx
1134     {
1135 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1136         uint64_t reserved_4_63         : 60;
1137         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[NIC_NXC]. */
1138         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1139         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1140         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1141 #else /* Word 0 - Little Endian */
1142         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1143         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1144         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1145         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[NIC_NXC]. */
1146         uint64_t reserved_4_63         : 60;
1147 #endif /* Word 0 - End */
1148     } cn81xx;
1149     struct bdk_bgxx_cmrx_int_ena_w1c_cn88xx
1150     {
1151 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1152         uint64_t reserved_3_63         : 61;
1153         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1154         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1155         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1156 #else /* Word 0 - Little Endian */
1157         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1158         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1159         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1160         uint64_t reserved_3_63         : 61;
1161 #endif /* Word 0 - End */
1162     } cn88xx;
1163     struct bdk_bgxx_cmrx_int_ena_w1c_cn83xx
1164     {
1165 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1166         uint64_t reserved_4_63         : 60;
1167         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1168         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[PKO_NXC]. */
1169         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[OVERFLW]. */
1170         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[PAUSE_DRP]. */
1171 #else /* Word 0 - Little Endian */
1172         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[PAUSE_DRP]. */
1173         uint64_t overflw               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[OVERFLW]. */
1174         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[PKO_NXC]. */
1175         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1176         uint64_t reserved_4_63         : 60;
1177 #endif /* Word 0 - End */
1178     } cn83xx;
1179 };
1180 typedef union bdk_bgxx_cmrx_int_ena_w1c bdk_bgxx_cmrx_int_ena_w1c_t;
1181 
1182 static inline uint64_t BDK_BGXX_CMRX_INT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_INT_ENA_W1C(unsigned long a,unsigned long b)1183 static inline uint64_t BDK_BGXX_CMRX_INT_ENA_W1C(unsigned long a, unsigned long b)
1184 {
1185     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1186         return 0x87e0e0000050ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1187     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1188         return 0x87e0e0000050ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1189     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1190         return 0x87e0e0000050ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1191     __bdk_csr_fatal("BGXX_CMRX_INT_ENA_W1C", 2, a, b, 0, 0);
1192 }
1193 
1194 #define typedef_BDK_BGXX_CMRX_INT_ENA_W1C(a,b) bdk_bgxx_cmrx_int_ena_w1c_t
1195 #define bustype_BDK_BGXX_CMRX_INT_ENA_W1C(a,b) BDK_CSR_TYPE_RSL
1196 #define basename_BDK_BGXX_CMRX_INT_ENA_W1C(a,b) "BGXX_CMRX_INT_ENA_W1C"
1197 #define device_bar_BDK_BGXX_CMRX_INT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
1198 #define busnum_BDK_BGXX_CMRX_INT_ENA_W1C(a,b) (a)
1199 #define arguments_BDK_BGXX_CMRX_INT_ENA_W1C(a,b) (a),(b),-1,-1
1200 
1201 /**
1202  * Register (RSL) bgx#_cmr#_int_ena_w1s
1203  *
1204  * BGX CMR Interrupt Enable Set Register
1205  * This register sets interrupt enable bits.
1206  */
1207 union bdk_bgxx_cmrx_int_ena_w1s
1208 {
1209     uint64_t u;
1210     struct bdk_bgxx_cmrx_int_ena_w1s_s
1211     {
1212 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1213         uint64_t reserved_4_63         : 60;
1214         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1215         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1216         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1217         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1218 #else /* Word 0 - Little Endian */
1219         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1220         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1221         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1222         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1223         uint64_t reserved_4_63         : 60;
1224 #endif /* Word 0 - End */
1225     } s;
1226     struct bdk_bgxx_cmrx_int_ena_w1s_cn81xx
1227     {
1228 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1229         uint64_t reserved_4_63         : 60;
1230         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[NIC_NXC]. */
1231         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1232         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1233         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1234 #else /* Word 0 - Little Endian */
1235         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1236         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1237         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1238         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[NIC_NXC]. */
1239         uint64_t reserved_4_63         : 60;
1240 #endif /* Word 0 - End */
1241     } cn81xx;
1242     struct bdk_bgxx_cmrx_int_ena_w1s_cn88xx
1243     {
1244 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1245         uint64_t reserved_3_63         : 61;
1246         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1247         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1248         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1249 #else /* Word 0 - Little Endian */
1250         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1251         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1252         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1253         uint64_t reserved_3_63         : 61;
1254 #endif /* Word 0 - End */
1255     } cn88xx;
1256     struct bdk_bgxx_cmrx_int_ena_w1s_cn83xx
1257     {
1258 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1259         uint64_t reserved_4_63         : 60;
1260         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1261         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[PKO_NXC]. */
1262         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[OVERFLW]. */
1263         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[PAUSE_DRP]. */
1264 #else /* Word 0 - Little Endian */
1265         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[PAUSE_DRP]. */
1266         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[OVERFLW]. */
1267         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[PKO_NXC]. */
1268         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1269         uint64_t reserved_4_63         : 60;
1270 #endif /* Word 0 - End */
1271     } cn83xx;
1272 };
1273 typedef union bdk_bgxx_cmrx_int_ena_w1s bdk_bgxx_cmrx_int_ena_w1s_t;
1274 
1275 static inline uint64_t BDK_BGXX_CMRX_INT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_INT_ENA_W1S(unsigned long a,unsigned long b)1276 static inline uint64_t BDK_BGXX_CMRX_INT_ENA_W1S(unsigned long a, unsigned long b)
1277 {
1278     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1279         return 0x87e0e0000058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1280     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1281         return 0x87e0e0000058ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1282     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1283         return 0x87e0e0000058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1284     __bdk_csr_fatal("BGXX_CMRX_INT_ENA_W1S", 2, a, b, 0, 0);
1285 }
1286 
1287 #define typedef_BDK_BGXX_CMRX_INT_ENA_W1S(a,b) bdk_bgxx_cmrx_int_ena_w1s_t
1288 #define bustype_BDK_BGXX_CMRX_INT_ENA_W1S(a,b) BDK_CSR_TYPE_RSL
1289 #define basename_BDK_BGXX_CMRX_INT_ENA_W1S(a,b) "BGXX_CMRX_INT_ENA_W1S"
1290 #define device_bar_BDK_BGXX_CMRX_INT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
1291 #define busnum_BDK_BGXX_CMRX_INT_ENA_W1S(a,b) (a)
1292 #define arguments_BDK_BGXX_CMRX_INT_ENA_W1S(a,b) (a),(b),-1,-1
1293 
1294 /**
1295  * Register (RSL) bgx#_cmr#_int_w1s
1296  *
1297  * BGX CMR Interrupt Set Register
1298  * This register sets interrupt bits.
1299  */
1300 union bdk_bgxx_cmrx_int_w1s
1301 {
1302     uint64_t u;
1303     struct bdk_bgxx_cmrx_int_w1s_s
1304     {
1305 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1306         uint64_t reserved_4_63         : 60;
1307         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1308         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1309         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1310         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1311 #else /* Word 0 - Little Endian */
1312         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1313         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1314         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1315         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1316         uint64_t reserved_4_63         : 60;
1317 #endif /* Word 0 - End */
1318     } s;
1319     struct bdk_bgxx_cmrx_int_w1s_cn81xx
1320     {
1321 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1322         uint64_t reserved_4_63         : 60;
1323         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[NIC_NXC]. */
1324         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1325         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1326         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1327 #else /* Word 0 - Little Endian */
1328         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1329         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1330         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1331         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[NIC_NXC]. */
1332         uint64_t reserved_4_63         : 60;
1333 #endif /* Word 0 - End */
1334     } cn81xx;
1335     struct bdk_bgxx_cmrx_int_w1s_cn88xx
1336     {
1337 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1338         uint64_t reserved_3_63         : 61;
1339         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1340         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1341         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1342 #else /* Word 0 - Little Endian */
1343         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PAUSE_DRP]. */
1344         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[OVERFLW]. */
1345         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR(0..3)_INT[PKO_NXC]. */
1346         uint64_t reserved_3_63         : 61;
1347 #endif /* Word 0 - End */
1348     } cn88xx;
1349     struct bdk_bgxx_cmrx_int_w1s_cn83xx
1350     {
1351 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1352         uint64_t reserved_4_63         : 60;
1353         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1354         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[PKO_NXC]. */
1355         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[OVERFLW]. */
1356         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[PAUSE_DRP]. */
1357 #else /* Word 0 - Little Endian */
1358         uint64_t pause_drp             : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[PAUSE_DRP]. */
1359         uint64_t overflw               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[OVERFLW]. */
1360         uint64_t pko_nxc               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[PKO_NXC]. */
1361         uint64_t nic_nxc               : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_CMR(0..3)_INT[NIC_NXC]. */
1362         uint64_t reserved_4_63         : 60;
1363 #endif /* Word 0 - End */
1364     } cn83xx;
1365 };
1366 typedef union bdk_bgxx_cmrx_int_w1s bdk_bgxx_cmrx_int_w1s_t;
1367 
1368 static inline uint64_t BDK_BGXX_CMRX_INT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_INT_W1S(unsigned long a,unsigned long b)1369 static inline uint64_t BDK_BGXX_CMRX_INT_W1S(unsigned long a, unsigned long b)
1370 {
1371     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1372         return 0x87e0e0000048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1373     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1374         return 0x87e0e0000048ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1375     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1376         return 0x87e0e0000048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1377     __bdk_csr_fatal("BGXX_CMRX_INT_W1S", 2, a, b, 0, 0);
1378 }
1379 
1380 #define typedef_BDK_BGXX_CMRX_INT_W1S(a,b) bdk_bgxx_cmrx_int_w1s_t
1381 #define bustype_BDK_BGXX_CMRX_INT_W1S(a,b) BDK_CSR_TYPE_RSL
1382 #define basename_BDK_BGXX_CMRX_INT_W1S(a,b) "BGXX_CMRX_INT_W1S"
1383 #define device_bar_BDK_BGXX_CMRX_INT_W1S(a,b) 0x0 /* PF_BAR0 */
1384 #define busnum_BDK_BGXX_CMRX_INT_W1S(a,b) (a)
1385 #define arguments_BDK_BGXX_CMRX_INT_W1S(a,b) (a),(b),-1,-1
1386 
1387 /**
1388  * Register (RSL) bgx#_cmr#_prt_cbfc_ctl
1389  *
1390  * BGX CMR LMAC PFC Control Registers
1391  * See XOFF definition listed under BGX()_SMU()_CBFC_CTL.
1392  */
1393 union bdk_bgxx_cmrx_prt_cbfc_ctl
1394 {
1395     uint64_t u;
1396     struct bdk_bgxx_cmrx_prt_cbfc_ctl_s
1397     {
1398 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1399         uint64_t reserved_32_63        : 32;
1400         uint64_t phys_bp               : 16; /**< [ 31: 16](R/W) When the hardware is backpressuring any LMACs. (from either DRF or PFC packets or
1401                                                                  BGX()_CMR()_TX_OVR_BP[TX_CHAN_BP]) and all channels indicated by [PHYS_BP] are
1402                                                                  backpressured,
1403                                                                  simulate physical backpressure by deferring all packets on the transmitter.
1404                                                                  If LMAC_TYPE != SGMII/QSGMII, BGX()_SMU()_CBFC_CTL[RX_EN] or
1405                                                                  BGX()_SMU()_HG2_CONTROL[HG2RX_EN]
1406                                                                  additionally need to be set. */
1407         uint64_t reserved_0_15         : 16;
1408 #else /* Word 0 - Little Endian */
1409         uint64_t reserved_0_15         : 16;
1410         uint64_t phys_bp               : 16; /**< [ 31: 16](R/W) When the hardware is backpressuring any LMACs. (from either DRF or PFC packets or
1411                                                                  BGX()_CMR()_TX_OVR_BP[TX_CHAN_BP]) and all channels indicated by [PHYS_BP] are
1412                                                                  backpressured,
1413                                                                  simulate physical backpressure by deferring all packets on the transmitter.
1414                                                                  If LMAC_TYPE != SGMII/QSGMII, BGX()_SMU()_CBFC_CTL[RX_EN] or
1415                                                                  BGX()_SMU()_HG2_CONTROL[HG2RX_EN]
1416                                                                  additionally need to be set. */
1417         uint64_t reserved_32_63        : 32;
1418 #endif /* Word 0 - End */
1419     } s;
1420     /* struct bdk_bgxx_cmrx_prt_cbfc_ctl_s cn81xx; */
1421     struct bdk_bgxx_cmrx_prt_cbfc_ctl_cn88xx
1422     {
1423 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1424         uint64_t reserved_32_63        : 32;
1425         uint64_t phys_bp               : 16; /**< [ 31: 16](R/W) If LMAC_TYPE != SGMII, and BGX()_SMU()_CBFC_CTL[RX_EN] or
1426                                                                  BGX()_SMU()_HG2_CONTROL[HG2RX_EN] is set and the hardware is backpressuring any LMACs.
1427                                                                  (from either PFC packets or BGX()_CMR()_TX_OVR_BP[TX_CHAN_BP]) and all
1428                                                                  channels indicated by [PHYS_BP] are backpressured, simulate physical backpressure
1429                                                                  by deferring all packets on the transmitter. */
1430         uint64_t reserved_0_15         : 16;
1431 #else /* Word 0 - Little Endian */
1432         uint64_t reserved_0_15         : 16;
1433         uint64_t phys_bp               : 16; /**< [ 31: 16](R/W) If LMAC_TYPE != SGMII, and BGX()_SMU()_CBFC_CTL[RX_EN] or
1434                                                                  BGX()_SMU()_HG2_CONTROL[HG2RX_EN] is set and the hardware is backpressuring any LMACs.
1435                                                                  (from either PFC packets or BGX()_CMR()_TX_OVR_BP[TX_CHAN_BP]) and all
1436                                                                  channels indicated by [PHYS_BP] are backpressured, simulate physical backpressure
1437                                                                  by deferring all packets on the transmitter. */
1438         uint64_t reserved_32_63        : 32;
1439 #endif /* Word 0 - End */
1440     } cn88xx;
1441     struct bdk_bgxx_cmrx_prt_cbfc_ctl_cn83xx
1442     {
1443 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1444         uint64_t reserved_32_63        : 32;
1445         uint64_t phys_bp               : 16; /**< [ 31: 16](R/W) When the hardware is backpressuring any LMACs. (from either DFC or PFC packets or
1446                                                                  BGX()_CMR()_TX_OVR_BP[TX_CHAN_BP]) and all channels indicated by [PHYS_BP] are
1447                                                                  backpressured,
1448                                                                  simulate physical backpressure by deferring all packets on the transmitter.
1449                                                                  (i.e. signal to the mac an assertion of physical backpressure).
1450                                                                  If LMAC_TYPE != SGMII/QSGMII, BGX()_SMU()_CBFC_CTL[RX_EN] or
1451                                                                  BGX()_SMU()_HG2_CONTROL[HG2RX_EN]
1452                                                                  additionally need to be set. */
1453         uint64_t reserved_0_15         : 16;
1454 #else /* Word 0 - Little Endian */
1455         uint64_t reserved_0_15         : 16;
1456         uint64_t phys_bp               : 16; /**< [ 31: 16](R/W) When the hardware is backpressuring any LMACs. (from either DFC or PFC packets or
1457                                                                  BGX()_CMR()_TX_OVR_BP[TX_CHAN_BP]) and all channels indicated by [PHYS_BP] are
1458                                                                  backpressured,
1459                                                                  simulate physical backpressure by deferring all packets on the transmitter.
1460                                                                  (i.e. signal to the mac an assertion of physical backpressure).
1461                                                                  If LMAC_TYPE != SGMII/QSGMII, BGX()_SMU()_CBFC_CTL[RX_EN] or
1462                                                                  BGX()_SMU()_HG2_CONTROL[HG2RX_EN]
1463                                                                  additionally need to be set. */
1464         uint64_t reserved_32_63        : 32;
1465 #endif /* Word 0 - End */
1466     } cn83xx;
1467 };
1468 typedef union bdk_bgxx_cmrx_prt_cbfc_ctl bdk_bgxx_cmrx_prt_cbfc_ctl_t;
1469 
1470 static inline uint64_t BDK_BGXX_CMRX_PRT_CBFC_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_PRT_CBFC_CTL(unsigned long a,unsigned long b)1471 static inline uint64_t BDK_BGXX_CMRX_PRT_CBFC_CTL(unsigned long a, unsigned long b)
1472 {
1473     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1474         return 0x87e0e0000508ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1475     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1476         return 0x87e0e0000508ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1477     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1478         return 0x87e0e0000508ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1479     __bdk_csr_fatal("BGXX_CMRX_PRT_CBFC_CTL", 2, a, b, 0, 0);
1480 }
1481 
1482 #define typedef_BDK_BGXX_CMRX_PRT_CBFC_CTL(a,b) bdk_bgxx_cmrx_prt_cbfc_ctl_t
1483 #define bustype_BDK_BGXX_CMRX_PRT_CBFC_CTL(a,b) BDK_CSR_TYPE_RSL
1484 #define basename_BDK_BGXX_CMRX_PRT_CBFC_CTL(a,b) "BGXX_CMRX_PRT_CBFC_CTL"
1485 #define device_bar_BDK_BGXX_CMRX_PRT_CBFC_CTL(a,b) 0x0 /* PF_BAR0 */
1486 #define busnum_BDK_BGXX_CMRX_PRT_CBFC_CTL(a,b) (a)
1487 #define arguments_BDK_BGXX_CMRX_PRT_CBFC_CTL(a,b) (a),(b),-1,-1
1488 
1489 /**
1490  * Register (RSL) bgx#_cmr#_rx_bp_drop
1491  *
1492  * BGX Receive Backpressure Drop Register
1493  */
1494 union bdk_bgxx_cmrx_rx_bp_drop
1495 {
1496     uint64_t u;
1497     struct bdk_bgxx_cmrx_rx_bp_drop_s
1498     {
1499 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1500         uint64_t reserved_7_63         : 57;
1501         uint64_t mark                  : 7;  /**< [  6:  0](R/W) Number of eight-byte cycles to reserve in the RX FIFO. When the number of free
1502                                                                  entries in the RX FIFO is less than or equal to [MARK], incoming packet data is
1503                                                                  dropped. [MARK] additionally indicates the number of entries to reserve in the RX FIFO for
1504                                                                  closing partially received packets. [MARK] should typically be programmed to its reset
1505                                                                  value; failure to program correctly can lead to system instability. */
1506 #else /* Word 0 - Little Endian */
1507         uint64_t mark                  : 7;  /**< [  6:  0](R/W) Number of eight-byte cycles to reserve in the RX FIFO. When the number of free
1508                                                                  entries in the RX FIFO is less than or equal to [MARK], incoming packet data is
1509                                                                  dropped. [MARK] additionally indicates the number of entries to reserve in the RX FIFO for
1510                                                                  closing partially received packets. [MARK] should typically be programmed to its reset
1511                                                                  value; failure to program correctly can lead to system instability. */
1512         uint64_t reserved_7_63         : 57;
1513 #endif /* Word 0 - End */
1514     } s;
1515     /* struct bdk_bgxx_cmrx_rx_bp_drop_s cn; */
1516 };
1517 typedef union bdk_bgxx_cmrx_rx_bp_drop bdk_bgxx_cmrx_rx_bp_drop_t;
1518 
1519 static inline uint64_t BDK_BGXX_CMRX_RX_BP_DROP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_BP_DROP(unsigned long a,unsigned long b)1520 static inline uint64_t BDK_BGXX_CMRX_RX_BP_DROP(unsigned long a, unsigned long b)
1521 {
1522     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1523         return 0x87e0e00000c8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1524     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1525         return 0x87e0e00000c8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1526     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1527         return 0x87e0e00000c8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1528     __bdk_csr_fatal("BGXX_CMRX_RX_BP_DROP", 2, a, b, 0, 0);
1529 }
1530 
1531 #define typedef_BDK_BGXX_CMRX_RX_BP_DROP(a,b) bdk_bgxx_cmrx_rx_bp_drop_t
1532 #define bustype_BDK_BGXX_CMRX_RX_BP_DROP(a,b) BDK_CSR_TYPE_RSL
1533 #define basename_BDK_BGXX_CMRX_RX_BP_DROP(a,b) "BGXX_CMRX_RX_BP_DROP"
1534 #define device_bar_BDK_BGXX_CMRX_RX_BP_DROP(a,b) 0x0 /* PF_BAR0 */
1535 #define busnum_BDK_BGXX_CMRX_RX_BP_DROP(a,b) (a)
1536 #define arguments_BDK_BGXX_CMRX_RX_BP_DROP(a,b) (a),(b),-1,-1
1537 
1538 /**
1539  * Register (RSL) bgx#_cmr#_rx_bp_off
1540  *
1541  * BGX Receive Backpressure Off Register
1542  */
1543 union bdk_bgxx_cmrx_rx_bp_off
1544 {
1545     uint64_t u;
1546     struct bdk_bgxx_cmrx_rx_bp_off_s
1547     {
1548 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1549         uint64_t reserved_7_63         : 57;
1550         uint64_t mark                  : 7;  /**< [  6:  0](R/W) Low watermark (number of eight-byte cycles to deassert backpressure). Level is also used
1551                                                                  to exit the overflow dropping state. */
1552 #else /* Word 0 - Little Endian */
1553         uint64_t mark                  : 7;  /**< [  6:  0](R/W) Low watermark (number of eight-byte cycles to deassert backpressure). Level is also used
1554                                                                  to exit the overflow dropping state. */
1555         uint64_t reserved_7_63         : 57;
1556 #endif /* Word 0 - End */
1557     } s;
1558     /* struct bdk_bgxx_cmrx_rx_bp_off_s cn; */
1559 };
1560 typedef union bdk_bgxx_cmrx_rx_bp_off bdk_bgxx_cmrx_rx_bp_off_t;
1561 
1562 static inline uint64_t BDK_BGXX_CMRX_RX_BP_OFF(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_BP_OFF(unsigned long a,unsigned long b)1563 static inline uint64_t BDK_BGXX_CMRX_RX_BP_OFF(unsigned long a, unsigned long b)
1564 {
1565     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1566         return 0x87e0e00000d8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1567     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1568         return 0x87e0e00000d8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1569     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1570         return 0x87e0e00000d8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1571     __bdk_csr_fatal("BGXX_CMRX_RX_BP_OFF", 2, a, b, 0, 0);
1572 }
1573 
1574 #define typedef_BDK_BGXX_CMRX_RX_BP_OFF(a,b) bdk_bgxx_cmrx_rx_bp_off_t
1575 #define bustype_BDK_BGXX_CMRX_RX_BP_OFF(a,b) BDK_CSR_TYPE_RSL
1576 #define basename_BDK_BGXX_CMRX_RX_BP_OFF(a,b) "BGXX_CMRX_RX_BP_OFF"
1577 #define device_bar_BDK_BGXX_CMRX_RX_BP_OFF(a,b) 0x0 /* PF_BAR0 */
1578 #define busnum_BDK_BGXX_CMRX_RX_BP_OFF(a,b) (a)
1579 #define arguments_BDK_BGXX_CMRX_RX_BP_OFF(a,b) (a),(b),-1,-1
1580 
1581 /**
1582  * Register (RSL) bgx#_cmr#_rx_bp_on
1583  *
1584  * BGX Receive Backpressure On Register
1585  */
1586 union bdk_bgxx_cmrx_rx_bp_on
1587 {
1588     uint64_t u;
1589     struct bdk_bgxx_cmrx_rx_bp_on_s
1590     {
1591 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1592         uint64_t reserved_12_63        : 52;
1593         uint64_t mark                  : 12; /**< [ 11:  0](R/W) High watermark. Buffer depth in multiple of 16-bytes, at which BGX will
1594                                                                  assert backpressure for each individual LMAC. Must satisfy:
1595 
1596                                                                    BGX()_CMR()_RX_BP_OFF[MARK] \<= BGX()_CMR()_RX_BP_ON[MARK] \<
1597                                                                    (FIFO_SIZE - BGX()_CMR()_RX_BP_DROP[MARK]).
1598 
1599                                                                  A value of 0x0 immediately asserts backpressure.
1600 
1601                                                                  The recommended value is 1/4th the size of the per-LMAC RX FIFO_SIZE as
1602                                                                  determined by BGX()_CMR_RX_LMACS[LMACS]. For example in SGMII mode with
1603                                                                  four LMACs of type SGMII, where BGX()_CMR_RX_LMACS[LMACS]=0x4, there is
1604                                                                  16 KB of buffering. The recommended 1/4th size of that 16 KB is 4 KB, which
1605                                                                  in units of 16 bytes gives [MARK] = 0x100 (the reset value). */
1606 #else /* Word 0 - Little Endian */
1607         uint64_t mark                  : 12; /**< [ 11:  0](R/W) High watermark. Buffer depth in multiple of 16-bytes, at which BGX will
1608                                                                  assert backpressure for each individual LMAC. Must satisfy:
1609 
1610                                                                    BGX()_CMR()_RX_BP_OFF[MARK] \<= BGX()_CMR()_RX_BP_ON[MARK] \<
1611                                                                    (FIFO_SIZE - BGX()_CMR()_RX_BP_DROP[MARK]).
1612 
1613                                                                  A value of 0x0 immediately asserts backpressure.
1614 
1615                                                                  The recommended value is 1/4th the size of the per-LMAC RX FIFO_SIZE as
1616                                                                  determined by BGX()_CMR_RX_LMACS[LMACS]. For example in SGMII mode with
1617                                                                  four LMACs of type SGMII, where BGX()_CMR_RX_LMACS[LMACS]=0x4, there is
1618                                                                  16 KB of buffering. The recommended 1/4th size of that 16 KB is 4 KB, which
1619                                                                  in units of 16 bytes gives [MARK] = 0x100 (the reset value). */
1620         uint64_t reserved_12_63        : 52;
1621 #endif /* Word 0 - End */
1622     } s;
1623     /* struct bdk_bgxx_cmrx_rx_bp_on_s cn; */
1624 };
1625 typedef union bdk_bgxx_cmrx_rx_bp_on bdk_bgxx_cmrx_rx_bp_on_t;
1626 
1627 static inline uint64_t BDK_BGXX_CMRX_RX_BP_ON(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_BP_ON(unsigned long a,unsigned long b)1628 static inline uint64_t BDK_BGXX_CMRX_RX_BP_ON(unsigned long a, unsigned long b)
1629 {
1630     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1631         return 0x87e0e00000d0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1632     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1633         return 0x87e0e00000d0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1634     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1635         return 0x87e0e00000d0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1636     __bdk_csr_fatal("BGXX_CMRX_RX_BP_ON", 2, a, b, 0, 0);
1637 }
1638 
1639 #define typedef_BDK_BGXX_CMRX_RX_BP_ON(a,b) bdk_bgxx_cmrx_rx_bp_on_t
1640 #define bustype_BDK_BGXX_CMRX_RX_BP_ON(a,b) BDK_CSR_TYPE_RSL
1641 #define basename_BDK_BGXX_CMRX_RX_BP_ON(a,b) "BGXX_CMRX_RX_BP_ON"
1642 #define device_bar_BDK_BGXX_CMRX_RX_BP_ON(a,b) 0x0 /* PF_BAR0 */
1643 #define busnum_BDK_BGXX_CMRX_RX_BP_ON(a,b) (a)
1644 #define arguments_BDK_BGXX_CMRX_RX_BP_ON(a,b) (a),(b),-1,-1
1645 
1646 /**
1647  * Register (RSL) bgx#_cmr#_rx_bp_status
1648  *
1649  * BGX CMR Receive Backpressure Status Registers
1650  */
1651 union bdk_bgxx_cmrx_rx_bp_status
1652 {
1653     uint64_t u;
1654     struct bdk_bgxx_cmrx_rx_bp_status_s
1655     {
1656 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1657         uint64_t reserved_1_63         : 63;
1658         uint64_t bp                    : 1;  /**< [  0:  0](RO/H) Per-LMAC backpressure status.
1659                                                                  0 = LMAC is not backpressured.
1660                                                                  1 = LMAC is backpressured. */
1661 #else /* Word 0 - Little Endian */
1662         uint64_t bp                    : 1;  /**< [  0:  0](RO/H) Per-LMAC backpressure status.
1663                                                                  0 = LMAC is not backpressured.
1664                                                                  1 = LMAC is backpressured. */
1665         uint64_t reserved_1_63         : 63;
1666 #endif /* Word 0 - End */
1667     } s;
1668     /* struct bdk_bgxx_cmrx_rx_bp_status_s cn; */
1669 };
1670 typedef union bdk_bgxx_cmrx_rx_bp_status bdk_bgxx_cmrx_rx_bp_status_t;
1671 
1672 static inline uint64_t BDK_BGXX_CMRX_RX_BP_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_BP_STATUS(unsigned long a,unsigned long b)1673 static inline uint64_t BDK_BGXX_CMRX_RX_BP_STATUS(unsigned long a, unsigned long b)
1674 {
1675     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1676         return 0x87e0e00000f0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1677     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1678         return 0x87e0e00000f0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1679     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1680         return 0x87e0e00000f0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1681     __bdk_csr_fatal("BGXX_CMRX_RX_BP_STATUS", 2, a, b, 0, 0);
1682 }
1683 
1684 #define typedef_BDK_BGXX_CMRX_RX_BP_STATUS(a,b) bdk_bgxx_cmrx_rx_bp_status_t
1685 #define bustype_BDK_BGXX_CMRX_RX_BP_STATUS(a,b) BDK_CSR_TYPE_RSL
1686 #define basename_BDK_BGXX_CMRX_RX_BP_STATUS(a,b) "BGXX_CMRX_RX_BP_STATUS"
1687 #define device_bar_BDK_BGXX_CMRX_RX_BP_STATUS(a,b) 0x0 /* PF_BAR0 */
1688 #define busnum_BDK_BGXX_CMRX_RX_BP_STATUS(a,b) (a)
1689 #define arguments_BDK_BGXX_CMRX_RX_BP_STATUS(a,b) (a),(b),-1,-1
1690 
1691 /**
1692  * Register (RSL) bgx#_cmr#_rx_dmac_ctl
1693  *
1694  * BGX CMR Receive DMAC Address-Control Register
1695  * Internal:
1696  * "* ALGORITHM
1697  * Here is some pseudo code that represents the address filter behavior.
1698  * dmac_addr_filter(uint8 prt, uint48 dmac) {
1699  * for (lmac=0, lmac\<4, lmac++) {
1700  *   if (is_bcst(dmac))                               // broadcast accept
1701  *     return (BGX()_CMR({lmac})_RX_DMAC_CTL[BCST_ACCEPT] ? ACCEPT : REJECT);
1702  *   if (is_mcst(dmac) && BGX()_CMR({lmac})_RX_DMAC_CTL[MCST_MODE] == 0)   // multicast reject
1703  *     return REJECT;
1704  *   if (is_mcst(dmac) && BGX()_CMR({lmac})_RX_DMAC_CTL[MCST_MODE] == 1)   // multicast accept
1705  *     return ACCEPT;
1706  *   else        // DMAC CAM filter
1707  *     cam_hit = 0;
1708  *   for (i=0; i\<32; i++) {
1709  *     cam = BGX()_CMR_RX_DMAC({i})_CAM;
1710  *     if (cam[EN] && cam[ID] == {lmac} && cam[ADR] == dmac) {
1711  *       cam_hit = 1;
1712  *       break;
1713  *     }
1714  *   }
1715  *   if (cam_hit) {
1716  *     return (BGX()_CMR({lmac})_RX_DMAC_CTL[CAM_ACCEPT] ? ACCEPT : REJECT);
1717  *   else
1718  *     return (BGX()_CMR({lmac})_RX_DMAC_CTL[CAM_ACCEPT] ? REJECT : ACCEPT);
1719  *   }
1720  * }"
1721  */
1722 union bdk_bgxx_cmrx_rx_dmac_ctl
1723 {
1724     uint64_t u;
1725     struct bdk_bgxx_cmrx_rx_dmac_ctl_s
1726     {
1727 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1728         uint64_t reserved_4_63         : 60;
1729         uint64_t cam_accept            : 1;  /**< [  3:  3](R/W) Allow or deny DMAC address filter.
1730                                                                  0 = Reject the packet on DMAC CAM address match.
1731                                                                  1 = Accept the packet on DMAC CAM address match. */
1732         uint64_t mcst_mode             : 2;  /**< [  2:  1](R/W) Multicast mode.
1733                                                                  0x0 = Force reject all multicast packets.
1734                                                                  0x1 = Force accept all multicast packets.
1735                                                                  0x2 = Use the address filter CAM.
1736                                                                  0x3 = Reserved. */
1737         uint64_t bcst_accept           : 1;  /**< [  0:  0](R/W) Allow or deny broadcast packets.
1738                                                                  0 = Reject all broadcast packets.
1739                                                                  1 = Accept all broadcast packets. */
1740 #else /* Word 0 - Little Endian */
1741         uint64_t bcst_accept           : 1;  /**< [  0:  0](R/W) Allow or deny broadcast packets.
1742                                                                  0 = Reject all broadcast packets.
1743                                                                  1 = Accept all broadcast packets. */
1744         uint64_t mcst_mode             : 2;  /**< [  2:  1](R/W) Multicast mode.
1745                                                                  0x0 = Force reject all multicast packets.
1746                                                                  0x1 = Force accept all multicast packets.
1747                                                                  0x2 = Use the address filter CAM.
1748                                                                  0x3 = Reserved. */
1749         uint64_t cam_accept            : 1;  /**< [  3:  3](R/W) Allow or deny DMAC address filter.
1750                                                                  0 = Reject the packet on DMAC CAM address match.
1751                                                                  1 = Accept the packet on DMAC CAM address match. */
1752         uint64_t reserved_4_63         : 60;
1753 #endif /* Word 0 - End */
1754     } s;
1755     /* struct bdk_bgxx_cmrx_rx_dmac_ctl_s cn; */
1756 };
1757 typedef union bdk_bgxx_cmrx_rx_dmac_ctl bdk_bgxx_cmrx_rx_dmac_ctl_t;
1758 
1759 static inline uint64_t BDK_BGXX_CMRX_RX_DMAC_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_DMAC_CTL(unsigned long a,unsigned long b)1760 static inline uint64_t BDK_BGXX_CMRX_RX_DMAC_CTL(unsigned long a, unsigned long b)
1761 {
1762     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1763         return 0x87e0e00000e8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1764     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1765         return 0x87e0e00000e8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1766     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1767         return 0x87e0e00000e8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1768     __bdk_csr_fatal("BGXX_CMRX_RX_DMAC_CTL", 2, a, b, 0, 0);
1769 }
1770 
1771 #define typedef_BDK_BGXX_CMRX_RX_DMAC_CTL(a,b) bdk_bgxx_cmrx_rx_dmac_ctl_t
1772 #define bustype_BDK_BGXX_CMRX_RX_DMAC_CTL(a,b) BDK_CSR_TYPE_RSL
1773 #define basename_BDK_BGXX_CMRX_RX_DMAC_CTL(a,b) "BGXX_CMRX_RX_DMAC_CTL"
1774 #define device_bar_BDK_BGXX_CMRX_RX_DMAC_CTL(a,b) 0x0 /* PF_BAR0 */
1775 #define busnum_BDK_BGXX_CMRX_RX_DMAC_CTL(a,b) (a)
1776 #define arguments_BDK_BGXX_CMRX_RX_DMAC_CTL(a,b) (a),(b),-1,-1
1777 
1778 /**
1779  * Register (RSL) bgx#_cmr#_rx_fifo_len
1780  *
1781  * BGX CMR Receive FIFO Length Registers
1782  */
1783 union bdk_bgxx_cmrx_rx_fifo_len
1784 {
1785     uint64_t u;
1786     struct bdk_bgxx_cmrx_rx_fifo_len_s
1787     {
1788 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1789         uint64_t reserved_14_63        : 50;
1790         uint64_t busy                  : 1;  /**< [ 13: 13](RO/H) Indicates if GMP and CMR are busy processing a packet. Used when bringing an LMAC
1791                                                                  down since in low bandwidth cases, as the FIFO length may often appear to be 0x0. */
1792         uint64_t fifo_len              : 13; /**< [ 12:  0](RO/H) Per-LMAC FIFO length. Useful for determining if FIFO is empty when bringing an LMAC down. */
1793 #else /* Word 0 - Little Endian */
1794         uint64_t fifo_len              : 13; /**< [ 12:  0](RO/H) Per-LMAC FIFO length. Useful for determining if FIFO is empty when bringing an LMAC down. */
1795         uint64_t busy                  : 1;  /**< [ 13: 13](RO/H) Indicates if GMP and CMR are busy processing a packet. Used when bringing an LMAC
1796                                                                  down since in low bandwidth cases, as the FIFO length may often appear to be 0x0. */
1797         uint64_t reserved_14_63        : 50;
1798 #endif /* Word 0 - End */
1799     } s;
1800     /* struct bdk_bgxx_cmrx_rx_fifo_len_s cn81xx; */
1801     struct bdk_bgxx_cmrx_rx_fifo_len_cn88xx
1802     {
1803 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1804         uint64_t reserved_13_63        : 51;
1805         uint64_t fifo_len              : 13; /**< [ 12:  0](RO/H) Per-LMAC FIFO length. Useful for determining if FIFO is empty when bringing an LMAC down. */
1806 #else /* Word 0 - Little Endian */
1807         uint64_t fifo_len              : 13; /**< [ 12:  0](RO/H) Per-LMAC FIFO length. Useful for determining if FIFO is empty when bringing an LMAC down. */
1808         uint64_t reserved_13_63        : 51;
1809 #endif /* Word 0 - End */
1810     } cn88xx;
1811     /* struct bdk_bgxx_cmrx_rx_fifo_len_s cn83xx; */
1812 };
1813 typedef union bdk_bgxx_cmrx_rx_fifo_len bdk_bgxx_cmrx_rx_fifo_len_t;
1814 
1815 static inline uint64_t BDK_BGXX_CMRX_RX_FIFO_LEN(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_FIFO_LEN(unsigned long a,unsigned long b)1816 static inline uint64_t BDK_BGXX_CMRX_RX_FIFO_LEN(unsigned long a, unsigned long b)
1817 {
1818     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1819         return 0x87e0e0000108ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1820     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1821         return 0x87e0e0000108ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1822     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1823         return 0x87e0e0000108ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1824     __bdk_csr_fatal("BGXX_CMRX_RX_FIFO_LEN", 2, a, b, 0, 0);
1825 }
1826 
1827 #define typedef_BDK_BGXX_CMRX_RX_FIFO_LEN(a,b) bdk_bgxx_cmrx_rx_fifo_len_t
1828 #define bustype_BDK_BGXX_CMRX_RX_FIFO_LEN(a,b) BDK_CSR_TYPE_RSL
1829 #define basename_BDK_BGXX_CMRX_RX_FIFO_LEN(a,b) "BGXX_CMRX_RX_FIFO_LEN"
1830 #define device_bar_BDK_BGXX_CMRX_RX_FIFO_LEN(a,b) 0x0 /* PF_BAR0 */
1831 #define busnum_BDK_BGXX_CMRX_RX_FIFO_LEN(a,b) (a)
1832 #define arguments_BDK_BGXX_CMRX_RX_FIFO_LEN(a,b) (a),(b),-1,-1
1833 
1834 /**
1835  * Register (RSL) bgx#_cmr#_rx_id_map
1836  *
1837  * BGX CMR Receive ID Map Register
1838  * These registers set the RX LMAC ID mapping for X2P/NIC.
1839  */
1840 union bdk_bgxx_cmrx_rx_id_map
1841 {
1842     uint64_t u;
1843     struct bdk_bgxx_cmrx_rx_id_map_s
1844     {
1845 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1846         uint64_t reserved_15_63        : 49;
1847         uint64_t rid                   : 7;  /**< [ 14:  8](R/W) Reserved.
1848                                                                  Internal:
1849                                                                  Defeatured. Reassembly ID for Octeon PKI; not used in CN8XXX.
1850                                                                  Reassembly ID map for this LMAC. A shared pool of 96 reassembly IDs (RIDs) exists for all
1851                                                                  MACs.
1852 
1853                                                                  The RID for this LMAC must be constrained such that it does not overlap with any other MAC
1854                                                                  in the system. Its reset value has been chosen such that this condition is satisfied:
1855 
1856                                                                  _ RID reset value = 4*(BGX_ID + 1) + LMAC_ID
1857 
1858                                                                  Changes to RID must only occur when the LMAC is quiescent (i.e. the LMAC receive interface
1859                                                                  is down and the RX FIFO is empty). */
1860         uint64_t unused                : 2;  /**< [  7:  6](RAZ) Reserved. */
1861         uint64_t pknd                  : 6;  /**< [  5:  0](R/W) Port kind for this LMAC. */
1862 #else /* Word 0 - Little Endian */
1863         uint64_t pknd                  : 6;  /**< [  5:  0](R/W) Port kind for this LMAC. */
1864         uint64_t unused                : 2;  /**< [  7:  6](RAZ) Reserved. */
1865         uint64_t rid                   : 7;  /**< [ 14:  8](R/W) Reserved.
1866                                                                  Internal:
1867                                                                  Defeatured. Reassembly ID for Octeon PKI; not used in CN8XXX.
1868                                                                  Reassembly ID map for this LMAC. A shared pool of 96 reassembly IDs (RIDs) exists for all
1869                                                                  MACs.
1870 
1871                                                                  The RID for this LMAC must be constrained such that it does not overlap with any other MAC
1872                                                                  in the system. Its reset value has been chosen such that this condition is satisfied:
1873 
1874                                                                  _ RID reset value = 4*(BGX_ID + 1) + LMAC_ID
1875 
1876                                                                  Changes to RID must only occur when the LMAC is quiescent (i.e. the LMAC receive interface
1877                                                                  is down and the RX FIFO is empty). */
1878         uint64_t reserved_15_63        : 49;
1879 #endif /* Word 0 - End */
1880     } s;
1881     /* struct bdk_bgxx_cmrx_rx_id_map_s cn; */
1882 };
1883 typedef union bdk_bgxx_cmrx_rx_id_map bdk_bgxx_cmrx_rx_id_map_t;
1884 
1885 static inline uint64_t BDK_BGXX_CMRX_RX_ID_MAP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_ID_MAP(unsigned long a,unsigned long b)1886 static inline uint64_t BDK_BGXX_CMRX_RX_ID_MAP(unsigned long a, unsigned long b)
1887 {
1888     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1889         return 0x87e0e0000060ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1890     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1891         return 0x87e0e0000060ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1892     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1893         return 0x87e0e0000060ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1894     __bdk_csr_fatal("BGXX_CMRX_RX_ID_MAP", 2, a, b, 0, 0);
1895 }
1896 
1897 #define typedef_BDK_BGXX_CMRX_RX_ID_MAP(a,b) bdk_bgxx_cmrx_rx_id_map_t
1898 #define bustype_BDK_BGXX_CMRX_RX_ID_MAP(a,b) BDK_CSR_TYPE_RSL
1899 #define basename_BDK_BGXX_CMRX_RX_ID_MAP(a,b) "BGXX_CMRX_RX_ID_MAP"
1900 #define device_bar_BDK_BGXX_CMRX_RX_ID_MAP(a,b) 0x0 /* PF_BAR0 */
1901 #define busnum_BDK_BGXX_CMRX_RX_ID_MAP(a,b) (a)
1902 #define arguments_BDK_BGXX_CMRX_RX_ID_MAP(a,b) (a),(b),-1,-1
1903 
1904 /**
1905  * Register (RSL) bgx#_cmr#_rx_logl_xoff
1906  *
1907  * BGX CMR Receive Logical XOFF Registers
1908  */
1909 union bdk_bgxx_cmrx_rx_logl_xoff
1910 {
1911     uint64_t u;
1912     struct bdk_bgxx_cmrx_rx_logl_xoff_s
1913     {
1914 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1915         uint64_t reserved_16_63        : 48;
1916         uint64_t xoff                  : 16; /**< [ 15:  0](R/W1S/H) Together with BGX()_CMR()_RX_LOGL_XON, defines type of channel backpressure to
1917                                                                  apply to the MAC. In the case of SMU, Do not write when HiGig2 is
1918                                                                  enabled. Writing 1 sets the same physical register as that which is cleared by
1919                                                                  BGX()_CMR()_RX_LOGL_XON[XON]. An XOFF value of 1 will cause a backpressure on
1920                                                                  the MAC. */
1921 #else /* Word 0 - Little Endian */
1922         uint64_t xoff                  : 16; /**< [ 15:  0](R/W1S/H) Together with BGX()_CMR()_RX_LOGL_XON, defines type of channel backpressure to
1923                                                                  apply to the MAC. In the case of SMU, Do not write when HiGig2 is
1924                                                                  enabled. Writing 1 sets the same physical register as that which is cleared by
1925                                                                  BGX()_CMR()_RX_LOGL_XON[XON]. An XOFF value of 1 will cause a backpressure on
1926                                                                  the MAC. */
1927         uint64_t reserved_16_63        : 48;
1928 #endif /* Word 0 - End */
1929     } s;
1930     /* struct bdk_bgxx_cmrx_rx_logl_xoff_s cn; */
1931 };
1932 typedef union bdk_bgxx_cmrx_rx_logl_xoff bdk_bgxx_cmrx_rx_logl_xoff_t;
1933 
1934 static inline uint64_t BDK_BGXX_CMRX_RX_LOGL_XOFF(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_LOGL_XOFF(unsigned long a,unsigned long b)1935 static inline uint64_t BDK_BGXX_CMRX_RX_LOGL_XOFF(unsigned long a, unsigned long b)
1936 {
1937     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
1938         return 0x87e0e00000f8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1939     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
1940         return 0x87e0e00000f8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
1941     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
1942         return 0x87e0e00000f8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
1943     __bdk_csr_fatal("BGXX_CMRX_RX_LOGL_XOFF", 2, a, b, 0, 0);
1944 }
1945 
1946 #define typedef_BDK_BGXX_CMRX_RX_LOGL_XOFF(a,b) bdk_bgxx_cmrx_rx_logl_xoff_t
1947 #define bustype_BDK_BGXX_CMRX_RX_LOGL_XOFF(a,b) BDK_CSR_TYPE_RSL
1948 #define basename_BDK_BGXX_CMRX_RX_LOGL_XOFF(a,b) "BGXX_CMRX_RX_LOGL_XOFF"
1949 #define device_bar_BDK_BGXX_CMRX_RX_LOGL_XOFF(a,b) 0x0 /* PF_BAR0 */
1950 #define busnum_BDK_BGXX_CMRX_RX_LOGL_XOFF(a,b) (a)
1951 #define arguments_BDK_BGXX_CMRX_RX_LOGL_XOFF(a,b) (a),(b),-1,-1
1952 
1953 /**
1954  * Register (RSL) bgx#_cmr#_rx_logl_xon
1955  *
1956  * BGX CMR Receive Logical XON Registers
1957  */
1958 union bdk_bgxx_cmrx_rx_logl_xon
1959 {
1960     uint64_t u;
1961     struct bdk_bgxx_cmrx_rx_logl_xon_s
1962     {
1963 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1964         uint64_t reserved_16_63        : 48;
1965         uint64_t xon                   : 16; /**< [ 15:  0](R/W1C/H) Together with BGX()_CMR()_RX_LOGL_XOFF, defines type of channel backpressure to
1966                                                                  apply. Do not write when HiGig2 is enabled. Writing 1 clears the same physical register as
1967                                                                  that which is set by XOFF. An XON value of 1 means only NIC channel BP can cause a
1968                                                                  backpressure on the MAC. */
1969 #else /* Word 0 - Little Endian */
1970         uint64_t xon                   : 16; /**< [ 15:  0](R/W1C/H) Together with BGX()_CMR()_RX_LOGL_XOFF, defines type of channel backpressure to
1971                                                                  apply. Do not write when HiGig2 is enabled. Writing 1 clears the same physical register as
1972                                                                  that which is set by XOFF. An XON value of 1 means only NIC channel BP can cause a
1973                                                                  backpressure on the MAC. */
1974         uint64_t reserved_16_63        : 48;
1975 #endif /* Word 0 - End */
1976     } s;
1977     /* struct bdk_bgxx_cmrx_rx_logl_xon_s cn81xx; */
1978     struct bdk_bgxx_cmrx_rx_logl_xon_cn88xx
1979     {
1980 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1981         uint64_t reserved_16_63        : 48;
1982         uint64_t xon                   : 16; /**< [ 15:  0](R/W1C/H) Together with BGX()_CMR()_RX_LOGL_XOFF, defines type of channel backpressure to
1983                                                                  apply. Do not write when HiGig2 is enabled. Writing 1 clears the same physical register as
1984                                                                  that which is set by XOFF. An XON value of 1 means only NIC channel BP can cause a
1985                                                                  backpressure on SMU. */
1986 #else /* Word 0 - Little Endian */
1987         uint64_t xon                   : 16; /**< [ 15:  0](R/W1C/H) Together with BGX()_CMR()_RX_LOGL_XOFF, defines type of channel backpressure to
1988                                                                  apply. Do not write when HiGig2 is enabled. Writing 1 clears the same physical register as
1989                                                                  that which is set by XOFF. An XON value of 1 means only NIC channel BP can cause a
1990                                                                  backpressure on SMU. */
1991         uint64_t reserved_16_63        : 48;
1992 #endif /* Word 0 - End */
1993     } cn88xx;
1994     /* struct bdk_bgxx_cmrx_rx_logl_xon_s cn83xx; */
1995 };
1996 typedef union bdk_bgxx_cmrx_rx_logl_xon bdk_bgxx_cmrx_rx_logl_xon_t;
1997 
1998 static inline uint64_t BDK_BGXX_CMRX_RX_LOGL_XON(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_LOGL_XON(unsigned long a,unsigned long b)1999 static inline uint64_t BDK_BGXX_CMRX_RX_LOGL_XON(unsigned long a, unsigned long b)
2000 {
2001     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2002         return 0x87e0e0000100ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2003     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2004         return 0x87e0e0000100ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2005     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2006         return 0x87e0e0000100ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2007     __bdk_csr_fatal("BGXX_CMRX_RX_LOGL_XON", 2, a, b, 0, 0);
2008 }
2009 
2010 #define typedef_BDK_BGXX_CMRX_RX_LOGL_XON(a,b) bdk_bgxx_cmrx_rx_logl_xon_t
2011 #define bustype_BDK_BGXX_CMRX_RX_LOGL_XON(a,b) BDK_CSR_TYPE_RSL
2012 #define basename_BDK_BGXX_CMRX_RX_LOGL_XON(a,b) "BGXX_CMRX_RX_LOGL_XON"
2013 #define device_bar_BDK_BGXX_CMRX_RX_LOGL_XON(a,b) 0x0 /* PF_BAR0 */
2014 #define busnum_BDK_BGXX_CMRX_RX_LOGL_XON(a,b) (a)
2015 #define arguments_BDK_BGXX_CMRX_RX_LOGL_XON(a,b) (a),(b),-1,-1
2016 
2017 /**
2018  * Register (RSL) bgx#_cmr#_rx_pause_drop_time
2019  *
2020  * BGX CMR Receive Pause Drop-Time Register
2021  */
2022 union bdk_bgxx_cmrx_rx_pause_drop_time
2023 {
2024     uint64_t u;
2025     struct bdk_bgxx_cmrx_rx_pause_drop_time_s
2026     {
2027 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2028         uint64_t reserved_16_63        : 48;
2029         uint64_t pause_time            : 16; /**< [ 15:  0](R/W1C/H) Time extracted from the dropped PAUSE packet dropped due to RXB FIFO full or during partner reset. */
2030 #else /* Word 0 - Little Endian */
2031         uint64_t pause_time            : 16; /**< [ 15:  0](R/W1C/H) Time extracted from the dropped PAUSE packet dropped due to RXB FIFO full or during partner reset. */
2032         uint64_t reserved_16_63        : 48;
2033 #endif /* Word 0 - End */
2034     } s;
2035     /* struct bdk_bgxx_cmrx_rx_pause_drop_time_s cn; */
2036 };
2037 typedef union bdk_bgxx_cmrx_rx_pause_drop_time bdk_bgxx_cmrx_rx_pause_drop_time_t;
2038 
2039 static inline uint64_t BDK_BGXX_CMRX_RX_PAUSE_DROP_TIME(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_PAUSE_DROP_TIME(unsigned long a,unsigned long b)2040 static inline uint64_t BDK_BGXX_CMRX_RX_PAUSE_DROP_TIME(unsigned long a, unsigned long b)
2041 {
2042     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2043         return 0x87e0e0000068ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2044     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2045         return 0x87e0e0000068ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2046     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2047         return 0x87e0e0000068ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2048     __bdk_csr_fatal("BGXX_CMRX_RX_PAUSE_DROP_TIME", 2, a, b, 0, 0);
2049 }
2050 
2051 #define typedef_BDK_BGXX_CMRX_RX_PAUSE_DROP_TIME(a,b) bdk_bgxx_cmrx_rx_pause_drop_time_t
2052 #define bustype_BDK_BGXX_CMRX_RX_PAUSE_DROP_TIME(a,b) BDK_CSR_TYPE_RSL
2053 #define basename_BDK_BGXX_CMRX_RX_PAUSE_DROP_TIME(a,b) "BGXX_CMRX_RX_PAUSE_DROP_TIME"
2054 #define device_bar_BDK_BGXX_CMRX_RX_PAUSE_DROP_TIME(a,b) 0x0 /* PF_BAR0 */
2055 #define busnum_BDK_BGXX_CMRX_RX_PAUSE_DROP_TIME(a,b) (a)
2056 #define arguments_BDK_BGXX_CMRX_RX_PAUSE_DROP_TIME(a,b) (a),(b),-1,-1
2057 
2058 /**
2059  * Register (RSL) bgx#_cmr#_rx_stat0
2060  *
2061  * BGX Receive Status Register 0
2062  * These registers provide a count of received packets that meet the following conditions:
2063  * * are not recognized as PAUSE packets.
2064  * * are not dropped due DMAC filtering.
2065  * * are not dropped due FIFO full status.
2066  * * do not have any other OPCODE (FCS, Length, etc).
2067  */
2068 union bdk_bgxx_cmrx_rx_stat0
2069 {
2070     uint64_t u;
2071     struct bdk_bgxx_cmrx_rx_stat0_s
2072     {
2073 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2074         uint64_t reserved_48_63        : 16;
2075         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of received packets. [CNT] will wrap and is cleared if LMAC is disabled with
2076                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2077 #else /* Word 0 - Little Endian */
2078         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of received packets. [CNT] will wrap and is cleared if LMAC is disabled with
2079                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2080         uint64_t reserved_48_63        : 16;
2081 #endif /* Word 0 - End */
2082     } s;
2083     /* struct bdk_bgxx_cmrx_rx_stat0_s cn; */
2084 };
2085 typedef union bdk_bgxx_cmrx_rx_stat0 bdk_bgxx_cmrx_rx_stat0_t;
2086 
2087 static inline uint64_t BDK_BGXX_CMRX_RX_STAT0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_STAT0(unsigned long a,unsigned long b)2088 static inline uint64_t BDK_BGXX_CMRX_RX_STAT0(unsigned long a, unsigned long b)
2089 {
2090     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2091         return 0x87e0e0000070ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2092     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2093         return 0x87e0e0000070ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2094     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2095         return 0x87e0e0000070ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2096     __bdk_csr_fatal("BGXX_CMRX_RX_STAT0", 2, a, b, 0, 0);
2097 }
2098 
2099 #define typedef_BDK_BGXX_CMRX_RX_STAT0(a,b) bdk_bgxx_cmrx_rx_stat0_t
2100 #define bustype_BDK_BGXX_CMRX_RX_STAT0(a,b) BDK_CSR_TYPE_RSL
2101 #define basename_BDK_BGXX_CMRX_RX_STAT0(a,b) "BGXX_CMRX_RX_STAT0"
2102 #define device_bar_BDK_BGXX_CMRX_RX_STAT0(a,b) 0x0 /* PF_BAR0 */
2103 #define busnum_BDK_BGXX_CMRX_RX_STAT0(a,b) (a)
2104 #define arguments_BDK_BGXX_CMRX_RX_STAT0(a,b) (a),(b),-1,-1
2105 
2106 /**
2107  * Register (RSL) bgx#_cmr#_rx_stat1
2108  *
2109  * BGX Receive Status Register 1
2110  * These registers provide a count of octets of received packets.
2111  */
2112 union bdk_bgxx_cmrx_rx_stat1
2113 {
2114     uint64_t u;
2115     struct bdk_bgxx_cmrx_rx_stat1_s
2116     {
2117 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2118         uint64_t reserved_48_63        : 16;
2119         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of received packets. [CNT] will wrap and is cleared if LMAC is disabled with
2120                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2121 #else /* Word 0 - Little Endian */
2122         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of received packets. [CNT] will wrap and is cleared if LMAC is disabled with
2123                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2124         uint64_t reserved_48_63        : 16;
2125 #endif /* Word 0 - End */
2126     } s;
2127     /* struct bdk_bgxx_cmrx_rx_stat1_s cn; */
2128 };
2129 typedef union bdk_bgxx_cmrx_rx_stat1 bdk_bgxx_cmrx_rx_stat1_t;
2130 
2131 static inline uint64_t BDK_BGXX_CMRX_RX_STAT1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_STAT1(unsigned long a,unsigned long b)2132 static inline uint64_t BDK_BGXX_CMRX_RX_STAT1(unsigned long a, unsigned long b)
2133 {
2134     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2135         return 0x87e0e0000078ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2136     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2137         return 0x87e0e0000078ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2138     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2139         return 0x87e0e0000078ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2140     __bdk_csr_fatal("BGXX_CMRX_RX_STAT1", 2, a, b, 0, 0);
2141 }
2142 
2143 #define typedef_BDK_BGXX_CMRX_RX_STAT1(a,b) bdk_bgxx_cmrx_rx_stat1_t
2144 #define bustype_BDK_BGXX_CMRX_RX_STAT1(a,b) BDK_CSR_TYPE_RSL
2145 #define basename_BDK_BGXX_CMRX_RX_STAT1(a,b) "BGXX_CMRX_RX_STAT1"
2146 #define device_bar_BDK_BGXX_CMRX_RX_STAT1(a,b) 0x0 /* PF_BAR0 */
2147 #define busnum_BDK_BGXX_CMRX_RX_STAT1(a,b) (a)
2148 #define arguments_BDK_BGXX_CMRX_RX_STAT1(a,b) (a),(b),-1,-1
2149 
2150 /**
2151  * Register (RSL) bgx#_cmr#_rx_stat2
2152  *
2153  * BGX Receive Status Register 2
2154  * These registers provide a count of all packets received that were recognized as flow-control
2155  * or PAUSE packets. PAUSE packets with any kind of error are counted in
2156  * BGX()_CMR()_RX_STAT8 (error stats register). Pause packets can be optionally dropped
2157  * or forwarded based on BGX()_SMU()_RX_FRM_CTL[CTL_DRP]. This count increments
2158  * regardless of whether the packet is dropped. PAUSE packets are never counted in
2159  * BGX()_CMR()_RX_STAT0.
2160  */
2161 union bdk_bgxx_cmrx_rx_stat2
2162 {
2163     uint64_t u;
2164     struct bdk_bgxx_cmrx_rx_stat2_s
2165     {
2166 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2167         uint64_t reserved_48_63        : 16;
2168         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of received PAUSE packets. [CNT] will wrap and is cleared if LMAC is disabled with
2169                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2170 #else /* Word 0 - Little Endian */
2171         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of received PAUSE packets. [CNT] will wrap and is cleared if LMAC is disabled with
2172                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2173         uint64_t reserved_48_63        : 16;
2174 #endif /* Word 0 - End */
2175     } s;
2176     /* struct bdk_bgxx_cmrx_rx_stat2_s cn; */
2177 };
2178 typedef union bdk_bgxx_cmrx_rx_stat2 bdk_bgxx_cmrx_rx_stat2_t;
2179 
2180 static inline uint64_t BDK_BGXX_CMRX_RX_STAT2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_STAT2(unsigned long a,unsigned long b)2181 static inline uint64_t BDK_BGXX_CMRX_RX_STAT2(unsigned long a, unsigned long b)
2182 {
2183     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2184         return 0x87e0e0000080ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2185     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2186         return 0x87e0e0000080ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2187     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2188         return 0x87e0e0000080ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2189     __bdk_csr_fatal("BGXX_CMRX_RX_STAT2", 2, a, b, 0, 0);
2190 }
2191 
2192 #define typedef_BDK_BGXX_CMRX_RX_STAT2(a,b) bdk_bgxx_cmrx_rx_stat2_t
2193 #define bustype_BDK_BGXX_CMRX_RX_STAT2(a,b) BDK_CSR_TYPE_RSL
2194 #define basename_BDK_BGXX_CMRX_RX_STAT2(a,b) "BGXX_CMRX_RX_STAT2"
2195 #define device_bar_BDK_BGXX_CMRX_RX_STAT2(a,b) 0x0 /* PF_BAR0 */
2196 #define busnum_BDK_BGXX_CMRX_RX_STAT2(a,b) (a)
2197 #define arguments_BDK_BGXX_CMRX_RX_STAT2(a,b) (a),(b),-1,-1
2198 
2199 /**
2200  * Register (RSL) bgx#_cmr#_rx_stat3
2201  *
2202  * BGX Receive Status Register 3
2203  * These registers provide a count of octets of received PAUSE and control packets.
2204  */
2205 union bdk_bgxx_cmrx_rx_stat3
2206 {
2207     uint64_t u;
2208     struct bdk_bgxx_cmrx_rx_stat3_s
2209     {
2210 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2211         uint64_t reserved_48_63        : 16;
2212         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of received PAUSE packets. [CNT] will wrap and is cleared if LMAC is disabled
2213                                                                  with BGX()_CMR()_CONFIG[ENABLE]=0. */
2214 #else /* Word 0 - Little Endian */
2215         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of received PAUSE packets. [CNT] will wrap and is cleared if LMAC is disabled
2216                                                                  with BGX()_CMR()_CONFIG[ENABLE]=0. */
2217         uint64_t reserved_48_63        : 16;
2218 #endif /* Word 0 - End */
2219     } s;
2220     /* struct bdk_bgxx_cmrx_rx_stat3_s cn; */
2221 };
2222 typedef union bdk_bgxx_cmrx_rx_stat3 bdk_bgxx_cmrx_rx_stat3_t;
2223 
2224 static inline uint64_t BDK_BGXX_CMRX_RX_STAT3(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_STAT3(unsigned long a,unsigned long b)2225 static inline uint64_t BDK_BGXX_CMRX_RX_STAT3(unsigned long a, unsigned long b)
2226 {
2227     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2228         return 0x87e0e0000088ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2229     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2230         return 0x87e0e0000088ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2231     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2232         return 0x87e0e0000088ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2233     __bdk_csr_fatal("BGXX_CMRX_RX_STAT3", 2, a, b, 0, 0);
2234 }
2235 
2236 #define typedef_BDK_BGXX_CMRX_RX_STAT3(a,b) bdk_bgxx_cmrx_rx_stat3_t
2237 #define bustype_BDK_BGXX_CMRX_RX_STAT3(a,b) BDK_CSR_TYPE_RSL
2238 #define basename_BDK_BGXX_CMRX_RX_STAT3(a,b) "BGXX_CMRX_RX_STAT3"
2239 #define device_bar_BDK_BGXX_CMRX_RX_STAT3(a,b) 0x0 /* PF_BAR0 */
2240 #define busnum_BDK_BGXX_CMRX_RX_STAT3(a,b) (a)
2241 #define arguments_BDK_BGXX_CMRX_RX_STAT3(a,b) (a),(b),-1,-1
2242 
2243 /**
2244  * Register (RSL) bgx#_cmr#_rx_stat4
2245  *
2246  * BGX Receive Status Register 4
2247  * These registers provide a count of all packets received that were dropped by the DMAC filter.
2248  * Packets that match the DMAC are dropped and counted here regardless of whether they were ERR
2249  * packets, but does not include those reported in BGX()_CMR()_RX_STAT6. These packets
2250  * are never counted in BGX()_CMR()_RX_STAT0. Eight-byte packets as the result of
2251  * truncation or other means are not dropped by CNXXXX and will never appear in this count.
2252  */
2253 union bdk_bgxx_cmrx_rx_stat4
2254 {
2255     uint64_t u;
2256     struct bdk_bgxx_cmrx_rx_stat4_s
2257     {
2258 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2259         uint64_t reserved_48_63        : 16;
2260         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of filtered DMAC packets. [CNT] will wrap and is cleared if LMAC is disabled with
2261                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2262 #else /* Word 0 - Little Endian */
2263         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of filtered DMAC packets. [CNT] will wrap and is cleared if LMAC is disabled with
2264                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2265         uint64_t reserved_48_63        : 16;
2266 #endif /* Word 0 - End */
2267     } s;
2268     /* struct bdk_bgxx_cmrx_rx_stat4_s cn; */
2269 };
2270 typedef union bdk_bgxx_cmrx_rx_stat4 bdk_bgxx_cmrx_rx_stat4_t;
2271 
2272 static inline uint64_t BDK_BGXX_CMRX_RX_STAT4(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_STAT4(unsigned long a,unsigned long b)2273 static inline uint64_t BDK_BGXX_CMRX_RX_STAT4(unsigned long a, unsigned long b)
2274 {
2275     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2276         return 0x87e0e0000090ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2277     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2278         return 0x87e0e0000090ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2279     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2280         return 0x87e0e0000090ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2281     __bdk_csr_fatal("BGXX_CMRX_RX_STAT4", 2, a, b, 0, 0);
2282 }
2283 
2284 #define typedef_BDK_BGXX_CMRX_RX_STAT4(a,b) bdk_bgxx_cmrx_rx_stat4_t
2285 #define bustype_BDK_BGXX_CMRX_RX_STAT4(a,b) BDK_CSR_TYPE_RSL
2286 #define basename_BDK_BGXX_CMRX_RX_STAT4(a,b) "BGXX_CMRX_RX_STAT4"
2287 #define device_bar_BDK_BGXX_CMRX_RX_STAT4(a,b) 0x0 /* PF_BAR0 */
2288 #define busnum_BDK_BGXX_CMRX_RX_STAT4(a,b) (a)
2289 #define arguments_BDK_BGXX_CMRX_RX_STAT4(a,b) (a),(b),-1,-1
2290 
2291 /**
2292  * Register (RSL) bgx#_cmr#_rx_stat5
2293  *
2294  * BGX Receive Status Register 5
2295  * These registers provide a count of octets of filtered DMAC packets.
2296  */
2297 union bdk_bgxx_cmrx_rx_stat5
2298 {
2299     uint64_t u;
2300     struct bdk_bgxx_cmrx_rx_stat5_s
2301     {
2302 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2303         uint64_t reserved_48_63        : 16;
2304         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of filtered DMAC packets. [CNT] will wrap and is cleared if LMAC is disabled
2305                                                                  with BGX()_CMR()_CONFIG[ENABLE]=0. */
2306 #else /* Word 0 - Little Endian */
2307         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of filtered DMAC packets. [CNT] will wrap and is cleared if LMAC is disabled
2308                                                                  with BGX()_CMR()_CONFIG[ENABLE]=0. */
2309         uint64_t reserved_48_63        : 16;
2310 #endif /* Word 0 - End */
2311     } s;
2312     /* struct bdk_bgxx_cmrx_rx_stat5_s cn; */
2313 };
2314 typedef union bdk_bgxx_cmrx_rx_stat5 bdk_bgxx_cmrx_rx_stat5_t;
2315 
2316 static inline uint64_t BDK_BGXX_CMRX_RX_STAT5(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_STAT5(unsigned long a,unsigned long b)2317 static inline uint64_t BDK_BGXX_CMRX_RX_STAT5(unsigned long a, unsigned long b)
2318 {
2319     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2320         return 0x87e0e0000098ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2321     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2322         return 0x87e0e0000098ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2323     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2324         return 0x87e0e0000098ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2325     __bdk_csr_fatal("BGXX_CMRX_RX_STAT5", 2, a, b, 0, 0);
2326 }
2327 
2328 #define typedef_BDK_BGXX_CMRX_RX_STAT5(a,b) bdk_bgxx_cmrx_rx_stat5_t
2329 #define bustype_BDK_BGXX_CMRX_RX_STAT5(a,b) BDK_CSR_TYPE_RSL
2330 #define basename_BDK_BGXX_CMRX_RX_STAT5(a,b) "BGXX_CMRX_RX_STAT5"
2331 #define device_bar_BDK_BGXX_CMRX_RX_STAT5(a,b) 0x0 /* PF_BAR0 */
2332 #define busnum_BDK_BGXX_CMRX_RX_STAT5(a,b) (a)
2333 #define arguments_BDK_BGXX_CMRX_RX_STAT5(a,b) (a),(b),-1,-1
2334 
2335 /**
2336  * Register (RSL) bgx#_cmr#_rx_stat6
2337  *
2338  * BGX Receive Status Register 6
2339  * These registers provide a count of all packets received that were dropped due to a full
2340  * receive FIFO. They do not count any packet that is truncated at the point of overflow and sent
2341  * on to the NIC. These registers count all entire packets dropped by the FIFO for a given LMAC
2342  * regardless of DMAC or PAUSE type.
2343  */
2344 union bdk_bgxx_cmrx_rx_stat6
2345 {
2346     uint64_t u;
2347     struct bdk_bgxx_cmrx_rx_stat6_s
2348     {
2349 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2350         uint64_t reserved_48_63        : 16;
2351         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of dropped packets. [CNT] will wrap and is cleared if LMAC is disabled with
2352                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2353 #else /* Word 0 - Little Endian */
2354         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of dropped packets. [CNT] will wrap and is cleared if LMAC is disabled with
2355                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2356         uint64_t reserved_48_63        : 16;
2357 #endif /* Word 0 - End */
2358     } s;
2359     /* struct bdk_bgxx_cmrx_rx_stat6_s cn; */
2360 };
2361 typedef union bdk_bgxx_cmrx_rx_stat6 bdk_bgxx_cmrx_rx_stat6_t;
2362 
2363 static inline uint64_t BDK_BGXX_CMRX_RX_STAT6(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_STAT6(unsigned long a,unsigned long b)2364 static inline uint64_t BDK_BGXX_CMRX_RX_STAT6(unsigned long a, unsigned long b)
2365 {
2366     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2367         return 0x87e0e00000a0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2368     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2369         return 0x87e0e00000a0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2370     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2371         return 0x87e0e00000a0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2372     __bdk_csr_fatal("BGXX_CMRX_RX_STAT6", 2, a, b, 0, 0);
2373 }
2374 
2375 #define typedef_BDK_BGXX_CMRX_RX_STAT6(a,b) bdk_bgxx_cmrx_rx_stat6_t
2376 #define bustype_BDK_BGXX_CMRX_RX_STAT6(a,b) BDK_CSR_TYPE_RSL
2377 #define basename_BDK_BGXX_CMRX_RX_STAT6(a,b) "BGXX_CMRX_RX_STAT6"
2378 #define device_bar_BDK_BGXX_CMRX_RX_STAT6(a,b) 0x0 /* PF_BAR0 */
2379 #define busnum_BDK_BGXX_CMRX_RX_STAT6(a,b) (a)
2380 #define arguments_BDK_BGXX_CMRX_RX_STAT6(a,b) (a),(b),-1,-1
2381 
2382 /**
2383  * Register (RSL) bgx#_cmr#_rx_stat7
2384  *
2385  * BGX Receive Status Register 7
2386  * These registers provide a count of octets of received packets that were dropped due to a full
2387  * receive FIFO.
2388  */
2389 union bdk_bgxx_cmrx_rx_stat7
2390 {
2391     uint64_t u;
2392     struct bdk_bgxx_cmrx_rx_stat7_s
2393     {
2394 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2395         uint64_t reserved_48_63        : 16;
2396         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of dropped packets. [CNT] will wrap and is cleared if LMAC is disabled with
2397                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2398 #else /* Word 0 - Little Endian */
2399         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of dropped packets. [CNT] will wrap and is cleared if LMAC is disabled with
2400                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2401         uint64_t reserved_48_63        : 16;
2402 #endif /* Word 0 - End */
2403     } s;
2404     /* struct bdk_bgxx_cmrx_rx_stat7_s cn; */
2405 };
2406 typedef union bdk_bgxx_cmrx_rx_stat7 bdk_bgxx_cmrx_rx_stat7_t;
2407 
2408 static inline uint64_t BDK_BGXX_CMRX_RX_STAT7(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_STAT7(unsigned long a,unsigned long b)2409 static inline uint64_t BDK_BGXX_CMRX_RX_STAT7(unsigned long a, unsigned long b)
2410 {
2411     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2412         return 0x87e0e00000a8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2413     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2414         return 0x87e0e00000a8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2415     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2416         return 0x87e0e00000a8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2417     __bdk_csr_fatal("BGXX_CMRX_RX_STAT7", 2, a, b, 0, 0);
2418 }
2419 
2420 #define typedef_BDK_BGXX_CMRX_RX_STAT7(a,b) bdk_bgxx_cmrx_rx_stat7_t
2421 #define bustype_BDK_BGXX_CMRX_RX_STAT7(a,b) BDK_CSR_TYPE_RSL
2422 #define basename_BDK_BGXX_CMRX_RX_STAT7(a,b) "BGXX_CMRX_RX_STAT7"
2423 #define device_bar_BDK_BGXX_CMRX_RX_STAT7(a,b) 0x0 /* PF_BAR0 */
2424 #define busnum_BDK_BGXX_CMRX_RX_STAT7(a,b) (a)
2425 #define arguments_BDK_BGXX_CMRX_RX_STAT7(a,b) (a),(b),-1,-1
2426 
2427 /**
2428  * Register (RSL) bgx#_cmr#_rx_stat8
2429  *
2430  * BGX Receive Status Register 8
2431  * These registers provide a count of all packets received with some error that were not dropped
2432  * either due to the DMAC filter or lack of room in the receive FIFO.
2433  * This does not include packets which were counted in
2434  * BGX()_CMR()_RX_STAT2, BGX()_CMR()_RX_STAT4 nor
2435  * BGX()_CMR()_RX_STAT6.
2436  *
2437  * Which statistics are updated on control packet errors and drops are shown below:
2438  *
2439  * \<pre\>
2440  * if dropped {
2441  *   if !errored STAT8
2442  *   if overflow STAT6
2443  *   else if dmac drop STAT4
2444  *   else if filter drop STAT2
2445  * } else {
2446  *   if errored STAT2
2447  *   else STAT8
2448  * }
2449  * \</pre\>
2450  */
2451 union bdk_bgxx_cmrx_rx_stat8
2452 {
2453     uint64_t u;
2454     struct bdk_bgxx_cmrx_rx_stat8_s
2455     {
2456 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2457         uint64_t reserved_48_63        : 16;
2458         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of error packets. [CNT] will wrap and is cleared if LMAC is disabled with
2459                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2460 #else /* Word 0 - Little Endian */
2461         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of error packets. [CNT] will wrap and is cleared if LMAC is disabled with
2462                                                                  BGX()_CMR()_CONFIG[ENABLE]=0. */
2463         uint64_t reserved_48_63        : 16;
2464 #endif /* Word 0 - End */
2465     } s;
2466     /* struct bdk_bgxx_cmrx_rx_stat8_s cn; */
2467 };
2468 typedef union bdk_bgxx_cmrx_rx_stat8 bdk_bgxx_cmrx_rx_stat8_t;
2469 
2470 static inline uint64_t BDK_BGXX_CMRX_RX_STAT8(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_STAT8(unsigned long a,unsigned long b)2471 static inline uint64_t BDK_BGXX_CMRX_RX_STAT8(unsigned long a, unsigned long b)
2472 {
2473     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2474         return 0x87e0e00000b0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2475     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2476         return 0x87e0e00000b0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2477     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2478         return 0x87e0e00000b0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2479     __bdk_csr_fatal("BGXX_CMRX_RX_STAT8", 2, a, b, 0, 0);
2480 }
2481 
2482 #define typedef_BDK_BGXX_CMRX_RX_STAT8(a,b) bdk_bgxx_cmrx_rx_stat8_t
2483 #define bustype_BDK_BGXX_CMRX_RX_STAT8(a,b) BDK_CSR_TYPE_RSL
2484 #define basename_BDK_BGXX_CMRX_RX_STAT8(a,b) "BGXX_CMRX_RX_STAT8"
2485 #define device_bar_BDK_BGXX_CMRX_RX_STAT8(a,b) 0x0 /* PF_BAR0 */
2486 #define busnum_BDK_BGXX_CMRX_RX_STAT8(a,b) (a)
2487 #define arguments_BDK_BGXX_CMRX_RX_STAT8(a,b) (a),(b),-1,-1
2488 
2489 /**
2490  * Register (RSL) bgx#_cmr#_rx_weight
2491  *
2492  * BGX CMR Receive-Weight Register
2493  */
2494 union bdk_bgxx_cmrx_rx_weight
2495 {
2496     uint64_t u;
2497     struct bdk_bgxx_cmrx_rx_weight_s
2498     {
2499 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2500         uint64_t reserved_4_63         : 60;
2501         uint64_t weight                : 4;  /**< [  3:  0](R/W) For the weighted round robin algorithm in CMR RXB, weight to assign for this LMAC relative
2502                                                                  to other LMAC weights. Defaults to round-robin (non-weighted minimum setting of 0x1). A
2503                                                                  setting of 0x0 effectively takes the LMAC out of eligibility. */
2504 #else /* Word 0 - Little Endian */
2505         uint64_t weight                : 4;  /**< [  3:  0](R/W) For the weighted round robin algorithm in CMR RXB, weight to assign for this LMAC relative
2506                                                                  to other LMAC weights. Defaults to round-robin (non-weighted minimum setting of 0x1). A
2507                                                                  setting of 0x0 effectively takes the LMAC out of eligibility. */
2508         uint64_t reserved_4_63         : 60;
2509 #endif /* Word 0 - End */
2510     } s;
2511     /* struct bdk_bgxx_cmrx_rx_weight_s cn; */
2512 };
2513 typedef union bdk_bgxx_cmrx_rx_weight bdk_bgxx_cmrx_rx_weight_t;
2514 
2515 static inline uint64_t BDK_BGXX_CMRX_RX_WEIGHT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_RX_WEIGHT(unsigned long a,unsigned long b)2516 static inline uint64_t BDK_BGXX_CMRX_RX_WEIGHT(unsigned long a, unsigned long b)
2517 {
2518     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2519         return 0x87e0e00000e0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2520     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2521         return 0x87e0e00000e0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2522     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2523         return 0x87e0e00000e0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2524     __bdk_csr_fatal("BGXX_CMRX_RX_WEIGHT", 2, a, b, 0, 0);
2525 }
2526 
2527 #define typedef_BDK_BGXX_CMRX_RX_WEIGHT(a,b) bdk_bgxx_cmrx_rx_weight_t
2528 #define bustype_BDK_BGXX_CMRX_RX_WEIGHT(a,b) BDK_CSR_TYPE_RSL
2529 #define basename_BDK_BGXX_CMRX_RX_WEIGHT(a,b) "BGXX_CMRX_RX_WEIGHT"
2530 #define device_bar_BDK_BGXX_CMRX_RX_WEIGHT(a,b) 0x0 /* PF_BAR0 */
2531 #define busnum_BDK_BGXX_CMRX_RX_WEIGHT(a,b) (a)
2532 #define arguments_BDK_BGXX_CMRX_RX_WEIGHT(a,b) (a),(b),-1,-1
2533 
2534 /**
2535  * Register (RSL) bgx#_cmr#_tx_channel
2536  *
2537  * BGX CMR Transmit-Channels Registers
2538  */
2539 union bdk_bgxx_cmrx_tx_channel
2540 {
2541     uint64_t u;
2542     struct bdk_bgxx_cmrx_tx_channel_s
2543     {
2544 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2545         uint64_t reserved_32_63        : 32;
2546         uint64_t msk                   : 16; /**< [ 31: 16](R/W) Backpressure channel mask. BGX can completely ignore the channel backpressure for channel
2547                                                                  specified by this field. Any channel in which MSK\<n\> is set never sends backpressure
2548                                                                  information to NIC. */
2549         uint64_t dis                   : 16; /**< [ 15:  0](R/W) Credit return backpressure disable. BGX stops returning channel credits for any
2550                                                                  channel that is backpressured. These bits can be used to override that. If
2551                                                                  [DIS]\<n\> is set, channel credits may flow back regardless of the backpressure
2552                                                                  for that channel. */
2553 #else /* Word 0 - Little Endian */
2554         uint64_t dis                   : 16; /**< [ 15:  0](R/W) Credit return backpressure disable. BGX stops returning channel credits for any
2555                                                                  channel that is backpressured. These bits can be used to override that. If
2556                                                                  [DIS]\<n\> is set, channel credits may flow back regardless of the backpressure
2557                                                                  for that channel. */
2558         uint64_t msk                   : 16; /**< [ 31: 16](R/W) Backpressure channel mask. BGX can completely ignore the channel backpressure for channel
2559                                                                  specified by this field. Any channel in which MSK\<n\> is set never sends backpressure
2560                                                                  information to NIC. */
2561         uint64_t reserved_32_63        : 32;
2562 #endif /* Word 0 - End */
2563     } s;
2564     /* struct bdk_bgxx_cmrx_tx_channel_s cn81xx; */
2565     struct bdk_bgxx_cmrx_tx_channel_cn88xx
2566     {
2567 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2568         uint64_t reserved_32_63        : 32;
2569         uint64_t msk                   : 16; /**< [ 31: 16](R/W) Backpressure channel mask. BGX can completely ignore the channel backpressure for channel
2570                                                                  specified by this field. Any channel in which MSK\<n\> is set never sends backpressure
2571                                                                  information to TNS/NIC. */
2572         uint64_t dis                   : 16; /**< [ 15:  0](R/W) Credit return backpressure disable. BGX stops returning channel credits for any
2573                                                                  channel that is backpressured. These bits can be used to override that. If
2574                                                                  [DIS]\<n\> is set, channel credits may flow back regardless of the backpressure
2575                                                                  for that channel. */
2576 #else /* Word 0 - Little Endian */
2577         uint64_t dis                   : 16; /**< [ 15:  0](R/W) Credit return backpressure disable. BGX stops returning channel credits for any
2578                                                                  channel that is backpressured. These bits can be used to override that. If
2579                                                                  [DIS]\<n\> is set, channel credits may flow back regardless of the backpressure
2580                                                                  for that channel. */
2581         uint64_t msk                   : 16; /**< [ 31: 16](R/W) Backpressure channel mask. BGX can completely ignore the channel backpressure for channel
2582                                                                  specified by this field. Any channel in which MSK\<n\> is set never sends backpressure
2583                                                                  information to TNS/NIC. */
2584         uint64_t reserved_32_63        : 32;
2585 #endif /* Word 0 - End */
2586     } cn88xx;
2587     struct bdk_bgxx_cmrx_tx_channel_cn83xx
2588     {
2589 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2590         uint64_t reserved_32_63        : 32;
2591         uint64_t msk                   : 16; /**< [ 31: 16](R/W) Backpressure channel mask. BGX can completely ignore the channel backpressure for channel
2592                                                                  specified by this field. Any channel in which MSK\<n\> is set never sends backpressure
2593                                                                  information to PKO. */
2594         uint64_t dis                   : 16; /**< [ 15:  0](R/W) Credit return backpressure disable. BGX stops returning channel credits for any
2595                                                                  channel that is backpressured. These bits can be used to override that. If
2596                                                                  [DIS]\<n\> is set, channel credits may flow back regardless of the backpressure
2597                                                                  for that channel. */
2598 #else /* Word 0 - Little Endian */
2599         uint64_t dis                   : 16; /**< [ 15:  0](R/W) Credit return backpressure disable. BGX stops returning channel credits for any
2600                                                                  channel that is backpressured. These bits can be used to override that. If
2601                                                                  [DIS]\<n\> is set, channel credits may flow back regardless of the backpressure
2602                                                                  for that channel. */
2603         uint64_t msk                   : 16; /**< [ 31: 16](R/W) Backpressure channel mask. BGX can completely ignore the channel backpressure for channel
2604                                                                  specified by this field. Any channel in which MSK\<n\> is set never sends backpressure
2605                                                                  information to PKO. */
2606         uint64_t reserved_32_63        : 32;
2607 #endif /* Word 0 - End */
2608     } cn83xx;
2609 };
2610 typedef union bdk_bgxx_cmrx_tx_channel bdk_bgxx_cmrx_tx_channel_t;
2611 
2612 static inline uint64_t BDK_BGXX_CMRX_TX_CHANNEL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_CHANNEL(unsigned long a,unsigned long b)2613 static inline uint64_t BDK_BGXX_CMRX_TX_CHANNEL(unsigned long a, unsigned long b)
2614 {
2615     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2616         return 0x87e0e0000500ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2617     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2618         return 0x87e0e0000500ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2619     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2620         return 0x87e0e0000500ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2621     __bdk_csr_fatal("BGXX_CMRX_TX_CHANNEL", 2, a, b, 0, 0);
2622 }
2623 
2624 #define typedef_BDK_BGXX_CMRX_TX_CHANNEL(a,b) bdk_bgxx_cmrx_tx_channel_t
2625 #define bustype_BDK_BGXX_CMRX_TX_CHANNEL(a,b) BDK_CSR_TYPE_RSL
2626 #define basename_BDK_BGXX_CMRX_TX_CHANNEL(a,b) "BGXX_CMRX_TX_CHANNEL"
2627 #define device_bar_BDK_BGXX_CMRX_TX_CHANNEL(a,b) 0x0 /* PF_BAR0 */
2628 #define busnum_BDK_BGXX_CMRX_TX_CHANNEL(a,b) (a)
2629 #define arguments_BDK_BGXX_CMRX_TX_CHANNEL(a,b) (a),(b),-1,-1
2630 
2631 /**
2632  * Register (RSL) bgx#_cmr#_tx_fifo_len
2633  *
2634  * BGX CMR Transmit FIFO Length Registers
2635  */
2636 union bdk_bgxx_cmrx_tx_fifo_len
2637 {
2638     uint64_t u;
2639     struct bdk_bgxx_cmrx_tx_fifo_len_s
2640     {
2641 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2642         uint64_t reserved_15_63        : 49;
2643         uint64_t lmac_idle             : 1;  /**< [ 14: 14](RO/H) Idle signal to identify when all credits and other pipeline buffers are also cleared out
2644                                                                  and LMAC can be considered IDLE in the BGX CMR TX. */
2645         uint64_t fifo_len              : 14; /**< [ 13:  0](RO/H) Per-LMAC TXB main FIFO length. Useful for determining if main FIFO is empty when bringing
2646                                                                  an LMAC down. */
2647 #else /* Word 0 - Little Endian */
2648         uint64_t fifo_len              : 14; /**< [ 13:  0](RO/H) Per-LMAC TXB main FIFO length. Useful for determining if main FIFO is empty when bringing
2649                                                                  an LMAC down. */
2650         uint64_t lmac_idle             : 1;  /**< [ 14: 14](RO/H) Idle signal to identify when all credits and other pipeline buffers are also cleared out
2651                                                                  and LMAC can be considered IDLE in the BGX CMR TX. */
2652         uint64_t reserved_15_63        : 49;
2653 #endif /* Word 0 - End */
2654     } s;
2655     /* struct bdk_bgxx_cmrx_tx_fifo_len_s cn; */
2656 };
2657 typedef union bdk_bgxx_cmrx_tx_fifo_len bdk_bgxx_cmrx_tx_fifo_len_t;
2658 
2659 static inline uint64_t BDK_BGXX_CMRX_TX_FIFO_LEN(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_FIFO_LEN(unsigned long a,unsigned long b)2660 static inline uint64_t BDK_BGXX_CMRX_TX_FIFO_LEN(unsigned long a, unsigned long b)
2661 {
2662     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2663         return 0x87e0e0000518ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2664     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2665         return 0x87e0e0000518ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2666     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2667         return 0x87e0e0000518ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2668     __bdk_csr_fatal("BGXX_CMRX_TX_FIFO_LEN", 2, a, b, 0, 0);
2669 }
2670 
2671 #define typedef_BDK_BGXX_CMRX_TX_FIFO_LEN(a,b) bdk_bgxx_cmrx_tx_fifo_len_t
2672 #define bustype_BDK_BGXX_CMRX_TX_FIFO_LEN(a,b) BDK_CSR_TYPE_RSL
2673 #define basename_BDK_BGXX_CMRX_TX_FIFO_LEN(a,b) "BGXX_CMRX_TX_FIFO_LEN"
2674 #define device_bar_BDK_BGXX_CMRX_TX_FIFO_LEN(a,b) 0x0 /* PF_BAR0 */
2675 #define busnum_BDK_BGXX_CMRX_TX_FIFO_LEN(a,b) (a)
2676 #define arguments_BDK_BGXX_CMRX_TX_FIFO_LEN(a,b) (a),(b),-1,-1
2677 
2678 /**
2679  * Register (RSL) bgx#_cmr#_tx_hg2_status
2680  *
2681  * BGX CMR Transmit HiGig2 Status Registers
2682  */
2683 union bdk_bgxx_cmrx_tx_hg2_status
2684 {
2685     uint64_t u;
2686     struct bdk_bgxx_cmrx_tx_hg2_status_s
2687     {
2688 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2689         uint64_t reserved_32_63        : 32;
2690         uint64_t xof                   : 16; /**< [ 31: 16](RO/H) 16-bit XOF back pressure vector from HiGig2 message packet or from PFC packets. Non-
2691                                                                  zero only when logical back pressure is active. All bits are 0 when [LGTIM2GO] = 0x0. */
2692         uint64_t lgtim2go              : 16; /**< [ 15:  0](RO/H) Logical packet flow back pressure time remaining. Initial value set from XOF time field of
2693                                                                  HiGig2 message packet received or a function of the enabled and current timers for
2694                                                                  PFC packets. Nonzero only when logical back pressure is active. */
2695 #else /* Word 0 - Little Endian */
2696         uint64_t lgtim2go              : 16; /**< [ 15:  0](RO/H) Logical packet flow back pressure time remaining. Initial value set from XOF time field of
2697                                                                  HiGig2 message packet received or a function of the enabled and current timers for
2698                                                                  PFC packets. Nonzero only when logical back pressure is active. */
2699         uint64_t xof                   : 16; /**< [ 31: 16](RO/H) 16-bit XOF back pressure vector from HiGig2 message packet or from PFC packets. Non-
2700                                                                  zero only when logical back pressure is active. All bits are 0 when [LGTIM2GO] = 0x0. */
2701         uint64_t reserved_32_63        : 32;
2702 #endif /* Word 0 - End */
2703     } s;
2704     /* struct bdk_bgxx_cmrx_tx_hg2_status_s cn; */
2705 };
2706 typedef union bdk_bgxx_cmrx_tx_hg2_status bdk_bgxx_cmrx_tx_hg2_status_t;
2707 
2708 static inline uint64_t BDK_BGXX_CMRX_TX_HG2_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_HG2_STATUS(unsigned long a,unsigned long b)2709 static inline uint64_t BDK_BGXX_CMRX_TX_HG2_STATUS(unsigned long a, unsigned long b)
2710 {
2711     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2712         return 0x87e0e0000510ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2713     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2714         return 0x87e0e0000510ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2715     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2716         return 0x87e0e0000510ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2717     __bdk_csr_fatal("BGXX_CMRX_TX_HG2_STATUS", 2, a, b, 0, 0);
2718 }
2719 
2720 #define typedef_BDK_BGXX_CMRX_TX_HG2_STATUS(a,b) bdk_bgxx_cmrx_tx_hg2_status_t
2721 #define bustype_BDK_BGXX_CMRX_TX_HG2_STATUS(a,b) BDK_CSR_TYPE_RSL
2722 #define basename_BDK_BGXX_CMRX_TX_HG2_STATUS(a,b) "BGXX_CMRX_TX_HG2_STATUS"
2723 #define device_bar_BDK_BGXX_CMRX_TX_HG2_STATUS(a,b) 0x0 /* PF_BAR0 */
2724 #define busnum_BDK_BGXX_CMRX_TX_HG2_STATUS(a,b) (a)
2725 #define arguments_BDK_BGXX_CMRX_TX_HG2_STATUS(a,b) (a),(b),-1,-1
2726 
2727 /**
2728  * Register (RSL) bgx#_cmr#_tx_ovr_bp
2729  *
2730  * BGX CMR Transmit-Channels Backpressure Override Registers
2731  */
2732 union bdk_bgxx_cmrx_tx_ovr_bp
2733 {
2734     uint64_t u;
2735     struct bdk_bgxx_cmrx_tx_ovr_bp_s
2736     {
2737 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2738         uint64_t reserved_16_63        : 48;
2739         uint64_t tx_chan_bp            : 16; /**< [ 15:  0](R/W) Per-channel backpressure status sent to NIC.  Also see BGX()_PRT_CBFC_CTL for details on
2740                                                                  impact to physical backpressure.
2741                                                                  0 = Channel is available.
2742                                                                  1 = Channel is backpressured. */
2743 #else /* Word 0 - Little Endian */
2744         uint64_t tx_chan_bp            : 16; /**< [ 15:  0](R/W) Per-channel backpressure status sent to NIC.  Also see BGX()_PRT_CBFC_CTL for details on
2745                                                                  impact to physical backpressure.
2746                                                                  0 = Channel is available.
2747                                                                  1 = Channel is backpressured. */
2748         uint64_t reserved_16_63        : 48;
2749 #endif /* Word 0 - End */
2750     } s;
2751     /* struct bdk_bgxx_cmrx_tx_ovr_bp_s cn81xx; */
2752     struct bdk_bgxx_cmrx_tx_ovr_bp_cn88xx
2753     {
2754 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2755         uint64_t reserved_16_63        : 48;
2756         uint64_t tx_chan_bp            : 16; /**< [ 15:  0](R/W) Per-channel backpressure status sent to TNS/NIC.
2757                                                                  0 = Channel is available.
2758                                                                  1 = Channel is backpressured. */
2759 #else /* Word 0 - Little Endian */
2760         uint64_t tx_chan_bp            : 16; /**< [ 15:  0](R/W) Per-channel backpressure status sent to TNS/NIC.
2761                                                                  0 = Channel is available.
2762                                                                  1 = Channel is backpressured. */
2763         uint64_t reserved_16_63        : 48;
2764 #endif /* Word 0 - End */
2765     } cn88xx;
2766     struct bdk_bgxx_cmrx_tx_ovr_bp_cn83xx
2767     {
2768 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2769         uint64_t reserved_16_63        : 48;
2770         uint64_t tx_chan_bp            : 16; /**< [ 15:  0](R/W) Per-channel backpressure status sent to PKO/NIC. Also see BGX()_PRT_CBFC_CTL for
2771                                                                  details on impact to physical backpressure.
2772                                                                  0 = Channel is available.
2773                                                                  1 = Channel is backpressured. */
2774 #else /* Word 0 - Little Endian */
2775         uint64_t tx_chan_bp            : 16; /**< [ 15:  0](R/W) Per-channel backpressure status sent to PKO/NIC. Also see BGX()_PRT_CBFC_CTL for
2776                                                                  details on impact to physical backpressure.
2777                                                                  0 = Channel is available.
2778                                                                  1 = Channel is backpressured. */
2779         uint64_t reserved_16_63        : 48;
2780 #endif /* Word 0 - End */
2781     } cn83xx;
2782 };
2783 typedef union bdk_bgxx_cmrx_tx_ovr_bp bdk_bgxx_cmrx_tx_ovr_bp_t;
2784 
2785 static inline uint64_t BDK_BGXX_CMRX_TX_OVR_BP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_OVR_BP(unsigned long a,unsigned long b)2786 static inline uint64_t BDK_BGXX_CMRX_TX_OVR_BP(unsigned long a, unsigned long b)
2787 {
2788     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2789         return 0x87e0e0000520ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2790     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2791         return 0x87e0e0000520ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2792     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2793         return 0x87e0e0000520ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2794     __bdk_csr_fatal("BGXX_CMRX_TX_OVR_BP", 2, a, b, 0, 0);
2795 }
2796 
2797 #define typedef_BDK_BGXX_CMRX_TX_OVR_BP(a,b) bdk_bgxx_cmrx_tx_ovr_bp_t
2798 #define bustype_BDK_BGXX_CMRX_TX_OVR_BP(a,b) BDK_CSR_TYPE_RSL
2799 #define basename_BDK_BGXX_CMRX_TX_OVR_BP(a,b) "BGXX_CMRX_TX_OVR_BP"
2800 #define device_bar_BDK_BGXX_CMRX_TX_OVR_BP(a,b) 0x0 /* PF_BAR0 */
2801 #define busnum_BDK_BGXX_CMRX_TX_OVR_BP(a,b) (a)
2802 #define arguments_BDK_BGXX_CMRX_TX_OVR_BP(a,b) (a),(b),-1,-1
2803 
2804 /**
2805  * Register (RSL) bgx#_cmr#_tx_stat0
2806  *
2807  * BGX CMR Transmit Statistics Registers 0
2808  */
2809 union bdk_bgxx_cmrx_tx_stat0
2810 {
2811     uint64_t u;
2812     struct bdk_bgxx_cmrx_tx_stat0_s
2813     {
2814 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2815         uint64_t reserved_48_63        : 16;
2816         uint64_t xscol                 : 48; /**< [ 47:  0](R/W/H) Number of packets dropped (never successfully sent) due to excessive collision. Defined by
2817                                                                  BGX()_GMP_GMI_TX_COL_ATTEMPT[LIMIT]. Half-duplex mode only and does not account for late
2818                                                                  collisions.
2819 
2820                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
2821                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
2822 #else /* Word 0 - Little Endian */
2823         uint64_t xscol                 : 48; /**< [ 47:  0](R/W/H) Number of packets dropped (never successfully sent) due to excessive collision. Defined by
2824                                                                  BGX()_GMP_GMI_TX_COL_ATTEMPT[LIMIT]. Half-duplex mode only and does not account for late
2825                                                                  collisions.
2826 
2827                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
2828                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
2829         uint64_t reserved_48_63        : 16;
2830 #endif /* Word 0 - End */
2831     } s;
2832     /* struct bdk_bgxx_cmrx_tx_stat0_s cn; */
2833 };
2834 typedef union bdk_bgxx_cmrx_tx_stat0 bdk_bgxx_cmrx_tx_stat0_t;
2835 
2836 static inline uint64_t BDK_BGXX_CMRX_TX_STAT0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT0(unsigned long a,unsigned long b)2837 static inline uint64_t BDK_BGXX_CMRX_TX_STAT0(unsigned long a, unsigned long b)
2838 {
2839     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2840         return 0x87e0e0000600ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2841     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2842         return 0x87e0e0000600ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2843     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2844         return 0x87e0e0000600ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2845     __bdk_csr_fatal("BGXX_CMRX_TX_STAT0", 2, a, b, 0, 0);
2846 }
2847 
2848 #define typedef_BDK_BGXX_CMRX_TX_STAT0(a,b) bdk_bgxx_cmrx_tx_stat0_t
2849 #define bustype_BDK_BGXX_CMRX_TX_STAT0(a,b) BDK_CSR_TYPE_RSL
2850 #define basename_BDK_BGXX_CMRX_TX_STAT0(a,b) "BGXX_CMRX_TX_STAT0"
2851 #define device_bar_BDK_BGXX_CMRX_TX_STAT0(a,b) 0x0 /* PF_BAR0 */
2852 #define busnum_BDK_BGXX_CMRX_TX_STAT0(a,b) (a)
2853 #define arguments_BDK_BGXX_CMRX_TX_STAT0(a,b) (a),(b),-1,-1
2854 
2855 /**
2856  * Register (RSL) bgx#_cmr#_tx_stat1
2857  *
2858  * BGX CMR Transmit Statistics Registers 1
2859  */
2860 union bdk_bgxx_cmrx_tx_stat1
2861 {
2862     uint64_t u;
2863     struct bdk_bgxx_cmrx_tx_stat1_s
2864     {
2865 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2866         uint64_t reserved_48_63        : 16;
2867         uint64_t xsdef                 : 48; /**< [ 47:  0](R/W/H) A count of the number of times any frame was deferred for an excessive period of time.
2868                                                                  See maxDeferTime in the IEEE 802.3 specification. Half-duplex mode only and not updated
2869                                                                  for late collisions.
2870 
2871                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
2872                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
2873 #else /* Word 0 - Little Endian */
2874         uint64_t xsdef                 : 48; /**< [ 47:  0](R/W/H) A count of the number of times any frame was deferred for an excessive period of time.
2875                                                                  See maxDeferTime in the IEEE 802.3 specification. Half-duplex mode only and not updated
2876                                                                  for late collisions.
2877 
2878                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
2879                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
2880         uint64_t reserved_48_63        : 16;
2881 #endif /* Word 0 - End */
2882     } s;
2883     /* struct bdk_bgxx_cmrx_tx_stat1_s cn; */
2884 };
2885 typedef union bdk_bgxx_cmrx_tx_stat1 bdk_bgxx_cmrx_tx_stat1_t;
2886 
2887 static inline uint64_t BDK_BGXX_CMRX_TX_STAT1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT1(unsigned long a,unsigned long b)2888 static inline uint64_t BDK_BGXX_CMRX_TX_STAT1(unsigned long a, unsigned long b)
2889 {
2890     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2891         return 0x87e0e0000608ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2892     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2893         return 0x87e0e0000608ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2894     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2895         return 0x87e0e0000608ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2896     __bdk_csr_fatal("BGXX_CMRX_TX_STAT1", 2, a, b, 0, 0);
2897 }
2898 
2899 #define typedef_BDK_BGXX_CMRX_TX_STAT1(a,b) bdk_bgxx_cmrx_tx_stat1_t
2900 #define bustype_BDK_BGXX_CMRX_TX_STAT1(a,b) BDK_CSR_TYPE_RSL
2901 #define basename_BDK_BGXX_CMRX_TX_STAT1(a,b) "BGXX_CMRX_TX_STAT1"
2902 #define device_bar_BDK_BGXX_CMRX_TX_STAT1(a,b) 0x0 /* PF_BAR0 */
2903 #define busnum_BDK_BGXX_CMRX_TX_STAT1(a,b) (a)
2904 #define arguments_BDK_BGXX_CMRX_TX_STAT1(a,b) (a),(b),-1,-1
2905 
2906 /**
2907  * Register (RSL) bgx#_cmr#_tx_stat10
2908  *
2909  * BGX CMR Transmit Statistics Registers 10
2910  */
2911 union bdk_bgxx_cmrx_tx_stat10
2912 {
2913     uint64_t u;
2914     struct bdk_bgxx_cmrx_tx_stat10_s
2915     {
2916 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2917         uint64_t reserved_48_63        : 16;
2918         uint64_t hist4                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 256-511. Packet length is the sum of
2919                                                                  all data transmitted on the wire for the given packet including packet data, pad bytes,
2920                                                                  FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
2921 
2922                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
2923                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
2924 #else /* Word 0 - Little Endian */
2925         uint64_t hist4                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 256-511. Packet length is the sum of
2926                                                                  all data transmitted on the wire for the given packet including packet data, pad bytes,
2927                                                                  FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
2928 
2929                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
2930                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
2931         uint64_t reserved_48_63        : 16;
2932 #endif /* Word 0 - End */
2933     } s;
2934     /* struct bdk_bgxx_cmrx_tx_stat10_s cn; */
2935 };
2936 typedef union bdk_bgxx_cmrx_tx_stat10 bdk_bgxx_cmrx_tx_stat10_t;
2937 
2938 static inline uint64_t BDK_BGXX_CMRX_TX_STAT10(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT10(unsigned long a,unsigned long b)2939 static inline uint64_t BDK_BGXX_CMRX_TX_STAT10(unsigned long a, unsigned long b)
2940 {
2941     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2942         return 0x87e0e0000650ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2943     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2944         return 0x87e0e0000650ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2945     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2946         return 0x87e0e0000650ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2947     __bdk_csr_fatal("BGXX_CMRX_TX_STAT10", 2, a, b, 0, 0);
2948 }
2949 
2950 #define typedef_BDK_BGXX_CMRX_TX_STAT10(a,b) bdk_bgxx_cmrx_tx_stat10_t
2951 #define bustype_BDK_BGXX_CMRX_TX_STAT10(a,b) BDK_CSR_TYPE_RSL
2952 #define basename_BDK_BGXX_CMRX_TX_STAT10(a,b) "BGXX_CMRX_TX_STAT10"
2953 #define device_bar_BDK_BGXX_CMRX_TX_STAT10(a,b) 0x0 /* PF_BAR0 */
2954 #define busnum_BDK_BGXX_CMRX_TX_STAT10(a,b) (a)
2955 #define arguments_BDK_BGXX_CMRX_TX_STAT10(a,b) (a),(b),-1,-1
2956 
2957 /**
2958  * Register (RSL) bgx#_cmr#_tx_stat11
2959  *
2960  * BGX CMR Transmit Statistics Registers 11
2961  */
2962 union bdk_bgxx_cmrx_tx_stat11
2963 {
2964     uint64_t u;
2965     struct bdk_bgxx_cmrx_tx_stat11_s
2966     {
2967 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2968         uint64_t reserved_48_63        : 16;
2969         uint64_t hist5                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 512-1023. Packet length is the sum of
2970                                                                  all data transmitted on the wire for the given packet including packet data, pad bytes,
2971                                                                  FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
2972 
2973                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
2974                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
2975 #else /* Word 0 - Little Endian */
2976         uint64_t hist5                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 512-1023. Packet length is the sum of
2977                                                                  all data transmitted on the wire for the given packet including packet data, pad bytes,
2978                                                                  FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
2979 
2980                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
2981                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
2982         uint64_t reserved_48_63        : 16;
2983 #endif /* Word 0 - End */
2984     } s;
2985     /* struct bdk_bgxx_cmrx_tx_stat11_s cn; */
2986 };
2987 typedef union bdk_bgxx_cmrx_tx_stat11 bdk_bgxx_cmrx_tx_stat11_t;
2988 
2989 static inline uint64_t BDK_BGXX_CMRX_TX_STAT11(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT11(unsigned long a,unsigned long b)2990 static inline uint64_t BDK_BGXX_CMRX_TX_STAT11(unsigned long a, unsigned long b)
2991 {
2992     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
2993         return 0x87e0e0000658ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2994     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
2995         return 0x87e0e0000658ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
2996     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
2997         return 0x87e0e0000658ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
2998     __bdk_csr_fatal("BGXX_CMRX_TX_STAT11", 2, a, b, 0, 0);
2999 }
3000 
3001 #define typedef_BDK_BGXX_CMRX_TX_STAT11(a,b) bdk_bgxx_cmrx_tx_stat11_t
3002 #define bustype_BDK_BGXX_CMRX_TX_STAT11(a,b) BDK_CSR_TYPE_RSL
3003 #define basename_BDK_BGXX_CMRX_TX_STAT11(a,b) "BGXX_CMRX_TX_STAT11"
3004 #define device_bar_BDK_BGXX_CMRX_TX_STAT11(a,b) 0x0 /* PF_BAR0 */
3005 #define busnum_BDK_BGXX_CMRX_TX_STAT11(a,b) (a)
3006 #define arguments_BDK_BGXX_CMRX_TX_STAT11(a,b) (a),(b),-1,-1
3007 
3008 /**
3009  * Register (RSL) bgx#_cmr#_tx_stat12
3010  *
3011  * BGX CMR Transmit Statistics Registers 12
3012  */
3013 union bdk_bgxx_cmrx_tx_stat12
3014 {
3015     uint64_t u;
3016     struct bdk_bgxx_cmrx_tx_stat12_s
3017     {
3018 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3019         uint64_t reserved_48_63        : 16;
3020         uint64_t hist6                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 1024-1518. Packet length is the sum of
3021                                                                  all data transmitted on the wire for the given packet including packet data, pad bytes,
3022                                                                  FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
3023 
3024                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3025                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3026 #else /* Word 0 - Little Endian */
3027         uint64_t hist6                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 1024-1518. Packet length is the sum of
3028                                                                  all data transmitted on the wire for the given packet including packet data, pad bytes,
3029                                                                  FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
3030 
3031                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3032                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3033         uint64_t reserved_48_63        : 16;
3034 #endif /* Word 0 - End */
3035     } s;
3036     /* struct bdk_bgxx_cmrx_tx_stat12_s cn; */
3037 };
3038 typedef union bdk_bgxx_cmrx_tx_stat12 bdk_bgxx_cmrx_tx_stat12_t;
3039 
3040 static inline uint64_t BDK_BGXX_CMRX_TX_STAT12(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT12(unsigned long a,unsigned long b)3041 static inline uint64_t BDK_BGXX_CMRX_TX_STAT12(unsigned long a, unsigned long b)
3042 {
3043     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3044         return 0x87e0e0000660ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3045     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3046         return 0x87e0e0000660ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3047     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3048         return 0x87e0e0000660ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3049     __bdk_csr_fatal("BGXX_CMRX_TX_STAT12", 2, a, b, 0, 0);
3050 }
3051 
3052 #define typedef_BDK_BGXX_CMRX_TX_STAT12(a,b) bdk_bgxx_cmrx_tx_stat12_t
3053 #define bustype_BDK_BGXX_CMRX_TX_STAT12(a,b) BDK_CSR_TYPE_RSL
3054 #define basename_BDK_BGXX_CMRX_TX_STAT12(a,b) "BGXX_CMRX_TX_STAT12"
3055 #define device_bar_BDK_BGXX_CMRX_TX_STAT12(a,b) 0x0 /* PF_BAR0 */
3056 #define busnum_BDK_BGXX_CMRX_TX_STAT12(a,b) (a)
3057 #define arguments_BDK_BGXX_CMRX_TX_STAT12(a,b) (a),(b),-1,-1
3058 
3059 /**
3060  * Register (RSL) bgx#_cmr#_tx_stat13
3061  *
3062  * BGX CMR Transmit Statistics Registers 13
3063  */
3064 union bdk_bgxx_cmrx_tx_stat13
3065 {
3066     uint64_t u;
3067     struct bdk_bgxx_cmrx_tx_stat13_s
3068     {
3069 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3070         uint64_t reserved_48_63        : 16;
3071         uint64_t hist7                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count \> 1518. Packet length is the sum of all data
3072                                                                  transmitted on the wire for the given packet including packet data, pad bytes, FCS bytes,
3073                                                                  and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
3074 
3075                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3076                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3077 #else /* Word 0 - Little Endian */
3078         uint64_t hist7                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count \> 1518. Packet length is the sum of all data
3079                                                                  transmitted on the wire for the given packet including packet data, pad bytes, FCS bytes,
3080                                                                  and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
3081 
3082                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3083                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3084         uint64_t reserved_48_63        : 16;
3085 #endif /* Word 0 - End */
3086     } s;
3087     /* struct bdk_bgxx_cmrx_tx_stat13_s cn; */
3088 };
3089 typedef union bdk_bgxx_cmrx_tx_stat13 bdk_bgxx_cmrx_tx_stat13_t;
3090 
3091 static inline uint64_t BDK_BGXX_CMRX_TX_STAT13(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT13(unsigned long a,unsigned long b)3092 static inline uint64_t BDK_BGXX_CMRX_TX_STAT13(unsigned long a, unsigned long b)
3093 {
3094     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3095         return 0x87e0e0000668ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3096     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3097         return 0x87e0e0000668ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3098     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3099         return 0x87e0e0000668ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3100     __bdk_csr_fatal("BGXX_CMRX_TX_STAT13", 2, a, b, 0, 0);
3101 }
3102 
3103 #define typedef_BDK_BGXX_CMRX_TX_STAT13(a,b) bdk_bgxx_cmrx_tx_stat13_t
3104 #define bustype_BDK_BGXX_CMRX_TX_STAT13(a,b) BDK_CSR_TYPE_RSL
3105 #define basename_BDK_BGXX_CMRX_TX_STAT13(a,b) "BGXX_CMRX_TX_STAT13"
3106 #define device_bar_BDK_BGXX_CMRX_TX_STAT13(a,b) 0x0 /* PF_BAR0 */
3107 #define busnum_BDK_BGXX_CMRX_TX_STAT13(a,b) (a)
3108 #define arguments_BDK_BGXX_CMRX_TX_STAT13(a,b) (a),(b),-1,-1
3109 
3110 /**
3111  * Register (RSL) bgx#_cmr#_tx_stat14
3112  *
3113  * BGX CMR Transmit Statistics Registers 14
3114  */
3115 union bdk_bgxx_cmrx_tx_stat14
3116 {
3117     uint64_t u;
3118     struct bdk_bgxx_cmrx_tx_stat14_s
3119     {
3120 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3121         uint64_t reserved_48_63        : 16;
3122         uint64_t bcst                  : 48; /**< [ 47:  0](R/W/H) Number of packets sent to broadcast DMAC, excluding PAUSE or PFC control packets generated
3123                                                                  by BGX. Does not include MCST packets.
3124 
3125                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap.
3126 
3127                                                                  Note that BGX determines if the packet is MCST or BCST from the DMAC of the packet. BGX
3128                                                                  assumes that the DMAC lies in the first six bytes of the packet as per the 802.3 frame
3129                                                                  definition. If the system requires additional data before the L2 header, the MCST and BCST
3130                                                                  counters may not reflect reality and should be ignored by software. Cleared if LMAC is
3131                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3132 #else /* Word 0 - Little Endian */
3133         uint64_t bcst                  : 48; /**< [ 47:  0](R/W/H) Number of packets sent to broadcast DMAC, excluding PAUSE or PFC control packets generated
3134                                                                  by BGX. Does not include MCST packets.
3135 
3136                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap.
3137 
3138                                                                  Note that BGX determines if the packet is MCST or BCST from the DMAC of the packet. BGX
3139                                                                  assumes that the DMAC lies in the first six bytes of the packet as per the 802.3 frame
3140                                                                  definition. If the system requires additional data before the L2 header, the MCST and BCST
3141                                                                  counters may not reflect reality and should be ignored by software. Cleared if LMAC is
3142                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3143         uint64_t reserved_48_63        : 16;
3144 #endif /* Word 0 - End */
3145     } s;
3146     /* struct bdk_bgxx_cmrx_tx_stat14_s cn; */
3147 };
3148 typedef union bdk_bgxx_cmrx_tx_stat14 bdk_bgxx_cmrx_tx_stat14_t;
3149 
3150 static inline uint64_t BDK_BGXX_CMRX_TX_STAT14(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT14(unsigned long a,unsigned long b)3151 static inline uint64_t BDK_BGXX_CMRX_TX_STAT14(unsigned long a, unsigned long b)
3152 {
3153     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3154         return 0x87e0e0000670ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3155     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3156         return 0x87e0e0000670ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3157     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3158         return 0x87e0e0000670ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3159     __bdk_csr_fatal("BGXX_CMRX_TX_STAT14", 2, a, b, 0, 0);
3160 }
3161 
3162 #define typedef_BDK_BGXX_CMRX_TX_STAT14(a,b) bdk_bgxx_cmrx_tx_stat14_t
3163 #define bustype_BDK_BGXX_CMRX_TX_STAT14(a,b) BDK_CSR_TYPE_RSL
3164 #define basename_BDK_BGXX_CMRX_TX_STAT14(a,b) "BGXX_CMRX_TX_STAT14"
3165 #define device_bar_BDK_BGXX_CMRX_TX_STAT14(a,b) 0x0 /* PF_BAR0 */
3166 #define busnum_BDK_BGXX_CMRX_TX_STAT14(a,b) (a)
3167 #define arguments_BDK_BGXX_CMRX_TX_STAT14(a,b) (a),(b),-1,-1
3168 
3169 /**
3170  * Register (RSL) bgx#_cmr#_tx_stat15
3171  *
3172  * BGX CMR Transmit Statistics Registers 15
3173  */
3174 union bdk_bgxx_cmrx_tx_stat15
3175 {
3176     uint64_t u;
3177     struct bdk_bgxx_cmrx_tx_stat15_s
3178     {
3179 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3180         uint64_t reserved_48_63        : 16;
3181         uint64_t mcst                  : 48; /**< [ 47:  0](R/W/H) Number of packets sent to multicast DMAC, excluding PAUSE or PFC control packets generated
3182                                                                  by BGX. Does not include BCST packets.
3183 
3184                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap.
3185 
3186                                                                  Note that BGX determines if the packet is MCST or BCST from the DMAC of the packet. BGX
3187                                                                  assumes that the DMAC lies in the first six bytes of the packet as per the 802.3 frame
3188                                                                  definition. If the system requires additional data before the L2 header, then the MCST and
3189                                                                  BCST counters may not reflect reality and should be ignored by software. Cleared if LMAC
3190                                                                  is disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3191 #else /* Word 0 - Little Endian */
3192         uint64_t mcst                  : 48; /**< [ 47:  0](R/W/H) Number of packets sent to multicast DMAC, excluding PAUSE or PFC control packets generated
3193                                                                  by BGX. Does not include BCST packets.
3194 
3195                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap.
3196 
3197                                                                  Note that BGX determines if the packet is MCST or BCST from the DMAC of the packet. BGX
3198                                                                  assumes that the DMAC lies in the first six bytes of the packet as per the 802.3 frame
3199                                                                  definition. If the system requires additional data before the L2 header, then the MCST and
3200                                                                  BCST counters may not reflect reality and should be ignored by software. Cleared if LMAC
3201                                                                  is disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3202         uint64_t reserved_48_63        : 16;
3203 #endif /* Word 0 - End */
3204     } s;
3205     /* struct bdk_bgxx_cmrx_tx_stat15_s cn; */
3206 };
3207 typedef union bdk_bgxx_cmrx_tx_stat15 bdk_bgxx_cmrx_tx_stat15_t;
3208 
3209 static inline uint64_t BDK_BGXX_CMRX_TX_STAT15(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT15(unsigned long a,unsigned long b)3210 static inline uint64_t BDK_BGXX_CMRX_TX_STAT15(unsigned long a, unsigned long b)
3211 {
3212     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3213         return 0x87e0e0000678ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3214     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3215         return 0x87e0e0000678ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3216     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3217         return 0x87e0e0000678ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3218     __bdk_csr_fatal("BGXX_CMRX_TX_STAT15", 2, a, b, 0, 0);
3219 }
3220 
3221 #define typedef_BDK_BGXX_CMRX_TX_STAT15(a,b) bdk_bgxx_cmrx_tx_stat15_t
3222 #define bustype_BDK_BGXX_CMRX_TX_STAT15(a,b) BDK_CSR_TYPE_RSL
3223 #define basename_BDK_BGXX_CMRX_TX_STAT15(a,b) "BGXX_CMRX_TX_STAT15"
3224 #define device_bar_BDK_BGXX_CMRX_TX_STAT15(a,b) 0x0 /* PF_BAR0 */
3225 #define busnum_BDK_BGXX_CMRX_TX_STAT15(a,b) (a)
3226 #define arguments_BDK_BGXX_CMRX_TX_STAT15(a,b) (a),(b),-1,-1
3227 
3228 /**
3229  * Register (RSL) bgx#_cmr#_tx_stat16
3230  *
3231  * BGX CMR Transmit Statistics Registers 16
3232  */
3233 union bdk_bgxx_cmrx_tx_stat16
3234 {
3235     uint64_t u;
3236     struct bdk_bgxx_cmrx_tx_stat16_s
3237     {
3238 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3239         uint64_t reserved_48_63        : 16;
3240         uint64_t undflw                : 48; /**< [ 47:  0](R/W/H) Number of underflow packets.
3241 
3242                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3243                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3244 #else /* Word 0 - Little Endian */
3245         uint64_t undflw                : 48; /**< [ 47:  0](R/W/H) Number of underflow packets.
3246 
3247                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3248                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3249         uint64_t reserved_48_63        : 16;
3250 #endif /* Word 0 - End */
3251     } s;
3252     /* struct bdk_bgxx_cmrx_tx_stat16_s cn; */
3253 };
3254 typedef union bdk_bgxx_cmrx_tx_stat16 bdk_bgxx_cmrx_tx_stat16_t;
3255 
3256 static inline uint64_t BDK_BGXX_CMRX_TX_STAT16(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT16(unsigned long a,unsigned long b)3257 static inline uint64_t BDK_BGXX_CMRX_TX_STAT16(unsigned long a, unsigned long b)
3258 {
3259     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3260         return 0x87e0e0000680ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3261     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3262         return 0x87e0e0000680ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3263     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3264         return 0x87e0e0000680ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3265     __bdk_csr_fatal("BGXX_CMRX_TX_STAT16", 2, a, b, 0, 0);
3266 }
3267 
3268 #define typedef_BDK_BGXX_CMRX_TX_STAT16(a,b) bdk_bgxx_cmrx_tx_stat16_t
3269 #define bustype_BDK_BGXX_CMRX_TX_STAT16(a,b) BDK_CSR_TYPE_RSL
3270 #define basename_BDK_BGXX_CMRX_TX_STAT16(a,b) "BGXX_CMRX_TX_STAT16"
3271 #define device_bar_BDK_BGXX_CMRX_TX_STAT16(a,b) 0x0 /* PF_BAR0 */
3272 #define busnum_BDK_BGXX_CMRX_TX_STAT16(a,b) (a)
3273 #define arguments_BDK_BGXX_CMRX_TX_STAT16(a,b) (a),(b),-1,-1
3274 
3275 /**
3276  * Register (RSL) bgx#_cmr#_tx_stat17
3277  *
3278  * BGX CMR Transmit Statistics Registers 17
3279  */
3280 union bdk_bgxx_cmrx_tx_stat17
3281 {
3282     uint64_t u;
3283     struct bdk_bgxx_cmrx_tx_stat17_s
3284     {
3285 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3286         uint64_t reserved_48_63        : 16;
3287         uint64_t ctl                   : 48; /**< [ 47:  0](R/W/H) Number of PAUSE or PFC control packets generated by BGX. It does not include control
3288                                                                  packets forwarded or generated by the cores. Does not track the number of generated HG2
3289                                                                  messages.
3290 
3291                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3292                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3293 #else /* Word 0 - Little Endian */
3294         uint64_t ctl                   : 48; /**< [ 47:  0](R/W/H) Number of PAUSE or PFC control packets generated by BGX. It does not include control
3295                                                                  packets forwarded or generated by the cores. Does not track the number of generated HG2
3296                                                                  messages.
3297 
3298                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3299                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3300         uint64_t reserved_48_63        : 16;
3301 #endif /* Word 0 - End */
3302     } s;
3303     /* struct bdk_bgxx_cmrx_tx_stat17_s cn; */
3304 };
3305 typedef union bdk_bgxx_cmrx_tx_stat17 bdk_bgxx_cmrx_tx_stat17_t;
3306 
3307 static inline uint64_t BDK_BGXX_CMRX_TX_STAT17(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT17(unsigned long a,unsigned long b)3308 static inline uint64_t BDK_BGXX_CMRX_TX_STAT17(unsigned long a, unsigned long b)
3309 {
3310     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3311         return 0x87e0e0000688ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3312     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3313         return 0x87e0e0000688ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3314     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3315         return 0x87e0e0000688ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3316     __bdk_csr_fatal("BGXX_CMRX_TX_STAT17", 2, a, b, 0, 0);
3317 }
3318 
3319 #define typedef_BDK_BGXX_CMRX_TX_STAT17(a,b) bdk_bgxx_cmrx_tx_stat17_t
3320 #define bustype_BDK_BGXX_CMRX_TX_STAT17(a,b) BDK_CSR_TYPE_RSL
3321 #define basename_BDK_BGXX_CMRX_TX_STAT17(a,b) "BGXX_CMRX_TX_STAT17"
3322 #define device_bar_BDK_BGXX_CMRX_TX_STAT17(a,b) 0x0 /* PF_BAR0 */
3323 #define busnum_BDK_BGXX_CMRX_TX_STAT17(a,b) (a)
3324 #define arguments_BDK_BGXX_CMRX_TX_STAT17(a,b) (a),(b),-1,-1
3325 
3326 /**
3327  * Register (RSL) bgx#_cmr#_tx_stat2
3328  *
3329  * BGX CMR Transmit Statistics Registers 2
3330  */
3331 union bdk_bgxx_cmrx_tx_stat2
3332 {
3333     uint64_t u;
3334     struct bdk_bgxx_cmrx_tx_stat2_s
3335     {
3336 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3337         uint64_t reserved_48_63        : 16;
3338         uint64_t mcol                  : 48; /**< [ 47:  0](R/W/H) Number of packets sent with multiple collisions. Must be less than
3339                                                                  BGX()_GMP_GMI_TX_COL_ATTEMPT[LIMIT]. Half-duplex mode only and not updated
3340                                                                  for late collisions.
3341 
3342                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3343                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3344 #else /* Word 0 - Little Endian */
3345         uint64_t mcol                  : 48; /**< [ 47:  0](R/W/H) Number of packets sent with multiple collisions. Must be less than
3346                                                                  BGX()_GMP_GMI_TX_COL_ATTEMPT[LIMIT]. Half-duplex mode only and not updated
3347                                                                  for late collisions.
3348 
3349                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3350                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3351         uint64_t reserved_48_63        : 16;
3352 #endif /* Word 0 - End */
3353     } s;
3354     /* struct bdk_bgxx_cmrx_tx_stat2_s cn; */
3355 };
3356 typedef union bdk_bgxx_cmrx_tx_stat2 bdk_bgxx_cmrx_tx_stat2_t;
3357 
3358 static inline uint64_t BDK_BGXX_CMRX_TX_STAT2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT2(unsigned long a,unsigned long b)3359 static inline uint64_t BDK_BGXX_CMRX_TX_STAT2(unsigned long a, unsigned long b)
3360 {
3361     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3362         return 0x87e0e0000610ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3363     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3364         return 0x87e0e0000610ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3365     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3366         return 0x87e0e0000610ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3367     __bdk_csr_fatal("BGXX_CMRX_TX_STAT2", 2, a, b, 0, 0);
3368 }
3369 
3370 #define typedef_BDK_BGXX_CMRX_TX_STAT2(a,b) bdk_bgxx_cmrx_tx_stat2_t
3371 #define bustype_BDK_BGXX_CMRX_TX_STAT2(a,b) BDK_CSR_TYPE_RSL
3372 #define basename_BDK_BGXX_CMRX_TX_STAT2(a,b) "BGXX_CMRX_TX_STAT2"
3373 #define device_bar_BDK_BGXX_CMRX_TX_STAT2(a,b) 0x0 /* PF_BAR0 */
3374 #define busnum_BDK_BGXX_CMRX_TX_STAT2(a,b) (a)
3375 #define arguments_BDK_BGXX_CMRX_TX_STAT2(a,b) (a),(b),-1,-1
3376 
3377 /**
3378  * Register (RSL) bgx#_cmr#_tx_stat3
3379  *
3380  * BGX CMR Transmit Statistics Registers 3
3381  */
3382 union bdk_bgxx_cmrx_tx_stat3
3383 {
3384     uint64_t u;
3385     struct bdk_bgxx_cmrx_tx_stat3_s
3386     {
3387 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3388         uint64_t reserved_48_63        : 16;
3389         uint64_t scol                  : 48; /**< [ 47:  0](R/W/H) Number of packets sent with a single collision. Half-duplex mode only and not updated
3390                                                                  for late collisions.
3391 
3392                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3393                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3394 #else /* Word 0 - Little Endian */
3395         uint64_t scol                  : 48; /**< [ 47:  0](R/W/H) Number of packets sent with a single collision. Half-duplex mode only and not updated
3396                                                                  for late collisions.
3397 
3398                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3399                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3400         uint64_t reserved_48_63        : 16;
3401 #endif /* Word 0 - End */
3402     } s;
3403     /* struct bdk_bgxx_cmrx_tx_stat3_s cn; */
3404 };
3405 typedef union bdk_bgxx_cmrx_tx_stat3 bdk_bgxx_cmrx_tx_stat3_t;
3406 
3407 static inline uint64_t BDK_BGXX_CMRX_TX_STAT3(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT3(unsigned long a,unsigned long b)3408 static inline uint64_t BDK_BGXX_CMRX_TX_STAT3(unsigned long a, unsigned long b)
3409 {
3410     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3411         return 0x87e0e0000618ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3412     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3413         return 0x87e0e0000618ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3414     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3415         return 0x87e0e0000618ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3416     __bdk_csr_fatal("BGXX_CMRX_TX_STAT3", 2, a, b, 0, 0);
3417 }
3418 
3419 #define typedef_BDK_BGXX_CMRX_TX_STAT3(a,b) bdk_bgxx_cmrx_tx_stat3_t
3420 #define bustype_BDK_BGXX_CMRX_TX_STAT3(a,b) BDK_CSR_TYPE_RSL
3421 #define basename_BDK_BGXX_CMRX_TX_STAT3(a,b) "BGXX_CMRX_TX_STAT3"
3422 #define device_bar_BDK_BGXX_CMRX_TX_STAT3(a,b) 0x0 /* PF_BAR0 */
3423 #define busnum_BDK_BGXX_CMRX_TX_STAT3(a,b) (a)
3424 #define arguments_BDK_BGXX_CMRX_TX_STAT3(a,b) (a),(b),-1,-1
3425 
3426 /**
3427  * Register (RSL) bgx#_cmr#_tx_stat4
3428  *
3429  * BGX CMR Transmit Statistics Registers 4
3430  */
3431 union bdk_bgxx_cmrx_tx_stat4
3432 {
3433     uint64_t u;
3434     struct bdk_bgxx_cmrx_tx_stat4_s
3435     {
3436 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3437         uint64_t reserved_48_63        : 16;
3438         uint64_t octs                  : 48; /**< [ 47:  0](R/W/H) Number of total octets sent on the interface, excluding PAUSE or PFC control packets
3439                                                                  generated by BGX. Does not count octets from frames that were truncated due to collisions
3440                                                                  in half-duplex mode.
3441                                                                  Octet counts are the sum of all data transmitted on the wire including packet data, pad
3442                                                                  bytes, FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND
3443                                                                  cycles.
3444 
3445                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3446                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3447 #else /* Word 0 - Little Endian */
3448         uint64_t octs                  : 48; /**< [ 47:  0](R/W/H) Number of total octets sent on the interface, excluding PAUSE or PFC control packets
3449                                                                  generated by BGX. Does not count octets from frames that were truncated due to collisions
3450                                                                  in half-duplex mode.
3451                                                                  Octet counts are the sum of all data transmitted on the wire including packet data, pad
3452                                                                  bytes, FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND
3453                                                                  cycles.
3454 
3455                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3456                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3457         uint64_t reserved_48_63        : 16;
3458 #endif /* Word 0 - End */
3459     } s;
3460     /* struct bdk_bgxx_cmrx_tx_stat4_s cn; */
3461 };
3462 typedef union bdk_bgxx_cmrx_tx_stat4 bdk_bgxx_cmrx_tx_stat4_t;
3463 
3464 static inline uint64_t BDK_BGXX_CMRX_TX_STAT4(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT4(unsigned long a,unsigned long b)3465 static inline uint64_t BDK_BGXX_CMRX_TX_STAT4(unsigned long a, unsigned long b)
3466 {
3467     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3468         return 0x87e0e0000620ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3469     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3470         return 0x87e0e0000620ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3471     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3472         return 0x87e0e0000620ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3473     __bdk_csr_fatal("BGXX_CMRX_TX_STAT4", 2, a, b, 0, 0);
3474 }
3475 
3476 #define typedef_BDK_BGXX_CMRX_TX_STAT4(a,b) bdk_bgxx_cmrx_tx_stat4_t
3477 #define bustype_BDK_BGXX_CMRX_TX_STAT4(a,b) BDK_CSR_TYPE_RSL
3478 #define basename_BDK_BGXX_CMRX_TX_STAT4(a,b) "BGXX_CMRX_TX_STAT4"
3479 #define device_bar_BDK_BGXX_CMRX_TX_STAT4(a,b) 0x0 /* PF_BAR0 */
3480 #define busnum_BDK_BGXX_CMRX_TX_STAT4(a,b) (a)
3481 #define arguments_BDK_BGXX_CMRX_TX_STAT4(a,b) (a),(b),-1,-1
3482 
3483 /**
3484  * Register (RSL) bgx#_cmr#_tx_stat5
3485  *
3486  * BGX CMR Transmit Statistics Registers 5
3487  */
3488 union bdk_bgxx_cmrx_tx_stat5
3489 {
3490     uint64_t u;
3491     struct bdk_bgxx_cmrx_tx_stat5_s
3492     {
3493 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3494         uint64_t reserved_48_63        : 16;
3495         uint64_t pkts                  : 48; /**< [ 47:  0](R/W/H) Number of total frames sent on the interface, excluding PAUSE or PFC control packets
3496                                                                  generated by BGX. Does not count octets from frames that were truncated due to collisions
3497                                                                  in half-duplex mode.
3498 
3499                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3500                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3501 #else /* Word 0 - Little Endian */
3502         uint64_t pkts                  : 48; /**< [ 47:  0](R/W/H) Number of total frames sent on the interface, excluding PAUSE or PFC control packets
3503                                                                  generated by BGX. Does not count octets from frames that were truncated due to collisions
3504                                                                  in half-duplex mode.
3505 
3506                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3507                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3508         uint64_t reserved_48_63        : 16;
3509 #endif /* Word 0 - End */
3510     } s;
3511     /* struct bdk_bgxx_cmrx_tx_stat5_s cn; */
3512 };
3513 typedef union bdk_bgxx_cmrx_tx_stat5 bdk_bgxx_cmrx_tx_stat5_t;
3514 
3515 static inline uint64_t BDK_BGXX_CMRX_TX_STAT5(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT5(unsigned long a,unsigned long b)3516 static inline uint64_t BDK_BGXX_CMRX_TX_STAT5(unsigned long a, unsigned long b)
3517 {
3518     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3519         return 0x87e0e0000628ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3520     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3521         return 0x87e0e0000628ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3522     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3523         return 0x87e0e0000628ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3524     __bdk_csr_fatal("BGXX_CMRX_TX_STAT5", 2, a, b, 0, 0);
3525 }
3526 
3527 #define typedef_BDK_BGXX_CMRX_TX_STAT5(a,b) bdk_bgxx_cmrx_tx_stat5_t
3528 #define bustype_BDK_BGXX_CMRX_TX_STAT5(a,b) BDK_CSR_TYPE_RSL
3529 #define basename_BDK_BGXX_CMRX_TX_STAT5(a,b) "BGXX_CMRX_TX_STAT5"
3530 #define device_bar_BDK_BGXX_CMRX_TX_STAT5(a,b) 0x0 /* PF_BAR0 */
3531 #define busnum_BDK_BGXX_CMRX_TX_STAT5(a,b) (a)
3532 #define arguments_BDK_BGXX_CMRX_TX_STAT5(a,b) (a),(b),-1,-1
3533 
3534 /**
3535  * Register (RSL) bgx#_cmr#_tx_stat6
3536  *
3537  * BGX CMR Transmit Statistics Registers 6
3538  */
3539 union bdk_bgxx_cmrx_tx_stat6
3540 {
3541     uint64_t u;
3542     struct bdk_bgxx_cmrx_tx_stat6_s
3543     {
3544 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3545         uint64_t reserved_48_63        : 16;
3546         uint64_t hist0                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count \< 64, excluding PAUSE or PFC control packets
3547                                                                  generated by BGX. Packet length is the sum of all data transmitted on the wire for the
3548                                                                  given packet including packet data, pad bytes, FCS bytes, and JAM bytes. The octet counts
3549                                                                  do not include PREAMBLE byte or EXTEND cycles.
3550 
3551                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3552                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3553 #else /* Word 0 - Little Endian */
3554         uint64_t hist0                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count \< 64, excluding PAUSE or PFC control packets
3555                                                                  generated by BGX. Packet length is the sum of all data transmitted on the wire for the
3556                                                                  given packet including packet data, pad bytes, FCS bytes, and JAM bytes. The octet counts
3557                                                                  do not include PREAMBLE byte or EXTEND cycles.
3558 
3559                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3560                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3561         uint64_t reserved_48_63        : 16;
3562 #endif /* Word 0 - End */
3563     } s;
3564     /* struct bdk_bgxx_cmrx_tx_stat6_s cn; */
3565 };
3566 typedef union bdk_bgxx_cmrx_tx_stat6 bdk_bgxx_cmrx_tx_stat6_t;
3567 
3568 static inline uint64_t BDK_BGXX_CMRX_TX_STAT6(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT6(unsigned long a,unsigned long b)3569 static inline uint64_t BDK_BGXX_CMRX_TX_STAT6(unsigned long a, unsigned long b)
3570 {
3571     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3572         return 0x87e0e0000630ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3573     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3574         return 0x87e0e0000630ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3575     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3576         return 0x87e0e0000630ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3577     __bdk_csr_fatal("BGXX_CMRX_TX_STAT6", 2, a, b, 0, 0);
3578 }
3579 
3580 #define typedef_BDK_BGXX_CMRX_TX_STAT6(a,b) bdk_bgxx_cmrx_tx_stat6_t
3581 #define bustype_BDK_BGXX_CMRX_TX_STAT6(a,b) BDK_CSR_TYPE_RSL
3582 #define basename_BDK_BGXX_CMRX_TX_STAT6(a,b) "BGXX_CMRX_TX_STAT6"
3583 #define device_bar_BDK_BGXX_CMRX_TX_STAT6(a,b) 0x0 /* PF_BAR0 */
3584 #define busnum_BDK_BGXX_CMRX_TX_STAT6(a,b) (a)
3585 #define arguments_BDK_BGXX_CMRX_TX_STAT6(a,b) (a),(b),-1,-1
3586 
3587 /**
3588  * Register (RSL) bgx#_cmr#_tx_stat7
3589  *
3590  * BGX CMR Transmit Statistics Registers 7
3591  */
3592 union bdk_bgxx_cmrx_tx_stat7
3593 {
3594     uint64_t u;
3595     struct bdk_bgxx_cmrx_tx_stat7_s
3596     {
3597 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3598         uint64_t reserved_48_63        : 16;
3599         uint64_t hist1                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count of 64, excluding PAUSE or PFC control packets
3600                                                                  generated by BGX. Packet length is the sum of all data transmitted on the wire for the
3601                                                                  given packet including packet data, pad bytes, FCS bytes, and JAM bytes. The octet counts
3602                                                                  do not include PREAMBLE byte or EXTEND cycles.
3603 
3604                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3605                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3606 #else /* Word 0 - Little Endian */
3607         uint64_t hist1                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count of 64, excluding PAUSE or PFC control packets
3608                                                                  generated by BGX. Packet length is the sum of all data transmitted on the wire for the
3609                                                                  given packet including packet data, pad bytes, FCS bytes, and JAM bytes. The octet counts
3610                                                                  do not include PREAMBLE byte or EXTEND cycles.
3611 
3612                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3613                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3614         uint64_t reserved_48_63        : 16;
3615 #endif /* Word 0 - End */
3616     } s;
3617     /* struct bdk_bgxx_cmrx_tx_stat7_s cn; */
3618 };
3619 typedef union bdk_bgxx_cmrx_tx_stat7 bdk_bgxx_cmrx_tx_stat7_t;
3620 
3621 static inline uint64_t BDK_BGXX_CMRX_TX_STAT7(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT7(unsigned long a,unsigned long b)3622 static inline uint64_t BDK_BGXX_CMRX_TX_STAT7(unsigned long a, unsigned long b)
3623 {
3624     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3625         return 0x87e0e0000638ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3626     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3627         return 0x87e0e0000638ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3628     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3629         return 0x87e0e0000638ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3630     __bdk_csr_fatal("BGXX_CMRX_TX_STAT7", 2, a, b, 0, 0);
3631 }
3632 
3633 #define typedef_BDK_BGXX_CMRX_TX_STAT7(a,b) bdk_bgxx_cmrx_tx_stat7_t
3634 #define bustype_BDK_BGXX_CMRX_TX_STAT7(a,b) BDK_CSR_TYPE_RSL
3635 #define basename_BDK_BGXX_CMRX_TX_STAT7(a,b) "BGXX_CMRX_TX_STAT7"
3636 #define device_bar_BDK_BGXX_CMRX_TX_STAT7(a,b) 0x0 /* PF_BAR0 */
3637 #define busnum_BDK_BGXX_CMRX_TX_STAT7(a,b) (a)
3638 #define arguments_BDK_BGXX_CMRX_TX_STAT7(a,b) (a),(b),-1,-1
3639 
3640 /**
3641  * Register (RSL) bgx#_cmr#_tx_stat8
3642  *
3643  * BGX CMR Transmit Statistics Registers 8
3644  */
3645 union bdk_bgxx_cmrx_tx_stat8
3646 {
3647     uint64_t u;
3648     struct bdk_bgxx_cmrx_tx_stat8_s
3649     {
3650 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3651         uint64_t reserved_48_63        : 16;
3652         uint64_t hist2                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 65-127. Packet length is the sum of all
3653                                                                  data transmitted on the wire for the given packet including packet data, pad bytes, FCS
3654                                                                  bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
3655 
3656                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3657                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3658 #else /* Word 0 - Little Endian */
3659         uint64_t hist2                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 65-127. Packet length is the sum of all
3660                                                                  data transmitted on the wire for the given packet including packet data, pad bytes, FCS
3661                                                                  bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
3662 
3663                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3664                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3665         uint64_t reserved_48_63        : 16;
3666 #endif /* Word 0 - End */
3667     } s;
3668     /* struct bdk_bgxx_cmrx_tx_stat8_s cn; */
3669 };
3670 typedef union bdk_bgxx_cmrx_tx_stat8 bdk_bgxx_cmrx_tx_stat8_t;
3671 
3672 static inline uint64_t BDK_BGXX_CMRX_TX_STAT8(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT8(unsigned long a,unsigned long b)3673 static inline uint64_t BDK_BGXX_CMRX_TX_STAT8(unsigned long a, unsigned long b)
3674 {
3675     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3676         return 0x87e0e0000640ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3677     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3678         return 0x87e0e0000640ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3679     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3680         return 0x87e0e0000640ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3681     __bdk_csr_fatal("BGXX_CMRX_TX_STAT8", 2, a, b, 0, 0);
3682 }
3683 
3684 #define typedef_BDK_BGXX_CMRX_TX_STAT8(a,b) bdk_bgxx_cmrx_tx_stat8_t
3685 #define bustype_BDK_BGXX_CMRX_TX_STAT8(a,b) BDK_CSR_TYPE_RSL
3686 #define basename_BDK_BGXX_CMRX_TX_STAT8(a,b) "BGXX_CMRX_TX_STAT8"
3687 #define device_bar_BDK_BGXX_CMRX_TX_STAT8(a,b) 0x0 /* PF_BAR0 */
3688 #define busnum_BDK_BGXX_CMRX_TX_STAT8(a,b) (a)
3689 #define arguments_BDK_BGXX_CMRX_TX_STAT8(a,b) (a),(b),-1,-1
3690 
3691 /**
3692  * Register (RSL) bgx#_cmr#_tx_stat9
3693  *
3694  * BGX CMR Transmit Statistics Registers 9
3695  */
3696 union bdk_bgxx_cmrx_tx_stat9
3697 {
3698     uint64_t u;
3699     struct bdk_bgxx_cmrx_tx_stat9_s
3700     {
3701 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3702         uint64_t reserved_48_63        : 16;
3703         uint64_t hist3                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 128-255. Packet length is the sum of
3704                                                                  all data transmitted on the wire for the given packet including packet data, pad bytes,
3705                                                                  FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
3706 
3707                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3708                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3709 #else /* Word 0 - Little Endian */
3710         uint64_t hist3                 : 48; /**< [ 47:  0](R/W/H) Number of packets sent with an octet count between 128-255. Packet length is the sum of
3711                                                                  all data transmitted on the wire for the given packet including packet data, pad bytes,
3712                                                                  FCS bytes, and JAM bytes. The octet counts do not include PREAMBLE byte or EXTEND cycles.
3713 
3714                                                                  Not cleared on read; cleared on a write with 0x0. Counters will wrap. Cleared if LMAC is
3715                                                                  disabled with BGX()_CMR()_CONFIG[ENABLE]=0. */
3716         uint64_t reserved_48_63        : 16;
3717 #endif /* Word 0 - End */
3718     } s;
3719     /* struct bdk_bgxx_cmrx_tx_stat9_s cn; */
3720 };
3721 typedef union bdk_bgxx_cmrx_tx_stat9 bdk_bgxx_cmrx_tx_stat9_t;
3722 
3723 static inline uint64_t BDK_BGXX_CMRX_TX_STAT9(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMRX_TX_STAT9(unsigned long a,unsigned long b)3724 static inline uint64_t BDK_BGXX_CMRX_TX_STAT9(unsigned long a, unsigned long b)
3725 {
3726     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
3727         return 0x87e0e0000648ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3728     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
3729         return 0x87e0e0000648ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
3730     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
3731         return 0x87e0e0000648ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
3732     __bdk_csr_fatal("BGXX_CMRX_TX_STAT9", 2, a, b, 0, 0);
3733 }
3734 
3735 #define typedef_BDK_BGXX_CMRX_TX_STAT9(a,b) bdk_bgxx_cmrx_tx_stat9_t
3736 #define bustype_BDK_BGXX_CMRX_TX_STAT9(a,b) BDK_CSR_TYPE_RSL
3737 #define basename_BDK_BGXX_CMRX_TX_STAT9(a,b) "BGXX_CMRX_TX_STAT9"
3738 #define device_bar_BDK_BGXX_CMRX_TX_STAT9(a,b) 0x0 /* PF_BAR0 */
3739 #define busnum_BDK_BGXX_CMRX_TX_STAT9(a,b) (a)
3740 #define arguments_BDK_BGXX_CMRX_TX_STAT9(a,b) (a),(b),-1,-1
3741 
3742 /**
3743  * Register (RSL) bgx#_cmr_bad
3744  *
3745  * BGX CMR Bad Registers
3746  */
3747 union bdk_bgxx_cmr_bad
3748 {
3749     uint64_t u;
3750     struct bdk_bgxx_cmr_bad_s
3751     {
3752 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3753         uint64_t reserved_1_63         : 63;
3754         uint64_t rxb_nxl               : 1;  /**< [  0:  0](R/W1C/H) Receive side LMAC ID \> BGX()_CMR_RX_LMACS. */
3755 #else /* Word 0 - Little Endian */
3756         uint64_t rxb_nxl               : 1;  /**< [  0:  0](R/W1C/H) Receive side LMAC ID \> BGX()_CMR_RX_LMACS. */
3757         uint64_t reserved_1_63         : 63;
3758 #endif /* Word 0 - End */
3759     } s;
3760     /* struct bdk_bgxx_cmr_bad_s cn; */
3761 };
3762 typedef union bdk_bgxx_cmr_bad bdk_bgxx_cmr_bad_t;
3763 
3764 static inline uint64_t BDK_BGXX_CMR_BAD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_BAD(unsigned long a)3765 static inline uint64_t BDK_BGXX_CMR_BAD(unsigned long a)
3766 {
3767     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
3768         return 0x87e0e0001020ll + 0x1000000ll * ((a) & 0x1);
3769     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
3770         return 0x87e0e0001020ll + 0x1000000ll * ((a) & 0x3);
3771     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
3772         return 0x87e0e0001020ll + 0x1000000ll * ((a) & 0x1);
3773     __bdk_csr_fatal("BGXX_CMR_BAD", 1, a, 0, 0, 0);
3774 }
3775 
3776 #define typedef_BDK_BGXX_CMR_BAD(a) bdk_bgxx_cmr_bad_t
3777 #define bustype_BDK_BGXX_CMR_BAD(a) BDK_CSR_TYPE_RSL
3778 #define basename_BDK_BGXX_CMR_BAD(a) "BGXX_CMR_BAD"
3779 #define device_bar_BDK_BGXX_CMR_BAD(a) 0x0 /* PF_BAR0 */
3780 #define busnum_BDK_BGXX_CMR_BAD(a) (a)
3781 #define arguments_BDK_BGXX_CMR_BAD(a) (a),-1,-1,-1
3782 
3783 /**
3784  * Register (RSL) bgx#_cmr_bist_status
3785  *
3786  * BGX Built-in Self-Test Registers
3787  */
3788 union bdk_bgxx_cmr_bist_status
3789 {
3790     uint64_t u;
3791     struct bdk_bgxx_cmr_bist_status_s
3792     {
3793 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3794         uint64_t reserved_27_63        : 37;
3795         uint64_t status                : 27; /**< [ 26:  0](RO/H) '"BIST results. Hardware sets a bit to 1 for memory that fails; 0 indicates pass or never
3796                                                                  run.'
3797 
3798                                                                  Internal:
3799                                                                  "\<0\> = bgx#.rxb.infif_gmp.
3800                                                                  \<1\> = bgx#.rxb.infif_smu.
3801                                                                  \<2\> = bgx#.rxb.fif_bnk00.
3802                                                                  \<3\> = bgx#.rxb.fif_bnk01.
3803                                                                  \<4\> = bgx#.rxb.fif_bnk10.
3804                                                                  \<5\> = bgx#.rxb.fif_bnk11.
3805                                                                  \<6\> = bgx#.rxb.pki_skd_fif.
3806                                                                  \<7\> = bgx#.rxb.nic_skd_fif.
3807                                                                  \<8\> = bgx#.rxb_mix0_fif.
3808                                                                  \<9\> = bgx#.rxb_mix1_fif.
3809                                                                  \<10\> = 0.
3810                                                                  \<11\> = bgx#.txb_fif_bnk0.
3811                                                                  \<12\> = bgx#.txb_fif_bnk1.
3812                                                                  \<13\> = bgx#.txb_skd_m0_pko_fif.
3813                                                                  \<14\> = bgx#.txb_skd_m1_pko_fif.
3814                                                                  \<15\> = bgx#.txb_skd_m2_pko_fif.
3815                                                                  \<16\> = bgx#.txb_skd_m3_pko_fif.
3816                                                                  \<17\> = bgx#.txb_skd_m0_nic_fif.
3817                                                                  \<18\> = bgx#.txb_skd_m1_nic_fif.
3818                                                                  \<19\> = bgx#.txb_skd_m2_nic_fif.
3819                                                                  \<20\> = bgx#.txb_skd_m3_nic_fif.
3820                                                                  \<21\> = bgx#.txb_mix0_fif.
3821                                                                  \<22\> = bgx#.txb_mix1_fif.
3822                                                                  \<23\> = bgx#.txb_ncsi_fif.
3823                                                                  \<24\> = 0." */
3824 #else /* Word 0 - Little Endian */
3825         uint64_t status                : 27; /**< [ 26:  0](RO/H) '"BIST results. Hardware sets a bit to 1 for memory that fails; 0 indicates pass or never
3826                                                                  run.'
3827 
3828                                                                  Internal:
3829                                                                  "\<0\> = bgx#.rxb.infif_gmp.
3830                                                                  \<1\> = bgx#.rxb.infif_smu.
3831                                                                  \<2\> = bgx#.rxb.fif_bnk00.
3832                                                                  \<3\> = bgx#.rxb.fif_bnk01.
3833                                                                  \<4\> = bgx#.rxb.fif_bnk10.
3834                                                                  \<5\> = bgx#.rxb.fif_bnk11.
3835                                                                  \<6\> = bgx#.rxb.pki_skd_fif.
3836                                                                  \<7\> = bgx#.rxb.nic_skd_fif.
3837                                                                  \<8\> = bgx#.rxb_mix0_fif.
3838                                                                  \<9\> = bgx#.rxb_mix1_fif.
3839                                                                  \<10\> = 0.
3840                                                                  \<11\> = bgx#.txb_fif_bnk0.
3841                                                                  \<12\> = bgx#.txb_fif_bnk1.
3842                                                                  \<13\> = bgx#.txb_skd_m0_pko_fif.
3843                                                                  \<14\> = bgx#.txb_skd_m1_pko_fif.
3844                                                                  \<15\> = bgx#.txb_skd_m2_pko_fif.
3845                                                                  \<16\> = bgx#.txb_skd_m3_pko_fif.
3846                                                                  \<17\> = bgx#.txb_skd_m0_nic_fif.
3847                                                                  \<18\> = bgx#.txb_skd_m1_nic_fif.
3848                                                                  \<19\> = bgx#.txb_skd_m2_nic_fif.
3849                                                                  \<20\> = bgx#.txb_skd_m3_nic_fif.
3850                                                                  \<21\> = bgx#.txb_mix0_fif.
3851                                                                  \<22\> = bgx#.txb_mix1_fif.
3852                                                                  \<23\> = bgx#.txb_ncsi_fif.
3853                                                                  \<24\> = 0." */
3854         uint64_t reserved_27_63        : 37;
3855 #endif /* Word 0 - End */
3856     } s;
3857     struct bdk_bgxx_cmr_bist_status_cn81xx
3858     {
3859 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3860         uint64_t reserved_25_63        : 39;
3861         uint64_t status                : 25; /**< [ 24:  0](RO/H) '"BIST results. Hardware sets a bit to 1 for memory that fails; 0 indicates pass or never
3862                                                                  run.'
3863 
3864                                                                  Internal:
3865                                                                  "\<0\> = bgx#.rxb.infif_gmp.
3866                                                                  \<1\> = bgx#.rxb.infif_smu.
3867                                                                  \<2\> = bgx#.rxb.fif_bnk00.
3868                                                                  \<3\> = bgx#.rxb.fif_bnk01.
3869                                                                  \<4\> = bgx#.rxb.fif_bnk10.
3870                                                                  \<5\> = bgx#.rxb.fif_bnk11.
3871                                                                  \<6\> = bgx#.rxb.pki_skd_fif.
3872                                                                  \<7\> = bgx#.rxb.nic_skd_fif.
3873                                                                  \<8\> = bgx#.rxb_mix0_fif.
3874                                                                  \<9\> = bgx#.rxb_mix1_fif.
3875                                                                  \<10\> = 0.
3876                                                                  \<11\> = bgx#.txb_fif_bnk0.
3877                                                                  \<12\> = bgx#.txb_fif_bnk1.
3878                                                                  \<13\> = bgx#.txb_skd_m0_pko_fif.
3879                                                                  \<14\> = bgx#.txb_skd_m1_pko_fif.
3880                                                                  \<15\> = bgx#.txb_skd_m2_pko_fif.
3881                                                                  \<16\> = bgx#.txb_skd_m3_pko_fif.
3882                                                                  \<17\> = bgx#.txb_skd_m0_nic_fif.
3883                                                                  \<18\> = bgx#.txb_skd_m1_nic_fif.
3884                                                                  \<19\> = bgx#.txb_skd_m2_nic_fif.
3885                                                                  \<20\> = bgx#.txb_skd_m3_nic_fif.
3886                                                                  \<21\> = bgx#.txb_mix0_fif.
3887                                                                  \<22\> = bgx#.txb_mix1_fif.
3888                                                                  \<23\> = bgx#.txb_ncsi_fif.
3889                                                                  \<24\> = 0." */
3890 #else /* Word 0 - Little Endian */
3891         uint64_t status                : 25; /**< [ 24:  0](RO/H) '"BIST results. Hardware sets a bit to 1 for memory that fails; 0 indicates pass or never
3892                                                                  run.'
3893 
3894                                                                  Internal:
3895                                                                  "\<0\> = bgx#.rxb.infif_gmp.
3896                                                                  \<1\> = bgx#.rxb.infif_smu.
3897                                                                  \<2\> = bgx#.rxb.fif_bnk00.
3898                                                                  \<3\> = bgx#.rxb.fif_bnk01.
3899                                                                  \<4\> = bgx#.rxb.fif_bnk10.
3900                                                                  \<5\> = bgx#.rxb.fif_bnk11.
3901                                                                  \<6\> = bgx#.rxb.pki_skd_fif.
3902                                                                  \<7\> = bgx#.rxb.nic_skd_fif.
3903                                                                  \<8\> = bgx#.rxb_mix0_fif.
3904                                                                  \<9\> = bgx#.rxb_mix1_fif.
3905                                                                  \<10\> = 0.
3906                                                                  \<11\> = bgx#.txb_fif_bnk0.
3907                                                                  \<12\> = bgx#.txb_fif_bnk1.
3908                                                                  \<13\> = bgx#.txb_skd_m0_pko_fif.
3909                                                                  \<14\> = bgx#.txb_skd_m1_pko_fif.
3910                                                                  \<15\> = bgx#.txb_skd_m2_pko_fif.
3911                                                                  \<16\> = bgx#.txb_skd_m3_pko_fif.
3912                                                                  \<17\> = bgx#.txb_skd_m0_nic_fif.
3913                                                                  \<18\> = bgx#.txb_skd_m1_nic_fif.
3914                                                                  \<19\> = bgx#.txb_skd_m2_nic_fif.
3915                                                                  \<20\> = bgx#.txb_skd_m3_nic_fif.
3916                                                                  \<21\> = bgx#.txb_mix0_fif.
3917                                                                  \<22\> = bgx#.txb_mix1_fif.
3918                                                                  \<23\> = bgx#.txb_ncsi_fif.
3919                                                                  \<24\> = 0." */
3920         uint64_t reserved_25_63        : 39;
3921 #endif /* Word 0 - End */
3922     } cn81xx;
3923     struct bdk_bgxx_cmr_bist_status_cn88xx
3924     {
3925 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3926         uint64_t reserved_25_63        : 39;
3927         uint64_t status                : 25; /**< [ 24:  0](RO/H) '"BIST results. Hardware sets a bit to 1 for memory that fails; 0 indicates pass or never
3928                                                                  run.'
3929 
3930                                                                  Internal:
3931                                                                  "\<0\> = bgx#.rxb.infif_gmp.
3932                                                                  \<1\> = bgx#.rxb.infif_smu.
3933                                                                  \<2\> = bgx#.rxb.fif_bnk00.
3934                                                                  \<3\> = bgx#.rxb.fif_bnk01.
3935                                                                  \<4\> = bgx#.rxb.fif_bnk10.
3936                                                                  \<5\> = bgx#.rxb.fif_bnk11.
3937                                                                  \<6\> = bgx#.rxb.skd_fif.
3938                                                                  \<7\> = bgx#.rxb_mix0_fif.
3939                                                                  \<8\> = bgx#.rxb_mix1_fif.
3940                                                                  \<9\> = 0.
3941                                                                  \<10\> = bgx#.txb_fif_bnk0.
3942                                                                  \<11\> = bgx#.txb_fif_bnk1.
3943                                                                  \<12\> = bgx#.txb_skd_m0_fif.
3944                                                                  \<13\> = bgx#.txb_skd_m1_fif.
3945                                                                  \<14\> = bgx#.txb_skd_m2_fif.
3946                                                                  \<15\> = bgx#.txb_skd_m3_fif.
3947                                                                  \<16\> = bgx#.txb_mix0_fif.
3948                                                                  \<17\> = bgx#.txb_mix1_fif.
3949                                                                  \<18\> = bgx#.txb_ncsi_fif.
3950                                                                  \<24:19\> = 0x0." */
3951 #else /* Word 0 - Little Endian */
3952         uint64_t status                : 25; /**< [ 24:  0](RO/H) '"BIST results. Hardware sets a bit to 1 for memory that fails; 0 indicates pass or never
3953                                                                  run.'
3954 
3955                                                                  Internal:
3956                                                                  "\<0\> = bgx#.rxb.infif_gmp.
3957                                                                  \<1\> = bgx#.rxb.infif_smu.
3958                                                                  \<2\> = bgx#.rxb.fif_bnk00.
3959                                                                  \<3\> = bgx#.rxb.fif_bnk01.
3960                                                                  \<4\> = bgx#.rxb.fif_bnk10.
3961                                                                  \<5\> = bgx#.rxb.fif_bnk11.
3962                                                                  \<6\> = bgx#.rxb.skd_fif.
3963                                                                  \<7\> = bgx#.rxb_mix0_fif.
3964                                                                  \<8\> = bgx#.rxb_mix1_fif.
3965                                                                  \<9\> = 0.
3966                                                                  \<10\> = bgx#.txb_fif_bnk0.
3967                                                                  \<11\> = bgx#.txb_fif_bnk1.
3968                                                                  \<12\> = bgx#.txb_skd_m0_fif.
3969                                                                  \<13\> = bgx#.txb_skd_m1_fif.
3970                                                                  \<14\> = bgx#.txb_skd_m2_fif.
3971                                                                  \<15\> = bgx#.txb_skd_m3_fif.
3972                                                                  \<16\> = bgx#.txb_mix0_fif.
3973                                                                  \<17\> = bgx#.txb_mix1_fif.
3974                                                                  \<18\> = bgx#.txb_ncsi_fif.
3975                                                                  \<24:19\> = 0x0." */
3976         uint64_t reserved_25_63        : 39;
3977 #endif /* Word 0 - End */
3978     } cn88xx;
3979     struct bdk_bgxx_cmr_bist_status_cn83xx
3980     {
3981 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3982         uint64_t reserved_27_63        : 37;
3983         uint64_t status                : 27; /**< [ 26:  0](RO/H) '"BIST results. Hardware sets a bit to 1 for memory that fails; 0 indicates pass or never
3984                                                                  run.'
3985 
3986                                                                  Internal:
3987                                                                  "\<0\> = bgx#.rxb.infif_gmp.
3988                                                                  \<1\> = bgx#.rxb.infif_smu.
3989                                                                  \<2\> = bgx#.rxb.fif_bnk00.
3990                                                                  \<3\> = bgx#.rxb.fif_bnk01.
3991                                                                  \<4\> = bgx#.rxb.fif_bnk10.
3992                                                                  \<5\> = bgx#.rxb.fif_bnk11.
3993                                                                  \<6\> = bgx#.rxb.pki_skd_fif.
3994                                                                  \<7\> = bgx#.rxb.nic_skd_fif.
3995                                                                  \<8\> = bgx#.rxb_mix0_fif.
3996                                                                  \<9\> = bgx#.rxb_mix1_fif.
3997                                                                  \<10\> = 0.
3998                                                                  \<11\> = bgx#.txb_fif_mem0.
3999                                                                  \<12\> = bgx#.txb_fif_mem1.
4000                                                                  \<13\> = bgx#.txb_fif_mem2.
4001                                                                  \<14\> = bgx#.txb_fif_mem3.
4002                                                                  \<15\> = bgx#.txb_skd_m0_pko_fif.
4003                                                                  \<16\> = bgx#.txb_skd_m1_pko_fif.
4004                                                                  \<17\> = bgx#.txb_skd_m2_pko_fif.
4005                                                                  \<18\> = bgx#.txb_skd_m3_pko_fif.
4006                                                                  \<19\> = bgx#.txb_skd_m0_nic_fif.
4007                                                                  \<20\> = bgx#.txb_skd_m1_nic_fif.
4008                                                                  \<21\> = bgx#.txb_skd_m2_nic_fif.
4009                                                                  \<22\> = bgx#.txb_skd_m3_nic_fif.
4010                                                                  \<23\> = bgx#.txb_mix0_fif.
4011                                                                  \<24\> = bgx#.txb_mix1_fif.
4012                                                                  \<25\> = bgx#.txb_ncsi_fif.
4013                                                                  \<26\> = 0." */
4014 #else /* Word 0 - Little Endian */
4015         uint64_t status                : 27; /**< [ 26:  0](RO/H) '"BIST results. Hardware sets a bit to 1 for memory that fails; 0 indicates pass or never
4016                                                                  run.'
4017 
4018                                                                  Internal:
4019                                                                  "\<0\> = bgx#.rxb.infif_gmp.
4020                                                                  \<1\> = bgx#.rxb.infif_smu.
4021                                                                  \<2\> = bgx#.rxb.fif_bnk00.
4022                                                                  \<3\> = bgx#.rxb.fif_bnk01.
4023                                                                  \<4\> = bgx#.rxb.fif_bnk10.
4024                                                                  \<5\> = bgx#.rxb.fif_bnk11.
4025                                                                  \<6\> = bgx#.rxb.pki_skd_fif.
4026                                                                  \<7\> = bgx#.rxb.nic_skd_fif.
4027                                                                  \<8\> = bgx#.rxb_mix0_fif.
4028                                                                  \<9\> = bgx#.rxb_mix1_fif.
4029                                                                  \<10\> = 0.
4030                                                                  \<11\> = bgx#.txb_fif_mem0.
4031                                                                  \<12\> = bgx#.txb_fif_mem1.
4032                                                                  \<13\> = bgx#.txb_fif_mem2.
4033                                                                  \<14\> = bgx#.txb_fif_mem3.
4034                                                                  \<15\> = bgx#.txb_skd_m0_pko_fif.
4035                                                                  \<16\> = bgx#.txb_skd_m1_pko_fif.
4036                                                                  \<17\> = bgx#.txb_skd_m2_pko_fif.
4037                                                                  \<18\> = bgx#.txb_skd_m3_pko_fif.
4038                                                                  \<19\> = bgx#.txb_skd_m0_nic_fif.
4039                                                                  \<20\> = bgx#.txb_skd_m1_nic_fif.
4040                                                                  \<21\> = bgx#.txb_skd_m2_nic_fif.
4041                                                                  \<22\> = bgx#.txb_skd_m3_nic_fif.
4042                                                                  \<23\> = bgx#.txb_mix0_fif.
4043                                                                  \<24\> = bgx#.txb_mix1_fif.
4044                                                                  \<25\> = bgx#.txb_ncsi_fif.
4045                                                                  \<26\> = 0." */
4046         uint64_t reserved_27_63        : 37;
4047 #endif /* Word 0 - End */
4048     } cn83xx;
4049 };
4050 typedef union bdk_bgxx_cmr_bist_status bdk_bgxx_cmr_bist_status_t;
4051 
4052 static inline uint64_t BDK_BGXX_CMR_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_BIST_STATUS(unsigned long a)4053 static inline uint64_t BDK_BGXX_CMR_BIST_STATUS(unsigned long a)
4054 {
4055     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4056         return 0x87e0e0000460ll + 0x1000000ll * ((a) & 0x1);
4057     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
4058         return 0x87e0e0000460ll + 0x1000000ll * ((a) & 0x3);
4059     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
4060         return 0x87e0e0000460ll + 0x1000000ll * ((a) & 0x1);
4061     __bdk_csr_fatal("BGXX_CMR_BIST_STATUS", 1, a, 0, 0, 0);
4062 }
4063 
4064 #define typedef_BDK_BGXX_CMR_BIST_STATUS(a) bdk_bgxx_cmr_bist_status_t
4065 #define bustype_BDK_BGXX_CMR_BIST_STATUS(a) BDK_CSR_TYPE_RSL
4066 #define basename_BDK_BGXX_CMR_BIST_STATUS(a) "BGXX_CMR_BIST_STATUS"
4067 #define device_bar_BDK_BGXX_CMR_BIST_STATUS(a) 0x0 /* PF_BAR0 */
4068 #define busnum_BDK_BGXX_CMR_BIST_STATUS(a) (a)
4069 #define arguments_BDK_BGXX_CMR_BIST_STATUS(a) (a),-1,-1,-1
4070 
4071 /**
4072  * Register (RSL) bgx#_cmr_chan_msk_and
4073  *
4074  * BGX CMR Backpressure Channel Mask AND Registers
4075  */
4076 union bdk_bgxx_cmr_chan_msk_and
4077 {
4078     uint64_t u;
4079     struct bdk_bgxx_cmr_chan_msk_and_s
4080     {
4081 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4082         uint64_t msk_and               : 64; /**< [ 63:  0](R/W) Assert physical backpressure when the backpressure channel vector combined with [MSK_AND]
4083                                                                  indicates backpressure as follows:
4084                                                                  _ phys_bp_msk_and = [MSK_AND]\<x:y\> != 0 && (chan_vector\<x:y\> & [MSK_AND]\<x:y\>) ==
4085                                                                  [MSK_AND]\<x:y\>
4086                                                                  _ phys_bp = phys_bp_msk_or || phys_bp_msk_and
4087 
4088                                                                  x/y are as follows:
4089                                                                  _ LMAC 0: \<x:y\> = \<15:0\>.
4090                                                                  _ LMAC 1: \<x:y\> = \<31:16\>.
4091                                                                  _ LMAC 2: \<x:y\> = \<47:32\>.
4092                                                                  _ LMAC 3: \<x:y\> = \<63:48\>. */
4093 #else /* Word 0 - Little Endian */
4094         uint64_t msk_and               : 64; /**< [ 63:  0](R/W) Assert physical backpressure when the backpressure channel vector combined with [MSK_AND]
4095                                                                  indicates backpressure as follows:
4096                                                                  _ phys_bp_msk_and = [MSK_AND]\<x:y\> != 0 && (chan_vector\<x:y\> & [MSK_AND]\<x:y\>) ==
4097                                                                  [MSK_AND]\<x:y\>
4098                                                                  _ phys_bp = phys_bp_msk_or || phys_bp_msk_and
4099 
4100                                                                  x/y are as follows:
4101                                                                  _ LMAC 0: \<x:y\> = \<15:0\>.
4102                                                                  _ LMAC 1: \<x:y\> = \<31:16\>.
4103                                                                  _ LMAC 2: \<x:y\> = \<47:32\>.
4104                                                                  _ LMAC 3: \<x:y\> = \<63:48\>. */
4105 #endif /* Word 0 - End */
4106     } s;
4107     /* struct bdk_bgxx_cmr_chan_msk_and_s cn; */
4108 };
4109 typedef union bdk_bgxx_cmr_chan_msk_and bdk_bgxx_cmr_chan_msk_and_t;
4110 
4111 static inline uint64_t BDK_BGXX_CMR_CHAN_MSK_AND(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_CHAN_MSK_AND(unsigned long a)4112 static inline uint64_t BDK_BGXX_CMR_CHAN_MSK_AND(unsigned long a)
4113 {
4114     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4115         return 0x87e0e0000450ll + 0x1000000ll * ((a) & 0x1);
4116     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
4117         return 0x87e0e0000450ll + 0x1000000ll * ((a) & 0x3);
4118     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
4119         return 0x87e0e0000450ll + 0x1000000ll * ((a) & 0x1);
4120     __bdk_csr_fatal("BGXX_CMR_CHAN_MSK_AND", 1, a, 0, 0, 0);
4121 }
4122 
4123 #define typedef_BDK_BGXX_CMR_CHAN_MSK_AND(a) bdk_bgxx_cmr_chan_msk_and_t
4124 #define bustype_BDK_BGXX_CMR_CHAN_MSK_AND(a) BDK_CSR_TYPE_RSL
4125 #define basename_BDK_BGXX_CMR_CHAN_MSK_AND(a) "BGXX_CMR_CHAN_MSK_AND"
4126 #define device_bar_BDK_BGXX_CMR_CHAN_MSK_AND(a) 0x0 /* PF_BAR0 */
4127 #define busnum_BDK_BGXX_CMR_CHAN_MSK_AND(a) (a)
4128 #define arguments_BDK_BGXX_CMR_CHAN_MSK_AND(a) (a),-1,-1,-1
4129 
4130 /**
4131  * Register (RSL) bgx#_cmr_chan_msk_or
4132  *
4133  * BGX Backpressure Channel Mask OR Registers
4134  */
4135 union bdk_bgxx_cmr_chan_msk_or
4136 {
4137     uint64_t u;
4138     struct bdk_bgxx_cmr_chan_msk_or_s
4139     {
4140 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4141         uint64_t msk_or                : 64; /**< [ 63:  0](R/W) Assert physical backpressure when the backpressure channel vector combined with [MSK_OR]
4142                                                                  indicates backpressure as follows:
4143 
4144                                                                  _ phys_bp_msk_or = (chan_vector\<x:y\> & [MSK_OR]\<x:y\>) != 0
4145                                                                  _ phys_bp = phys_bp_msk_or || phys_bp_msk_and
4146 
4147                                                                  x/y are as follows:
4148                                                                  _ LMAC 0: \<x:y\> = \<15:0\>.
4149                                                                  _ LMAC 1: \<x:y\> = \<31:16\>.
4150                                                                  _ LMAC 2: \<x:y\> = \<47:32\>.
4151                                                                  _ LMAC 3: \<x:y\> = \<63:48\>. */
4152 #else /* Word 0 - Little Endian */
4153         uint64_t msk_or                : 64; /**< [ 63:  0](R/W) Assert physical backpressure when the backpressure channel vector combined with [MSK_OR]
4154                                                                  indicates backpressure as follows:
4155 
4156                                                                  _ phys_bp_msk_or = (chan_vector\<x:y\> & [MSK_OR]\<x:y\>) != 0
4157                                                                  _ phys_bp = phys_bp_msk_or || phys_bp_msk_and
4158 
4159                                                                  x/y are as follows:
4160                                                                  _ LMAC 0: \<x:y\> = \<15:0\>.
4161                                                                  _ LMAC 1: \<x:y\> = \<31:16\>.
4162                                                                  _ LMAC 2: \<x:y\> = \<47:32\>.
4163                                                                  _ LMAC 3: \<x:y\> = \<63:48\>. */
4164 #endif /* Word 0 - End */
4165     } s;
4166     /* struct bdk_bgxx_cmr_chan_msk_or_s cn; */
4167 };
4168 typedef union bdk_bgxx_cmr_chan_msk_or bdk_bgxx_cmr_chan_msk_or_t;
4169 
4170 static inline uint64_t BDK_BGXX_CMR_CHAN_MSK_OR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_CHAN_MSK_OR(unsigned long a)4171 static inline uint64_t BDK_BGXX_CMR_CHAN_MSK_OR(unsigned long a)
4172 {
4173     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4174         return 0x87e0e0000458ll + 0x1000000ll * ((a) & 0x1);
4175     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
4176         return 0x87e0e0000458ll + 0x1000000ll * ((a) & 0x3);
4177     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
4178         return 0x87e0e0000458ll + 0x1000000ll * ((a) & 0x1);
4179     __bdk_csr_fatal("BGXX_CMR_CHAN_MSK_OR", 1, a, 0, 0, 0);
4180 }
4181 
4182 #define typedef_BDK_BGXX_CMR_CHAN_MSK_OR(a) bdk_bgxx_cmr_chan_msk_or_t
4183 #define bustype_BDK_BGXX_CMR_CHAN_MSK_OR(a) BDK_CSR_TYPE_RSL
4184 #define basename_BDK_BGXX_CMR_CHAN_MSK_OR(a) "BGXX_CMR_CHAN_MSK_OR"
4185 #define device_bar_BDK_BGXX_CMR_CHAN_MSK_OR(a) 0x0 /* PF_BAR0 */
4186 #define busnum_BDK_BGXX_CMR_CHAN_MSK_OR(a) (a)
4187 #define arguments_BDK_BGXX_CMR_CHAN_MSK_OR(a) (a),-1,-1,-1
4188 
4189 /**
4190  * Register (RSL) bgx#_cmr_eco
4191  *
4192  * INTERNAL: BGX ECO Registers
4193  */
4194 union bdk_bgxx_cmr_eco
4195 {
4196     uint64_t u;
4197     struct bdk_bgxx_cmr_eco_s
4198     {
4199 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4200         uint64_t eco_ro                : 32; /**< [ 63: 32](RO) Internal:
4201                                                                  Reserved for ECO usage. */
4202         uint64_t eco_rw                : 32; /**< [ 31:  0](R/W) Internal:
4203                                                                  Reserved for ECO usage. */
4204 #else /* Word 0 - Little Endian */
4205         uint64_t eco_rw                : 32; /**< [ 31:  0](R/W) Internal:
4206                                                                  Reserved for ECO usage. */
4207         uint64_t eco_ro                : 32; /**< [ 63: 32](RO) Internal:
4208                                                                  Reserved for ECO usage. */
4209 #endif /* Word 0 - End */
4210     } s;
4211     /* struct bdk_bgxx_cmr_eco_s cn; */
4212 };
4213 typedef union bdk_bgxx_cmr_eco bdk_bgxx_cmr_eco_t;
4214 
4215 static inline uint64_t BDK_BGXX_CMR_ECO(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_ECO(unsigned long a)4216 static inline uint64_t BDK_BGXX_CMR_ECO(unsigned long a)
4217 {
4218     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4219         return 0x87e0e0001028ll + 0x1000000ll * ((a) & 0x1);
4220     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
4221         return 0x87e0e0001028ll + 0x1000000ll * ((a) & 0x3);
4222     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && (a<=1))
4223         return 0x87e0e0001028ll + 0x1000000ll * ((a) & 0x1);
4224     __bdk_csr_fatal("BGXX_CMR_ECO", 1, a, 0, 0, 0);
4225 }
4226 
4227 #define typedef_BDK_BGXX_CMR_ECO(a) bdk_bgxx_cmr_eco_t
4228 #define bustype_BDK_BGXX_CMR_ECO(a) BDK_CSR_TYPE_RSL
4229 #define basename_BDK_BGXX_CMR_ECO(a) "BGXX_CMR_ECO"
4230 #define device_bar_BDK_BGXX_CMR_ECO(a) 0x0 /* PF_BAR0 */
4231 #define busnum_BDK_BGXX_CMR_ECO(a) (a)
4232 #define arguments_BDK_BGXX_CMR_ECO(a) (a),-1,-1,-1
4233 
4234 /**
4235  * Register (RSL) bgx#_cmr_global_config
4236  *
4237  * BGX CMR Global Configuration Register
4238  * These registers configure the global CMR, PCS, and MAC.
4239  */
4240 union bdk_bgxx_cmr_global_config
4241 {
4242     uint64_t u;
4243     struct bdk_bgxx_cmr_global_config_s
4244     {
4245 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4246         uint64_t reserved_12_63        : 52;
4247         uint64_t cmr_x2p1_reset        : 1;  /**< [ 11: 11](R/W) If the master block connected to X2P interface 1 is reset, software also needs
4248                                                                  to reset the X2P interface in the BGX by setting this bit. It resets the X2P
4249                                                                  interface state in the BGX (skid FIFO and pending requests to the master block)
4250                                                                  and prevents the RXB FIFOs for all LMACs from pushing data to the
4251                                                                  interface. Because the X2P and NCSI interfaces share the main RXB FIFOs it will
4252                                                                  also impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP]
4253                                                                  bit first before setting this bit.
4254 
4255                                                                  Clearing this does not reset the X2P interface nor NCSI interface.  After the
4256                                                                  master block comes out of reset, software should clear this bit. */
4257         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Interface reset for the CMR NCSI block.
4258                                                                  Upon power up the CMR NCSI is in reset and the companion CNXXXX NCSI block will be
4259                                                                  commanded by the
4260                                                                  external BMC to enable one of the CNXXXX BGX NCSI interfaces for passing network traffic.
4261                                                                  Only one NCSI interface can be enabled in CNXXXX.  The BMC/NCSI will then proceed to
4262                                                                  configure
4263                                                                  the rest of the BGX csr for pass through traffic.
4264 
4265                                                                  When set, will reset the CMR NCSI interface effectively disabling it at a traffic boundary
4266                                                                  should traffic be flowing.  This bit will not reset the main RXB fifos. */
4267         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) NCSI drop.
4268                                                                  1 = Cleanly drop traffic going into the NCSI block of BGX.  Must set asserted
4269                                                                  with with [CMR_X2P_RESET]=1 (in the same write operation) to avoid partial packets
4270                                                                  to the NCSI interface while performing a X2P partner reset.
4271                                                                  0 = Allow traffic to flow through the NCSI block. */
4272         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Logical MAC ID that carries NCSI traffic for both RX and TX side of CMR.  On the RX side
4273                                                                  is
4274                                                                  also the LMAC_ID that is eligible for steering. */
4275         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4276                                                                  bytes, the packet will be removed.
4277                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4278         uint64_t interleave_mode       : 1;  /**< [  5:  5](R/W) A setting of 0 means the BGX will operate in non-interleaved mode where there is 1 packet
4279                                                                  from a given lmac in flight on the X2P interface to TNS/NIC.  A setting of 1 means the BGX
4280                                                                  will operate in interleaved mode where each valid consecutive cycle on the X2P interface
4281                                                                  may contain words from different lmacs.  In other words there will be multiple packets in
4282                                                                  flight from different lmacs at the same time. */
4283         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4284         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4285         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the NIC block is reset, software also needs to reset the X2P interface in the
4286                                                                  BGX by
4287                                                                  setting this bit to 1. It resets the X2P interface state in the BGX (skid FIFO and pending
4288                                                                  requests to NIC) and prevents the RXB FIFOs for all LMACs from pushing data to the
4289                                                                  interface.
4290 
4291                                                                  Setting this bit to 0 does not reset the X2P interface.
4292                                                                  After NIC comes out of reset, software should clear this bit. */
4293         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4294                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4295                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4296                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4297                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4298         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4299 #else /* Word 0 - Little Endian */
4300         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4301         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4302                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4303                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4304                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4305                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4306         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the NIC block is reset, software also needs to reset the X2P interface in the
4307                                                                  BGX by
4308                                                                  setting this bit to 1. It resets the X2P interface state in the BGX (skid FIFO and pending
4309                                                                  requests to NIC) and prevents the RXB FIFOs for all LMACs from pushing data to the
4310                                                                  interface.
4311 
4312                                                                  Setting this bit to 0 does not reset the X2P interface.
4313                                                                  After NIC comes out of reset, software should clear this bit. */
4314         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4315         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4316         uint64_t interleave_mode       : 1;  /**< [  5:  5](R/W) A setting of 0 means the BGX will operate in non-interleaved mode where there is 1 packet
4317                                                                  from a given lmac in flight on the X2P interface to TNS/NIC.  A setting of 1 means the BGX
4318                                                                  will operate in interleaved mode where each valid consecutive cycle on the X2P interface
4319                                                                  may contain words from different lmacs.  In other words there will be multiple packets in
4320                                                                  flight from different lmacs at the same time. */
4321         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4322                                                                  bytes, the packet will be removed.
4323                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4324         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Logical MAC ID that carries NCSI traffic for both RX and TX side of CMR.  On the RX side
4325                                                                  is
4326                                                                  also the LMAC_ID that is eligible for steering. */
4327         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) NCSI drop.
4328                                                                  1 = Cleanly drop traffic going into the NCSI block of BGX.  Must set asserted
4329                                                                  with with [CMR_X2P_RESET]=1 (in the same write operation) to avoid partial packets
4330                                                                  to the NCSI interface while performing a X2P partner reset.
4331                                                                  0 = Allow traffic to flow through the NCSI block. */
4332         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Interface reset for the CMR NCSI block.
4333                                                                  Upon power up the CMR NCSI is in reset and the companion CNXXXX NCSI block will be
4334                                                                  commanded by the
4335                                                                  external BMC to enable one of the CNXXXX BGX NCSI interfaces for passing network traffic.
4336                                                                  Only one NCSI interface can be enabled in CNXXXX.  The BMC/NCSI will then proceed to
4337                                                                  configure
4338                                                                  the rest of the BGX csr for pass through traffic.
4339 
4340                                                                  When set, will reset the CMR NCSI interface effectively disabling it at a traffic boundary
4341                                                                  should traffic be flowing.  This bit will not reset the main RXB fifos. */
4342         uint64_t cmr_x2p1_reset        : 1;  /**< [ 11: 11](R/W) If the master block connected to X2P interface 1 is reset, software also needs
4343                                                                  to reset the X2P interface in the BGX by setting this bit. It resets the X2P
4344                                                                  interface state in the BGX (skid FIFO and pending requests to the master block)
4345                                                                  and prevents the RXB FIFOs for all LMACs from pushing data to the
4346                                                                  interface. Because the X2P and NCSI interfaces share the main RXB FIFOs it will
4347                                                                  also impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP]
4348                                                                  bit first before setting this bit.
4349 
4350                                                                  Clearing this does not reset the X2P interface nor NCSI interface.  After the
4351                                                                  master block comes out of reset, software should clear this bit. */
4352         uint64_t reserved_12_63        : 52;
4353 #endif /* Word 0 - End */
4354     } s;
4355     struct bdk_bgxx_cmr_global_config_cn88xxp1
4356     {
4357 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4358         uint64_t reserved_11_63        : 53;
4359         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Interface reset for the CMR NCSI block.
4360                                                                  Upon power up the CMR NCSI is in reset and the companion CNXXXX NCSI block will be
4361                                                                  commanded by the
4362                                                                  external BMC to enable one of the CNXXXX BGX NCSI interfaces for passing network traffic.
4363                                                                  Only one NCSI interface can be enabled in CNXXXX.  The BMC/NCSI will then proceed to
4364                                                                  configure
4365                                                                  the rest of the BGX csr for pass through traffic.
4366 
4367                                                                  When set, will reset the CMR NCSI interface effectively disabling it at a traffic boundary
4368                                                                  should traffic be flowing.  This bit will not reset the main RXB fifos. */
4369         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) NCSI drop.
4370                                                                  1 = Cleanly drop traffic going into the NCSI block of BGX.  Must set asserted
4371                                                                  with with [CMR_X2P_RESET]=1 (in the same write operation) to avoid partial packets
4372                                                                  to the NCSI interface while performing a X2P partner reset.
4373                                                                  0 = Allow traffic to flow through the NCSI block. */
4374         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Logical MAC ID that carries NCSI traffic for both RX and TX side of CMR.  On the RX side
4375                                                                  is
4376                                                                  also the LMAC_ID that is eligible for steering. */
4377         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4378                                                                  bytes, the packet will be removed.
4379                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4380         uint64_t interleave_mode       : 1;  /**< [  5:  5](R/W) A setting of 0 means the BGX will operate in non-interleaved mode where there is 1 packet
4381                                                                  from a given lmac in flight on the X2P interface to TNS/NIC.  A setting of 1 means the BGX
4382                                                                  will operate in interleaved mode where each valid consecutive cycle on the X2P interface
4383                                                                  may contain words from different lmacs.  In other words there will be multiple packets in
4384                                                                  flight from different lmacs at the same time. */
4385         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4386         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4387         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the NIC or TNS block is reset, software also needs to reset the X2P interface in the
4388                                                                  BGX by
4389                                                                  setting this bit to 1. It resets the X2P interface state in the BGX (skid FIFO and pending
4390                                                                  requests to NIC) and prevents the RXB FIFOs for all LMACs from pushing data to the
4391                                                                  interface. Because the X2P and NCSI interfaces share the main RXB fifos it will also
4392                                                                  impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP] bit first before
4393                                                                  setting this bit.
4394 
4395                                                                  Setting this bit to 0 does not reset the X2P interface nor NCSI interface.
4396                                                                  After NIC/TNS comes out of reset, software should clear this bit. */
4397         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4398                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4399                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4400                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4401                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4402         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4403 #else /* Word 0 - Little Endian */
4404         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4405         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4406                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4407                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4408                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4409                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4410         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the NIC or TNS block is reset, software also needs to reset the X2P interface in the
4411                                                                  BGX by
4412                                                                  setting this bit to 1. It resets the X2P interface state in the BGX (skid FIFO and pending
4413                                                                  requests to NIC) and prevents the RXB FIFOs for all LMACs from pushing data to the
4414                                                                  interface. Because the X2P and NCSI interfaces share the main RXB fifos it will also
4415                                                                  impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP] bit first before
4416                                                                  setting this bit.
4417 
4418                                                                  Setting this bit to 0 does not reset the X2P interface nor NCSI interface.
4419                                                                  After NIC/TNS comes out of reset, software should clear this bit. */
4420         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4421         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4422         uint64_t interleave_mode       : 1;  /**< [  5:  5](R/W) A setting of 0 means the BGX will operate in non-interleaved mode where there is 1 packet
4423                                                                  from a given lmac in flight on the X2P interface to TNS/NIC.  A setting of 1 means the BGX
4424                                                                  will operate in interleaved mode where each valid consecutive cycle on the X2P interface
4425                                                                  may contain words from different lmacs.  In other words there will be multiple packets in
4426                                                                  flight from different lmacs at the same time. */
4427         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4428                                                                  bytes, the packet will be removed.
4429                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4430         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Logical MAC ID that carries NCSI traffic for both RX and TX side of CMR.  On the RX side
4431                                                                  is
4432                                                                  also the LMAC_ID that is eligible for steering. */
4433         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) NCSI drop.
4434                                                                  1 = Cleanly drop traffic going into the NCSI block of BGX.  Must set asserted
4435                                                                  with with [CMR_X2P_RESET]=1 (in the same write operation) to avoid partial packets
4436                                                                  to the NCSI interface while performing a X2P partner reset.
4437                                                                  0 = Allow traffic to flow through the NCSI block. */
4438         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Interface reset for the CMR NCSI block.
4439                                                                  Upon power up the CMR NCSI is in reset and the companion CNXXXX NCSI block will be
4440                                                                  commanded by the
4441                                                                  external BMC to enable one of the CNXXXX BGX NCSI interfaces for passing network traffic.
4442                                                                  Only one NCSI interface can be enabled in CNXXXX.  The BMC/NCSI will then proceed to
4443                                                                  configure
4444                                                                  the rest of the BGX csr for pass through traffic.
4445 
4446                                                                  When set, will reset the CMR NCSI interface effectively disabling it at a traffic boundary
4447                                                                  should traffic be flowing.  This bit will not reset the main RXB fifos. */
4448         uint64_t reserved_11_63        : 53;
4449 #endif /* Word 0 - End */
4450     } cn88xxp1;
4451     struct bdk_bgxx_cmr_global_config_cn81xx
4452     {
4453 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4454         uint64_t reserved_11_63        : 53;
4455         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Reserved. */
4456         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) Reserved. */
4457         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Reserved. */
4458         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4459                                                                  bytes, the packet will be removed.
4460                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4461         uint64_t interleave_mode       : 1;  /**< [  5:  5](RAZ) Reserved. */
4462         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4463         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4464         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the NIC block is reset, software also needs to reset the X2P interface in the
4465                                                                  BGX by
4466                                                                  setting this bit to 1. It resets the X2P interface state in the BGX (skid FIFO and pending
4467                                                                  requests to NIC) and prevents the RXB FIFOs for all LMACs from pushing data to the
4468                                                                  interface.
4469 
4470                                                                  Setting this bit to 0 does not reset the X2P interface.
4471                                                                  After NIC comes out of reset, software should clear this bit. */
4472         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4473                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4474                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4475                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4476                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4477         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4478 #else /* Word 0 - Little Endian */
4479         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4480         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4481                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4482                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4483                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4484                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4485         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the NIC block is reset, software also needs to reset the X2P interface in the
4486                                                                  BGX by
4487                                                                  setting this bit to 1. It resets the X2P interface state in the BGX (skid FIFO and pending
4488                                                                  requests to NIC) and prevents the RXB FIFOs for all LMACs from pushing data to the
4489                                                                  interface.
4490 
4491                                                                  Setting this bit to 0 does not reset the X2P interface.
4492                                                                  After NIC comes out of reset, software should clear this bit. */
4493         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4494         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4495         uint64_t interleave_mode       : 1;  /**< [  5:  5](RAZ) Reserved. */
4496         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4497                                                                  bytes, the packet will be removed.
4498                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4499         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Reserved. */
4500         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) Reserved. */
4501         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Reserved. */
4502         uint64_t reserved_11_63        : 53;
4503 #endif /* Word 0 - End */
4504     } cn81xx;
4505     struct bdk_bgxx_cmr_global_config_cn83xx
4506     {
4507 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4508         uint64_t reserved_12_63        : 52;
4509         uint64_t cmr_x2p1_reset        : 1;  /**< [ 11: 11](R/W) If the master block connected to X2P interface 1 is reset, software also needs
4510                                                                  to reset the X2P interface in the BGX by setting this bit. It resets the X2P
4511                                                                  interface state in the BGX (skid FIFO and pending requests to the master block)
4512                                                                  and prevents the RXB FIFOs for all LMACs from pushing data to the
4513                                                                  interface. Because the X2P and NCSI interfaces share the main RXB FIFOs it will
4514                                                                  also impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP]
4515                                                                  bit first before setting this bit.
4516 
4517                                                                  Clearing this does not reset the X2P interface nor NCSI interface.  After the
4518                                                                  master block comes out of reset, software should clear this bit. */
4519         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Interface reset for the CMR NCSI block.
4520                                                                  Upon power up the CMR NCSI is in reset and the companion CNXXXX NCSI block will be
4521                                                                  commanded by the
4522                                                                  external BMC to enable one of the CNXXXX BGX NCSI interfaces for passing network traffic.
4523                                                                  Only one NCSI interface can be enabled in CNXXXX.  The BMC/NCSI will then proceed to
4524                                                                  configure
4525                                                                  the rest of the BGX csr for pass through traffic.
4526 
4527                                                                  When set, will reset the CMR NCSI interface effectively disabling it at a traffic boundary
4528                                                                  should traffic be flowing.  This bit will not reset the main RXB fifos. */
4529         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) NCSI drop.
4530                                                                  1 = Cleanly drop traffic going into the NCSI block of BGX.  Must set asserted
4531                                                                  with with [CMR_X2P_RESET]=1 (in the same write operation) to avoid partial packets
4532                                                                  to the NCSI interface while performing a X2P partner reset.
4533                                                                  0 = Allow traffic to flow through the NCSI block. */
4534         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Logical MAC ID that carries NCSI traffic for both RX and TX side of CMR.  On the RX side
4535                                                                  is
4536                                                                  also the LMAC_ID that is eligible for steering. */
4537         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4538                                                                  bytes, the packet will be removed.
4539                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4540         uint64_t interleave_mode       : 1;  /**< [  5:  5](RAZ) Reserved. */
4541         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4542         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4543         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the master block connected to X2P interface 0 is reset, software also needs
4544                                                                  to reset the X2P interface in the BGX by setting this bit. It resets the X2P
4545                                                                  interface state in the BGX (skid FIFO and pending requests to the master block)
4546                                                                  and prevents the RXB FIFOs for all LMACs from pushing data to the
4547                                                                  interface. Because the X2P and NCSI interfaces share the main RXB FIFOs it will
4548                                                                  also impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP]
4549                                                                  bit first before setting this bit.
4550 
4551                                                                  Clearing this does not reset the X2P interface nor NCSI interface.  After the
4552                                                                  master block comes out of reset, software should clear this bit. */
4553         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4554                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4555                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4556                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4557                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4558         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4559 #else /* Word 0 - Little Endian */
4560         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4561         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4562                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4563                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4564                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4565                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4566         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the master block connected to X2P interface 0 is reset, software also needs
4567                                                                  to reset the X2P interface in the BGX by setting this bit. It resets the X2P
4568                                                                  interface state in the BGX (skid FIFO and pending requests to the master block)
4569                                                                  and prevents the RXB FIFOs for all LMACs from pushing data to the
4570                                                                  interface. Because the X2P and NCSI interfaces share the main RXB FIFOs it will
4571                                                                  also impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP]
4572                                                                  bit first before setting this bit.
4573 
4574                                                                  Clearing this does not reset the X2P interface nor NCSI interface.  After the
4575                                                                  master block comes out of reset, software should clear this bit. */
4576         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4577         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4578         uint64_t interleave_mode       : 1;  /**< [  5:  5](RAZ) Reserved. */
4579         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4580                                                                  bytes, the packet will be removed.
4581                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4582         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Logical MAC ID that carries NCSI traffic for both RX and TX side of CMR.  On the RX side
4583                                                                  is
4584                                                                  also the LMAC_ID that is eligible for steering. */
4585         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) NCSI drop.
4586                                                                  1 = Cleanly drop traffic going into the NCSI block of BGX.  Must set asserted
4587                                                                  with with [CMR_X2P_RESET]=1 (in the same write operation) to avoid partial packets
4588                                                                  to the NCSI interface while performing a X2P partner reset.
4589                                                                  0 = Allow traffic to flow through the NCSI block. */
4590         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Interface reset for the CMR NCSI block.
4591                                                                  Upon power up the CMR NCSI is in reset and the companion CNXXXX NCSI block will be
4592                                                                  commanded by the
4593                                                                  external BMC to enable one of the CNXXXX BGX NCSI interfaces for passing network traffic.
4594                                                                  Only one NCSI interface can be enabled in CNXXXX.  The BMC/NCSI will then proceed to
4595                                                                  configure
4596                                                                  the rest of the BGX csr for pass through traffic.
4597 
4598                                                                  When set, will reset the CMR NCSI interface effectively disabling it at a traffic boundary
4599                                                                  should traffic be flowing.  This bit will not reset the main RXB fifos. */
4600         uint64_t cmr_x2p1_reset        : 1;  /**< [ 11: 11](R/W) If the master block connected to X2P interface 1 is reset, software also needs
4601                                                                  to reset the X2P interface in the BGX by setting this bit. It resets the X2P
4602                                                                  interface state in the BGX (skid FIFO and pending requests to the master block)
4603                                                                  and prevents the RXB FIFOs for all LMACs from pushing data to the
4604                                                                  interface. Because the X2P and NCSI interfaces share the main RXB FIFOs it will
4605                                                                  also impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP]
4606                                                                  bit first before setting this bit.
4607 
4608                                                                  Clearing this does not reset the X2P interface nor NCSI interface.  After the
4609                                                                  master block comes out of reset, software should clear this bit. */
4610         uint64_t reserved_12_63        : 52;
4611 #endif /* Word 0 - End */
4612     } cn83xx;
4613     struct bdk_bgxx_cmr_global_config_cn88xxp2
4614     {
4615 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4616         uint64_t reserved_11_63        : 53;
4617         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Interface reset for the CMR NCSI block.
4618                                                                  Upon power up the CMR NCSI is in reset and the companion CNXXXX NCSI block will be
4619                                                                  commanded by the
4620                                                                  external BMC to enable one of the CNXXXX BGX NCSI interfaces for passing network traffic.
4621                                                                  Only one NCSI interface can be enabled in CNXXXX.  The BMC/NCSI will then proceed to
4622                                                                  configure
4623                                                                  the rest of the BGX csr for pass through traffic.
4624 
4625                                                                  When set, will reset the CMR NCSI interface effectively disabling it at a traffic boundary
4626                                                                  should traffic be flowing.  This bit will not reset the main RXB fifos. */
4627         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) NCSI drop.
4628                                                                  1 = Cleanly drop traffic going into the NCSI block of BGX.  Must set asserted
4629                                                                  with with [CMR_X2P_RESET]=1 (in the same write operation) to avoid partial packets
4630                                                                  to the NCSI interface while performing a X2P partner reset.
4631                                                                  0 = Allow traffic to flow through the NCSI block. */
4632         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Logical MAC ID that carries NCSI traffic for both RX and TX side of CMR.  On the RX side
4633                                                                  is
4634                                                                  also the LMAC_ID that is eligible for steering. */
4635         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4636                                                                  bytes, the packet will be removed.
4637                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4638         uint64_t interleave_mode       : 1;  /**< [  5:  5](RAZ) Reserved. */
4639         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4640         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4641         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the NIC or TNS block is reset, software also needs to reset the X2P interface in the
4642                                                                  BGX by
4643                                                                  setting this bit to 1. It resets the X2P interface state in the BGX (skid FIFO and pending
4644                                                                  requests to NIC) and prevents the RXB FIFOs for all LMACs from pushing data to the
4645                                                                  interface. Because the X2P and NCSI interfaces share the main RXB fifos it will also
4646                                                                  impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP] bit first before
4647                                                                  setting this bit.
4648 
4649                                                                  Setting this bit to 0 does not reset the X2P interface nor NCSI interface.
4650                                                                  After NIC/TNS comes out of reset, software should clear this bit. */
4651         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4652                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4653                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4654                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4655                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4656         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4657 #else /* Word 0 - Little Endian */
4658         uint64_t pmux_sds_sel          : 1;  /**< [  0:  0](R/W) SerDes/GSER output select. Must be 0. */
4659         uint64_t bgx_clk_enable        : 1;  /**< [  1:  1](R/W) The global clock enable for BGX. Setting this bit overrides clock enables set by
4660                                                                  BGX()_CMR()_CONFIG[ENABLE] and BGX()_CMR()_CONFIG[LMAC_TYPE], essentially
4661                                                                  turning on clocks for the entire BGX. Setting this bit to 0 results in not overriding
4662                                                                  clock enables set by BGX()_CMR()_CONFIG[ENABLE] and
4663                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. */
4664         uint64_t cmr_x2p_reset         : 1;  /**< [  2:  2](R/W) If the NIC or TNS block is reset, software also needs to reset the X2P interface in the
4665                                                                  BGX by
4666                                                                  setting this bit to 1. It resets the X2P interface state in the BGX (skid FIFO and pending
4667                                                                  requests to NIC) and prevents the RXB FIFOs for all LMACs from pushing data to the
4668                                                                  interface. Because the X2P and NCSI interfaces share the main RXB fifos it will also
4669                                                                  impact the NCSI interface therefore it is required to set [CMR_NCSI_DROP] bit first before
4670                                                                  setting this bit.
4671 
4672                                                                  Setting this bit to 0 does not reset the X2P interface nor NCSI interface.
4673                                                                  After NIC/TNS comes out of reset, software should clear this bit. */
4674         uint64_t cmr_mix0_reset        : 1;  /**< [  3:  3](R/W) Must be 0. */
4675         uint64_t cmr_mix1_reset        : 1;  /**< [  4:  4](R/W) Must be 0. */
4676         uint64_t interleave_mode       : 1;  /**< [  5:  5](RAZ) Reserved. */
4677         uint64_t fcs_strip             : 1;  /**< [  6:  6](R/W) A setting of 1 means the BGX strip the FCS bytes of every packet.  For packets less than 4
4678                                                                  bytes, the packet will be removed.
4679                                                                  A setting of 0 means the BGX will not modify or remove the FCS bytes. */
4680         uint64_t ncsi_lmac_id          : 2;  /**< [  8:  7](R/W) Logical MAC ID that carries NCSI traffic for both RX and TX side of CMR.  On the RX side
4681                                                                  is
4682                                                                  also the LMAC_ID that is eligible for steering. */
4683         uint64_t cmr_ncsi_drop         : 1;  /**< [  9:  9](R/W) NCSI drop.
4684                                                                  1 = Cleanly drop traffic going into the NCSI block of BGX.  Must set asserted
4685                                                                  with with [CMR_X2P_RESET]=1 (in the same write operation) to avoid partial packets
4686                                                                  to the NCSI interface while performing a X2P partner reset.
4687                                                                  0 = Allow traffic to flow through the NCSI block. */
4688         uint64_t cmr_ncsi_reset        : 1;  /**< [ 10: 10](R/W) Interface reset for the CMR NCSI block.
4689                                                                  Upon power up the CMR NCSI is in reset and the companion CNXXXX NCSI block will be
4690                                                                  commanded by the
4691                                                                  external BMC to enable one of the CNXXXX BGX NCSI interfaces for passing network traffic.
4692                                                                  Only one NCSI interface can be enabled in CNXXXX.  The BMC/NCSI will then proceed to
4693                                                                  configure
4694                                                                  the rest of the BGX csr for pass through traffic.
4695 
4696                                                                  When set, will reset the CMR NCSI interface effectively disabling it at a traffic boundary
4697                                                                  should traffic be flowing.  This bit will not reset the main RXB fifos. */
4698         uint64_t reserved_11_63        : 53;
4699 #endif /* Word 0 - End */
4700     } cn88xxp2;
4701 };
4702 typedef union bdk_bgxx_cmr_global_config bdk_bgxx_cmr_global_config_t;
4703 
4704 static inline uint64_t BDK_BGXX_CMR_GLOBAL_CONFIG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_GLOBAL_CONFIG(unsigned long a)4705 static inline uint64_t BDK_BGXX_CMR_GLOBAL_CONFIG(unsigned long a)
4706 {
4707     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4708         return 0x87e0e0000008ll + 0x1000000ll * ((a) & 0x1);
4709     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
4710         return 0x87e0e0000008ll + 0x1000000ll * ((a) & 0x3);
4711     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
4712         return 0x87e0e0000008ll + 0x1000000ll * ((a) & 0x1);
4713     __bdk_csr_fatal("BGXX_CMR_GLOBAL_CONFIG", 1, a, 0, 0, 0);
4714 }
4715 
4716 #define typedef_BDK_BGXX_CMR_GLOBAL_CONFIG(a) bdk_bgxx_cmr_global_config_t
4717 #define bustype_BDK_BGXX_CMR_GLOBAL_CONFIG(a) BDK_CSR_TYPE_RSL
4718 #define basename_BDK_BGXX_CMR_GLOBAL_CONFIG(a) "BGXX_CMR_GLOBAL_CONFIG"
4719 #define device_bar_BDK_BGXX_CMR_GLOBAL_CONFIG(a) 0x0 /* PF_BAR0 */
4720 #define busnum_BDK_BGXX_CMR_GLOBAL_CONFIG(a) (a)
4721 #define arguments_BDK_BGXX_CMR_GLOBAL_CONFIG(a) (a),-1,-1,-1
4722 
4723 /**
4724  * Register (RSL) bgx#_cmr_mem_ctrl
4725  *
4726  * BGX CMR Memory Control Register
4727  */
4728 union bdk_bgxx_cmr_mem_ctrl
4729 {
4730     uint64_t u;
4731     struct bdk_bgxx_cmr_mem_ctrl_s
4732     {
4733 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4734         uint64_t reserved_42_63        : 22;
4735         uint64_t txb_fif_m3_syn        : 2;  /**< [ 41: 40](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem3. */
4736         uint64_t txb_fif_m3_cdis       : 1;  /**< [ 39: 39](R/W) ECC-correction disable for the TXB main mem3. */
4737         uint64_t txb_fif_m2_syn        : 2;  /**< [ 38: 37](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem2. */
4738         uint64_t txb_fif_m2_cdis       : 1;  /**< [ 36: 36](R/W) ECC-correction disable for the TXB main mem2. */
4739         uint64_t txb_ncsi_synd         : 2;  /**< [ 35: 34](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4740         uint64_t txb_ncsi_cor_dis      : 1;  /**< [ 33: 33](R/W) ECC-correction disable for the TXB SKID FIFO */
4741         uint64_t txb_skid_m3_synd      : 2;  /**< [ 32: 31](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4742         uint64_t txb_skid_m3_cor_dis   : 1;  /**< [ 30: 30](R/W) ECC-correction disable for the TXB SKID FIFO */
4743         uint64_t txb_skid_m2_synd      : 2;  /**< [ 29: 28](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4744         uint64_t txb_skid_m2_cor_dis   : 1;  /**< [ 27: 27](R/W) ECC-correction disable for the TXB SKID FIFO */
4745         uint64_t txb_skid_m1_synd      : 2;  /**< [ 26: 25](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4746         uint64_t txb_skid_m1_cor_dis   : 1;  /**< [ 24: 24](R/W) ECC-correction disable for the TXB SKID FIFO */
4747         uint64_t txb_skid_m0_synd      : 2;  /**< [ 23: 22](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO. */
4748         uint64_t txb_skid_m0_cor_dis   : 1;  /**< [ 21: 21](R/W) ECC-correction disable for the TXB SKID FIFO. */
4749         uint64_t reserved_15_20        : 6;
4750         uint64_t rxb_skid_synd         : 2;  /**< [ 14: 13](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB SKID FIFO. */
4751         uint64_t rxb_skid_cor_dis      : 1;  /**< [ 12: 12](R/W) ECC-correction disable for the RXB SKID FIFO. */
4752         uint64_t rxb_fif_bk1_syn1      : 2;  /**< [ 11: 10](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf1. */
4753         uint64_t rxb_fif_bk1_cdis1     : 1;  /**< [  9:  9](R/W) ECC-correction disable for the RXB main bank1 srf1. */
4754         uint64_t rxb_fif_bk1_syn0      : 2;  /**< [  8:  7](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf0. */
4755         uint64_t rxb_fif_bk1_cdis0     : 1;  /**< [  6:  6](R/W) ECC-correction disable for the RXB main bank1 srf0. */
4756         uint64_t rxb_fif_bk0_syn1      : 2;  /**< [  5:  4](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf1. */
4757         uint64_t rxb_fif_bk0_cdis1     : 1;  /**< [  3:  3](R/W) ECC-correction disable for the RXB main bank0 srf1. */
4758         uint64_t rxb_fif_bk0_syn0      : 2;  /**< [  2:  1](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf0. */
4759         uint64_t rxb_fif_bk0_cdis0     : 1;  /**< [  0:  0](R/W) ECC-correction disable for the RXB main bank0 srf0. */
4760 #else /* Word 0 - Little Endian */
4761         uint64_t rxb_fif_bk0_cdis0     : 1;  /**< [  0:  0](R/W) ECC-correction disable for the RXB main bank0 srf0. */
4762         uint64_t rxb_fif_bk0_syn0      : 2;  /**< [  2:  1](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf0. */
4763         uint64_t rxb_fif_bk0_cdis1     : 1;  /**< [  3:  3](R/W) ECC-correction disable for the RXB main bank0 srf1. */
4764         uint64_t rxb_fif_bk0_syn1      : 2;  /**< [  5:  4](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf1. */
4765         uint64_t rxb_fif_bk1_cdis0     : 1;  /**< [  6:  6](R/W) ECC-correction disable for the RXB main bank1 srf0. */
4766         uint64_t rxb_fif_bk1_syn0      : 2;  /**< [  8:  7](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf0. */
4767         uint64_t rxb_fif_bk1_cdis1     : 1;  /**< [  9:  9](R/W) ECC-correction disable for the RXB main bank1 srf1. */
4768         uint64_t rxb_fif_bk1_syn1      : 2;  /**< [ 11: 10](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf1. */
4769         uint64_t rxb_skid_cor_dis      : 1;  /**< [ 12: 12](R/W) ECC-correction disable for the RXB SKID FIFO. */
4770         uint64_t rxb_skid_synd         : 2;  /**< [ 14: 13](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB SKID FIFO. */
4771         uint64_t reserved_15_20        : 6;
4772         uint64_t txb_skid_m0_cor_dis   : 1;  /**< [ 21: 21](R/W) ECC-correction disable for the TXB SKID FIFO. */
4773         uint64_t txb_skid_m0_synd      : 2;  /**< [ 23: 22](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO. */
4774         uint64_t txb_skid_m1_cor_dis   : 1;  /**< [ 24: 24](R/W) ECC-correction disable for the TXB SKID FIFO */
4775         uint64_t txb_skid_m1_synd      : 2;  /**< [ 26: 25](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4776         uint64_t txb_skid_m2_cor_dis   : 1;  /**< [ 27: 27](R/W) ECC-correction disable for the TXB SKID FIFO */
4777         uint64_t txb_skid_m2_synd      : 2;  /**< [ 29: 28](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4778         uint64_t txb_skid_m3_cor_dis   : 1;  /**< [ 30: 30](R/W) ECC-correction disable for the TXB SKID FIFO */
4779         uint64_t txb_skid_m3_synd      : 2;  /**< [ 32: 31](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4780         uint64_t txb_ncsi_cor_dis      : 1;  /**< [ 33: 33](R/W) ECC-correction disable for the TXB SKID FIFO */
4781         uint64_t txb_ncsi_synd         : 2;  /**< [ 35: 34](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4782         uint64_t txb_fif_m2_cdis       : 1;  /**< [ 36: 36](R/W) ECC-correction disable for the TXB main mem2. */
4783         uint64_t txb_fif_m2_syn        : 2;  /**< [ 38: 37](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem2. */
4784         uint64_t txb_fif_m3_cdis       : 1;  /**< [ 39: 39](R/W) ECC-correction disable for the TXB main mem3. */
4785         uint64_t txb_fif_m3_syn        : 2;  /**< [ 41: 40](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem3. */
4786         uint64_t reserved_42_63        : 22;
4787 #endif /* Word 0 - End */
4788     } s;
4789     struct bdk_bgxx_cmr_mem_ctrl_cn81xx
4790     {
4791 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4792         uint64_t reserved_36_63        : 28;
4793         uint64_t txb_ncsi_synd         : 2;  /**< [ 35: 34](R/W) Reserved. */
4794         uint64_t txb_ncsi_cor_dis      : 1;  /**< [ 33: 33](R/W) Reserved. */
4795         uint64_t txb_skid_m3_synd      : 2;  /**< [ 32: 31](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4796         uint64_t txb_skid_m3_cor_dis   : 1;  /**< [ 30: 30](R/W) ECC-correction disable for the TXB SKID FIFO */
4797         uint64_t txb_skid_m2_synd      : 2;  /**< [ 29: 28](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4798         uint64_t txb_skid_m2_cor_dis   : 1;  /**< [ 27: 27](R/W) ECC-correction disable for the TXB SKID FIFO */
4799         uint64_t txb_skid_m1_synd      : 2;  /**< [ 26: 25](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4800         uint64_t txb_skid_m1_cor_dis   : 1;  /**< [ 24: 24](R/W) ECC-correction disable for the TXB SKID FIFO */
4801         uint64_t txb_skid_m0_synd      : 2;  /**< [ 23: 22](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO. */
4802         uint64_t txb_skid_m0_cor_dis   : 1;  /**< [ 21: 21](R/W) ECC-correction disable for the TXB SKID FIFO. */
4803         uint64_t txb_fif_bk1_syn       : 2;  /**< [ 20: 19](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main bank1. */
4804         uint64_t txb_fif_bk1_cdis      : 1;  /**< [ 18: 18](R/W) ECC-correction disable for the TXB main bank1. */
4805         uint64_t txb_fif_bk0_syn       : 2;  /**< [ 17: 16](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main bank0. */
4806         uint64_t txb_fif_bk0_cdis      : 1;  /**< [ 15: 15](R/W) ECC-correction disable for the TXB main bank0. */
4807         uint64_t rxb_skid_synd         : 2;  /**< [ 14: 13](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB SKID FIFO. */
4808         uint64_t rxb_skid_cor_dis      : 1;  /**< [ 12: 12](R/W) ECC-correction disable for the RXB SKID FIFO. */
4809         uint64_t rxb_fif_bk1_syn1      : 2;  /**< [ 11: 10](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf1. */
4810         uint64_t rxb_fif_bk1_cdis1     : 1;  /**< [  9:  9](R/W) ECC-correction disable for the RXB main bank1 srf1. */
4811         uint64_t rxb_fif_bk1_syn0      : 2;  /**< [  8:  7](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf0. */
4812         uint64_t rxb_fif_bk1_cdis0     : 1;  /**< [  6:  6](R/W) ECC-correction disable for the RXB main bank1 srf0. */
4813         uint64_t rxb_fif_bk0_syn1      : 2;  /**< [  5:  4](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf1. */
4814         uint64_t rxb_fif_bk0_cdis1     : 1;  /**< [  3:  3](R/W) ECC-correction disable for the RXB main bank0 srf1. */
4815         uint64_t rxb_fif_bk0_syn0      : 2;  /**< [  2:  1](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf0. */
4816         uint64_t rxb_fif_bk0_cdis0     : 1;  /**< [  0:  0](R/W) ECC-correction disable for the RXB main bank0 srf0. */
4817 #else /* Word 0 - Little Endian */
4818         uint64_t rxb_fif_bk0_cdis0     : 1;  /**< [  0:  0](R/W) ECC-correction disable for the RXB main bank0 srf0. */
4819         uint64_t rxb_fif_bk0_syn0      : 2;  /**< [  2:  1](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf0. */
4820         uint64_t rxb_fif_bk0_cdis1     : 1;  /**< [  3:  3](R/W) ECC-correction disable for the RXB main bank0 srf1. */
4821         uint64_t rxb_fif_bk0_syn1      : 2;  /**< [  5:  4](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf1. */
4822         uint64_t rxb_fif_bk1_cdis0     : 1;  /**< [  6:  6](R/W) ECC-correction disable for the RXB main bank1 srf0. */
4823         uint64_t rxb_fif_bk1_syn0      : 2;  /**< [  8:  7](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf0. */
4824         uint64_t rxb_fif_bk1_cdis1     : 1;  /**< [  9:  9](R/W) ECC-correction disable for the RXB main bank1 srf1. */
4825         uint64_t rxb_fif_bk1_syn1      : 2;  /**< [ 11: 10](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf1. */
4826         uint64_t rxb_skid_cor_dis      : 1;  /**< [ 12: 12](R/W) ECC-correction disable for the RXB SKID FIFO. */
4827         uint64_t rxb_skid_synd         : 2;  /**< [ 14: 13](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB SKID FIFO. */
4828         uint64_t txb_fif_bk0_cdis      : 1;  /**< [ 15: 15](R/W) ECC-correction disable for the TXB main bank0. */
4829         uint64_t txb_fif_bk0_syn       : 2;  /**< [ 17: 16](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main bank0. */
4830         uint64_t txb_fif_bk1_cdis      : 1;  /**< [ 18: 18](R/W) ECC-correction disable for the TXB main bank1. */
4831         uint64_t txb_fif_bk1_syn       : 2;  /**< [ 20: 19](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main bank1. */
4832         uint64_t txb_skid_m0_cor_dis   : 1;  /**< [ 21: 21](R/W) ECC-correction disable for the TXB SKID FIFO. */
4833         uint64_t txb_skid_m0_synd      : 2;  /**< [ 23: 22](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO. */
4834         uint64_t txb_skid_m1_cor_dis   : 1;  /**< [ 24: 24](R/W) ECC-correction disable for the TXB SKID FIFO */
4835         uint64_t txb_skid_m1_synd      : 2;  /**< [ 26: 25](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4836         uint64_t txb_skid_m2_cor_dis   : 1;  /**< [ 27: 27](R/W) ECC-correction disable for the TXB SKID FIFO */
4837         uint64_t txb_skid_m2_synd      : 2;  /**< [ 29: 28](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4838         uint64_t txb_skid_m3_cor_dis   : 1;  /**< [ 30: 30](R/W) ECC-correction disable for the TXB SKID FIFO */
4839         uint64_t txb_skid_m3_synd      : 2;  /**< [ 32: 31](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4840         uint64_t txb_ncsi_cor_dis      : 1;  /**< [ 33: 33](R/W) Reserved. */
4841         uint64_t txb_ncsi_synd         : 2;  /**< [ 35: 34](R/W) Reserved. */
4842         uint64_t reserved_36_63        : 28;
4843 #endif /* Word 0 - End */
4844     } cn81xx;
4845     struct bdk_bgxx_cmr_mem_ctrl_cn88xx
4846     {
4847 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4848         uint64_t reserved_36_63        : 28;
4849         uint64_t txb_ncsi_synd         : 2;  /**< [ 35: 34](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4850         uint64_t txb_ncsi_cor_dis      : 1;  /**< [ 33: 33](R/W) ECC-correction disable for the TXB SKID FIFO */
4851         uint64_t txb_skid_m3_synd      : 2;  /**< [ 32: 31](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4852         uint64_t txb_skid_m3_cor_dis   : 1;  /**< [ 30: 30](R/W) ECC-correction disable for the TXB SKID FIFO */
4853         uint64_t txb_skid_m2_synd      : 2;  /**< [ 29: 28](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4854         uint64_t txb_skid_m2_cor_dis   : 1;  /**< [ 27: 27](R/W) ECC-correction disable for the TXB SKID FIFO */
4855         uint64_t txb_skid_m1_synd      : 2;  /**< [ 26: 25](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4856         uint64_t txb_skid_m1_cor_dis   : 1;  /**< [ 24: 24](R/W) ECC-correction disable for the TXB SKID FIFO */
4857         uint64_t txb_skid_m0_synd      : 2;  /**< [ 23: 22](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO. */
4858         uint64_t txb_skid_m0_cor_dis   : 1;  /**< [ 21: 21](R/W) ECC-correction disable for the TXB SKID FIFO. */
4859         uint64_t txb_fif_bk1_syn       : 2;  /**< [ 20: 19](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main bank1. */
4860         uint64_t txb_fif_bk1_cdis      : 1;  /**< [ 18: 18](R/W) ECC-correction disable for the TXB main bank1. */
4861         uint64_t txb_fif_bk0_syn       : 2;  /**< [ 17: 16](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main bank0. */
4862         uint64_t txb_fif_bk0_cdis      : 1;  /**< [ 15: 15](R/W) ECC-correction disable for the TXB main bank0. */
4863         uint64_t rxb_skid_synd         : 2;  /**< [ 14: 13](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB SKID FIFO. */
4864         uint64_t rxb_skid_cor_dis      : 1;  /**< [ 12: 12](R/W) ECC-correction disable for the RXB SKID FIFO. */
4865         uint64_t rxb_fif_bk1_syn1      : 2;  /**< [ 11: 10](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf1. */
4866         uint64_t rxb_fif_bk1_cdis1     : 1;  /**< [  9:  9](R/W) ECC-correction disable for the RXB main bank1 srf1. */
4867         uint64_t rxb_fif_bk1_syn0      : 2;  /**< [  8:  7](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf0. */
4868         uint64_t rxb_fif_bk1_cdis0     : 1;  /**< [  6:  6](R/W) ECC-correction disable for the RXB main bank1 srf0. */
4869         uint64_t rxb_fif_bk0_syn1      : 2;  /**< [  5:  4](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf1. */
4870         uint64_t rxb_fif_bk0_cdis1     : 1;  /**< [  3:  3](R/W) ECC-correction disable for the RXB main bank0 srf1. */
4871         uint64_t rxb_fif_bk0_syn0      : 2;  /**< [  2:  1](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf0. */
4872         uint64_t rxb_fif_bk0_cdis0     : 1;  /**< [  0:  0](R/W) ECC-correction disable for the RXB main bank0 srf0. */
4873 #else /* Word 0 - Little Endian */
4874         uint64_t rxb_fif_bk0_cdis0     : 1;  /**< [  0:  0](R/W) ECC-correction disable for the RXB main bank0 srf0. */
4875         uint64_t rxb_fif_bk0_syn0      : 2;  /**< [  2:  1](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf0. */
4876         uint64_t rxb_fif_bk0_cdis1     : 1;  /**< [  3:  3](R/W) ECC-correction disable for the RXB main bank0 srf1. */
4877         uint64_t rxb_fif_bk0_syn1      : 2;  /**< [  5:  4](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf1. */
4878         uint64_t rxb_fif_bk1_cdis0     : 1;  /**< [  6:  6](R/W) ECC-correction disable for the RXB main bank1 srf0. */
4879         uint64_t rxb_fif_bk1_syn0      : 2;  /**< [  8:  7](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf0. */
4880         uint64_t rxb_fif_bk1_cdis1     : 1;  /**< [  9:  9](R/W) ECC-correction disable for the RXB main bank1 srf1. */
4881         uint64_t rxb_fif_bk1_syn1      : 2;  /**< [ 11: 10](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf1. */
4882         uint64_t rxb_skid_cor_dis      : 1;  /**< [ 12: 12](R/W) ECC-correction disable for the RXB SKID FIFO. */
4883         uint64_t rxb_skid_synd         : 2;  /**< [ 14: 13](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB SKID FIFO. */
4884         uint64_t txb_fif_bk0_cdis      : 1;  /**< [ 15: 15](R/W) ECC-correction disable for the TXB main bank0. */
4885         uint64_t txb_fif_bk0_syn       : 2;  /**< [ 17: 16](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main bank0. */
4886         uint64_t txb_fif_bk1_cdis      : 1;  /**< [ 18: 18](R/W) ECC-correction disable for the TXB main bank1. */
4887         uint64_t txb_fif_bk1_syn       : 2;  /**< [ 20: 19](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main bank1. */
4888         uint64_t txb_skid_m0_cor_dis   : 1;  /**< [ 21: 21](R/W) ECC-correction disable for the TXB SKID FIFO. */
4889         uint64_t txb_skid_m0_synd      : 2;  /**< [ 23: 22](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO. */
4890         uint64_t txb_skid_m1_cor_dis   : 1;  /**< [ 24: 24](R/W) ECC-correction disable for the TXB SKID FIFO */
4891         uint64_t txb_skid_m1_synd      : 2;  /**< [ 26: 25](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4892         uint64_t txb_skid_m2_cor_dis   : 1;  /**< [ 27: 27](R/W) ECC-correction disable for the TXB SKID FIFO */
4893         uint64_t txb_skid_m2_synd      : 2;  /**< [ 29: 28](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4894         uint64_t txb_skid_m3_cor_dis   : 1;  /**< [ 30: 30](R/W) ECC-correction disable for the TXB SKID FIFO */
4895         uint64_t txb_skid_m3_synd      : 2;  /**< [ 32: 31](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4896         uint64_t txb_ncsi_cor_dis      : 1;  /**< [ 33: 33](R/W) ECC-correction disable for the TXB SKID FIFO */
4897         uint64_t txb_ncsi_synd         : 2;  /**< [ 35: 34](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4898         uint64_t reserved_36_63        : 28;
4899 #endif /* Word 0 - End */
4900     } cn88xx;
4901     struct bdk_bgxx_cmr_mem_ctrl_cn83xx
4902     {
4903 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4904         uint64_t reserved_42_63        : 22;
4905         uint64_t txb_fif_m3_syn        : 2;  /**< [ 41: 40](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem3. */
4906         uint64_t txb_fif_m3_cdis       : 1;  /**< [ 39: 39](R/W) ECC-correction disable for the TXB main mem3. */
4907         uint64_t txb_fif_m2_syn        : 2;  /**< [ 38: 37](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem2. */
4908         uint64_t txb_fif_m2_cdis       : 1;  /**< [ 36: 36](R/W) ECC-correction disable for the TXB main mem2. */
4909         uint64_t txb_ncsi_synd         : 2;  /**< [ 35: 34](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4910         uint64_t txb_ncsi_cor_dis      : 1;  /**< [ 33: 33](R/W) ECC-correction disable for the TXB SKID FIFO */
4911         uint64_t txb_skid_m3_synd      : 2;  /**< [ 32: 31](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4912         uint64_t txb_skid_m3_cor_dis   : 1;  /**< [ 30: 30](R/W) ECC-correction disable for the TXB SKID FIFO */
4913         uint64_t txb_skid_m2_synd      : 2;  /**< [ 29: 28](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4914         uint64_t txb_skid_m2_cor_dis   : 1;  /**< [ 27: 27](R/W) ECC-correction disable for the TXB SKID FIFO */
4915         uint64_t txb_skid_m1_synd      : 2;  /**< [ 26: 25](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4916         uint64_t txb_skid_m1_cor_dis   : 1;  /**< [ 24: 24](R/W) ECC-correction disable for the TXB SKID FIFO */
4917         uint64_t txb_skid_m0_synd      : 2;  /**< [ 23: 22](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO. */
4918         uint64_t txb_skid_m0_cor_dis   : 1;  /**< [ 21: 21](R/W) ECC-correction disable for the TXB SKID FIFO. */
4919         uint64_t txb_fif_m1_syn        : 2;  /**< [ 20: 19](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem1. */
4920         uint64_t txb_fif_m1_cdis       : 1;  /**< [ 18: 18](R/W) ECC-correction disable for the TXB main mem1. */
4921         uint64_t txb_fif_m0_syn        : 2;  /**< [ 17: 16](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem0. */
4922         uint64_t txb_fif_m0_cdis       : 1;  /**< [ 15: 15](R/W) ECC-correction disable for the TXB main mem0. */
4923         uint64_t rxb_skid_synd         : 2;  /**< [ 14: 13](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB SKID FIFO. */
4924         uint64_t rxb_skid_cor_dis      : 1;  /**< [ 12: 12](R/W) ECC-correction disable for the RXB SKID FIFO. */
4925         uint64_t rxb_fif_bk1_syn1      : 2;  /**< [ 11: 10](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf1. */
4926         uint64_t rxb_fif_bk1_cdis1     : 1;  /**< [  9:  9](R/W) ECC-correction disable for the RXB main bank1 srf1. */
4927         uint64_t rxb_fif_bk1_syn0      : 2;  /**< [  8:  7](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf0. */
4928         uint64_t rxb_fif_bk1_cdis0     : 1;  /**< [  6:  6](R/W) ECC-correction disable for the RXB main bank1 srf0. */
4929         uint64_t rxb_fif_bk0_syn1      : 2;  /**< [  5:  4](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf1. */
4930         uint64_t rxb_fif_bk0_cdis1     : 1;  /**< [  3:  3](R/W) ECC-correction disable for the RXB main bank0 srf1. */
4931         uint64_t rxb_fif_bk0_syn0      : 2;  /**< [  2:  1](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf0. */
4932         uint64_t rxb_fif_bk0_cdis0     : 1;  /**< [  0:  0](R/W) ECC-correction disable for the RXB main bank0 srf0. */
4933 #else /* Word 0 - Little Endian */
4934         uint64_t rxb_fif_bk0_cdis0     : 1;  /**< [  0:  0](R/W) ECC-correction disable for the RXB main bank0 srf0. */
4935         uint64_t rxb_fif_bk0_syn0      : 2;  /**< [  2:  1](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf0. */
4936         uint64_t rxb_fif_bk0_cdis1     : 1;  /**< [  3:  3](R/W) ECC-correction disable for the RXB main bank0 srf1. */
4937         uint64_t rxb_fif_bk0_syn1      : 2;  /**< [  5:  4](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank0 srf1. */
4938         uint64_t rxb_fif_bk1_cdis0     : 1;  /**< [  6:  6](R/W) ECC-correction disable for the RXB main bank1 srf0. */
4939         uint64_t rxb_fif_bk1_syn0      : 2;  /**< [  8:  7](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf0. */
4940         uint64_t rxb_fif_bk1_cdis1     : 1;  /**< [  9:  9](R/W) ECC-correction disable for the RXB main bank1 srf1. */
4941         uint64_t rxb_fif_bk1_syn1      : 2;  /**< [ 11: 10](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB main bank1 srf1. */
4942         uint64_t rxb_skid_cor_dis      : 1;  /**< [ 12: 12](R/W) ECC-correction disable for the RXB SKID FIFO. */
4943         uint64_t rxb_skid_synd         : 2;  /**< [ 14: 13](R/W) Syndrome to flip and generate single-bit/double-bit error for RXB SKID FIFO. */
4944         uint64_t txb_fif_m0_cdis       : 1;  /**< [ 15: 15](R/W) ECC-correction disable for the TXB main mem0. */
4945         uint64_t txb_fif_m0_syn        : 2;  /**< [ 17: 16](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem0. */
4946         uint64_t txb_fif_m1_cdis       : 1;  /**< [ 18: 18](R/W) ECC-correction disable for the TXB main mem1. */
4947         uint64_t txb_fif_m1_syn        : 2;  /**< [ 20: 19](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem1. */
4948         uint64_t txb_skid_m0_cor_dis   : 1;  /**< [ 21: 21](R/W) ECC-correction disable for the TXB SKID FIFO. */
4949         uint64_t txb_skid_m0_synd      : 2;  /**< [ 23: 22](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO. */
4950         uint64_t txb_skid_m1_cor_dis   : 1;  /**< [ 24: 24](R/W) ECC-correction disable for the TXB SKID FIFO */
4951         uint64_t txb_skid_m1_synd      : 2;  /**< [ 26: 25](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4952         uint64_t txb_skid_m2_cor_dis   : 1;  /**< [ 27: 27](R/W) ECC-correction disable for the TXB SKID FIFO */
4953         uint64_t txb_skid_m2_synd      : 2;  /**< [ 29: 28](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4954         uint64_t txb_skid_m3_cor_dis   : 1;  /**< [ 30: 30](R/W) ECC-correction disable for the TXB SKID FIFO */
4955         uint64_t txb_skid_m3_synd      : 2;  /**< [ 32: 31](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4956         uint64_t txb_ncsi_cor_dis      : 1;  /**< [ 33: 33](R/W) ECC-correction disable for the TXB SKID FIFO */
4957         uint64_t txb_ncsi_synd         : 2;  /**< [ 35: 34](R/W) Syndrome to flip and generate single-bit/double-bit for TXB SKID FIFO */
4958         uint64_t txb_fif_m2_cdis       : 1;  /**< [ 36: 36](R/W) ECC-correction disable for the TXB main mem2. */
4959         uint64_t txb_fif_m2_syn        : 2;  /**< [ 38: 37](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem2. */
4960         uint64_t txb_fif_m3_cdis       : 1;  /**< [ 39: 39](R/W) ECC-correction disable for the TXB main mem3. */
4961         uint64_t txb_fif_m3_syn        : 2;  /**< [ 41: 40](R/W) Syndrome to flip and generate single-bit/double-bit error for TXB main mem3. */
4962         uint64_t reserved_42_63        : 22;
4963 #endif /* Word 0 - End */
4964     } cn83xx;
4965 };
4966 typedef union bdk_bgxx_cmr_mem_ctrl bdk_bgxx_cmr_mem_ctrl_t;
4967 
4968 static inline uint64_t BDK_BGXX_CMR_MEM_CTRL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_MEM_CTRL(unsigned long a)4969 static inline uint64_t BDK_BGXX_CMR_MEM_CTRL(unsigned long a)
4970 {
4971     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
4972         return 0x87e0e0000030ll + 0x1000000ll * ((a) & 0x1);
4973     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
4974         return 0x87e0e0000030ll + 0x1000000ll * ((a) & 0x3);
4975     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
4976         return 0x87e0e0000030ll + 0x1000000ll * ((a) & 0x1);
4977     __bdk_csr_fatal("BGXX_CMR_MEM_CTRL", 1, a, 0, 0, 0);
4978 }
4979 
4980 #define typedef_BDK_BGXX_CMR_MEM_CTRL(a) bdk_bgxx_cmr_mem_ctrl_t
4981 #define bustype_BDK_BGXX_CMR_MEM_CTRL(a) BDK_CSR_TYPE_RSL
4982 #define basename_BDK_BGXX_CMR_MEM_CTRL(a) "BGXX_CMR_MEM_CTRL"
4983 #define device_bar_BDK_BGXX_CMR_MEM_CTRL(a) 0x0 /* PF_BAR0 */
4984 #define busnum_BDK_BGXX_CMR_MEM_CTRL(a) (a)
4985 #define arguments_BDK_BGXX_CMR_MEM_CTRL(a) (a),-1,-1,-1
4986 
4987 /**
4988  * Register (RSL) bgx#_cmr_mem_int
4989  *
4990  * BGX CMR Memory Interrupt Register
4991  */
4992 union bdk_bgxx_cmr_mem_int
4993 {
4994     uint64_t u;
4995     struct bdk_bgxx_cmr_mem_int_s
4996     {
4997 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4998         uint64_t reserved_40_63        : 24;
4999         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1C/H) TXB Main FIFO Mem3 single-bit error. */
5000         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1C/H) TXB Main FIFO Mem3 double-bit error. */
5001         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1C/H) TXB Main FIFO Mem2 single-bit error. */
5002         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1C/H) TXB Main FIFO Mem2 double-bit error. */
5003         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5004         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5005         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) TXB SKID FIFO single-bit error */
5006         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5007         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5008         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5009         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5010         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5011         uint64_t reserved_8_27         : 20;
5012         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) RXB main FIFO bank1 srf1 single-bit error. */
5013         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) RXB main FIFO bank1 srf1 double-bit error. */
5014         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) RXB main FIFO bank1 srf0 single-bit error. */
5015         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) RXB main FIFO bank1 srf0 double-bit error. */
5016         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) RXB main FIFO bank0 srf1 single-bit error. */
5017         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) RXB main FIFO bank0 srf1 double-bit error. */
5018         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) RXB main FIFO bank0 srf0 single-bit error. */
5019         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) RXB main FIFO bank0 srf0 double-bit error. */
5020 #else /* Word 0 - Little Endian */
5021         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) RXB main FIFO bank0 srf0 double-bit error. */
5022         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) RXB main FIFO bank0 srf0 single-bit error. */
5023         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) RXB main FIFO bank0 srf1 double-bit error. */
5024         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) RXB main FIFO bank0 srf1 single-bit error. */
5025         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) RXB main FIFO bank1 srf0 double-bit error. */
5026         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) RXB main FIFO bank1 srf0 single-bit error. */
5027         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) RXB main FIFO bank1 srf1 double-bit error. */
5028         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) RXB main FIFO bank1 srf1 single-bit error. */
5029         uint64_t reserved_8_27         : 20;
5030         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5031         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5032         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5033         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5034         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5035         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) TXB SKID FIFO single-bit error */
5036         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5037         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5038         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1C/H) TXB Main FIFO Mem2 double-bit error. */
5039         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1C/H) TXB Main FIFO Mem2 single-bit error. */
5040         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1C/H) TXB Main FIFO Mem3 double-bit error. */
5041         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1C/H) TXB Main FIFO Mem3 single-bit error. */
5042         uint64_t reserved_40_63        : 24;
5043 #endif /* Word 0 - End */
5044     } s;
5045     struct bdk_bgxx_cmr_mem_int_cn81xx
5046     {
5047 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5048         uint64_t reserved_36_63        : 28;
5049         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5050         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5051         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) TXB SKID FIFO single-bit error */
5052         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5053         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5054         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5055         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5056         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5057         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1C/H) Reserved. */
5058         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1C/H) Reserved. */
5059         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1C/H) Reserved. */
5060         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1C/H) Reserved. */
5061         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1C/H) Reserved. */
5062         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1C/H) Reserved. */
5063         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1C/H) Reserved. */
5064         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1C/H) Reserved. */
5065         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1C/H) RX SMU INFIFO overflow. */
5066         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1C/H) RX GMP INFIFO overflow. */
5067         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1C/H) Reserved. */
5068         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1C/H) Reserved. */
5069         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 15: 15](R/W1C/H) TXB Main FIFO Bank1 single-bit error. */
5070         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 14: 14](R/W1C/H) TXB Main FIFO Bank1 double-bit error. */
5071         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 13: 13](R/W1C/H) TXB Main FIFO Bank0 single-bit error. */
5072         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 12: 12](R/W1C/H) TXB Main FIFO Bank0 double-bit error. */
5073         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1C/H) RXB NIC SKID FIFO single-bit error. */
5074         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1C/H) RXB NIC SKID FIFO double-bit error. */
5075         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1C/H) RXB PKI SKID FIFO single-bit error. */
5076         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1C/H) RXB PKI SKID FIFO double-bit error. */
5077         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) RXB main FIFO bank1 srf1 single-bit error. */
5078         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) RXB main FIFO bank1 srf1 double-bit error. */
5079         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) RXB main FIFO bank1 srf0 single-bit error. */
5080         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) RXB main FIFO bank1 srf0 double-bit error. */
5081         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) RXB main FIFO bank0 srf1 single-bit error. */
5082         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) RXB main FIFO bank0 srf1 double-bit error. */
5083         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) RXB main FIFO bank0 srf0 single-bit error. */
5084         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) RXB main FIFO bank0 srf0 double-bit error. */
5085 #else /* Word 0 - Little Endian */
5086         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) RXB main FIFO bank0 srf0 double-bit error. */
5087         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) RXB main FIFO bank0 srf0 single-bit error. */
5088         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) RXB main FIFO bank0 srf1 double-bit error. */
5089         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) RXB main FIFO bank0 srf1 single-bit error. */
5090         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) RXB main FIFO bank1 srf0 double-bit error. */
5091         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) RXB main FIFO bank1 srf0 single-bit error. */
5092         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) RXB main FIFO bank1 srf1 double-bit error. */
5093         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) RXB main FIFO bank1 srf1 single-bit error. */
5094         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1C/H) RXB PKI SKID FIFO double-bit error. */
5095         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1C/H) RXB PKI SKID FIFO single-bit error. */
5096         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1C/H) RXB NIC SKID FIFO double-bit error. */
5097         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1C/H) RXB NIC SKID FIFO single-bit error. */
5098         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 12: 12](R/W1C/H) TXB Main FIFO Bank0 double-bit error. */
5099         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 13: 13](R/W1C/H) TXB Main FIFO Bank0 single-bit error. */
5100         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 14: 14](R/W1C/H) TXB Main FIFO Bank1 double-bit error. */
5101         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 15: 15](R/W1C/H) TXB Main FIFO Bank1 single-bit error. */
5102         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1C/H) Reserved. */
5103         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1C/H) Reserved. */
5104         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1C/H) RX GMP INFIFO overflow. */
5105         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1C/H) RX SMU INFIFO overflow. */
5106         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1C/H) Reserved. */
5107         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1C/H) Reserved. */
5108         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1C/H) Reserved. */
5109         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1C/H) Reserved. */
5110         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1C/H) Reserved. */
5111         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1C/H) Reserved. */
5112         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1C/H) Reserved. */
5113         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1C/H) Reserved. */
5114         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5115         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5116         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5117         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5118         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5119         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) TXB SKID FIFO single-bit error */
5120         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5121         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5122         uint64_t reserved_36_63        : 28;
5123 #endif /* Word 0 - End */
5124     } cn81xx;
5125     struct bdk_bgxx_cmr_mem_int_cn88xx
5126     {
5127 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5128         uint64_t reserved_26_63        : 38;
5129         uint64_t txb_ncsi_sbe          : 1;  /**< [ 25: 25](R/W1C/H) TXB SKID FIFO single-bit error */
5130         uint64_t txb_ncsi_dbe          : 1;  /**< [ 24: 24](R/W1C/H) TXB SKID FIFO double-bit error */
5131         uint64_t txb_skid_m3_sbe       : 1;  /**< [ 23: 23](R/W1C/H) TXB SKID FIFO single-bit error */
5132         uint64_t txb_skid_m3_dbe       : 1;  /**< [ 22: 22](R/W1C/H) TXB SKID FIFO double-bit error */
5133         uint64_t txb_skid_m2_sbe       : 1;  /**< [ 21: 21](R/W1C/H) TXB SKID FIFO single-bit error */
5134         uint64_t txb_skid_m2_dbe       : 1;  /**< [ 20: 20](R/W1C/H) TXB SKID FIFO double-bit error */
5135         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1C/H) TXB SKID FIFO single-bit error */
5136         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1C/H) TXB SKID FIFO double-bit error */
5137         uint64_t smu_in_overfl         : 1;  /**< [ 17: 17](R/W1C/H) RX SMU INFIFO overflow. */
5138         uint64_t gmp_in_overfl         : 1;  /**< [ 16: 16](R/W1C/H) RX GMP INFIFO overflow. */
5139         uint64_t txb_skid_m0_sbe       : 1;  /**< [ 15: 15](R/W1C/H) TXB SKID FIFO single-bit error. */
5140         uint64_t txb_skid_m0_dbe       : 1;  /**< [ 14: 14](R/W1C/H) TXB SKID FIFO double-bit error. */
5141         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 13: 13](R/W1C/H) TXB Main FIFO Bank1 single-bit error. */
5142         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 12: 12](R/W1C/H) TXB Main FIFO Bank1 double-bit error. */
5143         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 11: 11](R/W1C/H) TXB Main FIFO Bank0 single-bit error. */
5144         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 10: 10](R/W1C/H) TXB Main FIFO Bank0 double-bit error. */
5145         uint64_t rxb_skid_sbe          : 1;  /**< [  9:  9](R/W1C/H) RXB SKID FIFO single-bit error. */
5146         uint64_t rxb_skid_dbe          : 1;  /**< [  8:  8](R/W1C/H) RXB SKID FIFO double-bit error. */
5147         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) RXB main FIFO bank1 srf1 single-bit error. */
5148         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) RXB main FIFO bank1 srf1 double-bit error. */
5149         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) RXB main FIFO bank1 srf0 single-bit error. */
5150         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) RXB main FIFO bank1 srf0 double-bit error. */
5151         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) RXB main FIFO bank0 srf1 single-bit error. */
5152         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) RXB main FIFO bank0 srf1 double-bit error. */
5153         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) RXB main FIFO bank0 srf0 single-bit error. */
5154         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) RXB main FIFO bank0 srf0 double-bit error. */
5155 #else /* Word 0 - Little Endian */
5156         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) RXB main FIFO bank0 srf0 double-bit error. */
5157         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) RXB main FIFO bank0 srf0 single-bit error. */
5158         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) RXB main FIFO bank0 srf1 double-bit error. */
5159         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) RXB main FIFO bank0 srf1 single-bit error. */
5160         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) RXB main FIFO bank1 srf0 double-bit error. */
5161         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) RXB main FIFO bank1 srf0 single-bit error. */
5162         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) RXB main FIFO bank1 srf1 double-bit error. */
5163         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) RXB main FIFO bank1 srf1 single-bit error. */
5164         uint64_t rxb_skid_dbe          : 1;  /**< [  8:  8](R/W1C/H) RXB SKID FIFO double-bit error. */
5165         uint64_t rxb_skid_sbe          : 1;  /**< [  9:  9](R/W1C/H) RXB SKID FIFO single-bit error. */
5166         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 10: 10](R/W1C/H) TXB Main FIFO Bank0 double-bit error. */
5167         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 11: 11](R/W1C/H) TXB Main FIFO Bank0 single-bit error. */
5168         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 12: 12](R/W1C/H) TXB Main FIFO Bank1 double-bit error. */
5169         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 13: 13](R/W1C/H) TXB Main FIFO Bank1 single-bit error. */
5170         uint64_t txb_skid_m0_dbe       : 1;  /**< [ 14: 14](R/W1C/H) TXB SKID FIFO double-bit error. */
5171         uint64_t txb_skid_m0_sbe       : 1;  /**< [ 15: 15](R/W1C/H) TXB SKID FIFO single-bit error. */
5172         uint64_t gmp_in_overfl         : 1;  /**< [ 16: 16](R/W1C/H) RX GMP INFIFO overflow. */
5173         uint64_t smu_in_overfl         : 1;  /**< [ 17: 17](R/W1C/H) RX SMU INFIFO overflow. */
5174         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1C/H) TXB SKID FIFO double-bit error */
5175         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1C/H) TXB SKID FIFO single-bit error */
5176         uint64_t txb_skid_m2_dbe       : 1;  /**< [ 20: 20](R/W1C/H) TXB SKID FIFO double-bit error */
5177         uint64_t txb_skid_m2_sbe       : 1;  /**< [ 21: 21](R/W1C/H) TXB SKID FIFO single-bit error */
5178         uint64_t txb_skid_m3_dbe       : 1;  /**< [ 22: 22](R/W1C/H) TXB SKID FIFO double-bit error */
5179         uint64_t txb_skid_m3_sbe       : 1;  /**< [ 23: 23](R/W1C/H) TXB SKID FIFO single-bit error */
5180         uint64_t txb_ncsi_dbe          : 1;  /**< [ 24: 24](R/W1C/H) TXB SKID FIFO double-bit error */
5181         uint64_t txb_ncsi_sbe          : 1;  /**< [ 25: 25](R/W1C/H) TXB SKID FIFO single-bit error */
5182         uint64_t reserved_26_63        : 38;
5183 #endif /* Word 0 - End */
5184     } cn88xx;
5185     struct bdk_bgxx_cmr_mem_int_cn83xx
5186     {
5187 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5188         uint64_t reserved_40_63        : 24;
5189         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1C/H) TXB Main FIFO Mem3 single-bit error. */
5190         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1C/H) TXB Main FIFO Mem3 double-bit error. */
5191         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1C/H) TXB Main FIFO Mem2 single-bit error. */
5192         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1C/H) TXB Main FIFO Mem2 double-bit error. */
5193         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5194         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5195         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) TXB SKID FIFO single-bit error */
5196         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5197         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5198         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5199         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5200         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5201         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1C/H) TXB SKID NCSI FIFO single-bit error */
5202         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1C/H) TXB SKID NCSI FIFO double-bit error */
5203         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1C/H) TXB SKID PKO FIFO single-bit error */
5204         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1C/H) TXB SKID PKO FIFO double-bit error */
5205         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1C/H) TXB SKID PKO FIFO single-bit error */
5206         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1C/H) TXB SKID PKO FIFO double-bit error */
5207         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1C/H) TXB SKID PKO FIFO single-bit error */
5208         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1C/H) TXB SKID PKO FIFO double-bit error */
5209         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1C/H) RX SMU INFIFO overflow. */
5210         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1C/H) RX GMP INFIFO overflow. */
5211         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1C/H) TXB SKID PKO FIFO single-bit error. */
5212         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1C/H) TXB SKID PKO FIFO double-bit error. */
5213         uint64_t txb_fif_m1_sbe        : 1;  /**< [ 15: 15](R/W1C/H) TXB Main FIFO Mem1 single-bit error. */
5214         uint64_t txb_fif_m1_dbe        : 1;  /**< [ 14: 14](R/W1C/H) TXB Main FIFO Mem1 double-bit error. */
5215         uint64_t txb_fif_m0_sbe        : 1;  /**< [ 13: 13](R/W1C/H) TXB Main FIFO Mem0 single-bit error. */
5216         uint64_t txb_fif_m0_dbe        : 1;  /**< [ 12: 12](R/W1C/H) TXB Main FIFO Mem0 double-bit error. */
5217         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1C/H) RXB NIC SKID FIFO single-bit error. */
5218         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1C/H) RXB NIC SKID FIFO double-bit error. */
5219         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1C/H) RXB PKI SKID FIFO single-bit error. */
5220         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1C/H) RXB PKI SKID FIFO double-bit error. */
5221         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) RXB main FIFO bank1 srf1 single-bit error. */
5222         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) RXB main FIFO bank1 srf1 double-bit error. */
5223         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) RXB main FIFO bank1 srf0 single-bit error. */
5224         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) RXB main FIFO bank1 srf0 double-bit error. */
5225         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) RXB main FIFO bank0 srf1 single-bit error. */
5226         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) RXB main FIFO bank0 srf1 double-bit error. */
5227         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) RXB main FIFO bank0 srf0 single-bit error. */
5228         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) RXB main FIFO bank0 srf0 double-bit error. */
5229 #else /* Word 0 - Little Endian */
5230         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) RXB main FIFO bank0 srf0 double-bit error. */
5231         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) RXB main FIFO bank0 srf0 single-bit error. */
5232         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) RXB main FIFO bank0 srf1 double-bit error. */
5233         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) RXB main FIFO bank0 srf1 single-bit error. */
5234         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) RXB main FIFO bank1 srf0 double-bit error. */
5235         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) RXB main FIFO bank1 srf0 single-bit error. */
5236         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) RXB main FIFO bank1 srf1 double-bit error. */
5237         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) RXB main FIFO bank1 srf1 single-bit error. */
5238         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1C/H) RXB PKI SKID FIFO double-bit error. */
5239         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1C/H) RXB PKI SKID FIFO single-bit error. */
5240         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1C/H) RXB NIC SKID FIFO double-bit error. */
5241         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1C/H) RXB NIC SKID FIFO single-bit error. */
5242         uint64_t txb_fif_m0_dbe        : 1;  /**< [ 12: 12](R/W1C/H) TXB Main FIFO Mem0 double-bit error. */
5243         uint64_t txb_fif_m0_sbe        : 1;  /**< [ 13: 13](R/W1C/H) TXB Main FIFO Mem0 single-bit error. */
5244         uint64_t txb_fif_m1_dbe        : 1;  /**< [ 14: 14](R/W1C/H) TXB Main FIFO Mem1 double-bit error. */
5245         uint64_t txb_fif_m1_sbe        : 1;  /**< [ 15: 15](R/W1C/H) TXB Main FIFO Mem1 single-bit error. */
5246         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1C/H) TXB SKID PKO FIFO double-bit error. */
5247         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1C/H) TXB SKID PKO FIFO single-bit error. */
5248         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1C/H) RX GMP INFIFO overflow. */
5249         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1C/H) RX SMU INFIFO overflow. */
5250         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1C/H) TXB SKID PKO FIFO double-bit error */
5251         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1C/H) TXB SKID PKO FIFO single-bit error */
5252         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1C/H) TXB SKID PKO FIFO double-bit error */
5253         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1C/H) TXB SKID PKO FIFO single-bit error */
5254         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1C/H) TXB SKID PKO FIFO double-bit error */
5255         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1C/H) TXB SKID PKO FIFO single-bit error */
5256         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1C/H) TXB SKID NCSI FIFO double-bit error */
5257         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1C/H) TXB SKID NCSI FIFO single-bit error */
5258         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5259         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5260         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5261         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5262         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5263         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) TXB SKID FIFO single-bit error */
5264         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) TXB SKID NIC FIFO double-bit error */
5265         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) TXB SKID NIC FIFO single-bit error */
5266         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1C/H) TXB Main FIFO Mem2 double-bit error. */
5267         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1C/H) TXB Main FIFO Mem2 single-bit error. */
5268         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1C/H) TXB Main FIFO Mem3 double-bit error. */
5269         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1C/H) TXB Main FIFO Mem3 single-bit error. */
5270         uint64_t reserved_40_63        : 24;
5271 #endif /* Word 0 - End */
5272     } cn83xx;
5273 };
5274 typedef union bdk_bgxx_cmr_mem_int bdk_bgxx_cmr_mem_int_t;
5275 
5276 static inline uint64_t BDK_BGXX_CMR_MEM_INT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_MEM_INT(unsigned long a)5277 static inline uint64_t BDK_BGXX_CMR_MEM_INT(unsigned long a)
5278 {
5279     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5280         return 0x87e0e0000010ll + 0x1000000ll * ((a) & 0x1);
5281     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
5282         return 0x87e0e0000010ll + 0x1000000ll * ((a) & 0x3);
5283     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
5284         return 0x87e0e0000010ll + 0x1000000ll * ((a) & 0x1);
5285     __bdk_csr_fatal("BGXX_CMR_MEM_INT", 1, a, 0, 0, 0);
5286 }
5287 
5288 #define typedef_BDK_BGXX_CMR_MEM_INT(a) bdk_bgxx_cmr_mem_int_t
5289 #define bustype_BDK_BGXX_CMR_MEM_INT(a) BDK_CSR_TYPE_RSL
5290 #define basename_BDK_BGXX_CMR_MEM_INT(a) "BGXX_CMR_MEM_INT"
5291 #define device_bar_BDK_BGXX_CMR_MEM_INT(a) 0x0 /* PF_BAR0 */
5292 #define busnum_BDK_BGXX_CMR_MEM_INT(a) (a)
5293 #define arguments_BDK_BGXX_CMR_MEM_INT(a) (a),-1,-1,-1
5294 
5295 /**
5296  * Register (RSL) bgx#_cmr_mem_int_ena_w1c
5297  *
5298  * BGX CMR Memory Interrupt Enable Clear Register
5299  * This register clears interrupt enable bits.
5300  */
5301 union bdk_bgxx_cmr_mem_int_ena_w1c
5302 {
5303     uint64_t u;
5304     struct bdk_bgxx_cmr_mem_int_ena_w1c_s
5305     {
5306 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5307         uint64_t reserved_40_63        : 24;
5308         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5309         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5310         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5311         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5312         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5313         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5314         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5315         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5316         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5317         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5318         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5319         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5320         uint64_t reserved_20_27        : 8;
5321         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5322         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5323         uint64_t reserved_8_17         : 10;
5324         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5325         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5326         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5327         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5328         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5329         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5330         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5331         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5332 #else /* Word 0 - Little Endian */
5333         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5334         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5335         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5336         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5337         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5338         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5339         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5340         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5341         uint64_t reserved_8_17         : 10;
5342         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5343         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5344         uint64_t reserved_20_27        : 8;
5345         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5346         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5347         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5348         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5349         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5350         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5351         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5352         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5353         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5354         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5355         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5356         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5357         uint64_t reserved_40_63        : 24;
5358 #endif /* Word 0 - End */
5359     } s;
5360     struct bdk_bgxx_cmr_mem_int_ena_w1c_cn81xx
5361     {
5362 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5363         uint64_t reserved_36_63        : 28;
5364         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5365         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5366         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5367         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5368         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5369         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5370         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5371         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5372         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5373         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5374         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
5375         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
5376         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
5377         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
5378         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
5379         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
5380         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5381         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5382         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
5383         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
5384         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 15: 15](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
5385         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
5386         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
5387         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
5388         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
5389         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
5390         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
5391         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
5392         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5393         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5394         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5395         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5396         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5397         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5398         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5399         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5400 #else /* Word 0 - Little Endian */
5401         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5402         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5403         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5404         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5405         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5406         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5407         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5408         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5409         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
5410         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
5411         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
5412         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
5413         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
5414         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
5415         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
5416         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 15: 15](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
5417         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
5418         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
5419         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5420         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5421         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
5422         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
5423         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
5424         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
5425         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
5426         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
5427         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5428         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5429         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5430         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5431         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5432         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5433         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5434         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5435         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5436         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5437         uint64_t reserved_36_63        : 28;
5438 #endif /* Word 0 - End */
5439     } cn81xx;
5440     struct bdk_bgxx_cmr_mem_int_ena_w1c_cn88xx
5441     {
5442 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5443         uint64_t reserved_26_63        : 38;
5444         uint64_t txb_ncsi_sbe          : 1;  /**< [ 25: 25](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5445         uint64_t txb_ncsi_dbe          : 1;  /**< [ 24: 24](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5446         uint64_t txb_skid_m3_sbe       : 1;  /**< [ 23: 23](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_SBE]. */
5447         uint64_t txb_skid_m3_dbe       : 1;  /**< [ 22: 22](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_DBE]. */
5448         uint64_t txb_skid_m2_sbe       : 1;  /**< [ 21: 21](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_SBE]. */
5449         uint64_t txb_skid_m2_dbe       : 1;  /**< [ 20: 20](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_DBE]. */
5450         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5451         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5452         uint64_t smu_in_overfl         : 1;  /**< [ 17: 17](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5453         uint64_t gmp_in_overfl         : 1;  /**< [ 16: 16](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5454         uint64_t txb_skid_m0_sbe       : 1;  /**< [ 15: 15](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_SBE]. */
5455         uint64_t txb_skid_m0_dbe       : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_DBE]. */
5456         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
5457         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
5458         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
5459         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
5460         uint64_t rxb_skid_sbe          : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_SKID_SBE]. */
5461         uint64_t rxb_skid_dbe          : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_SKID_DBE]. */
5462         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5463         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5464         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5465         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5466         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5467         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5468         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5469         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5470 #else /* Word 0 - Little Endian */
5471         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5472         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5473         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5474         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5475         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5476         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5477         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5478         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5479         uint64_t rxb_skid_dbe          : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_SKID_DBE]. */
5480         uint64_t rxb_skid_sbe          : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[RXB_SKID_SBE]. */
5481         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
5482         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
5483         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
5484         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
5485         uint64_t txb_skid_m0_dbe       : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_DBE]. */
5486         uint64_t txb_skid_m0_sbe       : 1;  /**< [ 15: 15](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_SBE]. */
5487         uint64_t gmp_in_overfl         : 1;  /**< [ 16: 16](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5488         uint64_t smu_in_overfl         : 1;  /**< [ 17: 17](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5489         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5490         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5491         uint64_t txb_skid_m2_dbe       : 1;  /**< [ 20: 20](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_DBE]. */
5492         uint64_t txb_skid_m2_sbe       : 1;  /**< [ 21: 21](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_SBE]. */
5493         uint64_t txb_skid_m3_dbe       : 1;  /**< [ 22: 22](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_DBE]. */
5494         uint64_t txb_skid_m3_sbe       : 1;  /**< [ 23: 23](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_SBE]. */
5495         uint64_t txb_ncsi_dbe          : 1;  /**< [ 24: 24](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5496         uint64_t txb_ncsi_sbe          : 1;  /**< [ 25: 25](R/W1C/H) Reads or clears enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5497         uint64_t reserved_26_63        : 38;
5498 #endif /* Word 0 - End */
5499     } cn88xx;
5500     struct bdk_bgxx_cmr_mem_int_ena_w1c_cn83xx
5501     {
5502 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5503         uint64_t reserved_40_63        : 24;
5504         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5505         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5506         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5507         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5508         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5509         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5510         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5511         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5512         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5513         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5514         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5515         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5516         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5517         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5518         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
5519         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
5520         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
5521         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
5522         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
5523         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
5524         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5525         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5526         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
5527         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
5528         uint64_t txb_fif_m1_sbe        : 1;  /**< [ 15: 15](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_SBE]. */
5529         uint64_t txb_fif_m1_dbe        : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_DBE]. */
5530         uint64_t txb_fif_m0_sbe        : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_SBE]. */
5531         uint64_t txb_fif_m0_dbe        : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_DBE]. */
5532         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
5533         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
5534         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
5535         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
5536         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5537         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5538         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5539         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5540         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5541         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5542         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5543         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5544 #else /* Word 0 - Little Endian */
5545         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5546         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5547         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5548         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5549         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5550         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5551         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5552         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5553         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
5554         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
5555         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
5556         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
5557         uint64_t txb_fif_m0_dbe        : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_DBE]. */
5558         uint64_t txb_fif_m0_sbe        : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_SBE]. */
5559         uint64_t txb_fif_m1_dbe        : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_DBE]. */
5560         uint64_t txb_fif_m1_sbe        : 1;  /**< [ 15: 15](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_SBE]. */
5561         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
5562         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
5563         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5564         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5565         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
5566         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
5567         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
5568         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
5569         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
5570         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
5571         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5572         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5573         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5574         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5575         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5576         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5577         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5578         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5579         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5580         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5581         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5582         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5583         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5584         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1C/H) Reads or clears enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5585         uint64_t reserved_40_63        : 24;
5586 #endif /* Word 0 - End */
5587     } cn83xx;
5588 };
5589 typedef union bdk_bgxx_cmr_mem_int_ena_w1c bdk_bgxx_cmr_mem_int_ena_w1c_t;
5590 
5591 static inline uint64_t BDK_BGXX_CMR_MEM_INT_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_MEM_INT_ENA_W1C(unsigned long a)5592 static inline uint64_t BDK_BGXX_CMR_MEM_INT_ENA_W1C(unsigned long a)
5593 {
5594     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5595         return 0x87e0e0000020ll + 0x1000000ll * ((a) & 0x1);
5596     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
5597         return 0x87e0e0000020ll + 0x1000000ll * ((a) & 0x3);
5598     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
5599         return 0x87e0e0000020ll + 0x1000000ll * ((a) & 0x1);
5600     __bdk_csr_fatal("BGXX_CMR_MEM_INT_ENA_W1C", 1, a, 0, 0, 0);
5601 }
5602 
5603 #define typedef_BDK_BGXX_CMR_MEM_INT_ENA_W1C(a) bdk_bgxx_cmr_mem_int_ena_w1c_t
5604 #define bustype_BDK_BGXX_CMR_MEM_INT_ENA_W1C(a) BDK_CSR_TYPE_RSL
5605 #define basename_BDK_BGXX_CMR_MEM_INT_ENA_W1C(a) "BGXX_CMR_MEM_INT_ENA_W1C"
5606 #define device_bar_BDK_BGXX_CMR_MEM_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
5607 #define busnum_BDK_BGXX_CMR_MEM_INT_ENA_W1C(a) (a)
5608 #define arguments_BDK_BGXX_CMR_MEM_INT_ENA_W1C(a) (a),-1,-1,-1
5609 
5610 /**
5611  * Register (RSL) bgx#_cmr_mem_int_ena_w1s
5612  *
5613  * BGX CMR Memory Interrupt Enable Set Register
5614  * This register sets interrupt enable bits.
5615  */
5616 union bdk_bgxx_cmr_mem_int_ena_w1s
5617 {
5618     uint64_t u;
5619     struct bdk_bgxx_cmr_mem_int_ena_w1s_s
5620     {
5621 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5622         uint64_t reserved_40_63        : 24;
5623         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5624         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5625         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5626         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5627         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5628         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5629         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5630         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5631         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5632         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5633         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5634         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5635         uint64_t reserved_20_27        : 8;
5636         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5637         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5638         uint64_t reserved_8_17         : 10;
5639         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5640         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5641         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5642         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5643         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5644         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5645         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5646         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5647 #else /* Word 0 - Little Endian */
5648         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5649         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5650         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5651         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5652         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5653         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5654         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5655         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5656         uint64_t reserved_8_17         : 10;
5657         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5658         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5659         uint64_t reserved_20_27        : 8;
5660         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5661         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5662         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5663         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5664         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5665         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5666         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5667         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5668         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5669         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5670         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5671         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5672         uint64_t reserved_40_63        : 24;
5673 #endif /* Word 0 - End */
5674     } s;
5675     struct bdk_bgxx_cmr_mem_int_ena_w1s_cn81xx
5676     {
5677 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5678         uint64_t reserved_36_63        : 28;
5679         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5680         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5681         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5682         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5683         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5684         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5685         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5686         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5687         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5688         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5689         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
5690         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
5691         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
5692         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
5693         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
5694         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
5695         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5696         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5697         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
5698         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
5699         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
5700         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
5701         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
5702         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
5703         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
5704         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
5705         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
5706         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
5707         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5708         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5709         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5710         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5711         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5712         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5713         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5714         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5715 #else /* Word 0 - Little Endian */
5716         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5717         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5718         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5719         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5720         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5721         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5722         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5723         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5724         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
5725         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
5726         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
5727         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
5728         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
5729         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
5730         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
5731         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
5732         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
5733         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
5734         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5735         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5736         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
5737         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
5738         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
5739         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
5740         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
5741         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
5742         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5743         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5744         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5745         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5746         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5747         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5748         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5749         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5750         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5751         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5752         uint64_t reserved_36_63        : 28;
5753 #endif /* Word 0 - End */
5754     } cn81xx;
5755     struct bdk_bgxx_cmr_mem_int_ena_w1s_cn88xx
5756     {
5757 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5758         uint64_t reserved_26_63        : 38;
5759         uint64_t txb_ncsi_sbe          : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5760         uint64_t txb_ncsi_dbe          : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5761         uint64_t txb_skid_m3_sbe       : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_SBE]. */
5762         uint64_t txb_skid_m3_dbe       : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_DBE]. */
5763         uint64_t txb_skid_m2_sbe       : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_SBE]. */
5764         uint64_t txb_skid_m2_dbe       : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_DBE]. */
5765         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5766         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5767         uint64_t smu_in_overfl         : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5768         uint64_t gmp_in_overfl         : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5769         uint64_t txb_skid_m0_sbe       : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_SBE]. */
5770         uint64_t txb_skid_m0_dbe       : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_DBE]. */
5771         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
5772         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
5773         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
5774         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
5775         uint64_t rxb_skid_sbe          : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_SKID_SBE]. */
5776         uint64_t rxb_skid_dbe          : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_SKID_DBE]. */
5777         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5778         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5779         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5780         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5781         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5782         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5783         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5784         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5785 #else /* Word 0 - Little Endian */
5786         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5787         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5788         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5789         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5790         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5791         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5792         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5793         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5794         uint64_t rxb_skid_dbe          : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_SKID_DBE]. */
5795         uint64_t rxb_skid_sbe          : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[RXB_SKID_SBE]. */
5796         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
5797         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
5798         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
5799         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
5800         uint64_t txb_skid_m0_dbe       : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_DBE]. */
5801         uint64_t txb_skid_m0_sbe       : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_SBE]. */
5802         uint64_t gmp_in_overfl         : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5803         uint64_t smu_in_overfl         : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5804         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5805         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5806         uint64_t txb_skid_m2_dbe       : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_DBE]. */
5807         uint64_t txb_skid_m2_sbe       : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_SBE]. */
5808         uint64_t txb_skid_m3_dbe       : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_DBE]. */
5809         uint64_t txb_skid_m3_sbe       : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_SBE]. */
5810         uint64_t txb_ncsi_dbe          : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5811         uint64_t txb_ncsi_sbe          : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets enable for BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5812         uint64_t reserved_26_63        : 38;
5813 #endif /* Word 0 - End */
5814     } cn88xx;
5815     struct bdk_bgxx_cmr_mem_int_ena_w1s_cn83xx
5816     {
5817 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5818         uint64_t reserved_40_63        : 24;
5819         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5820         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5821         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5822         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5823         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5824         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5825         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5826         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5827         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5828         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5829         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5830         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5831         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5832         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5833         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
5834         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
5835         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
5836         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
5837         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
5838         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
5839         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5840         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5841         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
5842         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
5843         uint64_t txb_fif_m1_sbe        : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_SBE]. */
5844         uint64_t txb_fif_m1_dbe        : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_DBE]. */
5845         uint64_t txb_fif_m0_sbe        : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_SBE]. */
5846         uint64_t txb_fif_m0_dbe        : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_DBE]. */
5847         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
5848         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
5849         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
5850         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
5851         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5852         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5853         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5854         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5855         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5856         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5857         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5858         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5859 #else /* Word 0 - Little Endian */
5860         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5861         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5862         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5863         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5864         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5865         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5866         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5867         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5868         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
5869         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
5870         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
5871         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
5872         uint64_t txb_fif_m0_dbe        : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_DBE]. */
5873         uint64_t txb_fif_m0_sbe        : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_SBE]. */
5874         uint64_t txb_fif_m1_dbe        : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_DBE]. */
5875         uint64_t txb_fif_m1_sbe        : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_SBE]. */
5876         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
5877         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
5878         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[GMP_IN_OVERFL]. */
5879         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[SMU_IN_OVERFL]. */
5880         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
5881         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
5882         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
5883         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
5884         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
5885         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
5886         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_NCSI_DBE]. */
5887         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_NCSI_SBE]. */
5888         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5889         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5890         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5891         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5892         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5893         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5894         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5895         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5896         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5897         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5898         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5899         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1S/H) Reads or sets enable for BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5900         uint64_t reserved_40_63        : 24;
5901 #endif /* Word 0 - End */
5902     } cn83xx;
5903 };
5904 typedef union bdk_bgxx_cmr_mem_int_ena_w1s bdk_bgxx_cmr_mem_int_ena_w1s_t;
5905 
5906 static inline uint64_t BDK_BGXX_CMR_MEM_INT_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_MEM_INT_ENA_W1S(unsigned long a)5907 static inline uint64_t BDK_BGXX_CMR_MEM_INT_ENA_W1S(unsigned long a)
5908 {
5909     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
5910         return 0x87e0e0000028ll + 0x1000000ll * ((a) & 0x1);
5911     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
5912         return 0x87e0e0000028ll + 0x1000000ll * ((a) & 0x3);
5913     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
5914         return 0x87e0e0000028ll + 0x1000000ll * ((a) & 0x1);
5915     __bdk_csr_fatal("BGXX_CMR_MEM_INT_ENA_W1S", 1, a, 0, 0, 0);
5916 }
5917 
5918 #define typedef_BDK_BGXX_CMR_MEM_INT_ENA_W1S(a) bdk_bgxx_cmr_mem_int_ena_w1s_t
5919 #define bustype_BDK_BGXX_CMR_MEM_INT_ENA_W1S(a) BDK_CSR_TYPE_RSL
5920 #define basename_BDK_BGXX_CMR_MEM_INT_ENA_W1S(a) "BGXX_CMR_MEM_INT_ENA_W1S"
5921 #define device_bar_BDK_BGXX_CMR_MEM_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
5922 #define busnum_BDK_BGXX_CMR_MEM_INT_ENA_W1S(a) (a)
5923 #define arguments_BDK_BGXX_CMR_MEM_INT_ENA_W1S(a) (a),-1,-1,-1
5924 
5925 /**
5926  * Register (RSL) bgx#_cmr_mem_int_w1s
5927  *
5928  * BGX CMR Memory Interrupt Set Register
5929  * This register sets interrupt bits.
5930  */
5931 union bdk_bgxx_cmr_mem_int_w1s
5932 {
5933     uint64_t u;
5934     struct bdk_bgxx_cmr_mem_int_w1s_s
5935     {
5936 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5937         uint64_t reserved_40_63        : 24;
5938         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5939         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5940         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5941         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5942         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5943         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5944         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5945         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5946         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5947         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5948         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5949         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5950         uint64_t reserved_20_27        : 8;
5951         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5952         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5953         uint64_t reserved_8_17         : 10;
5954         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5955         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5956         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5957         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5958         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5959         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5960         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5961         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5962 #else /* Word 0 - Little Endian */
5963         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
5964         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
5965         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
5966         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
5967         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
5968         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
5969         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
5970         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
5971         uint64_t reserved_8_17         : 10;
5972         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
5973         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
5974         uint64_t reserved_20_27        : 8;
5975         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
5976         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
5977         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
5978         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5979         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5980         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5981         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5982         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5983         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
5984         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
5985         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
5986         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
5987         uint64_t reserved_40_63        : 24;
5988 #endif /* Word 0 - End */
5989     } s;
5990     struct bdk_bgxx_cmr_mem_int_w1s_cn81xx
5991     {
5992 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5993         uint64_t reserved_36_63        : 28;
5994         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
5995         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
5996         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
5997         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
5998         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
5999         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
6000         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
6001         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
6002         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
6003         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
6004         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
6005         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
6006         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
6007         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
6008         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
6009         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
6010         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
6011         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
6012         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
6013         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
6014         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
6015         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
6016         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
6017         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
6018         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
6019         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
6020         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
6021         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
6022         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
6023         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
6024         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
6025         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
6026         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
6027         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
6028         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
6029         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
6030 #else /* Word 0 - Little Endian */
6031         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
6032         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
6033         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
6034         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
6035         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
6036         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
6037         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
6038         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
6039         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
6040         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
6041         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
6042         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
6043         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
6044         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
6045         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
6046         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
6047         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
6048         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
6049         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
6050         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
6051         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
6052         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
6053         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
6054         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
6055         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
6056         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
6057         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
6058         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
6059         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
6060         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
6061         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
6062         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
6063         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
6064         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
6065         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
6066         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
6067         uint64_t reserved_36_63        : 28;
6068 #endif /* Word 0 - End */
6069     } cn81xx;
6070     struct bdk_bgxx_cmr_mem_int_w1s_cn88xx
6071     {
6072 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6073         uint64_t reserved_26_63        : 38;
6074         uint64_t txb_ncsi_sbe          : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
6075         uint64_t txb_ncsi_dbe          : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
6076         uint64_t txb_skid_m3_sbe       : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_SBE]. */
6077         uint64_t txb_skid_m3_dbe       : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_DBE]. */
6078         uint64_t txb_skid_m2_sbe       : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_SBE]. */
6079         uint64_t txb_skid_m2_dbe       : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_DBE]. */
6080         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
6081         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
6082         uint64_t smu_in_overfl         : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
6083         uint64_t gmp_in_overfl         : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
6084         uint64_t txb_skid_m0_sbe       : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_SBE]. */
6085         uint64_t txb_skid_m0_dbe       : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_DBE]. */
6086         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
6087         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
6088         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
6089         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
6090         uint64_t rxb_skid_sbe          : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_SKID_SBE]. */
6091         uint64_t rxb_skid_dbe          : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_SKID_DBE]. */
6092         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
6093         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
6094         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
6095         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
6096         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
6097         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
6098         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
6099         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
6100 #else /* Word 0 - Little Endian */
6101         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
6102         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
6103         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
6104         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
6105         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
6106         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
6107         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
6108         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
6109         uint64_t rxb_skid_dbe          : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_SKID_DBE]. */
6110         uint64_t rxb_skid_sbe          : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[RXB_SKID_SBE]. */
6111         uint64_t txb_fif_bk0_dbe       : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_DBE]. */
6112         uint64_t txb_fif_bk0_sbe       : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK0_SBE]. */
6113         uint64_t txb_fif_bk1_dbe       : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_DBE]. */
6114         uint64_t txb_fif_bk1_sbe       : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_FIF_BK1_SBE]. */
6115         uint64_t txb_skid_m0_dbe       : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_DBE]. */
6116         uint64_t txb_skid_m0_sbe       : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M0_SBE]. */
6117         uint64_t gmp_in_overfl         : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[GMP_IN_OVERFL]. */
6118         uint64_t smu_in_overfl         : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[SMU_IN_OVERFL]. */
6119         uint64_t txb_skid_m1_dbe       : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_DBE]. */
6120         uint64_t txb_skid_m1_sbe       : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M1_SBE]. */
6121         uint64_t txb_skid_m2_dbe       : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_DBE]. */
6122         uint64_t txb_skid_m2_sbe       : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M2_SBE]. */
6123         uint64_t txb_skid_m3_dbe       : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_DBE]. */
6124         uint64_t txb_skid_m3_sbe       : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_SKID_M3_SBE]. */
6125         uint64_t txb_ncsi_dbe          : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_NCSI_DBE]. */
6126         uint64_t txb_ncsi_sbe          : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets BGX(0..1)_CMR_MEM_INT[TXB_NCSI_SBE]. */
6127         uint64_t reserved_26_63        : 38;
6128 #endif /* Word 0 - End */
6129     } cn88xx;
6130     struct bdk_bgxx_cmr_mem_int_w1s_cn83xx
6131     {
6132 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6133         uint64_t reserved_40_63        : 24;
6134         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
6135         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
6136         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
6137         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
6138         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
6139         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
6140         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
6141         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
6142         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
6143         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
6144         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
6145         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
6146         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_NCSI_SBE]. */
6147         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_NCSI_DBE]. */
6148         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
6149         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
6150         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
6151         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
6152         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
6153         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
6154         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[SMU_IN_OVERFL]. */
6155         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[GMP_IN_OVERFL]. */
6156         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
6157         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
6158         uint64_t txb_fif_m1_sbe        : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_SBE]. */
6159         uint64_t txb_fif_m1_dbe        : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_DBE]. */
6160         uint64_t txb_fif_m0_sbe        : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_SBE]. */
6161         uint64_t txb_fif_m0_dbe        : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_DBE]. */
6162         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
6163         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
6164         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
6165         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
6166         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
6167         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
6168         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
6169         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
6170         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
6171         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
6172         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
6173         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
6174 #else /* Word 0 - Little Endian */
6175         uint64_t rxb_fif_bk0_dbe0      : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE0]. */
6176         uint64_t rxb_fif_bk0_sbe0      : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE0]. */
6177         uint64_t rxb_fif_bk0_dbe1      : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_DBE1]. */
6178         uint64_t rxb_fif_bk0_sbe1      : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK0_SBE1]. */
6179         uint64_t rxb_fif_bk1_dbe0      : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE0]. */
6180         uint64_t rxb_fif_bk1_sbe0      : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE0]. */
6181         uint64_t rxb_fif_bk1_dbe1      : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_DBE1]. */
6182         uint64_t rxb_fif_bk1_sbe1      : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_FIF_BK1_SBE1]. */
6183         uint64_t rxb_pki_skid_dbe      : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_DBE]. */
6184         uint64_t rxb_pki_skid_sbe      : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_PKI_SKID_SBE]. */
6185         uint64_t rxb_nic_skid_dbe      : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_DBE]. */
6186         uint64_t rxb_nic_skid_sbe      : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[RXB_NIC_SKID_SBE]. */
6187         uint64_t txb_fif_m0_dbe        : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_DBE]. */
6188         uint64_t txb_fif_m0_sbe        : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M0_SBE]. */
6189         uint64_t txb_fif_m1_dbe        : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_DBE]. */
6190         uint64_t txb_fif_m1_sbe        : 1;  /**< [ 15: 15](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M1_SBE]. */
6191         uint64_t txb_skid_m0_pko_dbe   : 1;  /**< [ 16: 16](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_DBE]. */
6192         uint64_t txb_skid_m0_pko_sbe   : 1;  /**< [ 17: 17](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_PKO_SBE]. */
6193         uint64_t gmp_in_overfl         : 1;  /**< [ 18: 18](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[GMP_IN_OVERFL]. */
6194         uint64_t smu_in_overfl         : 1;  /**< [ 19: 19](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[SMU_IN_OVERFL]. */
6195         uint64_t txb_skid_m1_pko_dbe   : 1;  /**< [ 20: 20](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_DBE]. */
6196         uint64_t txb_skid_m1_pko_sbe   : 1;  /**< [ 21: 21](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_PKO_SBE]. */
6197         uint64_t txb_skid_m2_pko_dbe   : 1;  /**< [ 22: 22](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_DBE]. */
6198         uint64_t txb_skid_m2_pko_sbe   : 1;  /**< [ 23: 23](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_PKO_SBE]. */
6199         uint64_t txb_skid_m3_pko_dbe   : 1;  /**< [ 24: 24](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_DBE]. */
6200         uint64_t txb_skid_m3_pko_sbe   : 1;  /**< [ 25: 25](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_PKO_SBE]. */
6201         uint64_t txb_ncsi_dbe          : 1;  /**< [ 26: 26](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_NCSI_DBE]. */
6202         uint64_t txb_ncsi_sbe          : 1;  /**< [ 27: 27](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_NCSI_SBE]. */
6203         uint64_t txb_skid_m0_nic_dbe   : 1;  /**< [ 28: 28](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_DBE]. */
6204         uint64_t txb_skid_m0_nic_sbe   : 1;  /**< [ 29: 29](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M0_NIC_SBE]. */
6205         uint64_t txb_skid_m1_nic_dbe   : 1;  /**< [ 30: 30](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_DBE]. */
6206         uint64_t txb_skid_m1_nic_sbe   : 1;  /**< [ 31: 31](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M1_NIC_SBE]. */
6207         uint64_t txb_skid_m2_nic_dbe   : 1;  /**< [ 32: 32](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_DBE]. */
6208         uint64_t txb_skid_m2_nic_sbe   : 1;  /**< [ 33: 33](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M2_NIC_SBE]. */
6209         uint64_t txb_skid_m3_nic_dbe   : 1;  /**< [ 34: 34](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_DBE]. */
6210         uint64_t txb_skid_m3_nic_sbe   : 1;  /**< [ 35: 35](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_SKID_M3_NIC_SBE]. */
6211         uint64_t txb_fif_m2_dbe        : 1;  /**< [ 36: 36](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_DBE]. */
6212         uint64_t txb_fif_m2_sbe        : 1;  /**< [ 37: 37](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M2_SBE]. */
6213         uint64_t txb_fif_m3_dbe        : 1;  /**< [ 38: 38](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_DBE]. */
6214         uint64_t txb_fif_m3_sbe        : 1;  /**< [ 39: 39](R/W1S/H) Reads or sets BGX(0..3)_CMR_MEM_INT[TXB_FIF_M3_SBE]. */
6215         uint64_t reserved_40_63        : 24;
6216 #endif /* Word 0 - End */
6217     } cn83xx;
6218 };
6219 typedef union bdk_bgxx_cmr_mem_int_w1s bdk_bgxx_cmr_mem_int_w1s_t;
6220 
6221 static inline uint64_t BDK_BGXX_CMR_MEM_INT_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_MEM_INT_W1S(unsigned long a)6222 static inline uint64_t BDK_BGXX_CMR_MEM_INT_W1S(unsigned long a)
6223 {
6224     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6225         return 0x87e0e0000018ll + 0x1000000ll * ((a) & 0x1);
6226     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
6227         return 0x87e0e0000018ll + 0x1000000ll * ((a) & 0x3);
6228     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6229         return 0x87e0e0000018ll + 0x1000000ll * ((a) & 0x1);
6230     __bdk_csr_fatal("BGXX_CMR_MEM_INT_W1S", 1, a, 0, 0, 0);
6231 }
6232 
6233 #define typedef_BDK_BGXX_CMR_MEM_INT_W1S(a) bdk_bgxx_cmr_mem_int_w1s_t
6234 #define bustype_BDK_BGXX_CMR_MEM_INT_W1S(a) BDK_CSR_TYPE_RSL
6235 #define basename_BDK_BGXX_CMR_MEM_INT_W1S(a) "BGXX_CMR_MEM_INT_W1S"
6236 #define device_bar_BDK_BGXX_CMR_MEM_INT_W1S(a) 0x0 /* PF_BAR0 */
6237 #define busnum_BDK_BGXX_CMR_MEM_INT_W1S(a) (a)
6238 #define arguments_BDK_BGXX_CMR_MEM_INT_W1S(a) (a),-1,-1,-1
6239 
6240 /**
6241  * Register (RSL) bgx#_cmr_nic_nxc_adr
6242  *
6243  * BGX CMR NIC NXC Exception Registers
6244  */
6245 union bdk_bgxx_cmr_nic_nxc_adr
6246 {
6247     uint64_t u;
6248     struct bdk_bgxx_cmr_nic_nxc_adr_s
6249     {
6250 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6251         uint64_t reserved_16_63        : 48;
6252         uint64_t lmac_id               : 4;  /**< [ 15: 12](RO/H) Logged LMAC ID associated with NXC exceptions associated with NIC. */
6253         uint64_t channel               : 12; /**< [ 11:  0](RO/H) Logged channel for NXC exceptions associated with NIC. */
6254 #else /* Word 0 - Little Endian */
6255         uint64_t channel               : 12; /**< [ 11:  0](RO/H) Logged channel for NXC exceptions associated with NIC. */
6256         uint64_t lmac_id               : 4;  /**< [ 15: 12](RO/H) Logged LMAC ID associated with NXC exceptions associated with NIC. */
6257         uint64_t reserved_16_63        : 48;
6258 #endif /* Word 0 - End */
6259     } s;
6260     /* struct bdk_bgxx_cmr_nic_nxc_adr_s cn; */
6261 };
6262 typedef union bdk_bgxx_cmr_nic_nxc_adr bdk_bgxx_cmr_nic_nxc_adr_t;
6263 
6264 static inline uint64_t BDK_BGXX_CMR_NIC_NXC_ADR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_NIC_NXC_ADR(unsigned long a)6265 static inline uint64_t BDK_BGXX_CMR_NIC_NXC_ADR(unsigned long a)
6266 {
6267     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6268         return 0x87e0e0001030ll + 0x1000000ll * ((a) & 0x1);
6269     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
6270         return 0x87e0e0001030ll + 0x1000000ll * ((a) & 0x3);
6271     __bdk_csr_fatal("BGXX_CMR_NIC_NXC_ADR", 1, a, 0, 0, 0);
6272 }
6273 
6274 #define typedef_BDK_BGXX_CMR_NIC_NXC_ADR(a) bdk_bgxx_cmr_nic_nxc_adr_t
6275 #define bustype_BDK_BGXX_CMR_NIC_NXC_ADR(a) BDK_CSR_TYPE_RSL
6276 #define basename_BDK_BGXX_CMR_NIC_NXC_ADR(a) "BGXX_CMR_NIC_NXC_ADR"
6277 #define device_bar_BDK_BGXX_CMR_NIC_NXC_ADR(a) 0x0 /* PF_BAR0 */
6278 #define busnum_BDK_BGXX_CMR_NIC_NXC_ADR(a) (a)
6279 #define arguments_BDK_BGXX_CMR_NIC_NXC_ADR(a) (a),-1,-1,-1
6280 
6281 /**
6282  * Register (RSL) bgx#_cmr_nxc_adr
6283  *
6284  * BGX CMR NCX Exception Registers
6285  */
6286 union bdk_bgxx_cmr_nxc_adr
6287 {
6288     uint64_t u;
6289     struct bdk_bgxx_cmr_nxc_adr_s
6290     {
6291 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6292         uint64_t reserved_16_63        : 48;
6293         uint64_t lmac_id               : 4;  /**< [ 15: 12](RO/H) Logged LMAC ID associated with NXC exceptions. */
6294         uint64_t channel               : 12; /**< [ 11:  0](RO/H) Logged channel for NXC exceptions. */
6295 #else /* Word 0 - Little Endian */
6296         uint64_t channel               : 12; /**< [ 11:  0](RO/H) Logged channel for NXC exceptions. */
6297         uint64_t lmac_id               : 4;  /**< [ 15: 12](RO/H) Logged LMAC ID associated with NXC exceptions. */
6298         uint64_t reserved_16_63        : 48;
6299 #endif /* Word 0 - End */
6300     } s;
6301     /* struct bdk_bgxx_cmr_nxc_adr_s cn; */
6302 };
6303 typedef union bdk_bgxx_cmr_nxc_adr bdk_bgxx_cmr_nxc_adr_t;
6304 
6305 static inline uint64_t BDK_BGXX_CMR_NXC_ADR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_NXC_ADR(unsigned long a)6306 static inline uint64_t BDK_BGXX_CMR_NXC_ADR(unsigned long a)
6307 {
6308     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6309         return 0x87e0e0001018ll + 0x1000000ll * ((a) & 0x1);
6310     __bdk_csr_fatal("BGXX_CMR_NXC_ADR", 1, a, 0, 0, 0);
6311 }
6312 
6313 #define typedef_BDK_BGXX_CMR_NXC_ADR(a) bdk_bgxx_cmr_nxc_adr_t
6314 #define bustype_BDK_BGXX_CMR_NXC_ADR(a) BDK_CSR_TYPE_RSL
6315 #define basename_BDK_BGXX_CMR_NXC_ADR(a) "BGXX_CMR_NXC_ADR"
6316 #define device_bar_BDK_BGXX_CMR_NXC_ADR(a) 0x0 /* PF_BAR0 */
6317 #define busnum_BDK_BGXX_CMR_NXC_ADR(a) (a)
6318 #define arguments_BDK_BGXX_CMR_NXC_ADR(a) (a),-1,-1,-1
6319 
6320 /**
6321  * Register (RSL) bgx#_cmr_pko_nxc_adr
6322  *
6323  * BGX CMR PKO NXC Exception Registers
6324  */
6325 union bdk_bgxx_cmr_pko_nxc_adr
6326 {
6327     uint64_t u;
6328     struct bdk_bgxx_cmr_pko_nxc_adr_s
6329     {
6330 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6331         uint64_t reserved_16_63        : 48;
6332         uint64_t lmac_id               : 4;  /**< [ 15: 12](RO/H) Logged LMAC ID associated with NXC exceptions associated with PKO. */
6333         uint64_t channel               : 12; /**< [ 11:  0](RO/H) Logged channel for NXC exceptions associated with PKO. */
6334 #else /* Word 0 - Little Endian */
6335         uint64_t channel               : 12; /**< [ 11:  0](RO/H) Logged channel for NXC exceptions associated with PKO. */
6336         uint64_t lmac_id               : 4;  /**< [ 15: 12](RO/H) Logged LMAC ID associated with NXC exceptions associated with PKO. */
6337         uint64_t reserved_16_63        : 48;
6338 #endif /* Word 0 - End */
6339     } s;
6340     /* struct bdk_bgxx_cmr_pko_nxc_adr_s cn; */
6341 };
6342 typedef union bdk_bgxx_cmr_pko_nxc_adr bdk_bgxx_cmr_pko_nxc_adr_t;
6343 
6344 static inline uint64_t BDK_BGXX_CMR_PKO_NXC_ADR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_PKO_NXC_ADR(unsigned long a)6345 static inline uint64_t BDK_BGXX_CMR_PKO_NXC_ADR(unsigned long a)
6346 {
6347     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6348         return 0x87e0e0001018ll + 0x1000000ll * ((a) & 0x1);
6349     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
6350         return 0x87e0e0001018ll + 0x1000000ll * ((a) & 0x3);
6351     __bdk_csr_fatal("BGXX_CMR_PKO_NXC_ADR", 1, a, 0, 0, 0);
6352 }
6353 
6354 #define typedef_BDK_BGXX_CMR_PKO_NXC_ADR(a) bdk_bgxx_cmr_pko_nxc_adr_t
6355 #define bustype_BDK_BGXX_CMR_PKO_NXC_ADR(a) BDK_CSR_TYPE_RSL
6356 #define basename_BDK_BGXX_CMR_PKO_NXC_ADR(a) "BGXX_CMR_PKO_NXC_ADR"
6357 #define device_bar_BDK_BGXX_CMR_PKO_NXC_ADR(a) 0x0 /* PF_BAR0 */
6358 #define busnum_BDK_BGXX_CMR_PKO_NXC_ADR(a) (a)
6359 #define arguments_BDK_BGXX_CMR_PKO_NXC_ADR(a) (a),-1,-1,-1
6360 
6361 /**
6362  * Register (RSL) bgx#_cmr_rx_dmac#_cam
6363  *
6364  * BGX CMR Receive CAM Registers
6365  * These registers provide access to the 32 DMAC CAM entries in BGX.
6366  */
6367 union bdk_bgxx_cmr_rx_dmacx_cam
6368 {
6369     uint64_t u;
6370     struct bdk_bgxx_cmr_rx_dmacx_cam_s
6371     {
6372 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6373         uint64_t reserved_51_63        : 13;
6374         uint64_t id                    : 2;  /**< [ 50: 49](R/W) Logical MAC ID that this DMAC CAM address applies to. BGX has 32 DMAC CAM entries that can
6375                                                                  be accessed with the BGX()_CMR_RX_DMAC()_CAM CSRs. These 32 DMAC entries can be used by
6376                                                                  any of the four SGMII MACs or the 10G/40G MACs using these register bits.
6377 
6378                                                                  A typical configuration is to provide eight CAM entries per LMAC ID, which is configured
6379                                                                  using the following settings:
6380                                                                  * LMAC interface 0: BGX()_CMR_RX_DMAC(0..7)_CAM[ID] = 0x0.
6381                                                                  * LMAC interface 1: BGX()_CMR_RX_DMAC(8..15)_CAM[ID] = 0x1.
6382                                                                  * LMAC interface 2: BGX()_CMR_RX_DMAC(16..23)_CAM[ID] = 0x2.
6383                                                                  * LMAC interface 3: BGX()_CMR_RX_DMAC(24..31)_CAM[ID] = 0x3. */
6384         uint64_t en                    : 1;  /**< [ 48: 48](R/W) CAM entry enable for this DMAC address.
6385                                                                  1 = Include this address in the matching algorithm.
6386                                                                  0 = Don't include this address in the matching algorithm. */
6387         uint64_t adr                   : 48; /**< [ 47:  0](R/W) DMAC address in the CAM used for matching. Specified in network byte order, i.e.
6388                                                                  ADR\<47:40\> is for the first DMAC byte on the wire. The CAM matches against unicast or
6389                                                                  multicast DMAC addresses. All BGX()_CMR_RX_DMAC()_CAM CSRs can be used in any of the LMAC
6390                                                                  combinations such that any BGX MAC can use any of the 32 common DMAC entries. */
6391 #else /* Word 0 - Little Endian */
6392         uint64_t adr                   : 48; /**< [ 47:  0](R/W) DMAC address in the CAM used for matching. Specified in network byte order, i.e.
6393                                                                  ADR\<47:40\> is for the first DMAC byte on the wire. The CAM matches against unicast or
6394                                                                  multicast DMAC addresses. All BGX()_CMR_RX_DMAC()_CAM CSRs can be used in any of the LMAC
6395                                                                  combinations such that any BGX MAC can use any of the 32 common DMAC entries. */
6396         uint64_t en                    : 1;  /**< [ 48: 48](R/W) CAM entry enable for this DMAC address.
6397                                                                  1 = Include this address in the matching algorithm.
6398                                                                  0 = Don't include this address in the matching algorithm. */
6399         uint64_t id                    : 2;  /**< [ 50: 49](R/W) Logical MAC ID that this DMAC CAM address applies to. BGX has 32 DMAC CAM entries that can
6400                                                                  be accessed with the BGX()_CMR_RX_DMAC()_CAM CSRs. These 32 DMAC entries can be used by
6401                                                                  any of the four SGMII MACs or the 10G/40G MACs using these register bits.
6402 
6403                                                                  A typical configuration is to provide eight CAM entries per LMAC ID, which is configured
6404                                                                  using the following settings:
6405                                                                  * LMAC interface 0: BGX()_CMR_RX_DMAC(0..7)_CAM[ID] = 0x0.
6406                                                                  * LMAC interface 1: BGX()_CMR_RX_DMAC(8..15)_CAM[ID] = 0x1.
6407                                                                  * LMAC interface 2: BGX()_CMR_RX_DMAC(16..23)_CAM[ID] = 0x2.
6408                                                                  * LMAC interface 3: BGX()_CMR_RX_DMAC(24..31)_CAM[ID] = 0x3. */
6409         uint64_t reserved_51_63        : 13;
6410 #endif /* Word 0 - End */
6411     } s;
6412     /* struct bdk_bgxx_cmr_rx_dmacx_cam_s cn; */
6413 };
6414 typedef union bdk_bgxx_cmr_rx_dmacx_cam bdk_bgxx_cmr_rx_dmacx_cam_t;
6415 
6416 static inline uint64_t BDK_BGXX_CMR_RX_DMACX_CAM(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_RX_DMACX_CAM(unsigned long a,unsigned long b)6417 static inline uint64_t BDK_BGXX_CMR_RX_DMACX_CAM(unsigned long a, unsigned long b)
6418 {
6419     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=31)))
6420         return 0x87e0e0000200ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1f);
6421     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=31)))
6422         return 0x87e0e0000200ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x1f);
6423     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=31)))
6424         return 0x87e0e0000200ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1f);
6425     __bdk_csr_fatal("BGXX_CMR_RX_DMACX_CAM", 2, a, b, 0, 0);
6426 }
6427 
6428 #define typedef_BDK_BGXX_CMR_RX_DMACX_CAM(a,b) bdk_bgxx_cmr_rx_dmacx_cam_t
6429 #define bustype_BDK_BGXX_CMR_RX_DMACX_CAM(a,b) BDK_CSR_TYPE_RSL
6430 #define basename_BDK_BGXX_CMR_RX_DMACX_CAM(a,b) "BGXX_CMR_RX_DMACX_CAM"
6431 #define device_bar_BDK_BGXX_CMR_RX_DMACX_CAM(a,b) 0x0 /* PF_BAR0 */
6432 #define busnum_BDK_BGXX_CMR_RX_DMACX_CAM(a,b) (a)
6433 #define arguments_BDK_BGXX_CMR_RX_DMACX_CAM(a,b) (a),(b),-1,-1
6434 
6435 /**
6436  * Register (RSL) bgx#_cmr_rx_lmacs
6437  *
6438  * BGX CMR Receive Logical MACs Registers
6439  */
6440 union bdk_bgxx_cmr_rx_lmacs
6441 {
6442     uint64_t u;
6443     struct bdk_bgxx_cmr_rx_lmacs_s
6444     {
6445 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6446         uint64_t reserved_3_63         : 61;
6447         uint64_t lmacs                 : 3;  /**< [  2:  0](R/W) Number of LMACS. Specifies the number of LMACs that can be enabled.
6448                                                                  This determines the logical RX buffer size per LMAC and the maximum
6449                                                                  LMAC ID that can be used:
6450 
6451                                                                  0x0 = Reserved.
6452                                                                  0x1 = BGX()_CONST[TX_FIFOSZ] bytes per LMAC, maximum LMAC ID is 0.
6453                                                                  0x2 = BGX()_CONST[TX_FIFOSZ]/2 bytes per LMAC, maximum LMAC ID is 1.
6454                                                                  0x3 = BGX()_CONST[TX_FIFOSZ]/4 bytes per LMAC, maximum LMAC ID is 2.
6455                                                                  0x4 = BGX()_CONST[TX_FIFOSZ]/4 bytes per LMAC, maximum LMAC ID is 3.
6456                                                                  0x5-0x7 = Reserved.
6457 
6458                                                                  Note the maximum LMAC ID is determined by the smaller of
6459                                                                  BGX()_CMR_RX_LMACS[LMACS] and BGX()_CMR_TX_LMACS[LMACS]. The two fields
6460                                                                  should be set to the same value for normal operation. */
6461 #else /* Word 0 - Little Endian */
6462         uint64_t lmacs                 : 3;  /**< [  2:  0](R/W) Number of LMACS. Specifies the number of LMACs that can be enabled.
6463                                                                  This determines the logical RX buffer size per LMAC and the maximum
6464                                                                  LMAC ID that can be used:
6465 
6466                                                                  0x0 = Reserved.
6467                                                                  0x1 = BGX()_CONST[TX_FIFOSZ] bytes per LMAC, maximum LMAC ID is 0.
6468                                                                  0x2 = BGX()_CONST[TX_FIFOSZ]/2 bytes per LMAC, maximum LMAC ID is 1.
6469                                                                  0x3 = BGX()_CONST[TX_FIFOSZ]/4 bytes per LMAC, maximum LMAC ID is 2.
6470                                                                  0x4 = BGX()_CONST[TX_FIFOSZ]/4 bytes per LMAC, maximum LMAC ID is 3.
6471                                                                  0x5-0x7 = Reserved.
6472 
6473                                                                  Note the maximum LMAC ID is determined by the smaller of
6474                                                                  BGX()_CMR_RX_LMACS[LMACS] and BGX()_CMR_TX_LMACS[LMACS]. The two fields
6475                                                                  should be set to the same value for normal operation. */
6476         uint64_t reserved_3_63         : 61;
6477 #endif /* Word 0 - End */
6478     } s;
6479     /* struct bdk_bgxx_cmr_rx_lmacs_s cn81xx; */
6480     struct bdk_bgxx_cmr_rx_lmacs_cn88xx
6481     {
6482 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6483         uint64_t reserved_3_63         : 61;
6484         uint64_t lmacs                 : 3;  /**< [  2:  0](R/W) Number of LMACS. Specifies the number of LMACs that can be enabled.
6485                                                                  This determines the logical RX buffer size per LMAC and the maximum
6486                                                                  LMAC ID that can be used:
6487 
6488                                                                  0x0 = Reserved.
6489                                                                  0x1 = 64 KB per LMAC, maximum LMAC ID is 0.
6490                                                                  0x2 = 32 KB per LMAC, maximum LMAC ID is 1.
6491                                                                  0x3 = 16 KB per LMAC, maximum LMAC ID is 2.
6492                                                                  0x4 = 16 KB per LMAC, maximum LMAC ID is 3.
6493                                                                  0x5-0x7 = Reserved.
6494 
6495                                                                  Note the maximum LMAC ID is determined by the smaller of
6496                                                                  BGX()_CMR_RX_LMACS[LMACS] and BGX()_CMR_TX_LMACS[LMACS]. The two fields
6497                                                                  should be set to the same value for normal operation. */
6498 #else /* Word 0 - Little Endian */
6499         uint64_t lmacs                 : 3;  /**< [  2:  0](R/W) Number of LMACS. Specifies the number of LMACs that can be enabled.
6500                                                                  This determines the logical RX buffer size per LMAC and the maximum
6501                                                                  LMAC ID that can be used:
6502 
6503                                                                  0x0 = Reserved.
6504                                                                  0x1 = 64 KB per LMAC, maximum LMAC ID is 0.
6505                                                                  0x2 = 32 KB per LMAC, maximum LMAC ID is 1.
6506                                                                  0x3 = 16 KB per LMAC, maximum LMAC ID is 2.
6507                                                                  0x4 = 16 KB per LMAC, maximum LMAC ID is 3.
6508                                                                  0x5-0x7 = Reserved.
6509 
6510                                                                  Note the maximum LMAC ID is determined by the smaller of
6511                                                                  BGX()_CMR_RX_LMACS[LMACS] and BGX()_CMR_TX_LMACS[LMACS]. The two fields
6512                                                                  should be set to the same value for normal operation. */
6513         uint64_t reserved_3_63         : 61;
6514 #endif /* Word 0 - End */
6515     } cn88xx;
6516     /* struct bdk_bgxx_cmr_rx_lmacs_s cn83xx; */
6517 };
6518 typedef union bdk_bgxx_cmr_rx_lmacs bdk_bgxx_cmr_rx_lmacs_t;
6519 
6520 static inline uint64_t BDK_BGXX_CMR_RX_LMACS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_RX_LMACS(unsigned long a)6521 static inline uint64_t BDK_BGXX_CMR_RX_LMACS(unsigned long a)
6522 {
6523     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6524         return 0x87e0e0000468ll + 0x1000000ll * ((a) & 0x1);
6525     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
6526         return 0x87e0e0000468ll + 0x1000000ll * ((a) & 0x3);
6527     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6528         return 0x87e0e0000468ll + 0x1000000ll * ((a) & 0x1);
6529     __bdk_csr_fatal("BGXX_CMR_RX_LMACS", 1, a, 0, 0, 0);
6530 }
6531 
6532 #define typedef_BDK_BGXX_CMR_RX_LMACS(a) bdk_bgxx_cmr_rx_lmacs_t
6533 #define bustype_BDK_BGXX_CMR_RX_LMACS(a) BDK_CSR_TYPE_RSL
6534 #define basename_BDK_BGXX_CMR_RX_LMACS(a) "BGXX_CMR_RX_LMACS"
6535 #define device_bar_BDK_BGXX_CMR_RX_LMACS(a) 0x0 /* PF_BAR0 */
6536 #define busnum_BDK_BGXX_CMR_RX_LMACS(a) (a)
6537 #define arguments_BDK_BGXX_CMR_RX_LMACS(a) (a),-1,-1,-1
6538 
6539 /**
6540  * Register (RSL) bgx#_cmr_rx_ovr_bp
6541  *
6542  * BGX CMR Receive-Ports Backpressure Override Registers
6543  * BGX()_CMR_RX_OVR_BP[EN\<0\>] must be set to one and BGX()_CMR_RX_OVR_BP[BP\<0\>] must be
6544  * cleared to zero (to forcibly disable hardware-automatic 802.3 PAUSE packet generation) with
6545  * the HiGig2 Protocol when BGX()_SMU()_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is
6546  * indicated by BGX()_SMU()_TX_CTL[HG_EN]=1 and BGX()_SMU()_RX_UDD_SKP[LEN]=16).
6547  * Hardware can only auto-generate backpressure through HiGig2 messages (optionally, when
6548  * BGX()_SMU()_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2 protocol.
6549  */
6550 union bdk_bgxx_cmr_rx_ovr_bp
6551 {
6552     uint64_t u;
6553     struct bdk_bgxx_cmr_rx_ovr_bp_s
6554     {
6555 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6556         uint64_t reserved_12_63        : 52;
6557         uint64_t en                    : 4;  /**< [ 11:  8](R/W) Per-LMAC enable backpressure override.
6558                                                                  0 = Don't enable.
6559                                                                  1 = Enable override.
6560 
6561                                                                  Bit\<8\> represents LMAC 0, ..., bit\<11\> represents LMAC 3. */
6562         uint64_t bp                    : 4;  /**< [  7:  4](R/W) Per-LMAC backpressure status to use:
6563                                                                  0 = LMAC is available.
6564                                                                  1 = LMAC should be backpressured.
6565 
6566                                                                  Bit\<4\> represents LMAC 0, ..., bit\<7\> represents LMAC 3. */
6567         uint64_t ign_fifo_bp           : 4;  /**< [  3:  0](R/W) Ignore BGX()_CMR()_RX_BP_ON[MARK] when computing backpressure. CMR does not backpressure
6568                                                                  the
6569                                                                  MAC due to the FIFO length passing BGX()_CMR()_RX_BP_ON[MARK]. */
6570 #else /* Word 0 - Little Endian */
6571         uint64_t ign_fifo_bp           : 4;  /**< [  3:  0](R/W) Ignore BGX()_CMR()_RX_BP_ON[MARK] when computing backpressure. CMR does not backpressure
6572                                                                  the
6573                                                                  MAC due to the FIFO length passing BGX()_CMR()_RX_BP_ON[MARK]. */
6574         uint64_t bp                    : 4;  /**< [  7:  4](R/W) Per-LMAC backpressure status to use:
6575                                                                  0 = LMAC is available.
6576                                                                  1 = LMAC should be backpressured.
6577 
6578                                                                  Bit\<4\> represents LMAC 0, ..., bit\<7\> represents LMAC 3. */
6579         uint64_t en                    : 4;  /**< [ 11:  8](R/W) Per-LMAC enable backpressure override.
6580                                                                  0 = Don't enable.
6581                                                                  1 = Enable override.
6582 
6583                                                                  Bit\<8\> represents LMAC 0, ..., bit\<11\> represents LMAC 3. */
6584         uint64_t reserved_12_63        : 52;
6585 #endif /* Word 0 - End */
6586     } s;
6587     /* struct bdk_bgxx_cmr_rx_ovr_bp_s cn; */
6588 };
6589 typedef union bdk_bgxx_cmr_rx_ovr_bp bdk_bgxx_cmr_rx_ovr_bp_t;
6590 
6591 static inline uint64_t BDK_BGXX_CMR_RX_OVR_BP(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_RX_OVR_BP(unsigned long a)6592 static inline uint64_t BDK_BGXX_CMR_RX_OVR_BP(unsigned long a)
6593 {
6594     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6595         return 0x87e0e0000470ll + 0x1000000ll * ((a) & 0x1);
6596     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
6597         return 0x87e0e0000470ll + 0x1000000ll * ((a) & 0x3);
6598     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6599         return 0x87e0e0000470ll + 0x1000000ll * ((a) & 0x1);
6600     __bdk_csr_fatal("BGXX_CMR_RX_OVR_BP", 1, a, 0, 0, 0);
6601 }
6602 
6603 #define typedef_BDK_BGXX_CMR_RX_OVR_BP(a) bdk_bgxx_cmr_rx_ovr_bp_t
6604 #define bustype_BDK_BGXX_CMR_RX_OVR_BP(a) BDK_CSR_TYPE_RSL
6605 #define basename_BDK_BGXX_CMR_RX_OVR_BP(a) "BGXX_CMR_RX_OVR_BP"
6606 #define device_bar_BDK_BGXX_CMR_RX_OVR_BP(a) 0x0 /* PF_BAR0 */
6607 #define busnum_BDK_BGXX_CMR_RX_OVR_BP(a) (a)
6608 #define arguments_BDK_BGXX_CMR_RX_OVR_BP(a) (a),-1,-1,-1
6609 
6610 /**
6611  * Register (RSL) bgx#_cmr_rx_stat10
6612  *
6613  * BGX Receive Status Register 10
6614  * This register provide a count of octets of dropped at the NCSI interface.
6615  */
6616 union bdk_bgxx_cmr_rx_stat10
6617 {
6618     uint64_t u;
6619     struct bdk_bgxx_cmr_rx_stat10_s
6620     {
6621 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6622         uint64_t reserved_48_63        : 16;
6623         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of dropped NCSI packets. CNT will wrap and is cleared if the NCSI interface is
6624                                                                  reset with BGX()_CMR_GLOBAL_CONFIG[CMR_NCSI_RESET]. */
6625 #else /* Word 0 - Little Endian */
6626         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of dropped NCSI packets. CNT will wrap and is cleared if the NCSI interface is
6627                                                                  reset with BGX()_CMR_GLOBAL_CONFIG[CMR_NCSI_RESET]. */
6628         uint64_t reserved_48_63        : 16;
6629 #endif /* Word 0 - End */
6630     } s;
6631     struct bdk_bgxx_cmr_rx_stat10_cn81xx
6632     {
6633 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6634         uint64_t reserved_48_63        : 16;
6635         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of dropped NCSI packets. [CNT] will wrap and is cleared if NCSI is reset with
6636                                                                  BGX()_CMR_GLOBAL_CONFIG[CMR_NCSI_RESET]. */
6637 #else /* Word 0 - Little Endian */
6638         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Octet count of dropped NCSI packets. [CNT] will wrap and is cleared if NCSI is reset with
6639                                                                  BGX()_CMR_GLOBAL_CONFIG[CMR_NCSI_RESET]. */
6640         uint64_t reserved_48_63        : 16;
6641 #endif /* Word 0 - End */
6642     } cn81xx;
6643     /* struct bdk_bgxx_cmr_rx_stat10_s cn88xx; */
6644     /* struct bdk_bgxx_cmr_rx_stat10_cn81xx cn83xx; */
6645 };
6646 typedef union bdk_bgxx_cmr_rx_stat10 bdk_bgxx_cmr_rx_stat10_t;
6647 
6648 static inline uint64_t BDK_BGXX_CMR_RX_STAT10(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_RX_STAT10(unsigned long a)6649 static inline uint64_t BDK_BGXX_CMR_RX_STAT10(unsigned long a)
6650 {
6651     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6652         return 0x87e0e00000c0ll + 0x1000000ll * ((a) & 0x1);
6653     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
6654         return 0x87e0e00000c0ll + 0x1000000ll * ((a) & 0x3);
6655     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6656         return 0x87e0e00000c0ll + 0x1000000ll * ((a) & 0x1);
6657     __bdk_csr_fatal("BGXX_CMR_RX_STAT10", 1, a, 0, 0, 0);
6658 }
6659 
6660 #define typedef_BDK_BGXX_CMR_RX_STAT10(a) bdk_bgxx_cmr_rx_stat10_t
6661 #define bustype_BDK_BGXX_CMR_RX_STAT10(a) BDK_CSR_TYPE_RSL
6662 #define basename_BDK_BGXX_CMR_RX_STAT10(a) "BGXX_CMR_RX_STAT10"
6663 #define device_bar_BDK_BGXX_CMR_RX_STAT10(a) 0x0 /* PF_BAR0 */
6664 #define busnum_BDK_BGXX_CMR_RX_STAT10(a) (a)
6665 #define arguments_BDK_BGXX_CMR_RX_STAT10(a) (a),-1,-1,-1
6666 
6667 /**
6668  * Register (RSL) bgx#_cmr_rx_stat9
6669  *
6670  * BGX Receive Status Register 9
6671  * This registers provides a count of packets dropped at the NCSI interface.
6672  * The count of dropped NCSI packets is not accounted for in any other stats
6673  * registers.
6674  */
6675 union bdk_bgxx_cmr_rx_stat9
6676 {
6677     uint64_t u;
6678     struct bdk_bgxx_cmr_rx_stat9_s
6679     {
6680 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6681         uint64_t reserved_48_63        : 16;
6682         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of dropped packets. CNT will wrap and is cleared if the NCSI interface is reset with
6683                                                                  BGX()_CMR_GLOBAL_CONFIG[CMR_NCSI_RESET]. */
6684 #else /* Word 0 - Little Endian */
6685         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of dropped packets. CNT will wrap and is cleared if the NCSI interface is reset with
6686                                                                  BGX()_CMR_GLOBAL_CONFIG[CMR_NCSI_RESET]. */
6687         uint64_t reserved_48_63        : 16;
6688 #endif /* Word 0 - End */
6689     } s;
6690     struct bdk_bgxx_cmr_rx_stat9_cn81xx
6691     {
6692 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6693         uint64_t reserved_48_63        : 16;
6694         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of dropped packets. [CNT] will wrap and is cleared if NCSI is reset with
6695                                                                  BGX()_CMR_GLOBAL_CONFIG[CMR_NCSI_RESET]. */
6696 #else /* Word 0 - Little Endian */
6697         uint64_t cnt                   : 48; /**< [ 47:  0](R/W/H) Count of dropped packets. [CNT] will wrap and is cleared if NCSI is reset with
6698                                                                  BGX()_CMR_GLOBAL_CONFIG[CMR_NCSI_RESET]. */
6699         uint64_t reserved_48_63        : 16;
6700 #endif /* Word 0 - End */
6701     } cn81xx;
6702     /* struct bdk_bgxx_cmr_rx_stat9_s cn88xx; */
6703     /* struct bdk_bgxx_cmr_rx_stat9_cn81xx cn83xx; */
6704 };
6705 typedef union bdk_bgxx_cmr_rx_stat9 bdk_bgxx_cmr_rx_stat9_t;
6706 
6707 static inline uint64_t BDK_BGXX_CMR_RX_STAT9(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_RX_STAT9(unsigned long a)6708 static inline uint64_t BDK_BGXX_CMR_RX_STAT9(unsigned long a)
6709 {
6710     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6711         return 0x87e0e00000b8ll + 0x1000000ll * ((a) & 0x1);
6712     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
6713         return 0x87e0e00000b8ll + 0x1000000ll * ((a) & 0x3);
6714     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6715         return 0x87e0e00000b8ll + 0x1000000ll * ((a) & 0x1);
6716     __bdk_csr_fatal("BGXX_CMR_RX_STAT9", 1, a, 0, 0, 0);
6717 }
6718 
6719 #define typedef_BDK_BGXX_CMR_RX_STAT9(a) bdk_bgxx_cmr_rx_stat9_t
6720 #define bustype_BDK_BGXX_CMR_RX_STAT9(a) BDK_CSR_TYPE_RSL
6721 #define basename_BDK_BGXX_CMR_RX_STAT9(a) "BGXX_CMR_RX_STAT9"
6722 #define device_bar_BDK_BGXX_CMR_RX_STAT9(a) 0x0 /* PF_BAR0 */
6723 #define busnum_BDK_BGXX_CMR_RX_STAT9(a) (a)
6724 #define arguments_BDK_BGXX_CMR_RX_STAT9(a) (a),-1,-1,-1
6725 
6726 /**
6727  * Register (RSL) bgx#_cmr_rx_steering#
6728  *
6729  * BGX CMR Receive Steering Registers
6730  * These registers, along with BGX()_CMR_RX_STEERING_VETYPE(), provide eight filters for
6731  * identifying and steering NCSI receive traffic.
6732  *
6733  * Steering is done for the designated LMAC specified by BGX()_CMR_GLOBAL_CONFIG[NCSI_LMAC_ID].
6734  * The steering algorithm is applied after the RX DMAC filter specified by
6735  * BGX()_CMR()_RX_DMAC_CTL and BGX()_CMR_RX_DMAC()_CAM. As such, the DMAC filter and steering
6736  * filters should be set in a consistent manner.
6737  *
6738  * Internal:
6739  * "* ALGORITHM
6740  * // Steering of RX packets for LMAC identified by BGX()_CMR_GLOBAL_CONFIG[NCSI_LMAC_ID].
6741  * rx_steering(uint48 pkt_dmac, uint16 pkt_etype, uint16 pkt_vlan_id) {
6742  *    for (int i = 0; i \< 8; i++) {
6743  *       steer = BGX()_CMR_RX_STEERING(i);
6744  *       vetype = BGX()_CMR_RX_STEERING_VETYPE(i);
6745  *       if (steer[MCST_EN] || steer[DMAC_EN] || vetype[VLAN_EN] || vetype[VLAN_TAG_EN]) {
6746  *          // Filter is enabled.
6747  *          if (   (!steer[MCST_EN] || is_mcst(pkt_dmac))
6748  *              && (!steer[DMAC_EN] || pkt_dmac == steer[DMAC])
6749  *              && (!vetype[VLAN_EN] || pkt_vlan_id == vetype[VLAN_ID])
6750  *              && (!vetype[VLAN_TAG_EN] || pkt_etype == vetype[VLAN_ETYPE]) )
6751  *          {
6752  *             // Filter match (all enabled matching criteria are met).
6753  *             return steer[DEST];
6754  *          }
6755  *       }
6756  *    }
6757  *    return BGX()_CMR_RX_STEERING_DEFAULT[DEST]; // No match
6758  * }"
6759  */
6760 union bdk_bgxx_cmr_rx_steeringx
6761 {
6762     uint64_t u;
6763     struct bdk_bgxx_cmr_rx_steeringx_s
6764     {
6765 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6766         uint64_t reserved_52_63        : 12;
6767         uint64_t dest                  : 2;  /**< [ 51: 50](R/W) Destination for traffic that meets all criteria of the matching algorithm:
6768                                                                  0x0 = Steer this traffic exclusively to NCSI.
6769                                                                  0x1 = Steer this traffic exclusively to TNS/NIC.
6770                                                                  0x2 = Steer this traffic to BOTH TNS/NIC and NCSI.
6771                                                                  0x3 = Steer this traffic to the bit bucket (drop). */
6772         uint64_t mcst_en               : 1;  /**< [ 49: 49](R/W) Enable for identifying multicast packets:
6773                                                                  1 = Include multicast packets in the matching algorithm.
6774                                                                  0 = Do not include multicast packets in the matching algorithm. */
6775         uint64_t dmac_en               : 1;  /**< [ 48: 48](R/W) Enable DMAC address check:
6776                                                                  1 = Include DMAC address checking in the matching algorithm.
6777                                                                  0 = Do not include DMAC address checking in the matching algorithm. */
6778         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) DMAC address used for the matching algorithm when [DMAC_EN] is set. Broadcast can be
6779                                                                  specified with value 0xFFFF_FFFFFFFF. */
6780 #else /* Word 0 - Little Endian */
6781         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) DMAC address used for the matching algorithm when [DMAC_EN] is set. Broadcast can be
6782                                                                  specified with value 0xFFFF_FFFFFFFF. */
6783         uint64_t dmac_en               : 1;  /**< [ 48: 48](R/W) Enable DMAC address check:
6784                                                                  1 = Include DMAC address checking in the matching algorithm.
6785                                                                  0 = Do not include DMAC address checking in the matching algorithm. */
6786         uint64_t mcst_en               : 1;  /**< [ 49: 49](R/W) Enable for identifying multicast packets:
6787                                                                  1 = Include multicast packets in the matching algorithm.
6788                                                                  0 = Do not include multicast packets in the matching algorithm. */
6789         uint64_t dest                  : 2;  /**< [ 51: 50](R/W) Destination for traffic that meets all criteria of the matching algorithm:
6790                                                                  0x0 = Steer this traffic exclusively to NCSI.
6791                                                                  0x1 = Steer this traffic exclusively to TNS/NIC.
6792                                                                  0x2 = Steer this traffic to BOTH TNS/NIC and NCSI.
6793                                                                  0x3 = Steer this traffic to the bit bucket (drop). */
6794         uint64_t reserved_52_63        : 12;
6795 #endif /* Word 0 - End */
6796     } s;
6797     struct bdk_bgxx_cmr_rx_steeringx_cn81xx
6798     {
6799 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6800         uint64_t reserved_52_63        : 12;
6801         uint64_t dest                  : 2;  /**< [ 51: 50](R/W) Destination for traffic that meets all criteria of the matching algorithm:
6802                                                                  0x0 = Steer this traffic exclusively to NCSI.
6803                                                                  0x1 = Steer this traffic exclusively to NIC.
6804                                                                  0x2 = Steer this traffic to BOTH NIC and NCSI.
6805                                                                  0x3 = Steer this traffic to the bit bucket (drop). */
6806         uint64_t mcst_en               : 1;  /**< [ 49: 49](R/W) Enable for identifying multicast packets:
6807                                                                  1 = Include multicast packets in the matching algorithm.
6808                                                                  0 = Do not include multicast packets in the matching algorithm. */
6809         uint64_t dmac_en               : 1;  /**< [ 48: 48](R/W) Enable DMAC address check:
6810                                                                  1 = Include DMAC address checking in the matching algorithm.
6811                                                                  0 = Do not include DMAC address checking in the matching algorithm. */
6812         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) DMAC address used for the matching algorithm when [DMAC_EN] is set. Broadcast can be
6813                                                                  specified with value 0xFFFF_FFFFFFFF. */
6814 #else /* Word 0 - Little Endian */
6815         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) DMAC address used for the matching algorithm when [DMAC_EN] is set. Broadcast can be
6816                                                                  specified with value 0xFFFF_FFFFFFFF. */
6817         uint64_t dmac_en               : 1;  /**< [ 48: 48](R/W) Enable DMAC address check:
6818                                                                  1 = Include DMAC address checking in the matching algorithm.
6819                                                                  0 = Do not include DMAC address checking in the matching algorithm. */
6820         uint64_t mcst_en               : 1;  /**< [ 49: 49](R/W) Enable for identifying multicast packets:
6821                                                                  1 = Include multicast packets in the matching algorithm.
6822                                                                  0 = Do not include multicast packets in the matching algorithm. */
6823         uint64_t dest                  : 2;  /**< [ 51: 50](R/W) Destination for traffic that meets all criteria of the matching algorithm:
6824                                                                  0x0 = Steer this traffic exclusively to NCSI.
6825                                                                  0x1 = Steer this traffic exclusively to NIC.
6826                                                                  0x2 = Steer this traffic to BOTH NIC and NCSI.
6827                                                                  0x3 = Steer this traffic to the bit bucket (drop). */
6828         uint64_t reserved_52_63        : 12;
6829 #endif /* Word 0 - End */
6830     } cn81xx;
6831     /* struct bdk_bgxx_cmr_rx_steeringx_s cn88xx; */
6832     struct bdk_bgxx_cmr_rx_steeringx_cn83xx
6833     {
6834 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6835         uint64_t reserved_52_63        : 12;
6836         uint64_t dest                  : 2;  /**< [ 51: 50](R/W) Destination for traffic that meets all criteria of the matching algorithm:
6837                                                                  0x0 = Steer this traffic exclusively to NCSI.
6838                                                                  0x1 = Steer this traffic exclusively to PKO/NIC.
6839                                                                  0x2 = Steer this traffic to BOTH PKO/NIC and NCSI.
6840                                                                  0x3 = Steer this traffic to the bit bucket (drop). */
6841         uint64_t mcst_en               : 1;  /**< [ 49: 49](R/W) Enable for identifying multicast packets:
6842                                                                  1 = Include multicast packets in the matching algorithm.
6843                                                                  0 = Do not include multicast packets in the matching algorithm. */
6844         uint64_t dmac_en               : 1;  /**< [ 48: 48](R/W) Enable DMAC address check:
6845                                                                  1 = Include DMAC address checking in the matching algorithm.
6846                                                                  0 = Do not include DMAC address checking in the matching algorithm. */
6847         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) DMAC address used for the matching algorithm when [DMAC_EN] is set. Broadcast can be
6848                                                                  specified with value 0xFFFF_FFFFFFFF. */
6849 #else /* Word 0 - Little Endian */
6850         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) DMAC address used for the matching algorithm when [DMAC_EN] is set. Broadcast can be
6851                                                                  specified with value 0xFFFF_FFFFFFFF. */
6852         uint64_t dmac_en               : 1;  /**< [ 48: 48](R/W) Enable DMAC address check:
6853                                                                  1 = Include DMAC address checking in the matching algorithm.
6854                                                                  0 = Do not include DMAC address checking in the matching algorithm. */
6855         uint64_t mcst_en               : 1;  /**< [ 49: 49](R/W) Enable for identifying multicast packets:
6856                                                                  1 = Include multicast packets in the matching algorithm.
6857                                                                  0 = Do not include multicast packets in the matching algorithm. */
6858         uint64_t dest                  : 2;  /**< [ 51: 50](R/W) Destination for traffic that meets all criteria of the matching algorithm:
6859                                                                  0x0 = Steer this traffic exclusively to NCSI.
6860                                                                  0x1 = Steer this traffic exclusively to PKO/NIC.
6861                                                                  0x2 = Steer this traffic to BOTH PKO/NIC and NCSI.
6862                                                                  0x3 = Steer this traffic to the bit bucket (drop). */
6863         uint64_t reserved_52_63        : 12;
6864 #endif /* Word 0 - End */
6865     } cn83xx;
6866 };
6867 typedef union bdk_bgxx_cmr_rx_steeringx bdk_bgxx_cmr_rx_steeringx_t;
6868 
6869 static inline uint64_t BDK_BGXX_CMR_RX_STEERINGX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_RX_STEERINGX(unsigned long a,unsigned long b)6870 static inline uint64_t BDK_BGXX_CMR_RX_STEERINGX(unsigned long a, unsigned long b)
6871 {
6872     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=7)))
6873         return 0x87e0e0000300ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x7);
6874     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=7)))
6875         return 0x87e0e0000300ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x7);
6876     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=7)))
6877         return 0x87e0e0000300ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x7);
6878     __bdk_csr_fatal("BGXX_CMR_RX_STEERINGX", 2, a, b, 0, 0);
6879 }
6880 
6881 #define typedef_BDK_BGXX_CMR_RX_STEERINGX(a,b) bdk_bgxx_cmr_rx_steeringx_t
6882 #define bustype_BDK_BGXX_CMR_RX_STEERINGX(a,b) BDK_CSR_TYPE_RSL
6883 #define basename_BDK_BGXX_CMR_RX_STEERINGX(a,b) "BGXX_CMR_RX_STEERINGX"
6884 #define device_bar_BDK_BGXX_CMR_RX_STEERINGX(a,b) 0x0 /* PF_BAR0 */
6885 #define busnum_BDK_BGXX_CMR_RX_STEERINGX(a,b) (a)
6886 #define arguments_BDK_BGXX_CMR_RX_STEERINGX(a,b) (a),(b),-1,-1
6887 
6888 /**
6889  * Register (RSL) bgx#_cmr_rx_steering_default
6890  *
6891  * BGX CMR Receive Steering Default Destination Register
6892  */
6893 union bdk_bgxx_cmr_rx_steering_default
6894 {
6895     uint64_t u;
6896     struct bdk_bgxx_cmr_rx_steering_default_s
6897     {
6898 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6899         uint64_t reserved_2_63         : 62;
6900         uint64_t dest                  : 2;  /**< [  1:  0](R/W) Destination for traffic that does not match any of the steering filters specified by
6901                                                                  BGX()_CMR_RX_STEERING() and and BGX()_CMR_RX_STEERING_VETYPE():
6902                                                                  0x0 = Steer traffic exclusively to NCSI.
6903                                                                  0x1 = Steer traffic exclusively to TNS/NIC.
6904                                                                  0x2 = Steer traffic to BOTH TNS/NIC and NCSI.
6905                                                                  0x3 = Steer traffic to the bit bucket (drop). */
6906 #else /* Word 0 - Little Endian */
6907         uint64_t dest                  : 2;  /**< [  1:  0](R/W) Destination for traffic that does not match any of the steering filters specified by
6908                                                                  BGX()_CMR_RX_STEERING() and and BGX()_CMR_RX_STEERING_VETYPE():
6909                                                                  0x0 = Steer traffic exclusively to NCSI.
6910                                                                  0x1 = Steer traffic exclusively to TNS/NIC.
6911                                                                  0x2 = Steer traffic to BOTH TNS/NIC and NCSI.
6912                                                                  0x3 = Steer traffic to the bit bucket (drop). */
6913         uint64_t reserved_2_63         : 62;
6914 #endif /* Word 0 - End */
6915     } s;
6916     struct bdk_bgxx_cmr_rx_steering_default_cn81xx
6917     {
6918 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6919         uint64_t reserved_2_63         : 62;
6920         uint64_t dest                  : 2;  /**< [  1:  0](R/W) Destination for traffic that does not match any of the steering filters specified by
6921                                                                  BGX()_CMR_RX_STEERING() and and BGX()_CMR_RX_STEERING_VETYPE():
6922                                                                  0x0 = Steer traffic exclusively to NCSI.
6923                                                                  0x1 = Steer traffic exclusively to NIC.
6924                                                                  0x2 = Steer traffic to BOTH NIC and NCSI.
6925                                                                  0x3 = Steer traffic to the bit bucket (drop). */
6926 #else /* Word 0 - Little Endian */
6927         uint64_t dest                  : 2;  /**< [  1:  0](R/W) Destination for traffic that does not match any of the steering filters specified by
6928                                                                  BGX()_CMR_RX_STEERING() and and BGX()_CMR_RX_STEERING_VETYPE():
6929                                                                  0x0 = Steer traffic exclusively to NCSI.
6930                                                                  0x1 = Steer traffic exclusively to NIC.
6931                                                                  0x2 = Steer traffic to BOTH NIC and NCSI.
6932                                                                  0x3 = Steer traffic to the bit bucket (drop). */
6933         uint64_t reserved_2_63         : 62;
6934 #endif /* Word 0 - End */
6935     } cn81xx;
6936     /* struct bdk_bgxx_cmr_rx_steering_default_s cn88xx; */
6937     struct bdk_bgxx_cmr_rx_steering_default_cn83xx
6938     {
6939 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6940         uint64_t reserved_2_63         : 62;
6941         uint64_t dest                  : 2;  /**< [  1:  0](R/W) Destination for traffic that does not match any of the steering filters specified by
6942                                                                  BGX()_CMR_RX_STEERING() and and BGX()_CMR_RX_STEERING_VETYPE():
6943                                                                  0x0 = Steer traffic exclusively to NCSI.
6944                                                                  0x1 = Steer traffic exclusively to PKO/NIC.
6945                                                                  0x2 = Steer traffic to BOTH PKO/NIC and NCSI.
6946                                                                  0x3 = Steer traffic to the bit bucket (drop). */
6947 #else /* Word 0 - Little Endian */
6948         uint64_t dest                  : 2;  /**< [  1:  0](R/W) Destination for traffic that does not match any of the steering filters specified by
6949                                                                  BGX()_CMR_RX_STEERING() and and BGX()_CMR_RX_STEERING_VETYPE():
6950                                                                  0x0 = Steer traffic exclusively to NCSI.
6951                                                                  0x1 = Steer traffic exclusively to PKO/NIC.
6952                                                                  0x2 = Steer traffic to BOTH PKO/NIC and NCSI.
6953                                                                  0x3 = Steer traffic to the bit bucket (drop). */
6954         uint64_t reserved_2_63         : 62;
6955 #endif /* Word 0 - End */
6956     } cn83xx;
6957 };
6958 typedef union bdk_bgxx_cmr_rx_steering_default bdk_bgxx_cmr_rx_steering_default_t;
6959 
6960 static inline uint64_t BDK_BGXX_CMR_RX_STEERING_DEFAULT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_RX_STEERING_DEFAULT(unsigned long a)6961 static inline uint64_t BDK_BGXX_CMR_RX_STEERING_DEFAULT(unsigned long a)
6962 {
6963     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
6964         return 0x87e0e0000448ll + 0x1000000ll * ((a) & 0x1);
6965     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
6966         return 0x87e0e0000448ll + 0x1000000ll * ((a) & 0x3);
6967     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
6968         return 0x87e0e0000448ll + 0x1000000ll * ((a) & 0x1);
6969     __bdk_csr_fatal("BGXX_CMR_RX_STEERING_DEFAULT", 1, a, 0, 0, 0);
6970 }
6971 
6972 #define typedef_BDK_BGXX_CMR_RX_STEERING_DEFAULT(a) bdk_bgxx_cmr_rx_steering_default_t
6973 #define bustype_BDK_BGXX_CMR_RX_STEERING_DEFAULT(a) BDK_CSR_TYPE_RSL
6974 #define basename_BDK_BGXX_CMR_RX_STEERING_DEFAULT(a) "BGXX_CMR_RX_STEERING_DEFAULT"
6975 #define device_bar_BDK_BGXX_CMR_RX_STEERING_DEFAULT(a) 0x0 /* PF_BAR0 */
6976 #define busnum_BDK_BGXX_CMR_RX_STEERING_DEFAULT(a) (a)
6977 #define arguments_BDK_BGXX_CMR_RX_STEERING_DEFAULT(a) (a),-1,-1,-1
6978 
6979 /**
6980  * Register (RSL) bgx#_cmr_rx_steering_vetype#
6981  *
6982  * BGX CMR Receive VLAN Ethertype Register
6983  * These registers, along with BGX()_CMR_RX_STEERING(), provide eight filters for identifying and
6984  * steering NCSI receive traffic.
6985  */
6986 union bdk_bgxx_cmr_rx_steering_vetypex
6987 {
6988     uint64_t u;
6989     struct bdk_bgxx_cmr_rx_steering_vetypex_s
6990     {
6991 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6992         uint64_t reserved_30_63        : 34;
6993         uint64_t vlan_en               : 1;  /**< [ 29: 29](R/W) Enable VLAN ID check:
6994                                                                  1 = Include VLAN ID checking in the matching algorithm.
6995                                                                  0 = Do not include VLAN ID checking in the matching algorithm. */
6996         uint64_t vlan_id               : 12; /**< [ 28: 17](R/W) VLAN ID used for the matching algorithm when [VLAN_EN] is set. */
6997         uint64_t vlan_tag_en           : 1;  /**< [ 16: 16](R/W) Enable VLAN tag Ethertype check:
6998                                                                  1 = Include VLAN tag Ethertype checking in the matching algorithm.
6999                                                                  0 = Do not include VLAN tag Ethertype checking in the matching algorithm. */
7000         uint64_t vlan_etype            : 16; /**< [ 15:  0](R/W) VLAN Ethertype for the matching algorithm when [VLAN_TAG_EN] is set.
7001                                                                  802.1Q and 802.1ad specify several Ethertypes used to identify VLAN tagged and VLAN double
7002                                                                  tagged packets. BGX will always match against the tag immediately following the SMAC
7003                                                                  address of the L2 header. */
7004 #else /* Word 0 - Little Endian */
7005         uint64_t vlan_etype            : 16; /**< [ 15:  0](R/W) VLAN Ethertype for the matching algorithm when [VLAN_TAG_EN] is set.
7006                                                                  802.1Q and 802.1ad specify several Ethertypes used to identify VLAN tagged and VLAN double
7007                                                                  tagged packets. BGX will always match against the tag immediately following the SMAC
7008                                                                  address of the L2 header. */
7009         uint64_t vlan_tag_en           : 1;  /**< [ 16: 16](R/W) Enable VLAN tag Ethertype check:
7010                                                                  1 = Include VLAN tag Ethertype checking in the matching algorithm.
7011                                                                  0 = Do not include VLAN tag Ethertype checking in the matching algorithm. */
7012         uint64_t vlan_id               : 12; /**< [ 28: 17](R/W) VLAN ID used for the matching algorithm when [VLAN_EN] is set. */
7013         uint64_t vlan_en               : 1;  /**< [ 29: 29](R/W) Enable VLAN ID check:
7014                                                                  1 = Include VLAN ID checking in the matching algorithm.
7015                                                                  0 = Do not include VLAN ID checking in the matching algorithm. */
7016         uint64_t reserved_30_63        : 34;
7017 #endif /* Word 0 - End */
7018     } s;
7019     /* struct bdk_bgxx_cmr_rx_steering_vetypex_s cn; */
7020 };
7021 typedef union bdk_bgxx_cmr_rx_steering_vetypex bdk_bgxx_cmr_rx_steering_vetypex_t;
7022 
7023 static inline uint64_t BDK_BGXX_CMR_RX_STEERING_VETYPEX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_RX_STEERING_VETYPEX(unsigned long a,unsigned long b)7024 static inline uint64_t BDK_BGXX_CMR_RX_STEERING_VETYPEX(unsigned long a, unsigned long b)
7025 {
7026     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=7)))
7027         return 0x87e0e0000400ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x7);
7028     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=7)))
7029         return 0x87e0e0000400ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x7);
7030     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=7)))
7031         return 0x87e0e0000400ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x7);
7032     __bdk_csr_fatal("BGXX_CMR_RX_STEERING_VETYPEX", 2, a, b, 0, 0);
7033 }
7034 
7035 #define typedef_BDK_BGXX_CMR_RX_STEERING_VETYPEX(a,b) bdk_bgxx_cmr_rx_steering_vetypex_t
7036 #define bustype_BDK_BGXX_CMR_RX_STEERING_VETYPEX(a,b) BDK_CSR_TYPE_RSL
7037 #define basename_BDK_BGXX_CMR_RX_STEERING_VETYPEX(a,b) "BGXX_CMR_RX_STEERING_VETYPEX"
7038 #define device_bar_BDK_BGXX_CMR_RX_STEERING_VETYPEX(a,b) 0x0 /* PF_BAR0 */
7039 #define busnum_BDK_BGXX_CMR_RX_STEERING_VETYPEX(a,b) (a)
7040 #define arguments_BDK_BGXX_CMR_RX_STEERING_VETYPEX(a,b) (a),(b),-1,-1
7041 
7042 /**
7043  * Register (RSL) bgx#_cmr_tx_lmacs
7044  *
7045  * BGX CMR Transmit Logical MACs Registers
7046  * This register sets the number of LMACs allowed on the TX interface. The value is important for
7047  * defining the partitioning of the transmit FIFO.
7048  */
7049 union bdk_bgxx_cmr_tx_lmacs
7050 {
7051     uint64_t u;
7052     struct bdk_bgxx_cmr_tx_lmacs_s
7053     {
7054 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7055         uint64_t reserved_3_63         : 61;
7056         uint64_t lmacs                 : 3;  /**< [  2:  0](R/W) Number of LMACS: Specifies the number of LMACs that can be enabled.
7057                                                                  This determines the logical TX buffer size per LMAC and the maximum
7058                                                                  LMAC ID that can be used:
7059 
7060                                                                  0x0 = Reserved.
7061                                                                  0x1 = 48 KB per LMAC, maximum LMAC ID is 0.
7062                                                                  0x2 = 24 KB per LMAC, maximum LMAC ID is 1.
7063                                                                  0x3 = 12 KB per LMAC, maximum LMAC ID is 2.
7064                                                                  0x4 = 12 KB per LMAC, maximum LMAC ID is 3.
7065                                                                  0x5-0x7 = Reserved.
7066 
7067                                                                  The maximum LMAC ID is determined by the smaller of BGX()_CMR_RX_LMACS[LMACS]
7068                                                                  and BGX()_CMR_TX_LMACS[LMACS]. The two fields should be set to the same value for
7069                                                                  normal operation.' */
7070 #else /* Word 0 - Little Endian */
7071         uint64_t lmacs                 : 3;  /**< [  2:  0](R/W) Number of LMACS: Specifies the number of LMACs that can be enabled.
7072                                                                  This determines the logical TX buffer size per LMAC and the maximum
7073                                                                  LMAC ID that can be used:
7074 
7075                                                                  0x0 = Reserved.
7076                                                                  0x1 = 48 KB per LMAC, maximum LMAC ID is 0.
7077                                                                  0x2 = 24 KB per LMAC, maximum LMAC ID is 1.
7078                                                                  0x3 = 12 KB per LMAC, maximum LMAC ID is 2.
7079                                                                  0x4 = 12 KB per LMAC, maximum LMAC ID is 3.
7080                                                                  0x5-0x7 = Reserved.
7081 
7082                                                                  The maximum LMAC ID is determined by the smaller of BGX()_CMR_RX_LMACS[LMACS]
7083                                                                  and BGX()_CMR_TX_LMACS[LMACS]. The two fields should be set to the same value for
7084                                                                  normal operation.' */
7085         uint64_t reserved_3_63         : 61;
7086 #endif /* Word 0 - End */
7087     } s;
7088     /* struct bdk_bgxx_cmr_tx_lmacs_s cn; */
7089 };
7090 typedef union bdk_bgxx_cmr_tx_lmacs bdk_bgxx_cmr_tx_lmacs_t;
7091 
7092 static inline uint64_t BDK_BGXX_CMR_TX_LMACS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CMR_TX_LMACS(unsigned long a)7093 static inline uint64_t BDK_BGXX_CMR_TX_LMACS(unsigned long a)
7094 {
7095     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
7096         return 0x87e0e0001000ll + 0x1000000ll * ((a) & 0x1);
7097     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
7098         return 0x87e0e0001000ll + 0x1000000ll * ((a) & 0x3);
7099     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
7100         return 0x87e0e0001000ll + 0x1000000ll * ((a) & 0x1);
7101     __bdk_csr_fatal("BGXX_CMR_TX_LMACS", 1, a, 0, 0, 0);
7102 }
7103 
7104 #define typedef_BDK_BGXX_CMR_TX_LMACS(a) bdk_bgxx_cmr_tx_lmacs_t
7105 #define bustype_BDK_BGXX_CMR_TX_LMACS(a) BDK_CSR_TYPE_RSL
7106 #define basename_BDK_BGXX_CMR_TX_LMACS(a) "BGXX_CMR_TX_LMACS"
7107 #define device_bar_BDK_BGXX_CMR_TX_LMACS(a) 0x0 /* PF_BAR0 */
7108 #define busnum_BDK_BGXX_CMR_TX_LMACS(a) (a)
7109 #define arguments_BDK_BGXX_CMR_TX_LMACS(a) (a),-1,-1,-1
7110 
7111 /**
7112  * Register (RSL) bgx#_const
7113  *
7114  * BGX CONST Registers
7115  * This register contains constants for software discovery.
7116  */
7117 union bdk_bgxx_const
7118 {
7119     uint64_t u;
7120     struct bdk_bgxx_const_s
7121     {
7122 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7123         uint64_t reserved_32_63        : 32;
7124         uint64_t lmacs                 : 8;  /**< [ 31: 24](RO) Number of LMACs. */
7125         uint64_t tx_fifosz             : 24; /**< [ 23:  0](RO) Number of bytes of transmit buffering in entire BGX. This buffering may be split
7126                                                                  between LMACs; see BGX()_CMR_TX_LMACS[LMACS]. */
7127 #else /* Word 0 - Little Endian */
7128         uint64_t tx_fifosz             : 24; /**< [ 23:  0](RO) Number of bytes of transmit buffering in entire BGX. This buffering may be split
7129                                                                  between LMACs; see BGX()_CMR_TX_LMACS[LMACS]. */
7130         uint64_t lmacs                 : 8;  /**< [ 31: 24](RO) Number of LMACs. */
7131         uint64_t reserved_32_63        : 32;
7132 #endif /* Word 0 - End */
7133     } s;
7134     struct bdk_bgxx_const_cn81xx
7135     {
7136 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7137         uint64_t reserved_32_63        : 32;
7138         uint64_t lmacs                 : 8;  /**< [ 31: 24](RO) Number of LMACs.
7139                                                                  If 0x0, indicates 4 LMACs, otherwise, the number of LMACs. */
7140         uint64_t tx_fifosz             : 24; /**< [ 23:  0](RO) Number of bytes of transmit buffering in entire BGX. This buffering may be split
7141                                                                  between LMACs; see BGX()_CMR_TX_LMACS[LMACS].  If 0x0, indicates size of 0xC000. */
7142 #else /* Word 0 - Little Endian */
7143         uint64_t tx_fifosz             : 24; /**< [ 23:  0](RO) Number of bytes of transmit buffering in entire BGX. This buffering may be split
7144                                                                  between LMACs; see BGX()_CMR_TX_LMACS[LMACS].  If 0x0, indicates size of 0xC000. */
7145         uint64_t lmacs                 : 8;  /**< [ 31: 24](RO) Number of LMACs.
7146                                                                  If 0x0, indicates 4 LMACs, otherwise, the number of LMACs. */
7147         uint64_t reserved_32_63        : 32;
7148 #endif /* Word 0 - End */
7149     } cn81xx;
7150     /* struct bdk_bgxx_const_s cn83xx; */
7151 };
7152 typedef union bdk_bgxx_const bdk_bgxx_const_t;
7153 
7154 static inline uint64_t BDK_BGXX_CONST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CONST(unsigned long a)7155 static inline uint64_t BDK_BGXX_CONST(unsigned long a)
7156 {
7157     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
7158         return 0x87e0e0040000ll + 0x1000000ll * ((a) & 0x1);
7159     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
7160         return 0x87e0e0040000ll + 0x1000000ll * ((a) & 0x3);
7161     __bdk_csr_fatal("BGXX_CONST", 1, a, 0, 0, 0);
7162 }
7163 
7164 #define typedef_BDK_BGXX_CONST(a) bdk_bgxx_const_t
7165 #define bustype_BDK_BGXX_CONST(a) BDK_CSR_TYPE_RSL
7166 #define basename_BDK_BGXX_CONST(a) "BGXX_CONST"
7167 #define device_bar_BDK_BGXX_CONST(a) 0x0 /* PF_BAR0 */
7168 #define busnum_BDK_BGXX_CONST(a) (a)
7169 #define arguments_BDK_BGXX_CONST(a) (a),-1,-1,-1
7170 
7171 /**
7172  * Register (RSL) bgx#_const1
7173  *
7174  * BGX CONST1 Registers
7175  * This register contains constants for software discovery.
7176  */
7177 union bdk_bgxx_const1
7178 {
7179     uint64_t u;
7180     struct bdk_bgxx_const1_s
7181     {
7182 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7183         uint64_t reserved_32_63        : 32;
7184         uint64_t res_types             : 24; /**< [ 31:  8](RO) Reserved for more LMAC TYPES. */
7185         uint64_t types                 : 8;  /**< [  7:  0](RO) LMAC types supported. Each bit if set corresponds to that value of BGX_LMAC_TYPES_E being
7186                                                                  supported.
7187                                                                  E.g. TYPES\<0\> if set indicates BGX_LMAC_TYPES_E::SGMII is supported. */
7188 #else /* Word 0 - Little Endian */
7189         uint64_t types                 : 8;  /**< [  7:  0](RO) LMAC types supported. Each bit if set corresponds to that value of BGX_LMAC_TYPES_E being
7190                                                                  supported.
7191                                                                  E.g. TYPES\<0\> if set indicates BGX_LMAC_TYPES_E::SGMII is supported. */
7192         uint64_t res_types             : 24; /**< [ 31:  8](RO) Reserved for more LMAC TYPES. */
7193         uint64_t reserved_32_63        : 32;
7194 #endif /* Word 0 - End */
7195     } s;
7196     struct bdk_bgxx_const1_cn81xx
7197     {
7198 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7199         uint64_t reserved_32_63        : 32;
7200         uint64_t res_types             : 24; /**< [ 31:  8](RO) Reserved for more LMAC TYPES. */
7201         uint64_t types                 : 8;  /**< [  7:  0](RO) LMAC types supported. Each bit if set corresponds to that value of
7202                                                                  BGX_LMAC_TYPES_E being supported. E.g. TYPES\<5\> if set indicates
7203                                                                  BGX_LMAC_TYPES_E::RGMII is supported. If 0x0, [TYPES] should be treated by
7204                                                                  software as if the read value was 0x5F (all but RGMII). */
7205 #else /* Word 0 - Little Endian */
7206         uint64_t types                 : 8;  /**< [  7:  0](RO) LMAC types supported. Each bit if set corresponds to that value of
7207                                                                  BGX_LMAC_TYPES_E being supported. E.g. TYPES\<5\> if set indicates
7208                                                                  BGX_LMAC_TYPES_E::RGMII is supported. If 0x0, [TYPES] should be treated by
7209                                                                  software as if the read value was 0x5F (all but RGMII). */
7210         uint64_t res_types             : 24; /**< [ 31:  8](RO) Reserved for more LMAC TYPES. */
7211         uint64_t reserved_32_63        : 32;
7212 #endif /* Word 0 - End */
7213     } cn81xx;
7214     /* struct bdk_bgxx_const1_s cn83xx; */
7215 };
7216 typedef union bdk_bgxx_const1 bdk_bgxx_const1_t;
7217 
7218 static inline uint64_t BDK_BGXX_CONST1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_CONST1(unsigned long a)7219 static inline uint64_t BDK_BGXX_CONST1(unsigned long a)
7220 {
7221     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
7222         return 0x87e0e0040008ll + 0x1000000ll * ((a) & 0x1);
7223     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
7224         return 0x87e0e0040008ll + 0x1000000ll * ((a) & 0x3);
7225     __bdk_csr_fatal("BGXX_CONST1", 1, a, 0, 0, 0);
7226 }
7227 
7228 #define typedef_BDK_BGXX_CONST1(a) bdk_bgxx_const1_t
7229 #define bustype_BDK_BGXX_CONST1(a) BDK_CSR_TYPE_RSL
7230 #define basename_BDK_BGXX_CONST1(a) "BGXX_CONST1"
7231 #define device_bar_BDK_BGXX_CONST1(a) 0x0 /* PF_BAR0 */
7232 #define busnum_BDK_BGXX_CONST1(a) (a)
7233 #define arguments_BDK_BGXX_CONST1(a) (a),-1,-1,-1
7234 
7235 /**
7236  * Register (RSL) bgx#_gmp_gmi_prt#_cfg
7237  *
7238  * BGX GMP GMI LMAC Configuration Registers
7239  * This register controls the configuration of the LMAC.
7240  */
7241 union bdk_bgxx_gmp_gmi_prtx_cfg
7242 {
7243     uint64_t u;
7244     struct bdk_bgxx_gmp_gmi_prtx_cfg_s
7245     {
7246 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7247         uint64_t reserved_14_63        : 50;
7248         uint64_t tx_idle               : 1;  /**< [ 13: 13](RO/H) TX machine is idle. */
7249         uint64_t rx_idle               : 1;  /**< [ 12: 12](RO/H) RX machine is idle. */
7250         uint64_t reserved_9_11         : 3;
7251         uint64_t speed_msb             : 1;  /**< [  8:  8](R/W) Link speed MSB (SGMII/QSGMII/1000Base-X only). See [SPEED]. */
7252         uint64_t reserved_4_7          : 4;
7253         uint64_t slottime              : 1;  /**< [  3:  3](R/W) Slot time for half-duplex operation
7254                                                                  (SGMII/QSGMII/1000Base-X only):
7255                                                                  0 = 512 bit times (10/100 Mb/s operation).
7256                                                                  1 = 4096 bit times (1000 Mb/s operation). */
7257         uint64_t duplex                : 1;  /**< [  2:  2](R/W) Duplex mode
7258                                                                  (SGMII/QSGMII/1000Base-X only):
7259                                                                  0 = half-duplex (collisions/extensions/bursts):
7260                                                                  1 = full-duplex. */
7261         uint64_t speed                 : 1;  /**< [  1:  1](R/W) Link Speed LSB (SGMII/QSGMII/1000Base-X only):
7262                                                                  _ [SPEED_MSB,SPEED] = 0x0: 100 Mb/s operation.
7263                                                                  _ [SPEED_MSB,SPEED] = 0x1: 1000 Mb/s operation.
7264                                                                  _ [SPEED_MSB,SPEED] = 0x2: 10 Mb/s operation.
7265                                                                  _ [SPEED_MSB,SPEED] = 0x3: Reserved. */
7266         uint64_t reserved_0            : 1;
7267 #else /* Word 0 - Little Endian */
7268         uint64_t reserved_0            : 1;
7269         uint64_t speed                 : 1;  /**< [  1:  1](R/W) Link Speed LSB (SGMII/QSGMII/1000Base-X only):
7270                                                                  _ [SPEED_MSB,SPEED] = 0x0: 100 Mb/s operation.
7271                                                                  _ [SPEED_MSB,SPEED] = 0x1: 1000 Mb/s operation.
7272                                                                  _ [SPEED_MSB,SPEED] = 0x2: 10 Mb/s operation.
7273                                                                  _ [SPEED_MSB,SPEED] = 0x3: Reserved. */
7274         uint64_t duplex                : 1;  /**< [  2:  2](R/W) Duplex mode
7275                                                                  (SGMII/QSGMII/1000Base-X only):
7276                                                                  0 = half-duplex (collisions/extensions/bursts):
7277                                                                  1 = full-duplex. */
7278         uint64_t slottime              : 1;  /**< [  3:  3](R/W) Slot time for half-duplex operation
7279                                                                  (SGMII/QSGMII/1000Base-X only):
7280                                                                  0 = 512 bit times (10/100 Mb/s operation).
7281                                                                  1 = 4096 bit times (1000 Mb/s operation). */
7282         uint64_t reserved_4_7          : 4;
7283         uint64_t speed_msb             : 1;  /**< [  8:  8](R/W) Link speed MSB (SGMII/QSGMII/1000Base-X only). See [SPEED]. */
7284         uint64_t reserved_9_11         : 3;
7285         uint64_t rx_idle               : 1;  /**< [ 12: 12](RO/H) RX machine is idle. */
7286         uint64_t tx_idle               : 1;  /**< [ 13: 13](RO/H) TX machine is idle. */
7287         uint64_t reserved_14_63        : 50;
7288 #endif /* Word 0 - End */
7289     } s;
7290     /* struct bdk_bgxx_gmp_gmi_prtx_cfg_s cn81xx; */
7291     struct bdk_bgxx_gmp_gmi_prtx_cfg_cn88xx
7292     {
7293 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7294         uint64_t reserved_14_63        : 50;
7295         uint64_t tx_idle               : 1;  /**< [ 13: 13](RO/H) TX machine is idle. */
7296         uint64_t rx_idle               : 1;  /**< [ 12: 12](RO/H) RX machine is idle. */
7297         uint64_t reserved_9_11         : 3;
7298         uint64_t speed_msb             : 1;  /**< [  8:  8](R/W) Link speed MSB (SGMII/1000Base-X only). See [SPEED]. */
7299         uint64_t reserved_4_7          : 4;
7300         uint64_t slottime              : 1;  /**< [  3:  3](R/W) Slot time for half-duplex operation
7301                                                                  (SGMII/1000Base-X only):
7302                                                                  0 = 512 bit times (10/100 Mb/s operation).
7303                                                                  1 = 4096 bit times (1000 Mb/s operation). */
7304         uint64_t duplex                : 1;  /**< [  2:  2](R/W) Duplex mode
7305                                                                  (SGMII/1000Base-X only):
7306                                                                  0 = half-duplex (collisions/extensions/bursts).
7307                                                                  1 = full-duplex. */
7308         uint64_t speed                 : 1;  /**< [  1:  1](R/W) Link Speed LSB (SGMII/1000Base-X only):
7309                                                                  _ [SPEED_MSB,SPEED] = 0x0: 100 Mb/s operation.
7310                                                                  _ [SPEED_MSB,SPEED] = 0x1: 1000 Mb/s operation.
7311                                                                  _ [SPEED_MSB,SPEED] = 0x2: 10 Mb/s operation.
7312                                                                  _ [SPEED_MSB,SPEED] = 0x3: Reserved. */
7313         uint64_t reserved_0            : 1;
7314 #else /* Word 0 - Little Endian */
7315         uint64_t reserved_0            : 1;
7316         uint64_t speed                 : 1;  /**< [  1:  1](R/W) Link Speed LSB (SGMII/1000Base-X only):
7317                                                                  _ [SPEED_MSB,SPEED] = 0x0: 100 Mb/s operation.
7318                                                                  _ [SPEED_MSB,SPEED] = 0x1: 1000 Mb/s operation.
7319                                                                  _ [SPEED_MSB,SPEED] = 0x2: 10 Mb/s operation.
7320                                                                  _ [SPEED_MSB,SPEED] = 0x3: Reserved. */
7321         uint64_t duplex                : 1;  /**< [  2:  2](R/W) Duplex mode
7322                                                                  (SGMII/1000Base-X only):
7323                                                                  0 = half-duplex (collisions/extensions/bursts).
7324                                                                  1 = full-duplex. */
7325         uint64_t slottime              : 1;  /**< [  3:  3](R/W) Slot time for half-duplex operation
7326                                                                  (SGMII/1000Base-X only):
7327                                                                  0 = 512 bit times (10/100 Mb/s operation).
7328                                                                  1 = 4096 bit times (1000 Mb/s operation). */
7329         uint64_t reserved_4_7          : 4;
7330         uint64_t speed_msb             : 1;  /**< [  8:  8](R/W) Link speed MSB (SGMII/1000Base-X only). See [SPEED]. */
7331         uint64_t reserved_9_11         : 3;
7332         uint64_t rx_idle               : 1;  /**< [ 12: 12](RO/H) RX machine is idle. */
7333         uint64_t tx_idle               : 1;  /**< [ 13: 13](RO/H) TX machine is idle. */
7334         uint64_t reserved_14_63        : 50;
7335 #endif /* Word 0 - End */
7336     } cn88xx;
7337     /* struct bdk_bgxx_gmp_gmi_prtx_cfg_s cn83xx; */
7338 };
7339 typedef union bdk_bgxx_gmp_gmi_prtx_cfg bdk_bgxx_gmp_gmi_prtx_cfg_t;
7340 
7341 static inline uint64_t BDK_BGXX_GMP_GMI_PRTX_CFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_PRTX_CFG(unsigned long a,unsigned long b)7342 static inline uint64_t BDK_BGXX_GMP_GMI_PRTX_CFG(unsigned long a, unsigned long b)
7343 {
7344     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
7345         return 0x87e0e0038020ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7346     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
7347         return 0x87e0e0038020ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
7348     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
7349         return 0x87e0e0038020ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7350     __bdk_csr_fatal("BGXX_GMP_GMI_PRTX_CFG", 2, a, b, 0, 0);
7351 }
7352 
7353 #define typedef_BDK_BGXX_GMP_GMI_PRTX_CFG(a,b) bdk_bgxx_gmp_gmi_prtx_cfg_t
7354 #define bustype_BDK_BGXX_GMP_GMI_PRTX_CFG(a,b) BDK_CSR_TYPE_RSL
7355 #define basename_BDK_BGXX_GMP_GMI_PRTX_CFG(a,b) "BGXX_GMP_GMI_PRTX_CFG"
7356 #define device_bar_BDK_BGXX_GMP_GMI_PRTX_CFG(a,b) 0x0 /* PF_BAR0 */
7357 #define busnum_BDK_BGXX_GMP_GMI_PRTX_CFG(a,b) (a)
7358 #define arguments_BDK_BGXX_GMP_GMI_PRTX_CFG(a,b) (a),(b),-1,-1
7359 
7360 /**
7361  * Register (RSL) bgx#_gmp_gmi_rx#_decision
7362  *
7363  * BGX GMP Packet-Decision Registers
7364  * This register specifies the byte count used to determine when to accept or to filter a packet.
7365  * As each byte in a packet is received by GMI, the L2 byte count is compared against
7366  * [CNT]. In normal operation, the L2 header begins after the
7367  * PREAMBLE + SFD (BGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] = 1) and any optional UDD skip
7368  * data (BGX()_GMP_GMI_RX()_UDD_SKP[LEN]).
7369  *
7370  * Internal:
7371  * Notes:
7372  * As each byte in a packet is received by GMI, the L2 byte count is compared
7373  * against the [CNT].  The L2 byte count is the number of bytes
7374  * from the beginning of the L2 header (DMAC).  In normal operation, the L2
7375  * header begins after the PREAMBLE+SFD (BGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK]=1) and any
7376  * optional UDD skip data (BGX()_GMP_GMI_RX()_UDD_SKP[LEN]).
7377  * When BGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the
7378  * packet and would require UDD skip length to account for them.
7379  *
7380  * Full Duplex:
7381  * _   L2 Size \<  [CNT] - Accept packet. No filtering is applied.
7382  * _   L2 Size \>= [CNT] - Apply filter. Accept packet based on PAUSE packet filter.
7383  *
7384  * Half Duplex:
7385  * _   L2 Size \<  [CNT] - Drop packet. Packet is unconditionally dropped.
7386  * _   L2 Size \>= [CNT] - Accept packet.
7387  *
7388  * where L2_size = MAX(0, total_packet_size - BGX()_GMP_GMI_RX()_UDD_SKP[LEN] -
7389  *                        ((BGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK]==1)*8))
7390  */
7391 union bdk_bgxx_gmp_gmi_rxx_decision
7392 {
7393     uint64_t u;
7394     struct bdk_bgxx_gmp_gmi_rxx_decision_s
7395     {
7396 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7397         uint64_t reserved_5_63         : 59;
7398         uint64_t cnt                   : 5;  /**< [  4:  0](R/W) The byte count used to decide when to accept or filter a packet. */
7399 #else /* Word 0 - Little Endian */
7400         uint64_t cnt                   : 5;  /**< [  4:  0](R/W) The byte count used to decide when to accept or filter a packet. */
7401         uint64_t reserved_5_63         : 59;
7402 #endif /* Word 0 - End */
7403     } s;
7404     /* struct bdk_bgxx_gmp_gmi_rxx_decision_s cn; */
7405 };
7406 typedef union bdk_bgxx_gmp_gmi_rxx_decision bdk_bgxx_gmp_gmi_rxx_decision_t;
7407 
7408 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_DECISION(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_DECISION(unsigned long a,unsigned long b)7409 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_DECISION(unsigned long a, unsigned long b)
7410 {
7411     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
7412         return 0x87e0e0038040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7413     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
7414         return 0x87e0e0038040ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
7415     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
7416         return 0x87e0e0038040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7417     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_DECISION", 2, a, b, 0, 0);
7418 }
7419 
7420 #define typedef_BDK_BGXX_GMP_GMI_RXX_DECISION(a,b) bdk_bgxx_gmp_gmi_rxx_decision_t
7421 #define bustype_BDK_BGXX_GMP_GMI_RXX_DECISION(a,b) BDK_CSR_TYPE_RSL
7422 #define basename_BDK_BGXX_GMP_GMI_RXX_DECISION(a,b) "BGXX_GMP_GMI_RXX_DECISION"
7423 #define device_bar_BDK_BGXX_GMP_GMI_RXX_DECISION(a,b) 0x0 /* PF_BAR0 */
7424 #define busnum_BDK_BGXX_GMP_GMI_RXX_DECISION(a,b) (a)
7425 #define arguments_BDK_BGXX_GMP_GMI_RXX_DECISION(a,b) (a),(b),-1,-1
7426 
7427 /**
7428  * Register (RSL) bgx#_gmp_gmi_rx#_frm_chk
7429  *
7430  * BGX GMP Frame Check Registers
7431  */
7432 union bdk_bgxx_gmp_gmi_rxx_frm_chk
7433 {
7434     uint64_t u;
7435     struct bdk_bgxx_gmp_gmi_rxx_frm_chk_s
7436     {
7437 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7438         uint64_t reserved_9_63         : 55;
7439         uint64_t skperr                : 1;  /**< [  8:  8](R/W) Skipper error. */
7440         uint64_t rcverr                : 1;  /**< [  7:  7](R/W) Frame was received with data-reception error. */
7441         uint64_t reserved_5_6          : 2;
7442         uint64_t fcserr                : 1;  /**< [  4:  4](R/W) Frame was received with FCS/CRC error. */
7443         uint64_t jabber                : 1;  /**< [  3:  3](R/W) Frame was received with length \> sys_length. */
7444         uint64_t reserved_2            : 1;
7445         uint64_t carext                : 1;  /**< [  1:  1](R/W) Carrier extend error. SGMII/QSGMII/1000Base-X only. */
7446         uint64_t minerr                : 1;  /**< [  0:  0](R/W) PAUSE frame was received with length \< minFrameSize. */
7447 #else /* Word 0 - Little Endian */
7448         uint64_t minerr                : 1;  /**< [  0:  0](R/W) PAUSE frame was received with length \< minFrameSize. */
7449         uint64_t carext                : 1;  /**< [  1:  1](R/W) Carrier extend error. SGMII/QSGMII/1000Base-X only. */
7450         uint64_t reserved_2            : 1;
7451         uint64_t jabber                : 1;  /**< [  3:  3](R/W) Frame was received with length \> sys_length. */
7452         uint64_t fcserr                : 1;  /**< [  4:  4](R/W) Frame was received with FCS/CRC error. */
7453         uint64_t reserved_5_6          : 2;
7454         uint64_t rcverr                : 1;  /**< [  7:  7](R/W) Frame was received with data-reception error. */
7455         uint64_t skperr                : 1;  /**< [  8:  8](R/W) Skipper error. */
7456         uint64_t reserved_9_63         : 55;
7457 #endif /* Word 0 - End */
7458     } s;
7459     /* struct bdk_bgxx_gmp_gmi_rxx_frm_chk_s cn81xx; */
7460     struct bdk_bgxx_gmp_gmi_rxx_frm_chk_cn88xx
7461     {
7462 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7463         uint64_t reserved_9_63         : 55;
7464         uint64_t skperr                : 1;  /**< [  8:  8](R/W) Skipper error. */
7465         uint64_t rcverr                : 1;  /**< [  7:  7](R/W) Frame was received with data-reception error. */
7466         uint64_t reserved_5_6          : 2;
7467         uint64_t fcserr                : 1;  /**< [  4:  4](R/W) Frame was received with FCS/CRC error. */
7468         uint64_t jabber                : 1;  /**< [  3:  3](R/W) Frame was received with length \> sys_length. */
7469         uint64_t reserved_2            : 1;
7470         uint64_t carext                : 1;  /**< [  1:  1](R/W) Carrier extend error. SGMII/1000Base-X only. */
7471         uint64_t minerr                : 1;  /**< [  0:  0](R/W) PAUSE frame was received with length \< minFrameSize. */
7472 #else /* Word 0 - Little Endian */
7473         uint64_t minerr                : 1;  /**< [  0:  0](R/W) PAUSE frame was received with length \< minFrameSize. */
7474         uint64_t carext                : 1;  /**< [  1:  1](R/W) Carrier extend error. SGMII/1000Base-X only. */
7475         uint64_t reserved_2            : 1;
7476         uint64_t jabber                : 1;  /**< [  3:  3](R/W) Frame was received with length \> sys_length. */
7477         uint64_t fcserr                : 1;  /**< [  4:  4](R/W) Frame was received with FCS/CRC error. */
7478         uint64_t reserved_5_6          : 2;
7479         uint64_t rcverr                : 1;  /**< [  7:  7](R/W) Frame was received with data-reception error. */
7480         uint64_t skperr                : 1;  /**< [  8:  8](R/W) Skipper error. */
7481         uint64_t reserved_9_63         : 55;
7482 #endif /* Word 0 - End */
7483     } cn88xx;
7484     /* struct bdk_bgxx_gmp_gmi_rxx_frm_chk_s cn83xx; */
7485 };
7486 typedef union bdk_bgxx_gmp_gmi_rxx_frm_chk bdk_bgxx_gmp_gmi_rxx_frm_chk_t;
7487 
7488 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_FRM_CHK(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_FRM_CHK(unsigned long a,unsigned long b)7489 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_FRM_CHK(unsigned long a, unsigned long b)
7490 {
7491     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
7492         return 0x87e0e0038030ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7493     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
7494         return 0x87e0e0038030ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
7495     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
7496         return 0x87e0e0038030ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7497     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_FRM_CHK", 2, a, b, 0, 0);
7498 }
7499 
7500 #define typedef_BDK_BGXX_GMP_GMI_RXX_FRM_CHK(a,b) bdk_bgxx_gmp_gmi_rxx_frm_chk_t
7501 #define bustype_BDK_BGXX_GMP_GMI_RXX_FRM_CHK(a,b) BDK_CSR_TYPE_RSL
7502 #define basename_BDK_BGXX_GMP_GMI_RXX_FRM_CHK(a,b) "BGXX_GMP_GMI_RXX_FRM_CHK"
7503 #define device_bar_BDK_BGXX_GMP_GMI_RXX_FRM_CHK(a,b) 0x0 /* PF_BAR0 */
7504 #define busnum_BDK_BGXX_GMP_GMI_RXX_FRM_CHK(a,b) (a)
7505 #define arguments_BDK_BGXX_GMP_GMI_RXX_FRM_CHK(a,b) (a),(b),-1,-1
7506 
7507 /**
7508  * Register (RSL) bgx#_gmp_gmi_rx#_frm_ctl
7509  *
7510  * BGX GMP Frame Control Registers
7511  * This register controls the handling of the frames.
7512  * The [CTL_BCK] and [CTL_DRP] bits control how the hardware handles incoming PAUSE packets. The
7513  * most
7514  * common modes of operation:
7515  * _ [CTL_BCK] = 1, [CTL_DRP] = 1: hardware handles everything.
7516  * _ [CTL_BCK] = 0, [CTL_DRP] = 0: software sees all PAUSE frames.
7517  * _ [CTL_BCK] = 0, [CTL_DRP] = 1: all PAUSE frames are completely ignored.
7518  *
7519  * These control bits should be set to [CTL_BCK] = 0, [CTL_DRP] = 0 in half-duplex mode. Since
7520  * PAUSE
7521  * packets only apply to full duplex operation, any PAUSE packet would constitute an exception
7522  * which should be handled by the processing cores. PAUSE packets should not be forwarded.
7523  *
7524  * Internal:
7525  * Notes:
7526  * [PRE_STRP]:
7527  * When [PRE_CHK] is set (indicating that the PREAMBLE will be sent), [PRE_STRP]
7528  * determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane
7529  * core as part of the packet.
7530  * In either mode, the PREAMBLE+SFD bytes are not counted toward the packet
7531  * size when checking against the MIN and MAX bounds.  Furthermore, the bytes
7532  * are skipped when locating the start of the L2 header for DMAC and Control
7533  * frame recognition.
7534  */
7535 union bdk_bgxx_gmp_gmi_rxx_frm_ctl
7536 {
7537     uint64_t u;
7538     struct bdk_bgxx_gmp_gmi_rxx_frm_ctl_s
7539     {
7540 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7541         uint64_t reserved_14_63        : 50;
7542         uint64_t rx_fc_type            : 1;  /**< [ 13: 13](R/W) Receive side flow control type select.
7543                                                                  0 = GMI MAC receives and processes ITU G.999.1 pause frames.
7544                                                                  1 = GMI MAC receives and processes 802.3 pause frames. */
7545         uint64_t ptp_mode              : 1;  /**< [ 12: 12](R/W) Timestamp mode. When [PTP_MODE] is set, a 64-bit timestamp is prepended to every incoming
7546                                                                  packet.
7547 
7548                                                                  The timestamp bytes are added to the packet in such a way as to not modify the packet's
7549                                                                  receive byte count. This implies that the BGX()_GMP_GMI_RX()_JABBER,
7550                                                                  BGX()_GMP_GMI_RX()_DECISION, BGX()_GMP_GMI_RX()_UDD_SKP, and
7551                                                                  BGX()_CMR()_RX_STAT0..BGX()_CMR()_RX_STAT8
7552                                                                  do not require any adjustment as they operate on the received
7553                                                                  packet size. When the packet reaches NIC, its size reflects the additional bytes. */
7554         uint64_t reserved_11           : 1;
7555         uint64_t null_dis              : 1;  /**< [ 10: 10](R/W) When set, do not modify the MOD bits on NULL ticks due to partial packets. */
7556         uint64_t pre_align             : 1;  /**< [  9:  9](R/W) When set, PREAMBLE parser aligns the SFD byte regardless of the number of previous
7557                                                                  PREAMBLE nibbles. In this mode, [PRE_STRP] should be set to account for the variable
7558                                                                  nature of the PREAMBLE. [PRE_CHK] must be set to enable this and all PREAMBLE features.
7559                                                                  SGMII at 10/100Mbs only. */
7560         uint64_t reserved_7_8          : 2;
7561         uint64_t pre_free              : 1;  /**< [  6:  6](RO/H) When set, PREAMBLE checking is less strict. GMI will begin the frame at the first SFD.
7562                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features. SGMII/QSGMII/1000Base-X
7563                                                                  only. */
7564         uint64_t ctl_smac              : 1;  /**< [  5:  5](R/W) Control PAUSE frames can match station SMAC. */
7565         uint64_t ctl_mcst              : 1;  /**< [  4:  4](R/W) Control PAUSE frames can match globally assigned multicast address. */
7566         uint64_t ctl_bck               : 1;  /**< [  3:  3](R/W) Forward PAUSE information to TX block. */
7567         uint64_t ctl_drp               : 1;  /**< [  2:  2](R/W) Drop control-PAUSE frames. */
7568         uint64_t pre_strp              : 1;  /**< [  1:  1](R/W) Strip off the preamble (when present).
7569                                                                  0 = PREAMBLE + SFD is sent to core as part of frame.
7570                                                                  1 = PREAMBLE + SFD is dropped.
7571                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features.
7572 
7573                                                                  If [PTP_MODE]=1 and [PRE_CHK]=1, [PRE_STRP] must be 1.
7574 
7575                                                                  When [PRE_CHK] is set (indicating that the PREAMBLE will be sent), [PRE_STRP] determines
7576                                                                  if
7577                                                                  the PREAMBLE+SFD bytes are thrown away or sent to the core as part of the packet. In
7578                                                                  either mode, the PREAMBLE+SFD bytes are not counted toward the packet size when checking
7579                                                                  against the MIN and MAX bounds. Furthermore, the bytes are skipped when locating the start
7580                                                                  of the L2 header for DMAC and control frame recognition. */
7581         uint64_t pre_chk               : 1;  /**< [  0:  0](R/W) Check the preamble for correctness. This port is configured to send a valid 802.3 PREAMBLE
7582                                                                  to begin every frame. GMI checks that a valid PREAMBLE is received (based on [PRE_FREE]).
7583                                                                  When a problem does occur within the PREAMBLE sequence, the frame is marked as bad and not
7584                                                                  sent into the core. The BGX()_GMP()_RX_INT[PCTERR] interrupt is also raised. */
7585 #else /* Word 0 - Little Endian */
7586         uint64_t pre_chk               : 1;  /**< [  0:  0](R/W) Check the preamble for correctness. This port is configured to send a valid 802.3 PREAMBLE
7587                                                                  to begin every frame. GMI checks that a valid PREAMBLE is received (based on [PRE_FREE]).
7588                                                                  When a problem does occur within the PREAMBLE sequence, the frame is marked as bad and not
7589                                                                  sent into the core. The BGX()_GMP()_RX_INT[PCTERR] interrupt is also raised. */
7590         uint64_t pre_strp              : 1;  /**< [  1:  1](R/W) Strip off the preamble (when present).
7591                                                                  0 = PREAMBLE + SFD is sent to core as part of frame.
7592                                                                  1 = PREAMBLE + SFD is dropped.
7593                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features.
7594 
7595                                                                  If [PTP_MODE]=1 and [PRE_CHK]=1, [PRE_STRP] must be 1.
7596 
7597                                                                  When [PRE_CHK] is set (indicating that the PREAMBLE will be sent), [PRE_STRP] determines
7598                                                                  if
7599                                                                  the PREAMBLE+SFD bytes are thrown away or sent to the core as part of the packet. In
7600                                                                  either mode, the PREAMBLE+SFD bytes are not counted toward the packet size when checking
7601                                                                  against the MIN and MAX bounds. Furthermore, the bytes are skipped when locating the start
7602                                                                  of the L2 header for DMAC and control frame recognition. */
7603         uint64_t ctl_drp               : 1;  /**< [  2:  2](R/W) Drop control-PAUSE frames. */
7604         uint64_t ctl_bck               : 1;  /**< [  3:  3](R/W) Forward PAUSE information to TX block. */
7605         uint64_t ctl_mcst              : 1;  /**< [  4:  4](R/W) Control PAUSE frames can match globally assigned multicast address. */
7606         uint64_t ctl_smac              : 1;  /**< [  5:  5](R/W) Control PAUSE frames can match station SMAC. */
7607         uint64_t pre_free              : 1;  /**< [  6:  6](RO/H) When set, PREAMBLE checking is less strict. GMI will begin the frame at the first SFD.
7608                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features. SGMII/QSGMII/1000Base-X
7609                                                                  only. */
7610         uint64_t reserved_7_8          : 2;
7611         uint64_t pre_align             : 1;  /**< [  9:  9](R/W) When set, PREAMBLE parser aligns the SFD byte regardless of the number of previous
7612                                                                  PREAMBLE nibbles. In this mode, [PRE_STRP] should be set to account for the variable
7613                                                                  nature of the PREAMBLE. [PRE_CHK] must be set to enable this and all PREAMBLE features.
7614                                                                  SGMII at 10/100Mbs only. */
7615         uint64_t null_dis              : 1;  /**< [ 10: 10](R/W) When set, do not modify the MOD bits on NULL ticks due to partial packets. */
7616         uint64_t reserved_11           : 1;
7617         uint64_t ptp_mode              : 1;  /**< [ 12: 12](R/W) Timestamp mode. When [PTP_MODE] is set, a 64-bit timestamp is prepended to every incoming
7618                                                                  packet.
7619 
7620                                                                  The timestamp bytes are added to the packet in such a way as to not modify the packet's
7621                                                                  receive byte count. This implies that the BGX()_GMP_GMI_RX()_JABBER,
7622                                                                  BGX()_GMP_GMI_RX()_DECISION, BGX()_GMP_GMI_RX()_UDD_SKP, and
7623                                                                  BGX()_CMR()_RX_STAT0..BGX()_CMR()_RX_STAT8
7624                                                                  do not require any adjustment as they operate on the received
7625                                                                  packet size. When the packet reaches NIC, its size reflects the additional bytes. */
7626         uint64_t rx_fc_type            : 1;  /**< [ 13: 13](R/W) Receive side flow control type select.
7627                                                                  0 = GMI MAC receives and processes ITU G.999.1 pause frames.
7628                                                                  1 = GMI MAC receives and processes 802.3 pause frames. */
7629         uint64_t reserved_14_63        : 50;
7630 #endif /* Word 0 - End */
7631     } s;
7632     struct bdk_bgxx_gmp_gmi_rxx_frm_ctl_cn81xx
7633     {
7634 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7635         uint64_t reserved_14_63        : 50;
7636         uint64_t rx_fc_type            : 1;  /**< [ 13: 13](R/W) Receive side flow control type select.
7637                                                                  0 = GMI MAC receives and processes ITU G.999.1 pause frames.
7638                                                                  1 = GMI MAC receives and processes 802.3 pause frames. */
7639         uint64_t ptp_mode              : 1;  /**< [ 12: 12](R/W) Timestamp mode. When [PTP_MODE] is set, a 64-bit timestamp is prepended to every incoming
7640                                                                  packet.
7641 
7642                                                                  The timestamp bytes are added to the packet in such a way as to not modify the packet's
7643                                                                  receive byte count. This implies that the BGX()_GMP_GMI_RX()_JABBER,
7644                                                                  BGX()_GMP_GMI_RX()_DECISION, BGX()_GMP_GMI_RX()_UDD_SKP, and
7645                                                                  BGX()_CMR()_RX_STAT0..BGX()_CMR()_RX_STAT8
7646                                                                  do not require any adjustment as they operate on the received
7647                                                                  packet size. When the packet reaches NIC, its size reflects the additional bytes. */
7648         uint64_t reserved_11           : 1;
7649         uint64_t null_dis              : 1;  /**< [ 10: 10](R/W) When set, do not modify the MOD bits on NULL ticks due to partial packets. */
7650         uint64_t pre_align             : 1;  /**< [  9:  9](R/W) When set, PREAMBLE parser aligns the SFD byte regardless of the number of previous
7651                                                                  PREAMBLE nibbles. In this mode, [PRE_STRP] should be set to account for the variable
7652                                                                  nature of the PREAMBLE. [PRE_CHK] must be set to enable this and all PREAMBLE features.
7653                                                                  SGMII at 10/100Mbs only. */
7654         uint64_t reserved_8            : 1;
7655         uint64_t reserved_7            : 1;
7656         uint64_t pre_free              : 1;  /**< [  6:  6](RO/H) When set, PREAMBLE checking is less strict. GMI will begin the frame at the first SFD.
7657                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features. SGMII/QSGMII/1000Base-X
7658                                                                  only. */
7659         uint64_t ctl_smac              : 1;  /**< [  5:  5](R/W) Control PAUSE frames can match station SMAC. */
7660         uint64_t ctl_mcst              : 1;  /**< [  4:  4](R/W) Control PAUSE frames can match globally assigned multicast address. */
7661         uint64_t ctl_bck               : 1;  /**< [  3:  3](R/W) Forward PAUSE information to TX block. */
7662         uint64_t ctl_drp               : 1;  /**< [  2:  2](R/W) Drop control-PAUSE frames. */
7663         uint64_t pre_strp              : 1;  /**< [  1:  1](R/W) Strip off the preamble (when present).
7664                                                                  0 = PREAMBLE + SFD is sent to core as part of frame.
7665                                                                  1 = PREAMBLE + SFD is dropped.
7666                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features.
7667 
7668                                                                  If [PTP_MODE]=1 and [PRE_CHK]=1, [PRE_STRP] must be 1.
7669 
7670                                                                  When [PRE_CHK] is set (indicating that the PREAMBLE will be sent), [PRE_STRP] determines
7671                                                                  if
7672                                                                  the PREAMBLE+SFD bytes are thrown away or sent to the core as part of the packet. In
7673                                                                  either mode, the PREAMBLE+SFD bytes are not counted toward the packet size when checking
7674                                                                  against the MIN and MAX bounds. Furthermore, the bytes are skipped when locating the start
7675                                                                  of the L2 header for DMAC and control frame recognition. */
7676         uint64_t pre_chk               : 1;  /**< [  0:  0](R/W) Check the preamble for correctness. This port is configured to send a valid 802.3 PREAMBLE
7677                                                                  to begin every frame. GMI checks that a valid PREAMBLE is received (based on [PRE_FREE]).
7678                                                                  When a problem does occur within the PREAMBLE sequence, the frame is marked as bad and not
7679                                                                  sent into the core. The BGX()_GMP()_RX_INT[PCTERR] interrupt is also raised. */
7680 #else /* Word 0 - Little Endian */
7681         uint64_t pre_chk               : 1;  /**< [  0:  0](R/W) Check the preamble for correctness. This port is configured to send a valid 802.3 PREAMBLE
7682                                                                  to begin every frame. GMI checks that a valid PREAMBLE is received (based on [PRE_FREE]).
7683                                                                  When a problem does occur within the PREAMBLE sequence, the frame is marked as bad and not
7684                                                                  sent into the core. The BGX()_GMP()_RX_INT[PCTERR] interrupt is also raised. */
7685         uint64_t pre_strp              : 1;  /**< [  1:  1](R/W) Strip off the preamble (when present).
7686                                                                  0 = PREAMBLE + SFD is sent to core as part of frame.
7687                                                                  1 = PREAMBLE + SFD is dropped.
7688                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features.
7689 
7690                                                                  If [PTP_MODE]=1 and [PRE_CHK]=1, [PRE_STRP] must be 1.
7691 
7692                                                                  When [PRE_CHK] is set (indicating that the PREAMBLE will be sent), [PRE_STRP] determines
7693                                                                  if
7694                                                                  the PREAMBLE+SFD bytes are thrown away or sent to the core as part of the packet. In
7695                                                                  either mode, the PREAMBLE+SFD bytes are not counted toward the packet size when checking
7696                                                                  against the MIN and MAX bounds. Furthermore, the bytes are skipped when locating the start
7697                                                                  of the L2 header for DMAC and control frame recognition. */
7698         uint64_t ctl_drp               : 1;  /**< [  2:  2](R/W) Drop control-PAUSE frames. */
7699         uint64_t ctl_bck               : 1;  /**< [  3:  3](R/W) Forward PAUSE information to TX block. */
7700         uint64_t ctl_mcst              : 1;  /**< [  4:  4](R/W) Control PAUSE frames can match globally assigned multicast address. */
7701         uint64_t ctl_smac              : 1;  /**< [  5:  5](R/W) Control PAUSE frames can match station SMAC. */
7702         uint64_t pre_free              : 1;  /**< [  6:  6](RO/H) When set, PREAMBLE checking is less strict. GMI will begin the frame at the first SFD.
7703                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features. SGMII/QSGMII/1000Base-X
7704                                                                  only. */
7705         uint64_t reserved_7            : 1;
7706         uint64_t reserved_8            : 1;
7707         uint64_t pre_align             : 1;  /**< [  9:  9](R/W) When set, PREAMBLE parser aligns the SFD byte regardless of the number of previous
7708                                                                  PREAMBLE nibbles. In this mode, [PRE_STRP] should be set to account for the variable
7709                                                                  nature of the PREAMBLE. [PRE_CHK] must be set to enable this and all PREAMBLE features.
7710                                                                  SGMII at 10/100Mbs only. */
7711         uint64_t null_dis              : 1;  /**< [ 10: 10](R/W) When set, do not modify the MOD bits on NULL ticks due to partial packets. */
7712         uint64_t reserved_11           : 1;
7713         uint64_t ptp_mode              : 1;  /**< [ 12: 12](R/W) Timestamp mode. When [PTP_MODE] is set, a 64-bit timestamp is prepended to every incoming
7714                                                                  packet.
7715 
7716                                                                  The timestamp bytes are added to the packet in such a way as to not modify the packet's
7717                                                                  receive byte count. This implies that the BGX()_GMP_GMI_RX()_JABBER,
7718                                                                  BGX()_GMP_GMI_RX()_DECISION, BGX()_GMP_GMI_RX()_UDD_SKP, and
7719                                                                  BGX()_CMR()_RX_STAT0..BGX()_CMR()_RX_STAT8
7720                                                                  do not require any adjustment as they operate on the received
7721                                                                  packet size. When the packet reaches NIC, its size reflects the additional bytes. */
7722         uint64_t rx_fc_type            : 1;  /**< [ 13: 13](R/W) Receive side flow control type select.
7723                                                                  0 = GMI MAC receives and processes ITU G.999.1 pause frames.
7724                                                                  1 = GMI MAC receives and processes 802.3 pause frames. */
7725         uint64_t reserved_14_63        : 50;
7726 #endif /* Word 0 - End */
7727     } cn81xx;
7728     struct bdk_bgxx_gmp_gmi_rxx_frm_ctl_cn88xx
7729     {
7730 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7731         uint64_t reserved_13_63        : 51;
7732         uint64_t ptp_mode              : 1;  /**< [ 12: 12](R/W) Timestamp mode. When [PTP_MODE] is set, a 64-bit timestamp is prepended to every incoming
7733                                                                  packet.
7734 
7735                                                                  The timestamp bytes are added to the packet in such a way as to not modify the packet's
7736                                                                  receive byte count. This implies that the BGX()_GMP_GMI_RX()_JABBER,
7737                                                                  BGX()_GMP_GMI_RX()_DECISION, BGX()_GMP_GMI_RX()_UDD_SKP, and
7738                                                                  BGX()_CMR()_RX_STAT0..BGX()_CMR()_RX_STAT8
7739                                                                  do not require any adjustment as they operate on the received
7740                                                                  packet size. When the packet reaches NIC, its size reflects the additional bytes. */
7741         uint64_t reserved_11           : 1;
7742         uint64_t null_dis              : 1;  /**< [ 10: 10](R/W) When set, do not modify the MOD bits on NULL ticks due to partial packets. */
7743         uint64_t pre_align             : 1;  /**< [  9:  9](R/W) When set, PREAMBLE parser aligns the SFD byte regardless of the number of previous
7744                                                                  PREAMBLE nibbles. In this mode, [PRE_STRP] should be set to account for the variable
7745                                                                  nature of the PREAMBLE. [PRE_CHK] must be set to enable this and all PREAMBLE features.
7746                                                                  SGMII at 10/100Mbs only. */
7747         uint64_t reserved_8            : 1;
7748         uint64_t reserved_7            : 1;
7749         uint64_t pre_free              : 1;  /**< [  6:  6](RO/H) When set, PREAMBLE checking is less strict. GMI will begin the frame at the first SFD.
7750                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features. SGMII/1000Base-X only. */
7751         uint64_t ctl_smac              : 1;  /**< [  5:  5](R/W) Control PAUSE frames can match station SMAC. */
7752         uint64_t ctl_mcst              : 1;  /**< [  4:  4](R/W) Control PAUSE frames can match globally assigned multicast address. */
7753         uint64_t ctl_bck               : 1;  /**< [  3:  3](R/W) Forward PAUSE information to TX block. */
7754         uint64_t ctl_drp               : 1;  /**< [  2:  2](R/W) Drop control-PAUSE frames. */
7755         uint64_t pre_strp              : 1;  /**< [  1:  1](R/W) Strip off the preamble (when present).
7756                                                                  0 = PREAMBLE + SFD is sent to core as part of frame.
7757                                                                  1 = PREAMBLE + SFD is dropped.
7758                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features.
7759 
7760                                                                  If [PTP_MODE]=1 and [PRE_CHK]=1, [PRE_STRP] must be 1.
7761 
7762                                                                  When [PRE_CHK] is set (indicating that the PREAMBLE will be sent), [PRE_STRP] determines
7763                                                                  if
7764                                                                  the PREAMBLE+SFD bytes are thrown away or sent to the core as part of the packet. In
7765                                                                  either mode, the PREAMBLE+SFD bytes are not counted toward the packet size when checking
7766                                                                  against the MIN and MAX bounds. Furthermore, the bytes are skipped when locating the start
7767                                                                  of the L2 header for DMAC and control frame recognition. */
7768         uint64_t pre_chk               : 1;  /**< [  0:  0](R/W) Check the preamble for correctness. This port is configured to send a valid 802.3 PREAMBLE
7769                                                                  to begin every frame. GMI checks that a valid PREAMBLE is received (based on [PRE_FREE]).
7770                                                                  When a problem does occur within the PREAMBLE sequence, the frame is marked as bad and not
7771                                                                  sent into the core. The BGX()_SMU()_RX_INT[PCTERR] interrupt is also raised.
7772 
7773                                                                  When BGX()_SMU()_TX_CTL[HG_EN] is set, [PRE_CHK] must be 0. If [PTP_MODE] = 1 and
7774                                                                  [PRE_CHK] = 1, [PRE_STRP] must be 1. */
7775 #else /* Word 0 - Little Endian */
7776         uint64_t pre_chk               : 1;  /**< [  0:  0](R/W) Check the preamble for correctness. This port is configured to send a valid 802.3 PREAMBLE
7777                                                                  to begin every frame. GMI checks that a valid PREAMBLE is received (based on [PRE_FREE]).
7778                                                                  When a problem does occur within the PREAMBLE sequence, the frame is marked as bad and not
7779                                                                  sent into the core. The BGX()_SMU()_RX_INT[PCTERR] interrupt is also raised.
7780 
7781                                                                  When BGX()_SMU()_TX_CTL[HG_EN] is set, [PRE_CHK] must be 0. If [PTP_MODE] = 1 and
7782                                                                  [PRE_CHK] = 1, [PRE_STRP] must be 1. */
7783         uint64_t pre_strp              : 1;  /**< [  1:  1](R/W) Strip off the preamble (when present).
7784                                                                  0 = PREAMBLE + SFD is sent to core as part of frame.
7785                                                                  1 = PREAMBLE + SFD is dropped.
7786                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features.
7787 
7788                                                                  If [PTP_MODE]=1 and [PRE_CHK]=1, [PRE_STRP] must be 1.
7789 
7790                                                                  When [PRE_CHK] is set (indicating that the PREAMBLE will be sent), [PRE_STRP] determines
7791                                                                  if
7792                                                                  the PREAMBLE+SFD bytes are thrown away or sent to the core as part of the packet. In
7793                                                                  either mode, the PREAMBLE+SFD bytes are not counted toward the packet size when checking
7794                                                                  against the MIN and MAX bounds. Furthermore, the bytes are skipped when locating the start
7795                                                                  of the L2 header for DMAC and control frame recognition. */
7796         uint64_t ctl_drp               : 1;  /**< [  2:  2](R/W) Drop control-PAUSE frames. */
7797         uint64_t ctl_bck               : 1;  /**< [  3:  3](R/W) Forward PAUSE information to TX block. */
7798         uint64_t ctl_mcst              : 1;  /**< [  4:  4](R/W) Control PAUSE frames can match globally assigned multicast address. */
7799         uint64_t ctl_smac              : 1;  /**< [  5:  5](R/W) Control PAUSE frames can match station SMAC. */
7800         uint64_t pre_free              : 1;  /**< [  6:  6](RO/H) When set, PREAMBLE checking is less strict. GMI will begin the frame at the first SFD.
7801                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features. SGMII/1000Base-X only. */
7802         uint64_t reserved_7            : 1;
7803         uint64_t reserved_8            : 1;
7804         uint64_t pre_align             : 1;  /**< [  9:  9](R/W) When set, PREAMBLE parser aligns the SFD byte regardless of the number of previous
7805                                                                  PREAMBLE nibbles. In this mode, [PRE_STRP] should be set to account for the variable
7806                                                                  nature of the PREAMBLE. [PRE_CHK] must be set to enable this and all PREAMBLE features.
7807                                                                  SGMII at 10/100Mbs only. */
7808         uint64_t null_dis              : 1;  /**< [ 10: 10](R/W) When set, do not modify the MOD bits on NULL ticks due to partial packets. */
7809         uint64_t reserved_11           : 1;
7810         uint64_t ptp_mode              : 1;  /**< [ 12: 12](R/W) Timestamp mode. When [PTP_MODE] is set, a 64-bit timestamp is prepended to every incoming
7811                                                                  packet.
7812 
7813                                                                  The timestamp bytes are added to the packet in such a way as to not modify the packet's
7814                                                                  receive byte count. This implies that the BGX()_GMP_GMI_RX()_JABBER,
7815                                                                  BGX()_GMP_GMI_RX()_DECISION, BGX()_GMP_GMI_RX()_UDD_SKP, and
7816                                                                  BGX()_CMR()_RX_STAT0..BGX()_CMR()_RX_STAT8
7817                                                                  do not require any adjustment as they operate on the received
7818                                                                  packet size. When the packet reaches NIC, its size reflects the additional bytes. */
7819         uint64_t reserved_13_63        : 51;
7820 #endif /* Word 0 - End */
7821     } cn88xx;
7822     /* struct bdk_bgxx_gmp_gmi_rxx_frm_ctl_cn81xx cn83xx; */
7823 };
7824 typedef union bdk_bgxx_gmp_gmi_rxx_frm_ctl bdk_bgxx_gmp_gmi_rxx_frm_ctl_t;
7825 
7826 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_FRM_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_FRM_CTL(unsigned long a,unsigned long b)7827 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_FRM_CTL(unsigned long a, unsigned long b)
7828 {
7829     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
7830         return 0x87e0e0038028ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7831     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
7832         return 0x87e0e0038028ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
7833     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
7834         return 0x87e0e0038028ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7835     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_FRM_CTL", 2, a, b, 0, 0);
7836 }
7837 
7838 #define typedef_BDK_BGXX_GMP_GMI_RXX_FRM_CTL(a,b) bdk_bgxx_gmp_gmi_rxx_frm_ctl_t
7839 #define bustype_BDK_BGXX_GMP_GMI_RXX_FRM_CTL(a,b) BDK_CSR_TYPE_RSL
7840 #define basename_BDK_BGXX_GMP_GMI_RXX_FRM_CTL(a,b) "BGXX_GMP_GMI_RXX_FRM_CTL"
7841 #define device_bar_BDK_BGXX_GMP_GMI_RXX_FRM_CTL(a,b) 0x0 /* PF_BAR0 */
7842 #define busnum_BDK_BGXX_GMP_GMI_RXX_FRM_CTL(a,b) (a)
7843 #define arguments_BDK_BGXX_GMP_GMI_RXX_FRM_CTL(a,b) (a),(b),-1,-1
7844 
7845 /**
7846  * Register (RSL) bgx#_gmp_gmi_rx#_ifg
7847  *
7848  * BGX GMI Minimum Interframe-Gap Cycles Registers
7849  * This register specifies the minimum number of interframe-gap (IFG) cycles between packets.
7850  */
7851 union bdk_bgxx_gmp_gmi_rxx_ifg
7852 {
7853     uint64_t u;
7854     struct bdk_bgxx_gmp_gmi_rxx_ifg_s
7855     {
7856 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7857         uint64_t reserved_4_63         : 60;
7858         uint64_t ifg                   : 4;  /**< [  3:  0](R/W) Min IFG (in IFG * 8 bits) between packets used to determine IFGERR. Normally IFG is 96
7859                                                                  bits. Values 0x1 or smaller are illegal.
7860 
7861                                                                  Note that in some operating modes, IFG cycles can be inserted or removed in order to
7862                                                                  achieve clock rate adaptation. For these reasons, the default value is slightly
7863                                                                  conservative and does not check up to the full 96 bits of IFG.
7864                                                                  (SGMII/QSGMII/1000Base-X only) */
7865 #else /* Word 0 - Little Endian */
7866         uint64_t ifg                   : 4;  /**< [  3:  0](R/W) Min IFG (in IFG * 8 bits) between packets used to determine IFGERR. Normally IFG is 96
7867                                                                  bits. Values 0x1 or smaller are illegal.
7868 
7869                                                                  Note that in some operating modes, IFG cycles can be inserted or removed in order to
7870                                                                  achieve clock rate adaptation. For these reasons, the default value is slightly
7871                                                                  conservative and does not check up to the full 96 bits of IFG.
7872                                                                  (SGMII/QSGMII/1000Base-X only) */
7873         uint64_t reserved_4_63         : 60;
7874 #endif /* Word 0 - End */
7875     } s;
7876     /* struct bdk_bgxx_gmp_gmi_rxx_ifg_s cn81xx; */
7877     struct bdk_bgxx_gmp_gmi_rxx_ifg_cn88xx
7878     {
7879 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7880         uint64_t reserved_4_63         : 60;
7881         uint64_t ifg                   : 4;  /**< [  3:  0](R/W) Min IFG (in IFG * 8 bits) between packets used to determine IFGERR. Normally IFG is 96
7882                                                                  bits. Values 0x1 or smaller are illegal.
7883 
7884                                                                  Note that in some operating modes, IFG cycles can be inserted or removed in order to
7885                                                                  achieve clock rate adaptation. For these reasons, the default value is slightly
7886                                                                  conservative and does not check up to the full 96 bits of IFG.
7887                                                                  (SGMII/1000Base-X only) */
7888 #else /* Word 0 - Little Endian */
7889         uint64_t ifg                   : 4;  /**< [  3:  0](R/W) Min IFG (in IFG * 8 bits) between packets used to determine IFGERR. Normally IFG is 96
7890                                                                  bits. Values 0x1 or smaller are illegal.
7891 
7892                                                                  Note that in some operating modes, IFG cycles can be inserted or removed in order to
7893                                                                  achieve clock rate adaptation. For these reasons, the default value is slightly
7894                                                                  conservative and does not check up to the full 96 bits of IFG.
7895                                                                  (SGMII/1000Base-X only) */
7896         uint64_t reserved_4_63         : 60;
7897 #endif /* Word 0 - End */
7898     } cn88xx;
7899     /* struct bdk_bgxx_gmp_gmi_rxx_ifg_s cn83xx; */
7900 };
7901 typedef union bdk_bgxx_gmp_gmi_rxx_ifg bdk_bgxx_gmp_gmi_rxx_ifg_t;
7902 
7903 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_IFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_IFG(unsigned long a,unsigned long b)7904 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_IFG(unsigned long a, unsigned long b)
7905 {
7906     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
7907         return 0x87e0e0038058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7908     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
7909         return 0x87e0e0038058ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
7910     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
7911         return 0x87e0e0038058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
7912     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_IFG", 2, a, b, 0, 0);
7913 }
7914 
7915 #define typedef_BDK_BGXX_GMP_GMI_RXX_IFG(a,b) bdk_bgxx_gmp_gmi_rxx_ifg_t
7916 #define bustype_BDK_BGXX_GMP_GMI_RXX_IFG(a,b) BDK_CSR_TYPE_RSL
7917 #define basename_BDK_BGXX_GMP_GMI_RXX_IFG(a,b) "BGXX_GMP_GMI_RXX_IFG"
7918 #define device_bar_BDK_BGXX_GMP_GMI_RXX_IFG(a,b) 0x0 /* PF_BAR0 */
7919 #define busnum_BDK_BGXX_GMP_GMI_RXX_IFG(a,b) (a)
7920 #define arguments_BDK_BGXX_GMP_GMI_RXX_IFG(a,b) (a),(b),-1,-1
7921 
7922 /**
7923  * Register (RSL) bgx#_gmp_gmi_rx#_int
7924  *
7925  * BGX GMP GMI RX Interrupt Registers
7926  * '"These registers allow interrupts to be sent to the control processor.
7927  * * Exception conditions \<10:0\> can also set the rcv/opcode in the received packet's work-queue
7928  * entry. BGX()_GMP_GMI_RX()_FRM_CHK provides a bit mask for configuring which conditions
7929  * set the error.
7930  * In half duplex operation, the expectation is that collisions will appear as either MINERR or
7931  * CAREXT errors.'
7932  *
7933  * Internal:
7934  * Notes:
7935  * (1) exception conditions 10:0 can also set the rcv/opcode in the received
7936  * packet's workQ entry.  The BGX()_GMP_GMI_RX()_FRM_CHK register provides a bit mask
7937  * for configuring which conditions set the error.
7938  *
7939  * (2) in half duplex operation, the expectation is that collisions will appear
7940  * as either MINERR o r CAREXT errors.
7941  *
7942  * (3) JABBER An RX jabber error indicates that a packet was received which
7943  * is longer than the maximum allowed packet as defined by the
7944  * system.  GMI will truncate the packet at the JABBER count.
7945  * Failure to do so could lead to system instabilty.
7946  *
7947  * (4) NIBERR This error is illegal at 1000Mbs speeds
7948  * (BGX()_GMP_GMI_PRT()_CFG[SPEED]==0) and will never assert.
7949  *
7950  * (5) MINERR total frame DA+SA+TL+DATA+PAD+FCS \< 64
7951  *
7952  * (6) ALNERR Indicates that the packet received was not an integer number of
7953  * bytes.  If FCS checking is enabled, ALNERR will only assert if
7954  * the FCS is bad.  If FCS checking is disabled, ALNERR will
7955  * assert in all non-integer frame cases.
7956  *
7957  * (7) Collisions Collisions can only occur in half-duplex mode.  A collision
7958  * is assumed by the receiver when the slottime
7959  * (BGX()_GMP_GMI_PRT()_CFG[SLOTTIME]) is not satisfied.  In 10/100 mode,
7960  * this will result in a frame \< SLOTTIME.  In 1000 mode, it
7961  * could result either in frame \< SLOTTIME or a carrier extend
7962  * error with the SLOTTIME.  These conditions are visible by...
7963  * . transfer ended before slottime COLDET
7964  * . carrier extend error           CAREXT
7965  *
7966  * (A) LENERR Length errors occur when the received packet does not match the
7967  * length field.  LENERR is only checked for packets between 64
7968  * and 1500 bytes.  For untagged frames, the length must exact
7969  * match.  For tagged frames the length or length+4 must match.
7970  *
7971  * (B) PCTERR checks that the frame begins with a valid PREAMBLE sequence.
7972  * Does not check the number of PREAMBLE cycles.
7973  *
7974  * (C) OVRERR *DON'T PUT IN HRM*
7975  * OVRERR is an architectural assertion check internal to GMI to
7976  * make sure no assumption was violated.  In a correctly operating
7977  * system, this interrupt can never fire.
7978  * GMI has an internal arbiter which selects which of four ports to
7979  * buffer in the main RX FIFO.  If we normally buffer eight bytes,
7980  * then each port will typically push a tick every eight cycles if
7981  * the packet interface is going as fast as possible.  If there
7982  * are four ports, they push every two cycles.  So that's the
7983  * assumption.  That the inbound module will always be able to
7984  * consume the tick before another is produced.  If that doesn't
7985  * happen that's when OVRERR will assert."
7986  */
7987 union bdk_bgxx_gmp_gmi_rxx_int
7988 {
7989     uint64_t u;
7990     struct bdk_bgxx_gmp_gmi_rxx_int_s
7991     {
7992 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7993         uint64_t reserved_12_63        : 52;
7994         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1C/H) Interframe gap violation. Does not necessarily indicate a failure. SGMII/QSGMII/1000Base-X only. */
7995         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1C/H) Collision detection. Collisions can only occur in half-duplex mode. A collision is assumed
7996                                                                  by the receiver when the slottime (BGX()_GMP_GMI_PRT()_CFG[SLOTTIME]) is not
7997                                                                  satisfied. In 10/100 mode, this will result in a frame \< SLOTTIME. In 1000 mode, it could
7998                                                                  result either in frame \< SLOTTIME or a carrier extend error with the SLOTTIME. These
7999                                                                  conditions are visible by 1) transfer ended before slottime - COLDET or 2) carrier extend
8000                                                                  error - CAREXT. */
8001         uint64_t falerr                : 1;  /**< [  9:  9](R/W1C/H) False-carrier error, or carrier-extend error after slottime is satisfied.
8002                                                                  SGMII/QSGMII/1000Base-X only. */
8003         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1C/H) Detected reserved opcode. */
8004         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1C/H) Bad preamble/protocol error. Checks that the frame begins with a valid PREAMBLE sequence.
8005                                                                  Does not check the number of PREAMBLE cycles. */
8006         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1C/H) Internal data aggregation overflow. This interrupt should never assert.
8007                                                                  SGMII/QSGMII/1000Base-X only. */
8008         uint64_t skperr                : 1;  /**< [  5:  5](R/W1C/H) Skipper error. */
8009         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1C/H) Data-reception error. Frame was received with data-reception error. */
8010         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1C/H) FCS/CRC error. Frame was received with FCS/CRC error. */
8011         uint64_t jabber                : 1;  /**< [  2:  2](R/W1C/H) System-length error: frame was received with length \> sys_length.
8012                                                                  An RX Jabber error indicates that a packet was received which is longer than the maximum
8013                                                                  allowed packet as defined by the system. GMI truncates the packet at the JABBER count.
8014                                                                  Failure to do so could lead to system instability. */
8015         uint64_t carext                : 1;  /**< [  1:  1](R/W1C/H) Carrier-extend error. (SGMII/QSGMII/1000Base-X only) */
8016         uint64_t minerr                : 1;  /**< [  0:  0](R/W1C/H) PAUSE frame was received with length \< minFrameSize. Frame length checks are typically
8017                                                                  handled in NIC, but PAUSE frames are normally discarded before being inspected by NIC.
8018                                                                  Total frame DA+SA+TL+DATA+PAD+FCS \< 64. */
8019 #else /* Word 0 - Little Endian */
8020         uint64_t minerr                : 1;  /**< [  0:  0](R/W1C/H) PAUSE frame was received with length \< minFrameSize. Frame length checks are typically
8021                                                                  handled in NIC, but PAUSE frames are normally discarded before being inspected by NIC.
8022                                                                  Total frame DA+SA+TL+DATA+PAD+FCS \< 64. */
8023         uint64_t carext                : 1;  /**< [  1:  1](R/W1C/H) Carrier-extend error. (SGMII/QSGMII/1000Base-X only) */
8024         uint64_t jabber                : 1;  /**< [  2:  2](R/W1C/H) System-length error: frame was received with length \> sys_length.
8025                                                                  An RX Jabber error indicates that a packet was received which is longer than the maximum
8026                                                                  allowed packet as defined by the system. GMI truncates the packet at the JABBER count.
8027                                                                  Failure to do so could lead to system instability. */
8028         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1C/H) FCS/CRC error. Frame was received with FCS/CRC error. */
8029         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1C/H) Data-reception error. Frame was received with data-reception error. */
8030         uint64_t skperr                : 1;  /**< [  5:  5](R/W1C/H) Skipper error. */
8031         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1C/H) Internal data aggregation overflow. This interrupt should never assert.
8032                                                                  SGMII/QSGMII/1000Base-X only. */
8033         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1C/H) Bad preamble/protocol error. Checks that the frame begins with a valid PREAMBLE sequence.
8034                                                                  Does not check the number of PREAMBLE cycles. */
8035         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1C/H) Detected reserved opcode. */
8036         uint64_t falerr                : 1;  /**< [  9:  9](R/W1C/H) False-carrier error, or carrier-extend error after slottime is satisfied.
8037                                                                  SGMII/QSGMII/1000Base-X only. */
8038         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1C/H) Collision detection. Collisions can only occur in half-duplex mode. A collision is assumed
8039                                                                  by the receiver when the slottime (BGX()_GMP_GMI_PRT()_CFG[SLOTTIME]) is not
8040                                                                  satisfied. In 10/100 mode, this will result in a frame \< SLOTTIME. In 1000 mode, it could
8041                                                                  result either in frame \< SLOTTIME or a carrier extend error with the SLOTTIME. These
8042                                                                  conditions are visible by 1) transfer ended before slottime - COLDET or 2) carrier extend
8043                                                                  error - CAREXT. */
8044         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1C/H) Interframe gap violation. Does not necessarily indicate a failure. SGMII/QSGMII/1000Base-X only. */
8045         uint64_t reserved_12_63        : 52;
8046 #endif /* Word 0 - End */
8047     } s;
8048     /* struct bdk_bgxx_gmp_gmi_rxx_int_s cn81xx; */
8049     struct bdk_bgxx_gmp_gmi_rxx_int_cn88xx
8050     {
8051 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8052         uint64_t reserved_12_63        : 52;
8053         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1C/H) Interframe gap violation. Does not necessarily indicate a failure. SGMII/1000Base-X only. */
8054         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1C/H) Collision detection. Collisions can only occur in half-duplex mode. A collision is assumed
8055                                                                  by the receiver when the slottime (BGX()_GMP_GMI_PRT()_CFG[SLOTTIME]) is not
8056                                                                  satisfied. In 10/100 mode, this will result in a frame \< SLOTTIME. In 1000 mode, it could
8057                                                                  result either in frame \< SLOTTIME or a carrier extend error with the SLOTTIME. These
8058                                                                  conditions are visible by 1) transfer ended before slottime - COLDET or 2) carrier extend
8059                                                                  error - CAREXT. */
8060         uint64_t falerr                : 1;  /**< [  9:  9](R/W1C/H) False-carrier error, or carrier-extend error after slottime is satisfied. SGMII/1000Base-X only. */
8061         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1C/H) Detected reserved opcode. */
8062         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1C/H) Bad preamble/protocol error. Checks that the frame begins with a valid PREAMBLE sequence.
8063                                                                  Does not check the number of PREAMBLE cycles. */
8064         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1C/H) Internal data aggregation overflow. This interrupt should never assert. SGMII/1000Base-X only. */
8065         uint64_t skperr                : 1;  /**< [  5:  5](R/W1C/H) Skipper error. */
8066         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1C/H) Data-reception error. Frame was received with data-reception error. */
8067         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1C/H) FCS/CRC error. Frame was received with FCS/CRC error. */
8068         uint64_t jabber                : 1;  /**< [  2:  2](R/W1C/H) System-length error: frame was received with length \> sys_length.
8069                                                                  An RX Jabber error indicates that a packet was received which is longer than the maximum
8070                                                                  allowed packet as defined by the system. GMI truncates the packet at the JABBER count.
8071                                                                  Failure to do so could lead to system instability. */
8072         uint64_t carext                : 1;  /**< [  1:  1](R/W1C/H) Carrier-extend error. (SGMII/1000Base-X only) */
8073         uint64_t minerr                : 1;  /**< [  0:  0](R/W1C/H) PAUSE frame was received with length \< minFrameSize. Frame length checks are typically
8074                                                                  handled in NIC, but PAUSE frames are normally discarded before being inspected by NIC.
8075                                                                  Total frame DA+SA+TL+DATA+PAD+FCS \< 64. */
8076 #else /* Word 0 - Little Endian */
8077         uint64_t minerr                : 1;  /**< [  0:  0](R/W1C/H) PAUSE frame was received with length \< minFrameSize. Frame length checks are typically
8078                                                                  handled in NIC, but PAUSE frames are normally discarded before being inspected by NIC.
8079                                                                  Total frame DA+SA+TL+DATA+PAD+FCS \< 64. */
8080         uint64_t carext                : 1;  /**< [  1:  1](R/W1C/H) Carrier-extend error. (SGMII/1000Base-X only) */
8081         uint64_t jabber                : 1;  /**< [  2:  2](R/W1C/H) System-length error: frame was received with length \> sys_length.
8082                                                                  An RX Jabber error indicates that a packet was received which is longer than the maximum
8083                                                                  allowed packet as defined by the system. GMI truncates the packet at the JABBER count.
8084                                                                  Failure to do so could lead to system instability. */
8085         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1C/H) FCS/CRC error. Frame was received with FCS/CRC error. */
8086         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1C/H) Data-reception error. Frame was received with data-reception error. */
8087         uint64_t skperr                : 1;  /**< [  5:  5](R/W1C/H) Skipper error. */
8088         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1C/H) Internal data aggregation overflow. This interrupt should never assert. SGMII/1000Base-X only. */
8089         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1C/H) Bad preamble/protocol error. Checks that the frame begins with a valid PREAMBLE sequence.
8090                                                                  Does not check the number of PREAMBLE cycles. */
8091         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1C/H) Detected reserved opcode. */
8092         uint64_t falerr                : 1;  /**< [  9:  9](R/W1C/H) False-carrier error, or carrier-extend error after slottime is satisfied. SGMII/1000Base-X only. */
8093         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1C/H) Collision detection. Collisions can only occur in half-duplex mode. A collision is assumed
8094                                                                  by the receiver when the slottime (BGX()_GMP_GMI_PRT()_CFG[SLOTTIME]) is not
8095                                                                  satisfied. In 10/100 mode, this will result in a frame \< SLOTTIME. In 1000 mode, it could
8096                                                                  result either in frame \< SLOTTIME or a carrier extend error with the SLOTTIME. These
8097                                                                  conditions are visible by 1) transfer ended before slottime - COLDET or 2) carrier extend
8098                                                                  error - CAREXT. */
8099         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1C/H) Interframe gap violation. Does not necessarily indicate a failure. SGMII/1000Base-X only. */
8100         uint64_t reserved_12_63        : 52;
8101 #endif /* Word 0 - End */
8102     } cn88xx;
8103     /* struct bdk_bgxx_gmp_gmi_rxx_int_s cn83xx; */
8104 };
8105 typedef union bdk_bgxx_gmp_gmi_rxx_int bdk_bgxx_gmp_gmi_rxx_int_t;
8106 
8107 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_INT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_INT(unsigned long a,unsigned long b)8108 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_INT(unsigned long a, unsigned long b)
8109 {
8110     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8111         return 0x87e0e0038000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8112     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8113         return 0x87e0e0038000ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8114     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8115         return 0x87e0e0038000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8116     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_INT", 2, a, b, 0, 0);
8117 }
8118 
8119 #define typedef_BDK_BGXX_GMP_GMI_RXX_INT(a,b) bdk_bgxx_gmp_gmi_rxx_int_t
8120 #define bustype_BDK_BGXX_GMP_GMI_RXX_INT(a,b) BDK_CSR_TYPE_RSL
8121 #define basename_BDK_BGXX_GMP_GMI_RXX_INT(a,b) "BGXX_GMP_GMI_RXX_INT"
8122 #define device_bar_BDK_BGXX_GMP_GMI_RXX_INT(a,b) 0x0 /* PF_BAR0 */
8123 #define busnum_BDK_BGXX_GMP_GMI_RXX_INT(a,b) (a)
8124 #define arguments_BDK_BGXX_GMP_GMI_RXX_INT(a,b) (a),(b),-1,-1
8125 
8126 /**
8127  * Register (RSL) bgx#_gmp_gmi_rx#_int_ena_w1c
8128  *
8129  * BGX GMP GMI RX Interrupt Enable Clear Registers
8130  * This register clears interrupt enable bits.
8131  */
8132 union bdk_bgxx_gmp_gmi_rxx_int_ena_w1c
8133 {
8134     uint64_t u;
8135     struct bdk_bgxx_gmp_gmi_rxx_int_ena_w1c_s
8136     {
8137 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8138         uint64_t reserved_12_63        : 52;
8139         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8140         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8141         uint64_t falerr                : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8142         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8143         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8144         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8145         uint64_t skperr                : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8146         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8147         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8148         uint64_t jabber                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8149         uint64_t carext                : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8150         uint64_t minerr                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8151 #else /* Word 0 - Little Endian */
8152         uint64_t minerr                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8153         uint64_t carext                : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8154         uint64_t jabber                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8155         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8156         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8157         uint64_t skperr                : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8158         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8159         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8160         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8161         uint64_t falerr                : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8162         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8163         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8164         uint64_t reserved_12_63        : 52;
8165 #endif /* Word 0 - End */
8166     } s;
8167     /* struct bdk_bgxx_gmp_gmi_rxx_int_ena_w1c_s cn81xx; */
8168     /* struct bdk_bgxx_gmp_gmi_rxx_int_ena_w1c_s cn88xx; */
8169     struct bdk_bgxx_gmp_gmi_rxx_int_ena_w1c_cn83xx
8170     {
8171 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8172         uint64_t reserved_12_63        : 52;
8173         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8174         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8175         uint64_t falerr                : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8176         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8177         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8178         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8179         uint64_t skperr                : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8180         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8181         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8182         uint64_t jabber                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8183         uint64_t carext                : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8184         uint64_t minerr                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8185 #else /* Word 0 - Little Endian */
8186         uint64_t minerr                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8187         uint64_t carext                : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8188         uint64_t jabber                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8189         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8190         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8191         uint64_t skperr                : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8192         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8193         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8194         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8195         uint64_t falerr                : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8196         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8197         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8198         uint64_t reserved_12_63        : 52;
8199 #endif /* Word 0 - End */
8200     } cn83xx;
8201 };
8202 typedef union bdk_bgxx_gmp_gmi_rxx_int_ena_w1c bdk_bgxx_gmp_gmi_rxx_int_ena_w1c_t;
8203 
8204 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1C(unsigned long a,unsigned long b)8205 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1C(unsigned long a, unsigned long b)
8206 {
8207     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8208         return 0x87e0e0038010ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8209     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8210         return 0x87e0e0038010ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8211     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8212         return 0x87e0e0038010ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8213     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_INT_ENA_W1C", 2, a, b, 0, 0);
8214 }
8215 
8216 #define typedef_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1C(a,b) bdk_bgxx_gmp_gmi_rxx_int_ena_w1c_t
8217 #define bustype_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1C(a,b) BDK_CSR_TYPE_RSL
8218 #define basename_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1C(a,b) "BGXX_GMP_GMI_RXX_INT_ENA_W1C"
8219 #define device_bar_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
8220 #define busnum_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1C(a,b) (a)
8221 #define arguments_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1C(a,b) (a),(b),-1,-1
8222 
8223 /**
8224  * Register (RSL) bgx#_gmp_gmi_rx#_int_ena_w1s
8225  *
8226  * BGX GMP GMI RX Interrupt Enable Set Registers
8227  * This register sets interrupt enable bits.
8228  */
8229 union bdk_bgxx_gmp_gmi_rxx_int_ena_w1s
8230 {
8231     uint64_t u;
8232     struct bdk_bgxx_gmp_gmi_rxx_int_ena_w1s_s
8233     {
8234 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8235         uint64_t reserved_12_63        : 52;
8236         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8237         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8238         uint64_t falerr                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8239         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8240         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8241         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8242         uint64_t skperr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8243         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8244         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8245         uint64_t jabber                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8246         uint64_t carext                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8247         uint64_t minerr                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8248 #else /* Word 0 - Little Endian */
8249         uint64_t minerr                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8250         uint64_t carext                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8251         uint64_t jabber                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8252         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8253         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8254         uint64_t skperr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8255         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8256         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8257         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8258         uint64_t falerr                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8259         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8260         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8261         uint64_t reserved_12_63        : 52;
8262 #endif /* Word 0 - End */
8263     } s;
8264     /* struct bdk_bgxx_gmp_gmi_rxx_int_ena_w1s_s cn81xx; */
8265     /* struct bdk_bgxx_gmp_gmi_rxx_int_ena_w1s_s cn88xx; */
8266     struct bdk_bgxx_gmp_gmi_rxx_int_ena_w1s_cn83xx
8267     {
8268 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8269         uint64_t reserved_12_63        : 52;
8270         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8271         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8272         uint64_t falerr                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8273         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8274         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8275         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8276         uint64_t skperr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8277         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8278         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8279         uint64_t jabber                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8280         uint64_t carext                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8281         uint64_t minerr                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8282 #else /* Word 0 - Little Endian */
8283         uint64_t minerr                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8284         uint64_t carext                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8285         uint64_t jabber                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8286         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8287         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8288         uint64_t skperr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8289         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8290         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8291         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8292         uint64_t falerr                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8293         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8294         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8295         uint64_t reserved_12_63        : 52;
8296 #endif /* Word 0 - End */
8297     } cn83xx;
8298 };
8299 typedef union bdk_bgxx_gmp_gmi_rxx_int_ena_w1s bdk_bgxx_gmp_gmi_rxx_int_ena_w1s_t;
8300 
8301 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1S(unsigned long a,unsigned long b)8302 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1S(unsigned long a, unsigned long b)
8303 {
8304     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8305         return 0x87e0e0038018ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8306     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8307         return 0x87e0e0038018ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8308     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8309         return 0x87e0e0038018ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8310     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_INT_ENA_W1S", 2, a, b, 0, 0);
8311 }
8312 
8313 #define typedef_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1S(a,b) bdk_bgxx_gmp_gmi_rxx_int_ena_w1s_t
8314 #define bustype_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1S(a,b) BDK_CSR_TYPE_RSL
8315 #define basename_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1S(a,b) "BGXX_GMP_GMI_RXX_INT_ENA_W1S"
8316 #define device_bar_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
8317 #define busnum_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1S(a,b) (a)
8318 #define arguments_BDK_BGXX_GMP_GMI_RXX_INT_ENA_W1S(a,b) (a),(b),-1,-1
8319 
8320 /**
8321  * Register (RSL) bgx#_gmp_gmi_rx#_int_w1s
8322  *
8323  * BGX GMP GMI RX Interrupt Set Registers
8324  * This register sets interrupt bits.
8325  */
8326 union bdk_bgxx_gmp_gmi_rxx_int_w1s
8327 {
8328     uint64_t u;
8329     struct bdk_bgxx_gmp_gmi_rxx_int_w1s_s
8330     {
8331 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8332         uint64_t reserved_12_63        : 52;
8333         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8334         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8335         uint64_t falerr                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8336         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8337         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8338         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8339         uint64_t skperr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8340         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8341         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8342         uint64_t jabber                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8343         uint64_t carext                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8344         uint64_t minerr                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8345 #else /* Word 0 - Little Endian */
8346         uint64_t minerr                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8347         uint64_t carext                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8348         uint64_t jabber                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8349         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8350         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8351         uint64_t skperr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8352         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8353         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8354         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8355         uint64_t falerr                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8356         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8357         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8358         uint64_t reserved_12_63        : 52;
8359 #endif /* Word 0 - End */
8360     } s;
8361     /* struct bdk_bgxx_gmp_gmi_rxx_int_w1s_s cn81xx; */
8362     /* struct bdk_bgxx_gmp_gmi_rxx_int_w1s_s cn88xx; */
8363     struct bdk_bgxx_gmp_gmi_rxx_int_w1s_cn83xx
8364     {
8365 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8366         uint64_t reserved_12_63        : 52;
8367         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8368         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8369         uint64_t falerr                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8370         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8371         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8372         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8373         uint64_t skperr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8374         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8375         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8376         uint64_t jabber                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8377         uint64_t carext                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8378         uint64_t minerr                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8379 #else /* Word 0 - Little Endian */
8380         uint64_t minerr                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[MINERR]. */
8381         uint64_t carext                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[CAREXT]. */
8382         uint64_t jabber                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[JABBER]. */
8383         uint64_t fcserr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[FCSERR]. */
8384         uint64_t rcverr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[RCVERR]. */
8385         uint64_t skperr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[SKPERR]. */
8386         uint64_t ovrerr                : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[OVRERR]. */
8387         uint64_t pcterr                : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[PCTERR]. */
8388         uint64_t rsverr                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[RSVERR]. */
8389         uint64_t falerr                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[FALERR]. */
8390         uint64_t coldet                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[COLDET]. */
8391         uint64_t ifgerr                : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_RX(0..3)_INT[IFGERR]. */
8392         uint64_t reserved_12_63        : 52;
8393 #endif /* Word 0 - End */
8394     } cn83xx;
8395 };
8396 typedef union bdk_bgxx_gmp_gmi_rxx_int_w1s bdk_bgxx_gmp_gmi_rxx_int_w1s_t;
8397 
8398 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_INT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_INT_W1S(unsigned long a,unsigned long b)8399 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_INT_W1S(unsigned long a, unsigned long b)
8400 {
8401     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8402         return 0x87e0e0038008ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8403     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8404         return 0x87e0e0038008ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8405     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8406         return 0x87e0e0038008ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8407     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_INT_W1S", 2, a, b, 0, 0);
8408 }
8409 
8410 #define typedef_BDK_BGXX_GMP_GMI_RXX_INT_W1S(a,b) bdk_bgxx_gmp_gmi_rxx_int_w1s_t
8411 #define bustype_BDK_BGXX_GMP_GMI_RXX_INT_W1S(a,b) BDK_CSR_TYPE_RSL
8412 #define basename_BDK_BGXX_GMP_GMI_RXX_INT_W1S(a,b) "BGXX_GMP_GMI_RXX_INT_W1S"
8413 #define device_bar_BDK_BGXX_GMP_GMI_RXX_INT_W1S(a,b) 0x0 /* PF_BAR0 */
8414 #define busnum_BDK_BGXX_GMP_GMI_RXX_INT_W1S(a,b) (a)
8415 #define arguments_BDK_BGXX_GMP_GMI_RXX_INT_W1S(a,b) (a),(b),-1,-1
8416 
8417 /**
8418  * Register (RSL) bgx#_gmp_gmi_rx#_jabber
8419  *
8420  * BGX GMP Maximum Packet-Size Registers
8421  * This register specifies the maximum size for packets, beyond which the GMI truncates.
8422  */
8423 union bdk_bgxx_gmp_gmi_rxx_jabber
8424 {
8425     uint64_t u;
8426     struct bdk_bgxx_gmp_gmi_rxx_jabber_s
8427     {
8428 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8429         uint64_t reserved_16_63        : 48;
8430         uint64_t cnt                   : 16; /**< [ 15:  0](R/W) Byte count for jabber check. Failing packets set the JABBER interrupt and are optionally
8431                                                                  sent with opcode = JABBER. GMI truncates the packet to [CNT] bytes.
8432                                                                  [CNT] must be 8-byte aligned such that CNT\<2:0\> = 000. */
8433 #else /* Word 0 - Little Endian */
8434         uint64_t cnt                   : 16; /**< [ 15:  0](R/W) Byte count for jabber check. Failing packets set the JABBER interrupt and are optionally
8435                                                                  sent with opcode = JABBER. GMI truncates the packet to [CNT] bytes.
8436                                                                  [CNT] must be 8-byte aligned such that CNT\<2:0\> = 000. */
8437         uint64_t reserved_16_63        : 48;
8438 #endif /* Word 0 - End */
8439     } s;
8440     /* struct bdk_bgxx_gmp_gmi_rxx_jabber_s cn; */
8441 };
8442 typedef union bdk_bgxx_gmp_gmi_rxx_jabber bdk_bgxx_gmp_gmi_rxx_jabber_t;
8443 
8444 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_JABBER(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_JABBER(unsigned long a,unsigned long b)8445 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_JABBER(unsigned long a, unsigned long b)
8446 {
8447     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8448         return 0x87e0e0038038ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8449     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8450         return 0x87e0e0038038ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8451     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8452         return 0x87e0e0038038ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8453     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_JABBER", 2, a, b, 0, 0);
8454 }
8455 
8456 #define typedef_BDK_BGXX_GMP_GMI_RXX_JABBER(a,b) bdk_bgxx_gmp_gmi_rxx_jabber_t
8457 #define bustype_BDK_BGXX_GMP_GMI_RXX_JABBER(a,b) BDK_CSR_TYPE_RSL
8458 #define basename_BDK_BGXX_GMP_GMI_RXX_JABBER(a,b) "BGXX_GMP_GMI_RXX_JABBER"
8459 #define device_bar_BDK_BGXX_GMP_GMI_RXX_JABBER(a,b) 0x0 /* PF_BAR0 */
8460 #define busnum_BDK_BGXX_GMP_GMI_RXX_JABBER(a,b) (a)
8461 #define arguments_BDK_BGXX_GMP_GMI_RXX_JABBER(a,b) (a),(b),-1,-1
8462 
8463 /**
8464  * Register (RSL) bgx#_gmp_gmi_rx#_udd_skp
8465  *
8466  * BGX GMP GMI User-Defined Data Skip Registers
8467  * This register specifies the amount of user-defined data (UDD) added before the start of the
8468  * L2C data.
8469  *
8470  * Internal:
8471  * Notes:
8472  * (1) The skip bytes are part of the packet and will be handled by NIC.
8473  *
8474  * (2) The system can determine if the UDD bytes are included in the FCS check
8475  * by using the FCSSEL field - if the FCS check is enabled.
8476  *
8477  * (3) Assume that the preamble/sfd is always at the start of the frame - even
8478  * before UDD bytes.  In most cases, there will be no preamble in these
8479  * cases since it will be packet interface in direct communication to
8480  * another packet interface (MAC to MAC) without a PHY involved.
8481  *
8482  * (4) We can still do address filtering and control packet filtering is the
8483  * user desires.
8484  *
8485  * (5) BGX()_GMP_GMI_RX()_UDD_SKP[LEN] must be 0 in half-duplex operation unless
8486  * BGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] is clear.  If BGX()_GMP_GMI_RX()_FRM_CTL[PRE_CHK] is
8487  * clear,
8488  * then BGX()_GMP_GMI_RX()_UDD_SKP[LEN] will normally be 8.
8489  *
8490  * (6) In all cases, the UDD bytes will be sent down the packet interface as
8491  * part of the packet.  The UDD bytes are never stripped from the actual
8492  * packet.
8493  */
8494 union bdk_bgxx_gmp_gmi_rxx_udd_skp
8495 {
8496     uint64_t u;
8497     struct bdk_bgxx_gmp_gmi_rxx_udd_skp_s
8498     {
8499 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8500         uint64_t reserved_9_63         : 55;
8501         uint64_t fcssel                : 1;  /**< [  8:  8](R/W) Include the skip bytes in the FCS calculation.
8502                                                                  0 = All skip bytes are included in FCS.
8503                                                                  1 = The skip bytes are not included in FCS.
8504 
8505                                                                  The skip bytes are part of the packet and are
8506                                                                  handled by NIC. The system can determine if the UDD bytes are included in the FCS check by
8507                                                                  using [FCSSEL], if the FCS check is enabled. */
8508         uint64_t reserved_7            : 1;
8509         uint64_t len                   : 7;  /**< [  6:  0](R/W) Amount of user-defined data before the start of the L2C data, in bytes.
8510                                                                  Setting to 0 means L2C comes first; maximum value is 64.
8511                                                                  LEN must be 0x0 in half-duplex operation.
8512 
8513                                                                  If LEN != 0, then BGX()_GMP_GMI_RX()_FRM_CHK[MINERR] will be disabled and
8514                                                                  BGX()_GMP_GMI_RX()_INT[MINERR] will be zero. */
8515 #else /* Word 0 - Little Endian */
8516         uint64_t len                   : 7;  /**< [  6:  0](R/W) Amount of user-defined data before the start of the L2C data, in bytes.
8517                                                                  Setting to 0 means L2C comes first; maximum value is 64.
8518                                                                  LEN must be 0x0 in half-duplex operation.
8519 
8520                                                                  If LEN != 0, then BGX()_GMP_GMI_RX()_FRM_CHK[MINERR] will be disabled and
8521                                                                  BGX()_GMP_GMI_RX()_INT[MINERR] will be zero. */
8522         uint64_t reserved_7            : 1;
8523         uint64_t fcssel                : 1;  /**< [  8:  8](R/W) Include the skip bytes in the FCS calculation.
8524                                                                  0 = All skip bytes are included in FCS.
8525                                                                  1 = The skip bytes are not included in FCS.
8526 
8527                                                                  The skip bytes are part of the packet and are
8528                                                                  handled by NIC. The system can determine if the UDD bytes are included in the FCS check by
8529                                                                  using [FCSSEL], if the FCS check is enabled. */
8530         uint64_t reserved_9_63         : 55;
8531 #endif /* Word 0 - End */
8532     } s;
8533     /* struct bdk_bgxx_gmp_gmi_rxx_udd_skp_s cn; */
8534 };
8535 typedef union bdk_bgxx_gmp_gmi_rxx_udd_skp bdk_bgxx_gmp_gmi_rxx_udd_skp_t;
8536 
8537 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_UDD_SKP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_RXX_UDD_SKP(unsigned long a,unsigned long b)8538 static inline uint64_t BDK_BGXX_GMP_GMI_RXX_UDD_SKP(unsigned long a, unsigned long b)
8539 {
8540     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8541         return 0x87e0e0038048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8542     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8543         return 0x87e0e0038048ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8544     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8545         return 0x87e0e0038048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8546     __bdk_csr_fatal("BGXX_GMP_GMI_RXX_UDD_SKP", 2, a, b, 0, 0);
8547 }
8548 
8549 #define typedef_BDK_BGXX_GMP_GMI_RXX_UDD_SKP(a,b) bdk_bgxx_gmp_gmi_rxx_udd_skp_t
8550 #define bustype_BDK_BGXX_GMP_GMI_RXX_UDD_SKP(a,b) BDK_CSR_TYPE_RSL
8551 #define basename_BDK_BGXX_GMP_GMI_RXX_UDD_SKP(a,b) "BGXX_GMP_GMI_RXX_UDD_SKP"
8552 #define device_bar_BDK_BGXX_GMP_GMI_RXX_UDD_SKP(a,b) 0x0 /* PF_BAR0 */
8553 #define busnum_BDK_BGXX_GMP_GMI_RXX_UDD_SKP(a,b) (a)
8554 #define arguments_BDK_BGXX_GMP_GMI_RXX_UDD_SKP(a,b) (a),(b),-1,-1
8555 
8556 /**
8557  * Register (RSL) bgx#_gmp_gmi_smac#
8558  *
8559  * BGX GMI SMAC Registers
8560  */
8561 union bdk_bgxx_gmp_gmi_smacx
8562 {
8563     uint64_t u;
8564     struct bdk_bgxx_gmp_gmi_smacx_s
8565     {
8566 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8567         uint64_t reserved_48_63        : 16;
8568         uint64_t smac                  : 48; /**< [ 47:  0](R/W) The SMAC field is used for generating and accepting control PAUSE packets. */
8569 #else /* Word 0 - Little Endian */
8570         uint64_t smac                  : 48; /**< [ 47:  0](R/W) The SMAC field is used for generating and accepting control PAUSE packets. */
8571         uint64_t reserved_48_63        : 16;
8572 #endif /* Word 0 - End */
8573     } s;
8574     /* struct bdk_bgxx_gmp_gmi_smacx_s cn; */
8575 };
8576 typedef union bdk_bgxx_gmp_gmi_smacx bdk_bgxx_gmp_gmi_smacx_t;
8577 
8578 static inline uint64_t BDK_BGXX_GMP_GMI_SMACX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_SMACX(unsigned long a,unsigned long b)8579 static inline uint64_t BDK_BGXX_GMP_GMI_SMACX(unsigned long a, unsigned long b)
8580 {
8581     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8582         return 0x87e0e0038230ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8583     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8584         return 0x87e0e0038230ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8585     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8586         return 0x87e0e0038230ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8587     __bdk_csr_fatal("BGXX_GMP_GMI_SMACX", 2, a, b, 0, 0);
8588 }
8589 
8590 #define typedef_BDK_BGXX_GMP_GMI_SMACX(a,b) bdk_bgxx_gmp_gmi_smacx_t
8591 #define bustype_BDK_BGXX_GMP_GMI_SMACX(a,b) BDK_CSR_TYPE_RSL
8592 #define basename_BDK_BGXX_GMP_GMI_SMACX(a,b) "BGXX_GMP_GMI_SMACX"
8593 #define device_bar_BDK_BGXX_GMP_GMI_SMACX(a,b) 0x0 /* PF_BAR0 */
8594 #define busnum_BDK_BGXX_GMP_GMI_SMACX(a,b) (a)
8595 #define arguments_BDK_BGXX_GMP_GMI_SMACX(a,b) (a),(b),-1,-1
8596 
8597 /**
8598  * Register (RSL) bgx#_gmp_gmi_tx#_append
8599  *
8600  * BGX GMI TX Append Control Registers
8601  */
8602 union bdk_bgxx_gmp_gmi_txx_append
8603 {
8604     uint64_t u;
8605     struct bdk_bgxx_gmp_gmi_txx_append_s
8606     {
8607 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8608         uint64_t reserved_4_63         : 60;
8609         uint64_t force_fcs             : 1;  /**< [  3:  3](R/W) Append the Ethernet FCS on each PAUSE packet. */
8610         uint64_t fcs                   : 1;  /**< [  2:  2](R/W) Append the Ethernet FCS on each packet. */
8611         uint64_t pad                   : 1;  /**< [  1:  1](R/W) Append PAD bytes such that minimum-sized packet is transmitted. */
8612         uint64_t preamble              : 1;  /**< [  0:  0](R/W) Prepend the Ethernet preamble on each transfer. */
8613 #else /* Word 0 - Little Endian */
8614         uint64_t preamble              : 1;  /**< [  0:  0](R/W) Prepend the Ethernet preamble on each transfer. */
8615         uint64_t pad                   : 1;  /**< [  1:  1](R/W) Append PAD bytes such that minimum-sized packet is transmitted. */
8616         uint64_t fcs                   : 1;  /**< [  2:  2](R/W) Append the Ethernet FCS on each packet. */
8617         uint64_t force_fcs             : 1;  /**< [  3:  3](R/W) Append the Ethernet FCS on each PAUSE packet. */
8618         uint64_t reserved_4_63         : 60;
8619 #endif /* Word 0 - End */
8620     } s;
8621     /* struct bdk_bgxx_gmp_gmi_txx_append_s cn; */
8622 };
8623 typedef union bdk_bgxx_gmp_gmi_txx_append bdk_bgxx_gmp_gmi_txx_append_t;
8624 
8625 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_APPEND(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_APPEND(unsigned long a,unsigned long b)8626 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_APPEND(unsigned long a, unsigned long b)
8627 {
8628     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8629         return 0x87e0e0038218ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8630     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8631         return 0x87e0e0038218ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8632     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8633         return 0x87e0e0038218ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8634     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_APPEND", 2, a, b, 0, 0);
8635 }
8636 
8637 #define typedef_BDK_BGXX_GMP_GMI_TXX_APPEND(a,b) bdk_bgxx_gmp_gmi_txx_append_t
8638 #define bustype_BDK_BGXX_GMP_GMI_TXX_APPEND(a,b) BDK_CSR_TYPE_RSL
8639 #define basename_BDK_BGXX_GMP_GMI_TXX_APPEND(a,b) "BGXX_GMP_GMI_TXX_APPEND"
8640 #define device_bar_BDK_BGXX_GMP_GMI_TXX_APPEND(a,b) 0x0 /* PF_BAR0 */
8641 #define busnum_BDK_BGXX_GMP_GMI_TXX_APPEND(a,b) (a)
8642 #define arguments_BDK_BGXX_GMP_GMI_TXX_APPEND(a,b) (a),(b),-1,-1
8643 
8644 /**
8645  * Register (RSL) bgx#_gmp_gmi_tx#_burst
8646  *
8647  * BGX GMI TX Burst-Counter Registers
8648  */
8649 union bdk_bgxx_gmp_gmi_txx_burst
8650 {
8651     uint64_t u;
8652     struct bdk_bgxx_gmp_gmi_txx_burst_s
8653     {
8654 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8655         uint64_t reserved_16_63        : 48;
8656         uint64_t burst                 : 16; /**< [ 15:  0](R/W) Burst (refer to 802.3 to set correctly). Only valid for 1000Mb/s half-duplex operation as
8657                                                                  follows:
8658                                                                  half duplex/1000Mb/s: 0x2000
8659                                                                  all other modes: 0x0
8660                                                                  SGMII/QSGMII/1000Base-X only. */
8661 #else /* Word 0 - Little Endian */
8662         uint64_t burst                 : 16; /**< [ 15:  0](R/W) Burst (refer to 802.3 to set correctly). Only valid for 1000Mb/s half-duplex operation as
8663                                                                  follows:
8664                                                                  half duplex/1000Mb/s: 0x2000
8665                                                                  all other modes: 0x0
8666                                                                  SGMII/QSGMII/1000Base-X only. */
8667         uint64_t reserved_16_63        : 48;
8668 #endif /* Word 0 - End */
8669     } s;
8670     /* struct bdk_bgxx_gmp_gmi_txx_burst_s cn81xx; */
8671     struct bdk_bgxx_gmp_gmi_txx_burst_cn88xx
8672     {
8673 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8674         uint64_t reserved_16_63        : 48;
8675         uint64_t burst                 : 16; /**< [ 15:  0](R/W) Burst (refer to 802.3 to set correctly). Only valid for 1000Mb/s half-duplex operation as
8676                                                                  follows:
8677                                                                  half duplex/1000Mb/s: 0x2000
8678                                                                  all other modes: 0x0
8679                                                                  SGMII/1000Base-X only. */
8680 #else /* Word 0 - Little Endian */
8681         uint64_t burst                 : 16; /**< [ 15:  0](R/W) Burst (refer to 802.3 to set correctly). Only valid for 1000Mb/s half-duplex operation as
8682                                                                  follows:
8683                                                                  half duplex/1000Mb/s: 0x2000
8684                                                                  all other modes: 0x0
8685                                                                  SGMII/1000Base-X only. */
8686         uint64_t reserved_16_63        : 48;
8687 #endif /* Word 0 - End */
8688     } cn88xx;
8689     /* struct bdk_bgxx_gmp_gmi_txx_burst_s cn83xx; */
8690 };
8691 typedef union bdk_bgxx_gmp_gmi_txx_burst bdk_bgxx_gmp_gmi_txx_burst_t;
8692 
8693 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_BURST(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_BURST(unsigned long a,unsigned long b)8694 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_BURST(unsigned long a, unsigned long b)
8695 {
8696     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8697         return 0x87e0e0038228ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8698     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8699         return 0x87e0e0038228ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8700     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8701         return 0x87e0e0038228ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8702     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_BURST", 2, a, b, 0, 0);
8703 }
8704 
8705 #define typedef_BDK_BGXX_GMP_GMI_TXX_BURST(a,b) bdk_bgxx_gmp_gmi_txx_burst_t
8706 #define bustype_BDK_BGXX_GMP_GMI_TXX_BURST(a,b) BDK_CSR_TYPE_RSL
8707 #define basename_BDK_BGXX_GMP_GMI_TXX_BURST(a,b) "BGXX_GMP_GMI_TXX_BURST"
8708 #define device_bar_BDK_BGXX_GMP_GMI_TXX_BURST(a,b) 0x0 /* PF_BAR0 */
8709 #define busnum_BDK_BGXX_GMP_GMI_TXX_BURST(a,b) (a)
8710 #define arguments_BDK_BGXX_GMP_GMI_TXX_BURST(a,b) (a),(b),-1,-1
8711 
8712 /**
8713  * Register (RSL) bgx#_gmp_gmi_tx#_ctl
8714  *
8715  * BGX GMI Transmit Control Registers
8716  */
8717 union bdk_bgxx_gmp_gmi_txx_ctl
8718 {
8719     uint64_t u;
8720     struct bdk_bgxx_gmp_gmi_txx_ctl_s
8721     {
8722 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8723         uint64_t reserved_4_63         : 60;
8724         uint64_t link_drain            : 1;  /**< [  3:  3](R/W) Enable dropping of full packets to allow BGX and PKO/NIC to drain their FIFOs.
8725                                                                  For diagnostic use only. */
8726         uint64_t tx_fc_type            : 1;  /**< [  2:  2](R/W) Transmit side flow control type select.
8727                                                                  0 = GMI MAC transmits ITU G.999.1 pause frames.
8728                                                                  1 = GMI MAC transmits 802.3 pause frames. */
8729         uint64_t xsdef_en              : 1;  /**< [  1:  1](R/W) Enables the excessive-deferral check for statistics and interrupts. SGMII/1000Base-X half-
8730                                                                  duplex only. */
8731         uint64_t xscol_en              : 1;  /**< [  0:  0](R/W) Enables the excessive-collision check for statistics and interrupts. SGMII/1000Base-X
8732                                                                  half-duplex only. */
8733 #else /* Word 0 - Little Endian */
8734         uint64_t xscol_en              : 1;  /**< [  0:  0](R/W) Enables the excessive-collision check for statistics and interrupts. SGMII/1000Base-X
8735                                                                  half-duplex only. */
8736         uint64_t xsdef_en              : 1;  /**< [  1:  1](R/W) Enables the excessive-deferral check for statistics and interrupts. SGMII/1000Base-X half-
8737                                                                  duplex only. */
8738         uint64_t tx_fc_type            : 1;  /**< [  2:  2](R/W) Transmit side flow control type select.
8739                                                                  0 = GMI MAC transmits ITU G.999.1 pause frames.
8740                                                                  1 = GMI MAC transmits 802.3 pause frames. */
8741         uint64_t link_drain            : 1;  /**< [  3:  3](R/W) Enable dropping of full packets to allow BGX and PKO/NIC to drain their FIFOs.
8742                                                                  For diagnostic use only. */
8743         uint64_t reserved_4_63         : 60;
8744 #endif /* Word 0 - End */
8745     } s;
8746     struct bdk_bgxx_gmp_gmi_txx_ctl_cn81xx
8747     {
8748 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8749         uint64_t reserved_3_63         : 61;
8750         uint64_t tx_fc_type            : 1;  /**< [  2:  2](R/W) Transmit side flow control type select.
8751                                                                  0 = GMI MAC transmits ITU G.999.1 pause frames.
8752                                                                  1 = GMI MAC transmits 802.3 pause frames. */
8753         uint64_t xsdef_en              : 1;  /**< [  1:  1](R/W) Enables the excessive-deferral check for statistics and interrupts. SGMII/1000Base-X half-
8754                                                                  duplex only. */
8755         uint64_t xscol_en              : 1;  /**< [  0:  0](R/W) Enables the excessive-collision check for statistics and interrupts. SGMII/1000Base-X
8756                                                                  half-duplex only. */
8757 #else /* Word 0 - Little Endian */
8758         uint64_t xscol_en              : 1;  /**< [  0:  0](R/W) Enables the excessive-collision check for statistics and interrupts. SGMII/1000Base-X
8759                                                                  half-duplex only. */
8760         uint64_t xsdef_en              : 1;  /**< [  1:  1](R/W) Enables the excessive-deferral check for statistics and interrupts. SGMII/1000Base-X half-
8761                                                                  duplex only. */
8762         uint64_t tx_fc_type            : 1;  /**< [  2:  2](R/W) Transmit side flow control type select.
8763                                                                  0 = GMI MAC transmits ITU G.999.1 pause frames.
8764                                                                  1 = GMI MAC transmits 802.3 pause frames. */
8765         uint64_t reserved_3_63         : 61;
8766 #endif /* Word 0 - End */
8767     } cn81xx;
8768     struct bdk_bgxx_gmp_gmi_txx_ctl_cn88xx
8769     {
8770 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8771         uint64_t reserved_2_63         : 62;
8772         uint64_t xsdef_en              : 1;  /**< [  1:  1](R/W) Enables the excessive-deferral check for statistics and interrupts. SGMII/1000Base-X half-
8773                                                                  duplex only. */
8774         uint64_t xscol_en              : 1;  /**< [  0:  0](R/W) Enables the excessive-collision check for statistics and interrupts. SGMII/1000Base-X
8775                                                                  half-duplex only. */
8776 #else /* Word 0 - Little Endian */
8777         uint64_t xscol_en              : 1;  /**< [  0:  0](R/W) Enables the excessive-collision check for statistics and interrupts. SGMII/1000Base-X
8778                                                                  half-duplex only. */
8779         uint64_t xsdef_en              : 1;  /**< [  1:  1](R/W) Enables the excessive-deferral check for statistics and interrupts. SGMII/1000Base-X half-
8780                                                                  duplex only. */
8781         uint64_t reserved_2_63         : 62;
8782 #endif /* Word 0 - End */
8783     } cn88xx;
8784     /* struct bdk_bgxx_gmp_gmi_txx_ctl_s cn83xx; */
8785 };
8786 typedef union bdk_bgxx_gmp_gmi_txx_ctl bdk_bgxx_gmp_gmi_txx_ctl_t;
8787 
8788 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_CTL(unsigned long a,unsigned long b)8789 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_CTL(unsigned long a, unsigned long b)
8790 {
8791     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8792         return 0x87e0e0038270ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8793     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8794         return 0x87e0e0038270ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8795     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8796         return 0x87e0e0038270ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8797     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_CTL", 2, a, b, 0, 0);
8798 }
8799 
8800 #define typedef_BDK_BGXX_GMP_GMI_TXX_CTL(a,b) bdk_bgxx_gmp_gmi_txx_ctl_t
8801 #define bustype_BDK_BGXX_GMP_GMI_TXX_CTL(a,b) BDK_CSR_TYPE_RSL
8802 #define basename_BDK_BGXX_GMP_GMI_TXX_CTL(a,b) "BGXX_GMP_GMI_TXX_CTL"
8803 #define device_bar_BDK_BGXX_GMP_GMI_TXX_CTL(a,b) 0x0 /* PF_BAR0 */
8804 #define busnum_BDK_BGXX_GMP_GMI_TXX_CTL(a,b) (a)
8805 #define arguments_BDK_BGXX_GMP_GMI_TXX_CTL(a,b) (a),(b),-1,-1
8806 
8807 /**
8808  * Register (RSL) bgx#_gmp_gmi_tx#_int
8809  *
8810  * BGX GMI TX Interrupt Registers
8811  */
8812 union bdk_bgxx_gmp_gmi_txx_int
8813 {
8814     uint64_t u;
8815     struct bdk_bgxx_gmp_gmi_txx_int_s
8816     {
8817 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8818         uint64_t reserved_5_63         : 59;
8819         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1C/H) A packet with a PTP request was not able to be sent due to XSCOL. */
8820         uint64_t late_col              : 1;  /**< [  3:  3](R/W1C/H) TX late collision. (SGMII/1000BASE-X half-duplex only) */
8821         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1C/H) TX excessive deferral. (SGMII/1000BASE-X half-duplex only) */
8822         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1C/H) TX excessive collisions. (SGMII/1000BASE-X half-duplex only) */
8823         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) TX underflow. */
8824 #else /* Word 0 - Little Endian */
8825         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) TX underflow. */
8826         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1C/H) TX excessive collisions. (SGMII/1000BASE-X half-duplex only) */
8827         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1C/H) TX excessive deferral. (SGMII/1000BASE-X half-duplex only) */
8828         uint64_t late_col              : 1;  /**< [  3:  3](R/W1C/H) TX late collision. (SGMII/1000BASE-X half-duplex only) */
8829         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1C/H) A packet with a PTP request was not able to be sent due to XSCOL. */
8830         uint64_t reserved_5_63         : 59;
8831 #endif /* Word 0 - End */
8832     } s;
8833     /* struct bdk_bgxx_gmp_gmi_txx_int_s cn; */
8834 };
8835 typedef union bdk_bgxx_gmp_gmi_txx_int bdk_bgxx_gmp_gmi_txx_int_t;
8836 
8837 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_INT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_INT(unsigned long a,unsigned long b)8838 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_INT(unsigned long a, unsigned long b)
8839 {
8840     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8841         return 0x87e0e0038500ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8842     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8843         return 0x87e0e0038500ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8844     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8845         return 0x87e0e0038500ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8846     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_INT", 2, a, b, 0, 0);
8847 }
8848 
8849 #define typedef_BDK_BGXX_GMP_GMI_TXX_INT(a,b) bdk_bgxx_gmp_gmi_txx_int_t
8850 #define bustype_BDK_BGXX_GMP_GMI_TXX_INT(a,b) BDK_CSR_TYPE_RSL
8851 #define basename_BDK_BGXX_GMP_GMI_TXX_INT(a,b) "BGXX_GMP_GMI_TXX_INT"
8852 #define device_bar_BDK_BGXX_GMP_GMI_TXX_INT(a,b) 0x0 /* PF_BAR0 */
8853 #define busnum_BDK_BGXX_GMP_GMI_TXX_INT(a,b) (a)
8854 #define arguments_BDK_BGXX_GMP_GMI_TXX_INT(a,b) (a),(b),-1,-1
8855 
8856 /**
8857  * Register (RSL) bgx#_gmp_gmi_tx#_int_ena_w1c
8858  *
8859  * BGX GMI TX Interrupt Enable Clear Registers
8860  * This register clears interrupt enable bits.
8861  */
8862 union bdk_bgxx_gmp_gmi_txx_int_ena_w1c
8863 {
8864     uint64_t u;
8865     struct bdk_bgxx_gmp_gmi_txx_int_ena_w1c_s
8866     {
8867 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8868         uint64_t reserved_5_63         : 59;
8869         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
8870         uint64_t late_col              : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
8871         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
8872         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
8873         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
8874 #else /* Word 0 - Little Endian */
8875         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
8876         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
8877         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
8878         uint64_t late_col              : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
8879         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
8880         uint64_t reserved_5_63         : 59;
8881 #endif /* Word 0 - End */
8882     } s;
8883     /* struct bdk_bgxx_gmp_gmi_txx_int_ena_w1c_s cn81xx; */
8884     /* struct bdk_bgxx_gmp_gmi_txx_int_ena_w1c_s cn88xx; */
8885     struct bdk_bgxx_gmp_gmi_txx_int_ena_w1c_cn83xx
8886     {
8887 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8888         uint64_t reserved_5_63         : 59;
8889         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
8890         uint64_t late_col              : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
8891         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
8892         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
8893         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
8894 #else /* Word 0 - Little Endian */
8895         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
8896         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
8897         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
8898         uint64_t late_col              : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
8899         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
8900         uint64_t reserved_5_63         : 59;
8901 #endif /* Word 0 - End */
8902     } cn83xx;
8903 };
8904 typedef union bdk_bgxx_gmp_gmi_txx_int_ena_w1c bdk_bgxx_gmp_gmi_txx_int_ena_w1c_t;
8905 
8906 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1C(unsigned long a,unsigned long b)8907 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1C(unsigned long a, unsigned long b)
8908 {
8909     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8910         return 0x87e0e0038510ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8911     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8912         return 0x87e0e0038510ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8913     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8914         return 0x87e0e0038510ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8915     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_INT_ENA_W1C", 2, a, b, 0, 0);
8916 }
8917 
8918 #define typedef_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1C(a,b) bdk_bgxx_gmp_gmi_txx_int_ena_w1c_t
8919 #define bustype_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1C(a,b) BDK_CSR_TYPE_RSL
8920 #define basename_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1C(a,b) "BGXX_GMP_GMI_TXX_INT_ENA_W1C"
8921 #define device_bar_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
8922 #define busnum_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1C(a,b) (a)
8923 #define arguments_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1C(a,b) (a),(b),-1,-1
8924 
8925 /**
8926  * Register (RSL) bgx#_gmp_gmi_tx#_int_ena_w1s
8927  *
8928  * BGX GMI TX Interrupt Enable Set Registers
8929  * This register sets interrupt enable bits.
8930  */
8931 union bdk_bgxx_gmp_gmi_txx_int_ena_w1s
8932 {
8933     uint64_t u;
8934     struct bdk_bgxx_gmp_gmi_txx_int_ena_w1s_s
8935     {
8936 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8937         uint64_t reserved_5_63         : 59;
8938         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
8939         uint64_t late_col              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
8940         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
8941         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
8942         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
8943 #else /* Word 0 - Little Endian */
8944         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
8945         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
8946         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
8947         uint64_t late_col              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
8948         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
8949         uint64_t reserved_5_63         : 59;
8950 #endif /* Word 0 - End */
8951     } s;
8952     /* struct bdk_bgxx_gmp_gmi_txx_int_ena_w1s_s cn81xx; */
8953     /* struct bdk_bgxx_gmp_gmi_txx_int_ena_w1s_s cn88xx; */
8954     struct bdk_bgxx_gmp_gmi_txx_int_ena_w1s_cn83xx
8955     {
8956 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8957         uint64_t reserved_5_63         : 59;
8958         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
8959         uint64_t late_col              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
8960         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
8961         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
8962         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
8963 #else /* Word 0 - Little Endian */
8964         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
8965         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
8966         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
8967         uint64_t late_col              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
8968         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
8969         uint64_t reserved_5_63         : 59;
8970 #endif /* Word 0 - End */
8971     } cn83xx;
8972 };
8973 typedef union bdk_bgxx_gmp_gmi_txx_int_ena_w1s bdk_bgxx_gmp_gmi_txx_int_ena_w1s_t;
8974 
8975 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1S(unsigned long a,unsigned long b)8976 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1S(unsigned long a, unsigned long b)
8977 {
8978     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
8979         return 0x87e0e0038518ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8980     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
8981         return 0x87e0e0038518ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
8982     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
8983         return 0x87e0e0038518ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
8984     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_INT_ENA_W1S", 2, a, b, 0, 0);
8985 }
8986 
8987 #define typedef_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1S(a,b) bdk_bgxx_gmp_gmi_txx_int_ena_w1s_t
8988 #define bustype_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1S(a,b) BDK_CSR_TYPE_RSL
8989 #define basename_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1S(a,b) "BGXX_GMP_GMI_TXX_INT_ENA_W1S"
8990 #define device_bar_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
8991 #define busnum_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1S(a,b) (a)
8992 #define arguments_BDK_BGXX_GMP_GMI_TXX_INT_ENA_W1S(a,b) (a),(b),-1,-1
8993 
8994 /**
8995  * Register (RSL) bgx#_gmp_gmi_tx#_int_w1s
8996  *
8997  * BGX GMI TX Interrupt Set Registers
8998  * This register sets interrupt bits.
8999  */
9000 union bdk_bgxx_gmp_gmi_txx_int_w1s
9001 {
9002     uint64_t u;
9003     struct bdk_bgxx_gmp_gmi_txx_int_w1s_s
9004     {
9005 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9006         uint64_t reserved_5_63         : 59;
9007         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
9008         uint64_t late_col              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
9009         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
9010         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
9011         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
9012 #else /* Word 0 - Little Endian */
9013         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
9014         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
9015         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
9016         uint64_t late_col              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
9017         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
9018         uint64_t reserved_5_63         : 59;
9019 #endif /* Word 0 - End */
9020     } s;
9021     /* struct bdk_bgxx_gmp_gmi_txx_int_w1s_s cn81xx; */
9022     /* struct bdk_bgxx_gmp_gmi_txx_int_w1s_s cn88xx; */
9023     struct bdk_bgxx_gmp_gmi_txx_int_w1s_cn83xx
9024     {
9025 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9026         uint64_t reserved_5_63         : 59;
9027         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
9028         uint64_t late_col              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
9029         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
9030         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
9031         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
9032 #else /* Word 0 - Little Endian */
9033         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[UNDFLW]. */
9034         uint64_t xscol                 : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSCOL]. */
9035         uint64_t xsdef                 : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[XSDEF]. */
9036         uint64_t late_col              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[LATE_COL]. */
9037         uint64_t ptp_lost              : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_GMP_GMI_TX(0..3)_INT[PTP_LOST]. */
9038         uint64_t reserved_5_63         : 59;
9039 #endif /* Word 0 - End */
9040     } cn83xx;
9041 };
9042 typedef union bdk_bgxx_gmp_gmi_txx_int_w1s bdk_bgxx_gmp_gmi_txx_int_w1s_t;
9043 
9044 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_INT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_INT_W1S(unsigned long a,unsigned long b)9045 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_INT_W1S(unsigned long a, unsigned long b)
9046 {
9047     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9048         return 0x87e0e0038508ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9049     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9050         return 0x87e0e0038508ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9051     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9052         return 0x87e0e0038508ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9053     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_INT_W1S", 2, a, b, 0, 0);
9054 }
9055 
9056 #define typedef_BDK_BGXX_GMP_GMI_TXX_INT_W1S(a,b) bdk_bgxx_gmp_gmi_txx_int_w1s_t
9057 #define bustype_BDK_BGXX_GMP_GMI_TXX_INT_W1S(a,b) BDK_CSR_TYPE_RSL
9058 #define basename_BDK_BGXX_GMP_GMI_TXX_INT_W1S(a,b) "BGXX_GMP_GMI_TXX_INT_W1S"
9059 #define device_bar_BDK_BGXX_GMP_GMI_TXX_INT_W1S(a,b) 0x0 /* PF_BAR0 */
9060 #define busnum_BDK_BGXX_GMP_GMI_TXX_INT_W1S(a,b) (a)
9061 #define arguments_BDK_BGXX_GMP_GMI_TXX_INT_W1S(a,b) (a),(b),-1,-1
9062 
9063 /**
9064  * Register (RSL) bgx#_gmp_gmi_tx#_min_pkt
9065  *
9066  * BGX GMI TX Minimum-Size-Packet Registers
9067  */
9068 union bdk_bgxx_gmp_gmi_txx_min_pkt
9069 {
9070     uint64_t u;
9071     struct bdk_bgxx_gmp_gmi_txx_min_pkt_s
9072     {
9073 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9074         uint64_t reserved_8_63         : 56;
9075         uint64_t min_size              : 8;  /**< [  7:  0](R/W) Minimum frame size in bytes before the FCS is applied.
9076                                                                  Padding is only appended when BGX()_GMP_GMI_TX()_APPEND[PAD] for the corresponding
9077                                                                  LMAC is set.
9078 
9079                                                                  When LMAC_TYPE=SGMII/QSGMII, packets are padded to [MIN_SIZE]+1. The reset value pads to
9080                                                                  60
9081                                                                  bytes. */
9082 #else /* Word 0 - Little Endian */
9083         uint64_t min_size              : 8;  /**< [  7:  0](R/W) Minimum frame size in bytes before the FCS is applied.
9084                                                                  Padding is only appended when BGX()_GMP_GMI_TX()_APPEND[PAD] for the corresponding
9085                                                                  LMAC is set.
9086 
9087                                                                  When LMAC_TYPE=SGMII/QSGMII, packets are padded to [MIN_SIZE]+1. The reset value pads to
9088                                                                  60
9089                                                                  bytes. */
9090         uint64_t reserved_8_63         : 56;
9091 #endif /* Word 0 - End */
9092     } s;
9093     /* struct bdk_bgxx_gmp_gmi_txx_min_pkt_s cn81xx; */
9094     struct bdk_bgxx_gmp_gmi_txx_min_pkt_cn88xx
9095     {
9096 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9097         uint64_t reserved_8_63         : 56;
9098         uint64_t min_size              : 8;  /**< [  7:  0](R/W) Minimum frame size in bytes before the FCS is applied.
9099                                                                  Padding is only appended when BGX()_GMP_GMI_TX()_APPEND[PAD] for the corresponding
9100                                                                  LMAC is set.
9101 
9102                                                                  In SGMII mode, packets are padded to [MIN_SIZE]+1. The reset value pads to 60 bytes. */
9103 #else /* Word 0 - Little Endian */
9104         uint64_t min_size              : 8;  /**< [  7:  0](R/W) Minimum frame size in bytes before the FCS is applied.
9105                                                                  Padding is only appended when BGX()_GMP_GMI_TX()_APPEND[PAD] for the corresponding
9106                                                                  LMAC is set.
9107 
9108                                                                  In SGMII mode, packets are padded to [MIN_SIZE]+1. The reset value pads to 60 bytes. */
9109         uint64_t reserved_8_63         : 56;
9110 #endif /* Word 0 - End */
9111     } cn88xx;
9112     /* struct bdk_bgxx_gmp_gmi_txx_min_pkt_s cn83xx; */
9113 };
9114 typedef union bdk_bgxx_gmp_gmi_txx_min_pkt bdk_bgxx_gmp_gmi_txx_min_pkt_t;
9115 
9116 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_MIN_PKT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_MIN_PKT(unsigned long a,unsigned long b)9117 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_MIN_PKT(unsigned long a, unsigned long b)
9118 {
9119     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9120         return 0x87e0e0038240ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9121     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9122         return 0x87e0e0038240ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9123     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9124         return 0x87e0e0038240ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9125     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_MIN_PKT", 2, a, b, 0, 0);
9126 }
9127 
9128 #define typedef_BDK_BGXX_GMP_GMI_TXX_MIN_PKT(a,b) bdk_bgxx_gmp_gmi_txx_min_pkt_t
9129 #define bustype_BDK_BGXX_GMP_GMI_TXX_MIN_PKT(a,b) BDK_CSR_TYPE_RSL
9130 #define basename_BDK_BGXX_GMP_GMI_TXX_MIN_PKT(a,b) "BGXX_GMP_GMI_TXX_MIN_PKT"
9131 #define device_bar_BDK_BGXX_GMP_GMI_TXX_MIN_PKT(a,b) 0x0 /* PF_BAR0 */
9132 #define busnum_BDK_BGXX_GMP_GMI_TXX_MIN_PKT(a,b) (a)
9133 #define arguments_BDK_BGXX_GMP_GMI_TXX_MIN_PKT(a,b) (a),(b),-1,-1
9134 
9135 /**
9136  * Register (RSL) bgx#_gmp_gmi_tx#_pause_pkt_interval
9137  *
9138  * BGX GMI TX PAUSE-Packet Transmission-Interval Registers
9139  * This register specifies how often PAUSE packets are sent.
9140  * Internal:
9141  * Notes:
9142  * Choosing proper values of BGX()_GMP_GMI_TX()_PAUSE_PKT_TIME[PTIME] and
9143  * BGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
9144  * designer.  It is suggested that TIME be much greater than INTERVAL and
9145  * BGX()_GMP_GMI_TX()_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
9146  * count and then when the backpressure condition is lifted, a PAUSE packet
9147  * with TIME==0 will be sent indicating that Octane is ready for additional
9148  * data.
9149  *
9150  * If the system chooses to not set BGX()_GMP_GMI_TX()_PAUSE_ZERO[SEND], then it is
9151  * suggested that TIME and INTERVAL are programmed such that they satisify the
9152  * following rule:
9153  *
9154  * _ INTERVAL \<= TIME - (largest_pkt_size + IFG + pause_pkt_size)
9155  *
9156  * where largest_pkt_size is that largest packet that the system can send
9157  * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
9158  * of the PAUSE packet (normally 64B).
9159  */
9160 union bdk_bgxx_gmp_gmi_txx_pause_pkt_interval
9161 {
9162     uint64_t u;
9163     struct bdk_bgxx_gmp_gmi_txx_pause_pkt_interval_s
9164     {
9165 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9166         uint64_t reserved_16_63        : 48;
9167         uint64_t interval              : 16; /**< [ 15:  0](R/W) Arbitrate for a 802.3 PAUSE packet every ([INTERVAL] * 512)
9168                                                                  bit-times. Normally, 0 \< [INTERVAL] \< BGX()_GMP_GMI_TX()_PAUSE_PKT_TIME[PTIME].
9169 
9170                                                                  [INTERVAL] = 0 only sends a single PAUSE packet for each backpressure event.
9171                                                                  BGX()_GMP_GMI_TX()_PAUSE_ZERO[SEND] must be 1 when [INTERVAL] = 0.
9172                                                                  [INTERVAL] should be 0x0 if BGX()_GMP_GMI_TX()_CTL[TX_FC_TYPE] is clear (G.999.1). */
9173 #else /* Word 0 - Little Endian */
9174         uint64_t interval              : 16; /**< [ 15:  0](R/W) Arbitrate for a 802.3 PAUSE packet every ([INTERVAL] * 512)
9175                                                                  bit-times. Normally, 0 \< [INTERVAL] \< BGX()_GMP_GMI_TX()_PAUSE_PKT_TIME[PTIME].
9176 
9177                                                                  [INTERVAL] = 0 only sends a single PAUSE packet for each backpressure event.
9178                                                                  BGX()_GMP_GMI_TX()_PAUSE_ZERO[SEND] must be 1 when [INTERVAL] = 0.
9179                                                                  [INTERVAL] should be 0x0 if BGX()_GMP_GMI_TX()_CTL[TX_FC_TYPE] is clear (G.999.1). */
9180         uint64_t reserved_16_63        : 48;
9181 #endif /* Word 0 - End */
9182     } s;
9183     /* struct bdk_bgxx_gmp_gmi_txx_pause_pkt_interval_s cn81xx; */
9184     struct bdk_bgxx_gmp_gmi_txx_pause_pkt_interval_cn88xx
9185     {
9186 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9187         uint64_t reserved_16_63        : 48;
9188         uint64_t interval              : 16; /**< [ 15:  0](R/W) Arbitrate for a 802.3 PAUSE packet every ([INTERVAL] * 512)
9189                                                                  bit-times. Normally, 0 \< [INTERVAL] \< BGX()_GMP_GMI_TX()_PAUSE_PKT_TIME[PTIME].
9190 
9191                                                                  [INTERVAL] = 0 only sends a single PAUSE packet for each backpressure event.
9192                                                                  BGX()_GMP_GMI_TX()_PAUSE_ZERO[SEND] must be 1 when [INTERVAL] = 0. */
9193 #else /* Word 0 - Little Endian */
9194         uint64_t interval              : 16; /**< [ 15:  0](R/W) Arbitrate for a 802.3 PAUSE packet every ([INTERVAL] * 512)
9195                                                                  bit-times. Normally, 0 \< [INTERVAL] \< BGX()_GMP_GMI_TX()_PAUSE_PKT_TIME[PTIME].
9196 
9197                                                                  [INTERVAL] = 0 only sends a single PAUSE packet for each backpressure event.
9198                                                                  BGX()_GMP_GMI_TX()_PAUSE_ZERO[SEND] must be 1 when [INTERVAL] = 0. */
9199         uint64_t reserved_16_63        : 48;
9200 #endif /* Word 0 - End */
9201     } cn88xx;
9202     /* struct bdk_bgxx_gmp_gmi_txx_pause_pkt_interval_s cn83xx; */
9203 };
9204 typedef union bdk_bgxx_gmp_gmi_txx_pause_pkt_interval bdk_bgxx_gmp_gmi_txx_pause_pkt_interval_t;
9205 
9206 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(unsigned long a,unsigned long b)9207 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(unsigned long a, unsigned long b)
9208 {
9209     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9210         return 0x87e0e0038248ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9211     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9212         return 0x87e0e0038248ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9213     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9214         return 0x87e0e0038248ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9215     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL", 2, a, b, 0, 0);
9216 }
9217 
9218 #define typedef_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(a,b) bdk_bgxx_gmp_gmi_txx_pause_pkt_interval_t
9219 #define bustype_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(a,b) BDK_CSR_TYPE_RSL
9220 #define basename_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(a,b) "BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL"
9221 #define device_bar_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(a,b) 0x0 /* PF_BAR0 */
9222 #define busnum_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(a,b) (a)
9223 #define arguments_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(a,b) (a),(b),-1,-1
9224 
9225 /**
9226  * Register (RSL) bgx#_gmp_gmi_tx#_pause_pkt_time
9227  *
9228  * BGX GMI TX PAUSE Packet PAUSE-Time Registers
9229  */
9230 union bdk_bgxx_gmp_gmi_txx_pause_pkt_time
9231 {
9232     uint64_t u;
9233     struct bdk_bgxx_gmp_gmi_txx_pause_pkt_time_s
9234     {
9235 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9236         uint64_t reserved_16_63        : 48;
9237         uint64_t ptime                 : 16; /**< [ 15:  0](R/W) Provides the pause_time field placed in outbound 802.3 PAUSE packets
9238                                                                  in 512 bit-times. Normally, [PTIME] \>
9239                                                                  BGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL[INTERVAL]. For programming information see
9240                                                                  BGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL.
9241                                                                  [PTIME] should be 0x0 if BGX()_GMP_GMI_TX()_CTL[TX_FC_TYPE] is clear (G.999.1). */
9242 #else /* Word 0 - Little Endian */
9243         uint64_t ptime                 : 16; /**< [ 15:  0](R/W) Provides the pause_time field placed in outbound 802.3 PAUSE packets
9244                                                                  in 512 bit-times. Normally, [PTIME] \>
9245                                                                  BGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL[INTERVAL]. For programming information see
9246                                                                  BGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL.
9247                                                                  [PTIME] should be 0x0 if BGX()_GMP_GMI_TX()_CTL[TX_FC_TYPE] is clear (G.999.1). */
9248         uint64_t reserved_16_63        : 48;
9249 #endif /* Word 0 - End */
9250     } s;
9251     /* struct bdk_bgxx_gmp_gmi_txx_pause_pkt_time_s cn81xx; */
9252     struct bdk_bgxx_gmp_gmi_txx_pause_pkt_time_cn88xx
9253     {
9254 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9255         uint64_t reserved_16_63        : 48;
9256         uint64_t ptime                 : 16; /**< [ 15:  0](R/W) Provides the pause_time field placed in outbound 802.3 PAUSE packets
9257                                                                  in 512 bit-times. Normally, [PTIME] \>
9258                                                                  BGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL[INTERVAL]. For programming information see
9259                                                                  BGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL. */
9260 #else /* Word 0 - Little Endian */
9261         uint64_t ptime                 : 16; /**< [ 15:  0](R/W) Provides the pause_time field placed in outbound 802.3 PAUSE packets
9262                                                                  in 512 bit-times. Normally, [PTIME] \>
9263                                                                  BGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL[INTERVAL]. For programming information see
9264                                                                  BGX()_GMP_GMI_TX()_PAUSE_PKT_INTERVAL. */
9265         uint64_t reserved_16_63        : 48;
9266 #endif /* Word 0 - End */
9267     } cn88xx;
9268     /* struct bdk_bgxx_gmp_gmi_txx_pause_pkt_time_s cn83xx; */
9269 };
9270 typedef union bdk_bgxx_gmp_gmi_txx_pause_pkt_time bdk_bgxx_gmp_gmi_txx_pause_pkt_time_t;
9271 
9272 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(unsigned long a,unsigned long b)9273 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(unsigned long a, unsigned long b)
9274 {
9275     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9276         return 0x87e0e0038238ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9277     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9278         return 0x87e0e0038238ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9279     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9280         return 0x87e0e0038238ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9281     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME", 2, a, b, 0, 0);
9282 }
9283 
9284 #define typedef_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(a,b) bdk_bgxx_gmp_gmi_txx_pause_pkt_time_t
9285 #define bustype_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(a,b) BDK_CSR_TYPE_RSL
9286 #define basename_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(a,b) "BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME"
9287 #define device_bar_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(a,b) 0x0 /* PF_BAR0 */
9288 #define busnum_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(a,b) (a)
9289 #define arguments_BDK_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(a,b) (a),(b),-1,-1
9290 
9291 /**
9292  * Register (RSL) bgx#_gmp_gmi_tx#_pause_togo
9293  *
9294  * BGX GMI TX Time-to-Backpressure Registers
9295  */
9296 union bdk_bgxx_gmp_gmi_txx_pause_togo
9297 {
9298     uint64_t u;
9299     struct bdk_bgxx_gmp_gmi_txx_pause_togo_s
9300     {
9301 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9302         uint64_t reserved_16_63        : 48;
9303         uint64_t ptime                 : 16; /**< [ 15:  0](RO/H) Amount of time remaining to backpressure, from the standard 802.3 PAUSE timer. */
9304 #else /* Word 0 - Little Endian */
9305         uint64_t ptime                 : 16; /**< [ 15:  0](RO/H) Amount of time remaining to backpressure, from the standard 802.3 PAUSE timer. */
9306         uint64_t reserved_16_63        : 48;
9307 #endif /* Word 0 - End */
9308     } s;
9309     /* struct bdk_bgxx_gmp_gmi_txx_pause_togo_s cn; */
9310 };
9311 typedef union bdk_bgxx_gmp_gmi_txx_pause_togo bdk_bgxx_gmp_gmi_txx_pause_togo_t;
9312 
9313 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_PAUSE_TOGO(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_PAUSE_TOGO(unsigned long a,unsigned long b)9314 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_PAUSE_TOGO(unsigned long a, unsigned long b)
9315 {
9316     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9317         return 0x87e0e0038258ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9318     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9319         return 0x87e0e0038258ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9320     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9321         return 0x87e0e0038258ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9322     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_PAUSE_TOGO", 2, a, b, 0, 0);
9323 }
9324 
9325 #define typedef_BDK_BGXX_GMP_GMI_TXX_PAUSE_TOGO(a,b) bdk_bgxx_gmp_gmi_txx_pause_togo_t
9326 #define bustype_BDK_BGXX_GMP_GMI_TXX_PAUSE_TOGO(a,b) BDK_CSR_TYPE_RSL
9327 #define basename_BDK_BGXX_GMP_GMI_TXX_PAUSE_TOGO(a,b) "BGXX_GMP_GMI_TXX_PAUSE_TOGO"
9328 #define device_bar_BDK_BGXX_GMP_GMI_TXX_PAUSE_TOGO(a,b) 0x0 /* PF_BAR0 */
9329 #define busnum_BDK_BGXX_GMP_GMI_TXX_PAUSE_TOGO(a,b) (a)
9330 #define arguments_BDK_BGXX_GMP_GMI_TXX_PAUSE_TOGO(a,b) (a),(b),-1,-1
9331 
9332 /**
9333  * Register (RSL) bgx#_gmp_gmi_tx#_pause_zero
9334  *
9335  * BGX GMI TX PAUSE-Zero-Enable Registers
9336  */
9337 union bdk_bgxx_gmp_gmi_txx_pause_zero
9338 {
9339     uint64_t u;
9340     struct bdk_bgxx_gmp_gmi_txx_pause_zero_s
9341     {
9342 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9343         uint64_t reserved_1_63         : 63;
9344         uint64_t send                  : 1;  /**< [  0:  0](R/W) Send PAUSE-zero enable. When this bit is set, and the backpressure condition is clear, it
9345                                                                  allows sending a PAUSE packet with pause_time of 0 to enable the channel.
9346                                                                  [SEND] should be set if BGX()_GMP_GMI_TX()_CTL[TX_FC_TYPE] is clear (G.999.1). */
9347 #else /* Word 0 - Little Endian */
9348         uint64_t send                  : 1;  /**< [  0:  0](R/W) Send PAUSE-zero enable. When this bit is set, and the backpressure condition is clear, it
9349                                                                  allows sending a PAUSE packet with pause_time of 0 to enable the channel.
9350                                                                  [SEND] should be set if BGX()_GMP_GMI_TX()_CTL[TX_FC_TYPE] is clear (G.999.1). */
9351         uint64_t reserved_1_63         : 63;
9352 #endif /* Word 0 - End */
9353     } s;
9354     /* struct bdk_bgxx_gmp_gmi_txx_pause_zero_s cn81xx; */
9355     struct bdk_bgxx_gmp_gmi_txx_pause_zero_cn88xx
9356     {
9357 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9358         uint64_t reserved_1_63         : 63;
9359         uint64_t send                  : 1;  /**< [  0:  0](R/W) Send PAUSE-zero enable.When this bit is set, and the backpressure condition is clear, it
9360                                                                  allows sending a PAUSE packet with pause_time of 0 to enable the channel. */
9361 #else /* Word 0 - Little Endian */
9362         uint64_t send                  : 1;  /**< [  0:  0](R/W) Send PAUSE-zero enable.When this bit is set, and the backpressure condition is clear, it
9363                                                                  allows sending a PAUSE packet with pause_time of 0 to enable the channel. */
9364         uint64_t reserved_1_63         : 63;
9365 #endif /* Word 0 - End */
9366     } cn88xx;
9367     /* struct bdk_bgxx_gmp_gmi_txx_pause_zero_s cn83xx; */
9368 };
9369 typedef union bdk_bgxx_gmp_gmi_txx_pause_zero bdk_bgxx_gmp_gmi_txx_pause_zero_t;
9370 
9371 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_PAUSE_ZERO(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_PAUSE_ZERO(unsigned long a,unsigned long b)9372 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_PAUSE_ZERO(unsigned long a, unsigned long b)
9373 {
9374     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9375         return 0x87e0e0038260ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9376     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9377         return 0x87e0e0038260ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9378     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9379         return 0x87e0e0038260ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9380     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_PAUSE_ZERO", 2, a, b, 0, 0);
9381 }
9382 
9383 #define typedef_BDK_BGXX_GMP_GMI_TXX_PAUSE_ZERO(a,b) bdk_bgxx_gmp_gmi_txx_pause_zero_t
9384 #define bustype_BDK_BGXX_GMP_GMI_TXX_PAUSE_ZERO(a,b) BDK_CSR_TYPE_RSL
9385 #define basename_BDK_BGXX_GMP_GMI_TXX_PAUSE_ZERO(a,b) "BGXX_GMP_GMI_TXX_PAUSE_ZERO"
9386 #define device_bar_BDK_BGXX_GMP_GMI_TXX_PAUSE_ZERO(a,b) 0x0 /* PF_BAR0 */
9387 #define busnum_BDK_BGXX_GMP_GMI_TXX_PAUSE_ZERO(a,b) (a)
9388 #define arguments_BDK_BGXX_GMP_GMI_TXX_PAUSE_ZERO(a,b) (a),(b),-1,-1
9389 
9390 /**
9391  * Register (RSL) bgx#_gmp_gmi_tx#_sgmii_ctl
9392  *
9393  * BGX SGMII Control Registers
9394  */
9395 union bdk_bgxx_gmp_gmi_txx_sgmii_ctl
9396 {
9397     uint64_t u;
9398     struct bdk_bgxx_gmp_gmi_txx_sgmii_ctl_s
9399     {
9400 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9401         uint64_t reserved_1_63         : 63;
9402         uint64_t align                 : 1;  /**< [  0:  0](R/W) Align the transmission to even cycles: (SGMII/1000BASE-X half-duplex only)
9403                                                                  Recommended value is: ALIGN = !BGX()_GMP_GMI_TX()_APPEND[PREAMBLE].
9404                                                                  (See Transmit Conversion to Code groups, Transmit Conversion to Code Groups for a complete
9405                                                                  discussion.)
9406 
9407                                                                  _ 0 = Data can be sent on any cycle. In this mode, the interface functions at maximum
9408                                                                  bandwidth. It is possible for the TX PCS machine to drop the first byte of the TX frame.
9409                                                                  When BGX()_GMP_GMI_TX()_APPEND[PREAMBLE] is set, the first byte is a preamble
9410                                                                  byte, which can be dropped to compensate for an extended IPG.
9411 
9412                                                                  _ 1 = Data is only sent on even cycles. In this mode, there can be bandwidth implications
9413                                                                  when sending odd-byte packets as the IPG can extend an extra cycle. There will be no loss
9414                                                                  of data. */
9415 #else /* Word 0 - Little Endian */
9416         uint64_t align                 : 1;  /**< [  0:  0](R/W) Align the transmission to even cycles: (SGMII/1000BASE-X half-duplex only)
9417                                                                  Recommended value is: ALIGN = !BGX()_GMP_GMI_TX()_APPEND[PREAMBLE].
9418                                                                  (See Transmit Conversion to Code groups, Transmit Conversion to Code Groups for a complete
9419                                                                  discussion.)
9420 
9421                                                                  _ 0 = Data can be sent on any cycle. In this mode, the interface functions at maximum
9422                                                                  bandwidth. It is possible for the TX PCS machine to drop the first byte of the TX frame.
9423                                                                  When BGX()_GMP_GMI_TX()_APPEND[PREAMBLE] is set, the first byte is a preamble
9424                                                                  byte, which can be dropped to compensate for an extended IPG.
9425 
9426                                                                  _ 1 = Data is only sent on even cycles. In this mode, there can be bandwidth implications
9427                                                                  when sending odd-byte packets as the IPG can extend an extra cycle. There will be no loss
9428                                                                  of data. */
9429         uint64_t reserved_1_63         : 63;
9430 #endif /* Word 0 - End */
9431     } s;
9432     /* struct bdk_bgxx_gmp_gmi_txx_sgmii_ctl_s cn; */
9433 };
9434 typedef union bdk_bgxx_gmp_gmi_txx_sgmii_ctl bdk_bgxx_gmp_gmi_txx_sgmii_ctl_t;
9435 
9436 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_SGMII_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_SGMII_CTL(unsigned long a,unsigned long b)9437 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_SGMII_CTL(unsigned long a, unsigned long b)
9438 {
9439     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9440         return 0x87e0e0038300ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9441     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9442         return 0x87e0e0038300ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9443     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9444         return 0x87e0e0038300ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9445     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_SGMII_CTL", 2, a, b, 0, 0);
9446 }
9447 
9448 #define typedef_BDK_BGXX_GMP_GMI_TXX_SGMII_CTL(a,b) bdk_bgxx_gmp_gmi_txx_sgmii_ctl_t
9449 #define bustype_BDK_BGXX_GMP_GMI_TXX_SGMII_CTL(a,b) BDK_CSR_TYPE_RSL
9450 #define basename_BDK_BGXX_GMP_GMI_TXX_SGMII_CTL(a,b) "BGXX_GMP_GMI_TXX_SGMII_CTL"
9451 #define device_bar_BDK_BGXX_GMP_GMI_TXX_SGMII_CTL(a,b) 0x0 /* PF_BAR0 */
9452 #define busnum_BDK_BGXX_GMP_GMI_TXX_SGMII_CTL(a,b) (a)
9453 #define arguments_BDK_BGXX_GMP_GMI_TXX_SGMII_CTL(a,b) (a),(b),-1,-1
9454 
9455 /**
9456  * Register (RSL) bgx#_gmp_gmi_tx#_slot
9457  *
9458  * BGX GMI TX Slottime Counter Registers
9459  */
9460 union bdk_bgxx_gmp_gmi_txx_slot
9461 {
9462     uint64_t u;
9463     struct bdk_bgxx_gmp_gmi_txx_slot_s
9464     {
9465 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9466         uint64_t reserved_10_63        : 54;
9467         uint64_t slot                  : 10; /**< [  9:  0](R/W) Slottime (refer to IEEE 802.3 to set correctly):
9468                                                                  10/100 Mbs: Set SLOT to 0x40.
9469                                                                  1000 Mbs: Set SLOT to 0x200.
9470 
9471                                                                  SGMII/QSGMII/1000Base-X only. */
9472 #else /* Word 0 - Little Endian */
9473         uint64_t slot                  : 10; /**< [  9:  0](R/W) Slottime (refer to IEEE 802.3 to set correctly):
9474                                                                  10/100 Mbs: Set SLOT to 0x40.
9475                                                                  1000 Mbs: Set SLOT to 0x200.
9476 
9477                                                                  SGMII/QSGMII/1000Base-X only. */
9478         uint64_t reserved_10_63        : 54;
9479 #endif /* Word 0 - End */
9480     } s;
9481     /* struct bdk_bgxx_gmp_gmi_txx_slot_s cn81xx; */
9482     struct bdk_bgxx_gmp_gmi_txx_slot_cn88xx
9483     {
9484 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9485         uint64_t reserved_10_63        : 54;
9486         uint64_t slot                  : 10; /**< [  9:  0](R/W) Slottime (refer to IEEE 802.3 to set correctly):
9487                                                                  10/100 Mbs: Set SLOT to 0x40.
9488                                                                  1000 Mbs: Set SLOT to 0x200.
9489 
9490                                                                  SGMII/1000Base-X only. */
9491 #else /* Word 0 - Little Endian */
9492         uint64_t slot                  : 10; /**< [  9:  0](R/W) Slottime (refer to IEEE 802.3 to set correctly):
9493                                                                  10/100 Mbs: Set SLOT to 0x40.
9494                                                                  1000 Mbs: Set SLOT to 0x200.
9495 
9496                                                                  SGMII/1000Base-X only. */
9497         uint64_t reserved_10_63        : 54;
9498 #endif /* Word 0 - End */
9499     } cn88xx;
9500     /* struct bdk_bgxx_gmp_gmi_txx_slot_s cn83xx; */
9501 };
9502 typedef union bdk_bgxx_gmp_gmi_txx_slot bdk_bgxx_gmp_gmi_txx_slot_t;
9503 
9504 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_SLOT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_SLOT(unsigned long a,unsigned long b)9505 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_SLOT(unsigned long a, unsigned long b)
9506 {
9507     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9508         return 0x87e0e0038220ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9509     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9510         return 0x87e0e0038220ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9511     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9512         return 0x87e0e0038220ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9513     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_SLOT", 2, a, b, 0, 0);
9514 }
9515 
9516 #define typedef_BDK_BGXX_GMP_GMI_TXX_SLOT(a,b) bdk_bgxx_gmp_gmi_txx_slot_t
9517 #define bustype_BDK_BGXX_GMP_GMI_TXX_SLOT(a,b) BDK_CSR_TYPE_RSL
9518 #define basename_BDK_BGXX_GMP_GMI_TXX_SLOT(a,b) "BGXX_GMP_GMI_TXX_SLOT"
9519 #define device_bar_BDK_BGXX_GMP_GMI_TXX_SLOT(a,b) 0x0 /* PF_BAR0 */
9520 #define busnum_BDK_BGXX_GMP_GMI_TXX_SLOT(a,b) (a)
9521 #define arguments_BDK_BGXX_GMP_GMI_TXX_SLOT(a,b) (a),(b),-1,-1
9522 
9523 /**
9524  * Register (RSL) bgx#_gmp_gmi_tx#_soft_pause
9525  *
9526  * BGX GMI TX Software PAUSE Registers
9527  */
9528 union bdk_bgxx_gmp_gmi_txx_soft_pause
9529 {
9530     uint64_t u;
9531     struct bdk_bgxx_gmp_gmi_txx_soft_pause_s
9532     {
9533 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9534         uint64_t reserved_16_63        : 48;
9535         uint64_t ptime                 : 16; /**< [ 15:  0](R/W) Back off the TX bus for ([PTIME] * 512) bit-times.
9536                                                                  [PTIME] should be 0x0 if BGX()_GMP_GMI_TX()_CTL[TX_FC_TYPE] is clear (G.999.1). */
9537 #else /* Word 0 - Little Endian */
9538         uint64_t ptime                 : 16; /**< [ 15:  0](R/W) Back off the TX bus for ([PTIME] * 512) bit-times.
9539                                                                  [PTIME] should be 0x0 if BGX()_GMP_GMI_TX()_CTL[TX_FC_TYPE] is clear (G.999.1). */
9540         uint64_t reserved_16_63        : 48;
9541 #endif /* Word 0 - End */
9542     } s;
9543     /* struct bdk_bgxx_gmp_gmi_txx_soft_pause_s cn81xx; */
9544     struct bdk_bgxx_gmp_gmi_txx_soft_pause_cn88xx
9545     {
9546 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9547         uint64_t reserved_16_63        : 48;
9548         uint64_t ptime                 : 16; /**< [ 15:  0](R/W) Back off the TX bus for ([PTIME] * 512) bit-times. */
9549 #else /* Word 0 - Little Endian */
9550         uint64_t ptime                 : 16; /**< [ 15:  0](R/W) Back off the TX bus for ([PTIME] * 512) bit-times. */
9551         uint64_t reserved_16_63        : 48;
9552 #endif /* Word 0 - End */
9553     } cn88xx;
9554     /* struct bdk_bgxx_gmp_gmi_txx_soft_pause_s cn83xx; */
9555 };
9556 typedef union bdk_bgxx_gmp_gmi_txx_soft_pause bdk_bgxx_gmp_gmi_txx_soft_pause_t;
9557 
9558 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_SOFT_PAUSE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_SOFT_PAUSE(unsigned long a,unsigned long b)9559 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_SOFT_PAUSE(unsigned long a, unsigned long b)
9560 {
9561     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9562         return 0x87e0e0038250ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9563     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9564         return 0x87e0e0038250ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9565     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9566         return 0x87e0e0038250ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9567     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_SOFT_PAUSE", 2, a, b, 0, 0);
9568 }
9569 
9570 #define typedef_BDK_BGXX_GMP_GMI_TXX_SOFT_PAUSE(a,b) bdk_bgxx_gmp_gmi_txx_soft_pause_t
9571 #define bustype_BDK_BGXX_GMP_GMI_TXX_SOFT_PAUSE(a,b) BDK_CSR_TYPE_RSL
9572 #define basename_BDK_BGXX_GMP_GMI_TXX_SOFT_PAUSE(a,b) "BGXX_GMP_GMI_TXX_SOFT_PAUSE"
9573 #define device_bar_BDK_BGXX_GMP_GMI_TXX_SOFT_PAUSE(a,b) 0x0 /* PF_BAR0 */
9574 #define busnum_BDK_BGXX_GMP_GMI_TXX_SOFT_PAUSE(a,b) (a)
9575 #define arguments_BDK_BGXX_GMP_GMI_TXX_SOFT_PAUSE(a,b) (a),(b),-1,-1
9576 
9577 /**
9578  * Register (RSL) bgx#_gmp_gmi_tx#_thresh
9579  *
9580  * BGX GMI TX Threshold Registers
9581  */
9582 union bdk_bgxx_gmp_gmi_txx_thresh
9583 {
9584     uint64_t u;
9585     struct bdk_bgxx_gmp_gmi_txx_thresh_s
9586     {
9587 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9588         uint64_t reserved_11_63        : 53;
9589         uint64_t cnt                   : 11; /**< [ 10:  0](R/W) Number of 128-bit words to accumulate in the TX FIFO before sending on the packet
9590                                                                  interface. This field should be large enough to prevent underflow on the packet interface
9591                                                                  and must never be set to 0x0. The recommended setting for
9592 
9593                                                                  In all modes, this register cannot exceed the TX FIFO depth configured by
9594                                                                  BGX()_CMR_TX_LMACS[LMACS]. */
9595 #else /* Word 0 - Little Endian */
9596         uint64_t cnt                   : 11; /**< [ 10:  0](R/W) Number of 128-bit words to accumulate in the TX FIFO before sending on the packet
9597                                                                  interface. This field should be large enough to prevent underflow on the packet interface
9598                                                                  and must never be set to 0x0. The recommended setting for
9599 
9600                                                                  In all modes, this register cannot exceed the TX FIFO depth configured by
9601                                                                  BGX()_CMR_TX_LMACS[LMACS]. */
9602         uint64_t reserved_11_63        : 53;
9603 #endif /* Word 0 - End */
9604     } s;
9605     /* struct bdk_bgxx_gmp_gmi_txx_thresh_s cn; */
9606 };
9607 typedef union bdk_bgxx_gmp_gmi_txx_thresh bdk_bgxx_gmp_gmi_txx_thresh_t;
9608 
9609 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_THRESH(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TXX_THRESH(unsigned long a,unsigned long b)9610 static inline uint64_t BDK_BGXX_GMP_GMI_TXX_THRESH(unsigned long a, unsigned long b)
9611 {
9612     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9613         return 0x87e0e0038210ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9614     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9615         return 0x87e0e0038210ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9616     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9617         return 0x87e0e0038210ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9618     __bdk_csr_fatal("BGXX_GMP_GMI_TXX_THRESH", 2, a, b, 0, 0);
9619 }
9620 
9621 #define typedef_BDK_BGXX_GMP_GMI_TXX_THRESH(a,b) bdk_bgxx_gmp_gmi_txx_thresh_t
9622 #define bustype_BDK_BGXX_GMP_GMI_TXX_THRESH(a,b) BDK_CSR_TYPE_RSL
9623 #define basename_BDK_BGXX_GMP_GMI_TXX_THRESH(a,b) "BGXX_GMP_GMI_TXX_THRESH"
9624 #define device_bar_BDK_BGXX_GMP_GMI_TXX_THRESH(a,b) 0x0 /* PF_BAR0 */
9625 #define busnum_BDK_BGXX_GMP_GMI_TXX_THRESH(a,b) (a)
9626 #define arguments_BDK_BGXX_GMP_GMI_TXX_THRESH(a,b) (a),(b),-1,-1
9627 
9628 /**
9629  * Register (RSL) bgx#_gmp_gmi_tx_col_attempt
9630  *
9631  * BGX TX Collision Attempts Before Dropping Frame Registers
9632  */
9633 union bdk_bgxx_gmp_gmi_tx_col_attempt
9634 {
9635     uint64_t u;
9636     struct bdk_bgxx_gmp_gmi_tx_col_attempt_s
9637     {
9638 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9639         uint64_t reserved_5_63         : 59;
9640         uint64_t limit                 : 5;  /**< [  4:  0](R/W) Number of collision attempts allowed. (SGMII/1000BASE-X half-duplex only.) */
9641 #else /* Word 0 - Little Endian */
9642         uint64_t limit                 : 5;  /**< [  4:  0](R/W) Number of collision attempts allowed. (SGMII/1000BASE-X half-duplex only.) */
9643         uint64_t reserved_5_63         : 59;
9644 #endif /* Word 0 - End */
9645     } s;
9646     /* struct bdk_bgxx_gmp_gmi_tx_col_attempt_s cn; */
9647 };
9648 typedef union bdk_bgxx_gmp_gmi_tx_col_attempt bdk_bgxx_gmp_gmi_tx_col_attempt_t;
9649 
9650 static inline uint64_t BDK_BGXX_GMP_GMI_TX_COL_ATTEMPT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TX_COL_ATTEMPT(unsigned long a)9651 static inline uint64_t BDK_BGXX_GMP_GMI_TX_COL_ATTEMPT(unsigned long a)
9652 {
9653     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9654         return 0x87e0e0039010ll + 0x1000000ll * ((a) & 0x1);
9655     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
9656         return 0x87e0e0039010ll + 0x1000000ll * ((a) & 0x3);
9657     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
9658         return 0x87e0e0039010ll + 0x1000000ll * ((a) & 0x1);
9659     __bdk_csr_fatal("BGXX_GMP_GMI_TX_COL_ATTEMPT", 1, a, 0, 0, 0);
9660 }
9661 
9662 #define typedef_BDK_BGXX_GMP_GMI_TX_COL_ATTEMPT(a) bdk_bgxx_gmp_gmi_tx_col_attempt_t
9663 #define bustype_BDK_BGXX_GMP_GMI_TX_COL_ATTEMPT(a) BDK_CSR_TYPE_RSL
9664 #define basename_BDK_BGXX_GMP_GMI_TX_COL_ATTEMPT(a) "BGXX_GMP_GMI_TX_COL_ATTEMPT"
9665 #define device_bar_BDK_BGXX_GMP_GMI_TX_COL_ATTEMPT(a) 0x0 /* PF_BAR0 */
9666 #define busnum_BDK_BGXX_GMP_GMI_TX_COL_ATTEMPT(a) (a)
9667 #define arguments_BDK_BGXX_GMP_GMI_TX_COL_ATTEMPT(a) (a),-1,-1,-1
9668 
9669 /**
9670  * Register (RSL) bgx#_gmp_gmi_tx_ifg
9671  *
9672  * BGX GMI TX Interframe-Gap Cycles Registers
9673  * Consider the following when programming IFG1 and IFG2:
9674  * * For 10/100/1000 Mb/s half-duplex systems that require IEEE 802.3 compatibility, IFG1 must be
9675  * in the range of 1-8, IFG2 must be in the range of 4-12, and the IFG1 + IFG2 sum must be 12.
9676  * * For 10/100/1000 Mb/s full-duplex systems that require IEEE 802.3 compatibility, IFG1 must be
9677  * in the range of 1-11, IFG2 must be in the range of 1-11, and the IFG1 + IFG2 sum must be 12.
9678  * For all other systems, IFG1 and IFG2 can be any value in the range of 1-15, allowing for a
9679  * total possible IFG sum of 2-30.
9680  */
9681 union bdk_bgxx_gmp_gmi_tx_ifg
9682 {
9683     uint64_t u;
9684     struct bdk_bgxx_gmp_gmi_tx_ifg_s
9685     {
9686 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9687         uint64_t reserved_8_63         : 56;
9688         uint64_t ifg2                  : 4;  /**< [  7:  4](R/W) Remainder of interFrameGap timing, equal to interFrameGap - IFG1 (in IFG2 * 8 bits). If
9689                                                                  CRS is detected during IFG2, the interFrameSpacing timer is not reset and a frame is
9690                                                                  transmitted once the timer expires. */
9691         uint64_t ifg1                  : 4;  /**< [  3:  0](R/W) First portion of interFrameGap timing, in the range of 0 to 2/3 (in IFG2 * 8 bits). If CRS
9692                                                                  is detected during IFG1, the interFrameSpacing timer is reset and a frame is not
9693                                                                  transmitted. */
9694 #else /* Word 0 - Little Endian */
9695         uint64_t ifg1                  : 4;  /**< [  3:  0](R/W) First portion of interFrameGap timing, in the range of 0 to 2/3 (in IFG2 * 8 bits). If CRS
9696                                                                  is detected during IFG1, the interFrameSpacing timer is reset and a frame is not
9697                                                                  transmitted. */
9698         uint64_t ifg2                  : 4;  /**< [  7:  4](R/W) Remainder of interFrameGap timing, equal to interFrameGap - IFG1 (in IFG2 * 8 bits). If
9699                                                                  CRS is detected during IFG2, the interFrameSpacing timer is not reset and a frame is
9700                                                                  transmitted once the timer expires. */
9701         uint64_t reserved_8_63         : 56;
9702 #endif /* Word 0 - End */
9703     } s;
9704     /* struct bdk_bgxx_gmp_gmi_tx_ifg_s cn; */
9705 };
9706 typedef union bdk_bgxx_gmp_gmi_tx_ifg bdk_bgxx_gmp_gmi_tx_ifg_t;
9707 
9708 static inline uint64_t BDK_BGXX_GMP_GMI_TX_IFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TX_IFG(unsigned long a)9709 static inline uint64_t BDK_BGXX_GMP_GMI_TX_IFG(unsigned long a)
9710 {
9711     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9712         return 0x87e0e0039000ll + 0x1000000ll * ((a) & 0x1);
9713     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
9714         return 0x87e0e0039000ll + 0x1000000ll * ((a) & 0x3);
9715     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
9716         return 0x87e0e0039000ll + 0x1000000ll * ((a) & 0x1);
9717     __bdk_csr_fatal("BGXX_GMP_GMI_TX_IFG", 1, a, 0, 0, 0);
9718 }
9719 
9720 #define typedef_BDK_BGXX_GMP_GMI_TX_IFG(a) bdk_bgxx_gmp_gmi_tx_ifg_t
9721 #define bustype_BDK_BGXX_GMP_GMI_TX_IFG(a) BDK_CSR_TYPE_RSL
9722 #define basename_BDK_BGXX_GMP_GMI_TX_IFG(a) "BGXX_GMP_GMI_TX_IFG"
9723 #define device_bar_BDK_BGXX_GMP_GMI_TX_IFG(a) 0x0 /* PF_BAR0 */
9724 #define busnum_BDK_BGXX_GMP_GMI_TX_IFG(a) (a)
9725 #define arguments_BDK_BGXX_GMP_GMI_TX_IFG(a) (a),-1,-1,-1
9726 
9727 /**
9728  * Register (RSL) bgx#_gmp_gmi_tx_jam
9729  *
9730  * BGX GMI TX JAM Pattern Registers
9731  * This register provides the pattern used in JAM bytes.
9732  */
9733 union bdk_bgxx_gmp_gmi_tx_jam
9734 {
9735     uint64_t u;
9736     struct bdk_bgxx_gmp_gmi_tx_jam_s
9737     {
9738 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9739         uint64_t reserved_8_63         : 56;
9740         uint64_t jam                   : 8;  /**< [  7:  0](R/W) JAM pattern. (SGMII/1000BASE-X half-duplex only.) */
9741 #else /* Word 0 - Little Endian */
9742         uint64_t jam                   : 8;  /**< [  7:  0](R/W) JAM pattern. (SGMII/1000BASE-X half-duplex only.) */
9743         uint64_t reserved_8_63         : 56;
9744 #endif /* Word 0 - End */
9745     } s;
9746     /* struct bdk_bgxx_gmp_gmi_tx_jam_s cn; */
9747 };
9748 typedef union bdk_bgxx_gmp_gmi_tx_jam bdk_bgxx_gmp_gmi_tx_jam_t;
9749 
9750 static inline uint64_t BDK_BGXX_GMP_GMI_TX_JAM(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TX_JAM(unsigned long a)9751 static inline uint64_t BDK_BGXX_GMP_GMI_TX_JAM(unsigned long a)
9752 {
9753     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9754         return 0x87e0e0039008ll + 0x1000000ll * ((a) & 0x1);
9755     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
9756         return 0x87e0e0039008ll + 0x1000000ll * ((a) & 0x3);
9757     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
9758         return 0x87e0e0039008ll + 0x1000000ll * ((a) & 0x1);
9759     __bdk_csr_fatal("BGXX_GMP_GMI_TX_JAM", 1, a, 0, 0, 0);
9760 }
9761 
9762 #define typedef_BDK_BGXX_GMP_GMI_TX_JAM(a) bdk_bgxx_gmp_gmi_tx_jam_t
9763 #define bustype_BDK_BGXX_GMP_GMI_TX_JAM(a) BDK_CSR_TYPE_RSL
9764 #define basename_BDK_BGXX_GMP_GMI_TX_JAM(a) "BGXX_GMP_GMI_TX_JAM"
9765 #define device_bar_BDK_BGXX_GMP_GMI_TX_JAM(a) 0x0 /* PF_BAR0 */
9766 #define busnum_BDK_BGXX_GMP_GMI_TX_JAM(a) (a)
9767 #define arguments_BDK_BGXX_GMP_GMI_TX_JAM(a) (a),-1,-1,-1
9768 
9769 /**
9770  * Register (RSL) bgx#_gmp_gmi_tx_lfsr
9771  *
9772  * BGX GMI TX LFSR Registers
9773  * This register shows the contents of the linear feedback shift register (LFSR), which is used
9774  * to implement truncated binary exponential backoff.
9775  */
9776 union bdk_bgxx_gmp_gmi_tx_lfsr
9777 {
9778     uint64_t u;
9779     struct bdk_bgxx_gmp_gmi_tx_lfsr_s
9780     {
9781 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9782         uint64_t reserved_16_63        : 48;
9783         uint64_t lfsr                  : 16; /**< [ 15:  0](R/W/H) Contains the current state of the LFSR, which is used to feed random numbers to compute
9784                                                                  truncated binary exponential backoff. (SGMII/1000Base-X half-duplex only.) */
9785 #else /* Word 0 - Little Endian */
9786         uint64_t lfsr                  : 16; /**< [ 15:  0](R/W/H) Contains the current state of the LFSR, which is used to feed random numbers to compute
9787                                                                  truncated binary exponential backoff. (SGMII/1000Base-X half-duplex only.) */
9788         uint64_t reserved_16_63        : 48;
9789 #endif /* Word 0 - End */
9790     } s;
9791     /* struct bdk_bgxx_gmp_gmi_tx_lfsr_s cn; */
9792 };
9793 typedef union bdk_bgxx_gmp_gmi_tx_lfsr bdk_bgxx_gmp_gmi_tx_lfsr_t;
9794 
9795 static inline uint64_t BDK_BGXX_GMP_GMI_TX_LFSR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TX_LFSR(unsigned long a)9796 static inline uint64_t BDK_BGXX_GMP_GMI_TX_LFSR(unsigned long a)
9797 {
9798     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9799         return 0x87e0e0039028ll + 0x1000000ll * ((a) & 0x1);
9800     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
9801         return 0x87e0e0039028ll + 0x1000000ll * ((a) & 0x3);
9802     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
9803         return 0x87e0e0039028ll + 0x1000000ll * ((a) & 0x1);
9804     __bdk_csr_fatal("BGXX_GMP_GMI_TX_LFSR", 1, a, 0, 0, 0);
9805 }
9806 
9807 #define typedef_BDK_BGXX_GMP_GMI_TX_LFSR(a) bdk_bgxx_gmp_gmi_tx_lfsr_t
9808 #define bustype_BDK_BGXX_GMP_GMI_TX_LFSR(a) BDK_CSR_TYPE_RSL
9809 #define basename_BDK_BGXX_GMP_GMI_TX_LFSR(a) "BGXX_GMP_GMI_TX_LFSR"
9810 #define device_bar_BDK_BGXX_GMP_GMI_TX_LFSR(a) 0x0 /* PF_BAR0 */
9811 #define busnum_BDK_BGXX_GMP_GMI_TX_LFSR(a) (a)
9812 #define arguments_BDK_BGXX_GMP_GMI_TX_LFSR(a) (a),-1,-1,-1
9813 
9814 /**
9815  * Register (RSL) bgx#_gmp_gmi_tx_pause_pkt_dmac
9816  *
9817  * BGX TX PAUSE-Packet DMAC-Field Registers
9818  */
9819 union bdk_bgxx_gmp_gmi_tx_pause_pkt_dmac
9820 {
9821     uint64_t u;
9822     struct bdk_bgxx_gmp_gmi_tx_pause_pkt_dmac_s
9823     {
9824 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9825         uint64_t reserved_48_63        : 16;
9826         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) The DMAC field, which is placed in outbound PAUSE packets. */
9827 #else /* Word 0 - Little Endian */
9828         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) The DMAC field, which is placed in outbound PAUSE packets. */
9829         uint64_t reserved_48_63        : 16;
9830 #endif /* Word 0 - End */
9831     } s;
9832     /* struct bdk_bgxx_gmp_gmi_tx_pause_pkt_dmac_s cn; */
9833 };
9834 typedef union bdk_bgxx_gmp_gmi_tx_pause_pkt_dmac bdk_bgxx_gmp_gmi_tx_pause_pkt_dmac_t;
9835 
9836 static inline uint64_t BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(unsigned long a)9837 static inline uint64_t BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(unsigned long a)
9838 {
9839     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9840         return 0x87e0e0039018ll + 0x1000000ll * ((a) & 0x1);
9841     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
9842         return 0x87e0e0039018ll + 0x1000000ll * ((a) & 0x3);
9843     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
9844         return 0x87e0e0039018ll + 0x1000000ll * ((a) & 0x1);
9845     __bdk_csr_fatal("BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC", 1, a, 0, 0, 0);
9846 }
9847 
9848 #define typedef_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(a) bdk_bgxx_gmp_gmi_tx_pause_pkt_dmac_t
9849 #define bustype_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(a) BDK_CSR_TYPE_RSL
9850 #define basename_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(a) "BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC"
9851 #define device_bar_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(a) 0x0 /* PF_BAR0 */
9852 #define busnum_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(a) (a)
9853 #define arguments_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(a) (a),-1,-1,-1
9854 
9855 /**
9856  * Register (RSL) bgx#_gmp_gmi_tx_pause_pkt_type
9857  *
9858  * BGX GMI TX PAUSE-Packet-PTYPE Field Registers
9859  * This register provides the PTYPE field that is placed in outbound PAUSE packets.
9860  */
9861 union bdk_bgxx_gmp_gmi_tx_pause_pkt_type
9862 {
9863     uint64_t u;
9864     struct bdk_bgxx_gmp_gmi_tx_pause_pkt_type_s
9865     {
9866 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9867         uint64_t reserved_16_63        : 48;
9868         uint64_t ptype                 : 16; /**< [ 15:  0](R/W) The PTYPE field placed in outbound PAUSE packets. */
9869 #else /* Word 0 - Little Endian */
9870         uint64_t ptype                 : 16; /**< [ 15:  0](R/W) The PTYPE field placed in outbound PAUSE packets. */
9871         uint64_t reserved_16_63        : 48;
9872 #endif /* Word 0 - End */
9873     } s;
9874     /* struct bdk_bgxx_gmp_gmi_tx_pause_pkt_type_s cn; */
9875 };
9876 typedef union bdk_bgxx_gmp_gmi_tx_pause_pkt_type bdk_bgxx_gmp_gmi_tx_pause_pkt_type_t;
9877 
9878 static inline uint64_t BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(unsigned long a)9879 static inline uint64_t BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(unsigned long a)
9880 {
9881     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
9882         return 0x87e0e0039020ll + 0x1000000ll * ((a) & 0x1);
9883     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
9884         return 0x87e0e0039020ll + 0x1000000ll * ((a) & 0x3);
9885     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
9886         return 0x87e0e0039020ll + 0x1000000ll * ((a) & 0x1);
9887     __bdk_csr_fatal("BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE", 1, a, 0, 0, 0);
9888 }
9889 
9890 #define typedef_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(a) bdk_bgxx_gmp_gmi_tx_pause_pkt_type_t
9891 #define bustype_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(a) BDK_CSR_TYPE_RSL
9892 #define basename_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(a) "BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE"
9893 #define device_bar_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(a) 0x0 /* PF_BAR0 */
9894 #define busnum_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(a) (a)
9895 #define arguments_BDK_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(a) (a),-1,-1,-1
9896 
9897 /**
9898  * Register (RSL) bgx#_gmp_pcs_an#_adv
9899  *
9900  * BGX GMP PCS Autonegotiation Advertisement Registers
9901  */
9902 union bdk_bgxx_gmp_pcs_anx_adv
9903 {
9904     uint64_t u;
9905     struct bdk_bgxx_gmp_pcs_anx_adv_s
9906     {
9907 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9908         uint64_t reserved_16_63        : 48;
9909         uint64_t np                    : 1;  /**< [ 15: 15](RO/H) Next page capable. This feature is not supported; this field is always 0. */
9910         uint64_t reserved_14           : 1;
9911         uint64_t rem_flt               : 2;  /**< [ 13: 12](R/W/H) Remote fault.
9912                                                                  0x0 = Link OK, XMIT = DATA.
9913                                                                  0x1 = Link failure (loss of sync, XMIT !=DATA).
9914                                                                  0x2 = Local device offline.
9915                                                                  0x3 = Autonegotiation error; failure to complete autonegotiation. AN error is set if
9916                                                                  resolution function precludes operation with link partner. */
9917         uint64_t reserved_9_11         : 3;
9918         uint64_t pause                 : 2;  /**< [  8:  7](R/W) PAUSE frame flow capability across link, exchanged during autonegotiation as follows:
9919                                                                  0x0 = No PAUSE.
9920                                                                  0x1 = Symmetric PAUSE.
9921                                                                  0x2 = Asymmetric PAUSE.
9922                                                                  0x3 = Both symmetric and asymmetric PAUSE to local device. */
9923         uint64_t hfd                   : 1;  /**< [  6:  6](R/W) Half-duplex. When set, local device is half-duplex capable. */
9924         uint64_t fd                    : 1;  /**< [  5:  5](R/W) Full-duplex. When set, local device is full-duplex capable. */
9925         uint64_t reserved_0_4          : 5;
9926 #else /* Word 0 - Little Endian */
9927         uint64_t reserved_0_4          : 5;
9928         uint64_t fd                    : 1;  /**< [  5:  5](R/W) Full-duplex. When set, local device is full-duplex capable. */
9929         uint64_t hfd                   : 1;  /**< [  6:  6](R/W) Half-duplex. When set, local device is half-duplex capable. */
9930         uint64_t pause                 : 2;  /**< [  8:  7](R/W) PAUSE frame flow capability across link, exchanged during autonegotiation as follows:
9931                                                                  0x0 = No PAUSE.
9932                                                                  0x1 = Symmetric PAUSE.
9933                                                                  0x2 = Asymmetric PAUSE.
9934                                                                  0x3 = Both symmetric and asymmetric PAUSE to local device. */
9935         uint64_t reserved_9_11         : 3;
9936         uint64_t rem_flt               : 2;  /**< [ 13: 12](R/W/H) Remote fault.
9937                                                                  0x0 = Link OK, XMIT = DATA.
9938                                                                  0x1 = Link failure (loss of sync, XMIT !=DATA).
9939                                                                  0x2 = Local device offline.
9940                                                                  0x3 = Autonegotiation error; failure to complete autonegotiation. AN error is set if
9941                                                                  resolution function precludes operation with link partner. */
9942         uint64_t reserved_14           : 1;
9943         uint64_t np                    : 1;  /**< [ 15: 15](RO/H) Next page capable. This feature is not supported; this field is always 0. */
9944         uint64_t reserved_16_63        : 48;
9945 #endif /* Word 0 - End */
9946     } s;
9947     /* struct bdk_bgxx_gmp_pcs_anx_adv_s cn; */
9948 };
9949 typedef union bdk_bgxx_gmp_pcs_anx_adv bdk_bgxx_gmp_pcs_anx_adv_t;
9950 
9951 static inline uint64_t BDK_BGXX_GMP_PCS_ANX_ADV(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_ANX_ADV(unsigned long a,unsigned long b)9952 static inline uint64_t BDK_BGXX_GMP_PCS_ANX_ADV(unsigned long a, unsigned long b)
9953 {
9954     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
9955         return 0x87e0e0030010ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9956     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
9957         return 0x87e0e0030010ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
9958     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
9959         return 0x87e0e0030010ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
9960     __bdk_csr_fatal("BGXX_GMP_PCS_ANX_ADV", 2, a, b, 0, 0);
9961 }
9962 
9963 #define typedef_BDK_BGXX_GMP_PCS_ANX_ADV(a,b) bdk_bgxx_gmp_pcs_anx_adv_t
9964 #define bustype_BDK_BGXX_GMP_PCS_ANX_ADV(a,b) BDK_CSR_TYPE_RSL
9965 #define basename_BDK_BGXX_GMP_PCS_ANX_ADV(a,b) "BGXX_GMP_PCS_ANX_ADV"
9966 #define device_bar_BDK_BGXX_GMP_PCS_ANX_ADV(a,b) 0x0 /* PF_BAR0 */
9967 #define busnum_BDK_BGXX_GMP_PCS_ANX_ADV(a,b) (a)
9968 #define arguments_BDK_BGXX_GMP_PCS_ANX_ADV(a,b) (a),(b),-1,-1
9969 
9970 /**
9971  * Register (RSL) bgx#_gmp_pcs_an#_ext_st
9972  *
9973  * BGX GMO PCS Autonegotiation Extended Status Registers
9974  */
9975 union bdk_bgxx_gmp_pcs_anx_ext_st
9976 {
9977     uint64_t u;
9978     struct bdk_bgxx_gmp_pcs_anx_ext_st_s
9979     {
9980 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9981         uint64_t reserved_16_63        : 48;
9982         uint64_t thou_xfd              : 1;  /**< [ 15: 15](RO/H) When set, PHY is 1000 BASE-X full duplex capable. */
9983         uint64_t thou_xhd              : 1;  /**< [ 14: 14](RO/H) When set, PHY is 1000 BASE-X half duplex capable. */
9984         uint64_t thou_tfd              : 1;  /**< [ 13: 13](RO/H) When set, PHY is 1000 BASE-T full duplex capable. */
9985         uint64_t thou_thd              : 1;  /**< [ 12: 12](RO/H) When set, PHY is 1000 BASE-T half duplex capable. */
9986         uint64_t reserved_0_11         : 12;
9987 #else /* Word 0 - Little Endian */
9988         uint64_t reserved_0_11         : 12;
9989         uint64_t thou_thd              : 1;  /**< [ 12: 12](RO/H) When set, PHY is 1000 BASE-T half duplex capable. */
9990         uint64_t thou_tfd              : 1;  /**< [ 13: 13](RO/H) When set, PHY is 1000 BASE-T full duplex capable. */
9991         uint64_t thou_xhd              : 1;  /**< [ 14: 14](RO/H) When set, PHY is 1000 BASE-X half duplex capable. */
9992         uint64_t thou_xfd              : 1;  /**< [ 15: 15](RO/H) When set, PHY is 1000 BASE-X full duplex capable. */
9993         uint64_t reserved_16_63        : 48;
9994 #endif /* Word 0 - End */
9995     } s;
9996     /* struct bdk_bgxx_gmp_pcs_anx_ext_st_s cn; */
9997 };
9998 typedef union bdk_bgxx_gmp_pcs_anx_ext_st bdk_bgxx_gmp_pcs_anx_ext_st_t;
9999 
10000 static inline uint64_t BDK_BGXX_GMP_PCS_ANX_EXT_ST(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_ANX_EXT_ST(unsigned long a,unsigned long b)10001 static inline uint64_t BDK_BGXX_GMP_PCS_ANX_EXT_ST(unsigned long a, unsigned long b)
10002 {
10003     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
10004         return 0x87e0e0030028ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10005     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
10006         return 0x87e0e0030028ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
10007     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
10008         return 0x87e0e0030028ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10009     __bdk_csr_fatal("BGXX_GMP_PCS_ANX_EXT_ST", 2, a, b, 0, 0);
10010 }
10011 
10012 #define typedef_BDK_BGXX_GMP_PCS_ANX_EXT_ST(a,b) bdk_bgxx_gmp_pcs_anx_ext_st_t
10013 #define bustype_BDK_BGXX_GMP_PCS_ANX_EXT_ST(a,b) BDK_CSR_TYPE_RSL
10014 #define basename_BDK_BGXX_GMP_PCS_ANX_EXT_ST(a,b) "BGXX_GMP_PCS_ANX_EXT_ST"
10015 #define device_bar_BDK_BGXX_GMP_PCS_ANX_EXT_ST(a,b) 0x0 /* PF_BAR0 */
10016 #define busnum_BDK_BGXX_GMP_PCS_ANX_EXT_ST(a,b) (a)
10017 #define arguments_BDK_BGXX_GMP_PCS_ANX_EXT_ST(a,b) (a),(b),-1,-1
10018 
10019 /**
10020  * Register (RSL) bgx#_gmp_pcs_an#_lp_abil
10021  *
10022  * BGX GMP PCS Autonegotiation Link Partner Ability Registers
10023  * This is the autonegotiation link partner ability register 5 as per IEEE 802.3, Clause 37.
10024  */
10025 union bdk_bgxx_gmp_pcs_anx_lp_abil
10026 {
10027     uint64_t u;
10028     struct bdk_bgxx_gmp_pcs_anx_lp_abil_s
10029     {
10030 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10031         uint64_t reserved_16_63        : 48;
10032         uint64_t np                    : 1;  /**< [ 15: 15](RO/H) Next page capable:
10033                                                                  0 = Link partner not next page capable.
10034                                                                  1 = Link partner next page capable. */
10035         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) When set, indicates acknowledgement received. */
10036         uint64_t rem_flt               : 2;  /**< [ 13: 12](RO/H) Link partner's link status as follows:
10037                                                                  0x0 = Link OK.
10038                                                                  0x1 = Offline.
10039                                                                  0x2 = Link failure.
10040                                                                  0x3 = Autonegotiation error. */
10041         uint64_t reserved_9_11         : 3;
10042         uint64_t pause                 : 2;  /**< [  8:  7](RO/H) Link partner PAUSE setting as follows:
10043                                                                  0x0 = No PAUSE.
10044                                                                  0x1 = Symmetric PAUSE.
10045                                                                  0x2 = Asymmetric PAUSE.
10046                                                                  0x3 = Both symmetric and asymmetric PAUSE to local device. */
10047         uint64_t hfd                   : 1;  /**< [  6:  6](RO/H) Half-duplex. When set, link partner is half-duplex capable. */
10048         uint64_t fd                    : 1;  /**< [  5:  5](RO/H) Full-duplex. When set, link partner is full-duplex capable. */
10049         uint64_t reserved_0_4          : 5;
10050 #else /* Word 0 - Little Endian */
10051         uint64_t reserved_0_4          : 5;
10052         uint64_t fd                    : 1;  /**< [  5:  5](RO/H) Full-duplex. When set, link partner is full-duplex capable. */
10053         uint64_t hfd                   : 1;  /**< [  6:  6](RO/H) Half-duplex. When set, link partner is half-duplex capable. */
10054         uint64_t pause                 : 2;  /**< [  8:  7](RO/H) Link partner PAUSE setting as follows:
10055                                                                  0x0 = No PAUSE.
10056                                                                  0x1 = Symmetric PAUSE.
10057                                                                  0x2 = Asymmetric PAUSE.
10058                                                                  0x3 = Both symmetric and asymmetric PAUSE to local device. */
10059         uint64_t reserved_9_11         : 3;
10060         uint64_t rem_flt               : 2;  /**< [ 13: 12](RO/H) Link partner's link status as follows:
10061                                                                  0x0 = Link OK.
10062                                                                  0x1 = Offline.
10063                                                                  0x2 = Link failure.
10064                                                                  0x3 = Autonegotiation error. */
10065         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) When set, indicates acknowledgement received. */
10066         uint64_t np                    : 1;  /**< [ 15: 15](RO/H) Next page capable:
10067                                                                  0 = Link partner not next page capable.
10068                                                                  1 = Link partner next page capable. */
10069         uint64_t reserved_16_63        : 48;
10070 #endif /* Word 0 - End */
10071     } s;
10072     /* struct bdk_bgxx_gmp_pcs_anx_lp_abil_s cn; */
10073 };
10074 typedef union bdk_bgxx_gmp_pcs_anx_lp_abil bdk_bgxx_gmp_pcs_anx_lp_abil_t;
10075 
10076 static inline uint64_t BDK_BGXX_GMP_PCS_ANX_LP_ABIL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_ANX_LP_ABIL(unsigned long a,unsigned long b)10077 static inline uint64_t BDK_BGXX_GMP_PCS_ANX_LP_ABIL(unsigned long a, unsigned long b)
10078 {
10079     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
10080         return 0x87e0e0030018ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10081     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
10082         return 0x87e0e0030018ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
10083     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
10084         return 0x87e0e0030018ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10085     __bdk_csr_fatal("BGXX_GMP_PCS_ANX_LP_ABIL", 2, a, b, 0, 0);
10086 }
10087 
10088 #define typedef_BDK_BGXX_GMP_PCS_ANX_LP_ABIL(a,b) bdk_bgxx_gmp_pcs_anx_lp_abil_t
10089 #define bustype_BDK_BGXX_GMP_PCS_ANX_LP_ABIL(a,b) BDK_CSR_TYPE_RSL
10090 #define basename_BDK_BGXX_GMP_PCS_ANX_LP_ABIL(a,b) "BGXX_GMP_PCS_ANX_LP_ABIL"
10091 #define device_bar_BDK_BGXX_GMP_PCS_ANX_LP_ABIL(a,b) 0x0 /* PF_BAR0 */
10092 #define busnum_BDK_BGXX_GMP_PCS_ANX_LP_ABIL(a,b) (a)
10093 #define arguments_BDK_BGXX_GMP_PCS_ANX_LP_ABIL(a,b) (a),(b),-1,-1
10094 
10095 /**
10096  * Register (RSL) bgx#_gmp_pcs_an#_results
10097  *
10098  * BGX GMP PCS Autonegotiation Results Registers
10099  * This register is not valid when BGX()_GMP_PCS_MISC()_CTL[AN_OVRD] is set to 1. If
10100  * BGX()_GMP_PCS_MISC()_CTL[AN_OVRD] is set to 0 and
10101  * BGX()_GMP_PCS_AN()_RESULTS[AN_CPT] is set to 1, this register is valid.
10102  */
10103 union bdk_bgxx_gmp_pcs_anx_results
10104 {
10105     uint64_t u;
10106     struct bdk_bgxx_gmp_pcs_anx_results_s
10107     {
10108 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10109         uint64_t reserved_7_63         : 57;
10110         uint64_t pause                 : 2;  /**< [  6:  5](RO/H) PAUSE selection ('don't care' for SGMII/QSGMII) as follows:
10111                                                                  0x0 = Disable PAUSE, TX and RX.
10112                                                                  0x1 = Enable PAUSE frames, RX only.
10113                                                                  0x2 = Enable PAUSE frames, TX only.
10114                                                                  0x3 = Enable PAUSE frames, TX and RX. */
10115         uint64_t spd                   : 2;  /**< [  4:  3](RO/H) Link speed selection as follows:
10116                                                                  0x0 = 10 Mb/s.
10117                                                                  0x1 = 100 Mb/s.
10118                                                                  0x2 = 1000 Mb/s.
10119                                                                  0x3 = Reserved. */
10120         uint64_t an_cpt                : 1;  /**< [  2:  2](RO/H) Autonegotiation completed.
10121                                                                  1 = Autonegotiation completed.
10122                                                                  0 = Autonegotiation not completed or failed. */
10123         uint64_t dup                   : 1;  /**< [  1:  1](RO/H) Duplex mode. 1 = full duplex, 0 = half duplex. */
10124         uint64_t link_ok               : 1;  /**< [  0:  0](RO/H) Link status: 1 = link up (OK), 1 = link down. */
10125 #else /* Word 0 - Little Endian */
10126         uint64_t link_ok               : 1;  /**< [  0:  0](RO/H) Link status: 1 = link up (OK), 1 = link down. */
10127         uint64_t dup                   : 1;  /**< [  1:  1](RO/H) Duplex mode. 1 = full duplex, 0 = half duplex. */
10128         uint64_t an_cpt                : 1;  /**< [  2:  2](RO/H) Autonegotiation completed.
10129                                                                  1 = Autonegotiation completed.
10130                                                                  0 = Autonegotiation not completed or failed. */
10131         uint64_t spd                   : 2;  /**< [  4:  3](RO/H) Link speed selection as follows:
10132                                                                  0x0 = 10 Mb/s.
10133                                                                  0x1 = 100 Mb/s.
10134                                                                  0x2 = 1000 Mb/s.
10135                                                                  0x3 = Reserved. */
10136         uint64_t pause                 : 2;  /**< [  6:  5](RO/H) PAUSE selection ('don't care' for SGMII/QSGMII) as follows:
10137                                                                  0x0 = Disable PAUSE, TX and RX.
10138                                                                  0x1 = Enable PAUSE frames, RX only.
10139                                                                  0x2 = Enable PAUSE frames, TX only.
10140                                                                  0x3 = Enable PAUSE frames, TX and RX. */
10141         uint64_t reserved_7_63         : 57;
10142 #endif /* Word 0 - End */
10143     } s;
10144     /* struct bdk_bgxx_gmp_pcs_anx_results_s cn81xx; */
10145     struct bdk_bgxx_gmp_pcs_anx_results_cn88xx
10146     {
10147 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10148         uint64_t reserved_7_63         : 57;
10149         uint64_t pause                 : 2;  /**< [  6:  5](RO/H) PAUSE selection ('don't care' for SGMII) as follows:
10150                                                                  0x0 = Disable PAUSE, TX and RX.
10151                                                                  0x1 = Enable PAUSE frames, RX only.
10152                                                                  0x2 = Enable PAUSE frames, TX only.
10153                                                                  0x3 = Enable PAUSE frames, TX and RX. */
10154         uint64_t spd                   : 2;  /**< [  4:  3](RO/H) Link speed selection as follows:
10155                                                                  0x0 = 10 Mb/s.
10156                                                                  0x1 = 100 Mb/s.
10157                                                                  0x2 = 1000 Mb/s.
10158                                                                  0x3 = Reserved. */
10159         uint64_t an_cpt                : 1;  /**< [  2:  2](RO/H) Autonegotiation completed.
10160                                                                  1 = Autonegotiation completed.
10161                                                                  0 = Autonegotiation not completed or failed. */
10162         uint64_t dup                   : 1;  /**< [  1:  1](RO/H) Duplex mode. 1 = full duplex, 0 = half duplex. */
10163         uint64_t link_ok               : 1;  /**< [  0:  0](RO/H) Link status: 1 = link up (OK), 1 = link down. */
10164 #else /* Word 0 - Little Endian */
10165         uint64_t link_ok               : 1;  /**< [  0:  0](RO/H) Link status: 1 = link up (OK), 1 = link down. */
10166         uint64_t dup                   : 1;  /**< [  1:  1](RO/H) Duplex mode. 1 = full duplex, 0 = half duplex. */
10167         uint64_t an_cpt                : 1;  /**< [  2:  2](RO/H) Autonegotiation completed.
10168                                                                  1 = Autonegotiation completed.
10169                                                                  0 = Autonegotiation not completed or failed. */
10170         uint64_t spd                   : 2;  /**< [  4:  3](RO/H) Link speed selection as follows:
10171                                                                  0x0 = 10 Mb/s.
10172                                                                  0x1 = 100 Mb/s.
10173                                                                  0x2 = 1000 Mb/s.
10174                                                                  0x3 = Reserved. */
10175         uint64_t pause                 : 2;  /**< [  6:  5](RO/H) PAUSE selection ('don't care' for SGMII) as follows:
10176                                                                  0x0 = Disable PAUSE, TX and RX.
10177                                                                  0x1 = Enable PAUSE frames, RX only.
10178                                                                  0x2 = Enable PAUSE frames, TX only.
10179                                                                  0x3 = Enable PAUSE frames, TX and RX. */
10180         uint64_t reserved_7_63         : 57;
10181 #endif /* Word 0 - End */
10182     } cn88xx;
10183     /* struct bdk_bgxx_gmp_pcs_anx_results_s cn83xx; */
10184 };
10185 typedef union bdk_bgxx_gmp_pcs_anx_results bdk_bgxx_gmp_pcs_anx_results_t;
10186 
10187 static inline uint64_t BDK_BGXX_GMP_PCS_ANX_RESULTS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_ANX_RESULTS(unsigned long a,unsigned long b)10188 static inline uint64_t BDK_BGXX_GMP_PCS_ANX_RESULTS(unsigned long a, unsigned long b)
10189 {
10190     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
10191         return 0x87e0e0030020ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10192     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
10193         return 0x87e0e0030020ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
10194     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
10195         return 0x87e0e0030020ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10196     __bdk_csr_fatal("BGXX_GMP_PCS_ANX_RESULTS", 2, a, b, 0, 0);
10197 }
10198 
10199 #define typedef_BDK_BGXX_GMP_PCS_ANX_RESULTS(a,b) bdk_bgxx_gmp_pcs_anx_results_t
10200 #define bustype_BDK_BGXX_GMP_PCS_ANX_RESULTS(a,b) BDK_CSR_TYPE_RSL
10201 #define basename_BDK_BGXX_GMP_PCS_ANX_RESULTS(a,b) "BGXX_GMP_PCS_ANX_RESULTS"
10202 #define device_bar_BDK_BGXX_GMP_PCS_ANX_RESULTS(a,b) 0x0 /* PF_BAR0 */
10203 #define busnum_BDK_BGXX_GMP_PCS_ANX_RESULTS(a,b) (a)
10204 #define arguments_BDK_BGXX_GMP_PCS_ANX_RESULTS(a,b) (a),(b),-1,-1
10205 
10206 /**
10207  * Register (RSL) bgx#_gmp_pcs_int#
10208  *
10209  * BGX GMP PCS Interrupt Registers
10210  */
10211 union bdk_bgxx_gmp_pcs_intx
10212 {
10213     uint64_t u;
10214     struct bdk_bgxx_gmp_pcs_intx_s
10215     {
10216 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10217         uint64_t reserved_13_63        : 51;
10218         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1C/H) Code group sync failure debug help. BGX()_GMP_PCS_INT()[DBG_SYNC] interrupt fires when
10219                                                                  code group
10220                                                                  synchronization state machine makes a transition from SYNC_ACQUIRED_1 state to
10221                                                                  SYNC_ACQUIRED_2 state. (See IEEE 802.3-2005, figure 37-9). It indicates that a bad code
10222                                                                  group was received after code group synchronization was achieved. This interrupt should be
10223                                                                  disabled during normal link operation. Use it as a debug help feature only. */
10224         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1C/H) Set whenever duplex mode changes on the link. */
10225         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1C/H) Set by hardware whenever RX sync state machine reaches a bad state. Should never be set
10226                                                                  during normal operation. */
10227         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1C/H) Set by hardware whenever autonegotiation state machine reaches a bad state. Should never
10228                                                                  be set during normal operation. */
10229         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1C/H) Set by hardware whenever code group sync or bit lock failure occurs. Cannot fire in loopback1 mode. */
10230         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1C/H) Set by hardware whenever RX state machine reaches a bad state. Should never be set during
10231                                                                  normal operation. */
10232         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1C/H) Set whenever RX receives a code group error in 10-bit to 8-bit decode logic. Cannot fire
10233                                                                  in loopback1 mode. */
10234         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1C/H) Set by hardware whenever TX state machine reaches a bad state. Should never be set during
10235                                                                  normal operation. */
10236         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1C/H) Set whenever hardware detects a TX FIFO overflow condition. */
10237         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1C/H) Set whenever hardware detects a TX FIFO underflow condition. */
10238         uint64_t an_err                : 1;  /**< [  2:  2](R/W1C/H) Autonegotiation error; AN resolution function failed. */
10239         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1C/H) Set whenever hardware detects a change in the XMIT variable. XMIT variable states are
10240                                                                  IDLE, CONFIG and DATA. */
10241         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1C/H) Set by hardware whenever link speed has changed. */
10242 #else /* Word 0 - Little Endian */
10243         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1C/H) Set by hardware whenever link speed has changed. */
10244         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1C/H) Set whenever hardware detects a change in the XMIT variable. XMIT variable states are
10245                                                                  IDLE, CONFIG and DATA. */
10246         uint64_t an_err                : 1;  /**< [  2:  2](R/W1C/H) Autonegotiation error; AN resolution function failed. */
10247         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1C/H) Set whenever hardware detects a TX FIFO underflow condition. */
10248         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1C/H) Set whenever hardware detects a TX FIFO overflow condition. */
10249         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1C/H) Set by hardware whenever TX state machine reaches a bad state. Should never be set during
10250                                                                  normal operation. */
10251         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1C/H) Set whenever RX receives a code group error in 10-bit to 8-bit decode logic. Cannot fire
10252                                                                  in loopback1 mode. */
10253         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1C/H) Set by hardware whenever RX state machine reaches a bad state. Should never be set during
10254                                                                  normal operation. */
10255         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1C/H) Set by hardware whenever code group sync or bit lock failure occurs. Cannot fire in loopback1 mode. */
10256         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1C/H) Set by hardware whenever autonegotiation state machine reaches a bad state. Should never
10257                                                                  be set during normal operation. */
10258         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1C/H) Set by hardware whenever RX sync state machine reaches a bad state. Should never be set
10259                                                                  during normal operation. */
10260         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1C/H) Set whenever duplex mode changes on the link. */
10261         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1C/H) Code group sync failure debug help. BGX()_GMP_PCS_INT()[DBG_SYNC] interrupt fires when
10262                                                                  code group
10263                                                                  synchronization state machine makes a transition from SYNC_ACQUIRED_1 state to
10264                                                                  SYNC_ACQUIRED_2 state. (See IEEE 802.3-2005, figure 37-9). It indicates that a bad code
10265                                                                  group was received after code group synchronization was achieved. This interrupt should be
10266                                                                  disabled during normal link operation. Use it as a debug help feature only. */
10267         uint64_t reserved_13_63        : 51;
10268 #endif /* Word 0 - End */
10269     } s;
10270     /* struct bdk_bgxx_gmp_pcs_intx_s cn; */
10271 };
10272 typedef union bdk_bgxx_gmp_pcs_intx bdk_bgxx_gmp_pcs_intx_t;
10273 
10274 static inline uint64_t BDK_BGXX_GMP_PCS_INTX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_INTX(unsigned long a,unsigned long b)10275 static inline uint64_t BDK_BGXX_GMP_PCS_INTX(unsigned long a, unsigned long b)
10276 {
10277     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
10278         return 0x87e0e0030080ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10279     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
10280         return 0x87e0e0030080ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
10281     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
10282         return 0x87e0e0030080ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10283     __bdk_csr_fatal("BGXX_GMP_PCS_INTX", 2, a, b, 0, 0);
10284 }
10285 
10286 #define typedef_BDK_BGXX_GMP_PCS_INTX(a,b) bdk_bgxx_gmp_pcs_intx_t
10287 #define bustype_BDK_BGXX_GMP_PCS_INTX(a,b) BDK_CSR_TYPE_RSL
10288 #define basename_BDK_BGXX_GMP_PCS_INTX(a,b) "BGXX_GMP_PCS_INTX"
10289 #define device_bar_BDK_BGXX_GMP_PCS_INTX(a,b) 0x0 /* PF_BAR0 */
10290 #define busnum_BDK_BGXX_GMP_PCS_INTX(a,b) (a)
10291 #define arguments_BDK_BGXX_GMP_PCS_INTX(a,b) (a),(b),-1,-1
10292 
10293 /**
10294  * Register (RSL) bgx#_gmp_pcs_int#_ena_w1c
10295  *
10296  * BGX GMP PCS Interrupt Enable Clear Registers
10297  * This register clears interrupt enable bits.
10298  */
10299 union bdk_bgxx_gmp_pcs_intx_ena_w1c
10300 {
10301     uint64_t u;
10302     struct bdk_bgxx_gmp_pcs_intx_ena_w1c_s
10303     {
10304 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10305         uint64_t reserved_13_63        : 51;
10306         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10307         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[DUP]. */
10308         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10309         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[AN_BAD]. */
10310         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXLOCK]. */
10311         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXBAD]. */
10312         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXERR]. */
10313         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXBAD]. */
10314         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFO]. */
10315         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFU]. */
10316         uint64_t an_err                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[AN_ERR]. */
10317         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[XMIT]. */
10318         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[LNKSPD]. */
10319 #else /* Word 0 - Little Endian */
10320         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[LNKSPD]. */
10321         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[XMIT]. */
10322         uint64_t an_err                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[AN_ERR]. */
10323         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFU]. */
10324         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFO]. */
10325         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXBAD]. */
10326         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXERR]. */
10327         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXBAD]. */
10328         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXLOCK]. */
10329         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[AN_BAD]. */
10330         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10331         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[DUP]. */
10332         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..1)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10333         uint64_t reserved_13_63        : 51;
10334 #endif /* Word 0 - End */
10335     } s;
10336     /* struct bdk_bgxx_gmp_pcs_intx_ena_w1c_s cn81xx; */
10337     /* struct bdk_bgxx_gmp_pcs_intx_ena_w1c_s cn88xx; */
10338     struct bdk_bgxx_gmp_pcs_intx_ena_w1c_cn83xx
10339     {
10340 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10341         uint64_t reserved_13_63        : 51;
10342         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10343         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[DUP]. */
10344         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10345         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[AN_BAD]. */
10346         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXLOCK]. */
10347         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXBAD]. */
10348         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXERR]. */
10349         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXBAD]. */
10350         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFO]. */
10351         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFU]. */
10352         uint64_t an_err                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[AN_ERR]. */
10353         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[XMIT]. */
10354         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[LNKSPD]. */
10355 #else /* Word 0 - Little Endian */
10356         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[LNKSPD]. */
10357         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[XMIT]. */
10358         uint64_t an_err                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[AN_ERR]. */
10359         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFU]. */
10360         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFO]. */
10361         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXBAD]. */
10362         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXERR]. */
10363         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXBAD]. */
10364         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXLOCK]. */
10365         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[AN_BAD]. */
10366         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10367         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[DUP]. */
10368         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..3)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10369         uint64_t reserved_13_63        : 51;
10370 #endif /* Word 0 - End */
10371     } cn83xx;
10372 };
10373 typedef union bdk_bgxx_gmp_pcs_intx_ena_w1c bdk_bgxx_gmp_pcs_intx_ena_w1c_t;
10374 
10375 static inline uint64_t BDK_BGXX_GMP_PCS_INTX_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_INTX_ENA_W1C(unsigned long a,unsigned long b)10376 static inline uint64_t BDK_BGXX_GMP_PCS_INTX_ENA_W1C(unsigned long a, unsigned long b)
10377 {
10378     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
10379         return 0x87e0e0030090ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10380     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
10381         return 0x87e0e0030090ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
10382     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
10383         return 0x87e0e0030090ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10384     __bdk_csr_fatal("BGXX_GMP_PCS_INTX_ENA_W1C", 2, a, b, 0, 0);
10385 }
10386 
10387 #define typedef_BDK_BGXX_GMP_PCS_INTX_ENA_W1C(a,b) bdk_bgxx_gmp_pcs_intx_ena_w1c_t
10388 #define bustype_BDK_BGXX_GMP_PCS_INTX_ENA_W1C(a,b) BDK_CSR_TYPE_RSL
10389 #define basename_BDK_BGXX_GMP_PCS_INTX_ENA_W1C(a,b) "BGXX_GMP_PCS_INTX_ENA_W1C"
10390 #define device_bar_BDK_BGXX_GMP_PCS_INTX_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
10391 #define busnum_BDK_BGXX_GMP_PCS_INTX_ENA_W1C(a,b) (a)
10392 #define arguments_BDK_BGXX_GMP_PCS_INTX_ENA_W1C(a,b) (a),(b),-1,-1
10393 
10394 /**
10395  * Register (RSL) bgx#_gmp_pcs_int#_ena_w1s
10396  *
10397  * BGX GMP PCS Interrupt Enable Set Registers
10398  * This register sets interrupt enable bits.
10399  */
10400 union bdk_bgxx_gmp_pcs_intx_ena_w1s
10401 {
10402     uint64_t u;
10403     struct bdk_bgxx_gmp_pcs_intx_ena_w1s_s
10404     {
10405 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10406         uint64_t reserved_13_63        : 51;
10407         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10408         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[DUP]. */
10409         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10410         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[AN_BAD]. */
10411         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXLOCK]. */
10412         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXBAD]. */
10413         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXERR]. */
10414         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXBAD]. */
10415         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFO]. */
10416         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFU]. */
10417         uint64_t an_err                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[AN_ERR]. */
10418         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[XMIT]. */
10419         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[LNKSPD]. */
10420 #else /* Word 0 - Little Endian */
10421         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[LNKSPD]. */
10422         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[XMIT]. */
10423         uint64_t an_err                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[AN_ERR]. */
10424         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFU]. */
10425         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFO]. */
10426         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[TXBAD]. */
10427         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXERR]. */
10428         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXBAD]. */
10429         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[RXLOCK]. */
10430         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[AN_BAD]. */
10431         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10432         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[DUP]. */
10433         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..1)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10434         uint64_t reserved_13_63        : 51;
10435 #endif /* Word 0 - End */
10436     } s;
10437     /* struct bdk_bgxx_gmp_pcs_intx_ena_w1s_s cn81xx; */
10438     /* struct bdk_bgxx_gmp_pcs_intx_ena_w1s_s cn88xx; */
10439     struct bdk_bgxx_gmp_pcs_intx_ena_w1s_cn83xx
10440     {
10441 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10442         uint64_t reserved_13_63        : 51;
10443         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10444         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[DUP]. */
10445         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10446         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[AN_BAD]. */
10447         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXLOCK]. */
10448         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXBAD]. */
10449         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXERR]. */
10450         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXBAD]. */
10451         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFO]. */
10452         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFU]. */
10453         uint64_t an_err                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[AN_ERR]. */
10454         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[XMIT]. */
10455         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[LNKSPD]. */
10456 #else /* Word 0 - Little Endian */
10457         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[LNKSPD]. */
10458         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[XMIT]. */
10459         uint64_t an_err                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[AN_ERR]. */
10460         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFU]. */
10461         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFO]. */
10462         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[TXBAD]. */
10463         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXERR]. */
10464         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXBAD]. */
10465         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[RXLOCK]. */
10466         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[AN_BAD]. */
10467         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10468         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[DUP]. */
10469         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..3)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10470         uint64_t reserved_13_63        : 51;
10471 #endif /* Word 0 - End */
10472     } cn83xx;
10473 };
10474 typedef union bdk_bgxx_gmp_pcs_intx_ena_w1s bdk_bgxx_gmp_pcs_intx_ena_w1s_t;
10475 
10476 static inline uint64_t BDK_BGXX_GMP_PCS_INTX_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_INTX_ENA_W1S(unsigned long a,unsigned long b)10477 static inline uint64_t BDK_BGXX_GMP_PCS_INTX_ENA_W1S(unsigned long a, unsigned long b)
10478 {
10479     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
10480         return 0x87e0e0030098ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10481     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
10482         return 0x87e0e0030098ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
10483     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
10484         return 0x87e0e0030098ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10485     __bdk_csr_fatal("BGXX_GMP_PCS_INTX_ENA_W1S", 2, a, b, 0, 0);
10486 }
10487 
10488 #define typedef_BDK_BGXX_GMP_PCS_INTX_ENA_W1S(a,b) bdk_bgxx_gmp_pcs_intx_ena_w1s_t
10489 #define bustype_BDK_BGXX_GMP_PCS_INTX_ENA_W1S(a,b) BDK_CSR_TYPE_RSL
10490 #define basename_BDK_BGXX_GMP_PCS_INTX_ENA_W1S(a,b) "BGXX_GMP_PCS_INTX_ENA_W1S"
10491 #define device_bar_BDK_BGXX_GMP_PCS_INTX_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
10492 #define busnum_BDK_BGXX_GMP_PCS_INTX_ENA_W1S(a,b) (a)
10493 #define arguments_BDK_BGXX_GMP_PCS_INTX_ENA_W1S(a,b) (a),(b),-1,-1
10494 
10495 /**
10496  * Register (RSL) bgx#_gmp_pcs_int#_w1s
10497  *
10498  * BGX GMP PCS Interrupt Set Registers
10499  * This register sets interrupt bits.
10500  */
10501 union bdk_bgxx_gmp_pcs_intx_w1s
10502 {
10503     uint64_t u;
10504     struct bdk_bgxx_gmp_pcs_intx_w1s_s
10505     {
10506 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10507         uint64_t reserved_13_63        : 51;
10508         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10509         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[DUP]. */
10510         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10511         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[AN_BAD]. */
10512         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[RXLOCK]. */
10513         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[RXBAD]. */
10514         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[RXERR]. */
10515         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[TXBAD]. */
10516         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFO]. */
10517         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFU]. */
10518         uint64_t an_err                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[AN_ERR]. */
10519         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[XMIT]. */
10520         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[LNKSPD]. */
10521 #else /* Word 0 - Little Endian */
10522         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[LNKSPD]. */
10523         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[XMIT]. */
10524         uint64_t an_err                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[AN_ERR]. */
10525         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFU]. */
10526         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[TXFIFO]. */
10527         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[TXBAD]. */
10528         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[RXERR]. */
10529         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[RXBAD]. */
10530         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[RXLOCK]. */
10531         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[AN_BAD]. */
10532         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10533         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[DUP]. */
10534         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..1)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10535         uint64_t reserved_13_63        : 51;
10536 #endif /* Word 0 - End */
10537     } s;
10538     /* struct bdk_bgxx_gmp_pcs_intx_w1s_s cn81xx; */
10539     /* struct bdk_bgxx_gmp_pcs_intx_w1s_s cn88xx; */
10540     struct bdk_bgxx_gmp_pcs_intx_w1s_cn83xx
10541     {
10542 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10543         uint64_t reserved_13_63        : 51;
10544         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10545         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[DUP]. */
10546         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10547         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[AN_BAD]. */
10548         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[RXLOCK]. */
10549         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[RXBAD]. */
10550         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[RXERR]. */
10551         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[TXBAD]. */
10552         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFO]. */
10553         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFU]. */
10554         uint64_t an_err                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[AN_ERR]. */
10555         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[XMIT]. */
10556         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[LNKSPD]. */
10557 #else /* Word 0 - Little Endian */
10558         uint64_t lnkspd                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[LNKSPD]. */
10559         uint64_t xmit                  : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[XMIT]. */
10560         uint64_t an_err                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[AN_ERR]. */
10561         uint64_t txfifu                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFU]. */
10562         uint64_t txfifo                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[TXFIFO]. */
10563         uint64_t txbad                 : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[TXBAD]. */
10564         uint64_t rxerr                 : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[RXERR]. */
10565         uint64_t rxbad                 : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[RXBAD]. */
10566         uint64_t rxlock                : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[RXLOCK]. */
10567         uint64_t an_bad                : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[AN_BAD]. */
10568         uint64_t sync_bad              : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[SYNC_BAD]. */
10569         uint64_t dup                   : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[DUP]. */
10570         uint64_t dbg_sync              : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..3)_GMP_PCS_INT(0..3)[DBG_SYNC]. */
10571         uint64_t reserved_13_63        : 51;
10572 #endif /* Word 0 - End */
10573     } cn83xx;
10574 };
10575 typedef union bdk_bgxx_gmp_pcs_intx_w1s bdk_bgxx_gmp_pcs_intx_w1s_t;
10576 
10577 static inline uint64_t BDK_BGXX_GMP_PCS_INTX_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_INTX_W1S(unsigned long a,unsigned long b)10578 static inline uint64_t BDK_BGXX_GMP_PCS_INTX_W1S(unsigned long a, unsigned long b)
10579 {
10580     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
10581         return 0x87e0e0030088ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10582     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
10583         return 0x87e0e0030088ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
10584     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
10585         return 0x87e0e0030088ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10586     __bdk_csr_fatal("BGXX_GMP_PCS_INTX_W1S", 2, a, b, 0, 0);
10587 }
10588 
10589 #define typedef_BDK_BGXX_GMP_PCS_INTX_W1S(a,b) bdk_bgxx_gmp_pcs_intx_w1s_t
10590 #define bustype_BDK_BGXX_GMP_PCS_INTX_W1S(a,b) BDK_CSR_TYPE_RSL
10591 #define basename_BDK_BGXX_GMP_PCS_INTX_W1S(a,b) "BGXX_GMP_PCS_INTX_W1S"
10592 #define device_bar_BDK_BGXX_GMP_PCS_INTX_W1S(a,b) 0x0 /* PF_BAR0 */
10593 #define busnum_BDK_BGXX_GMP_PCS_INTX_W1S(a,b) (a)
10594 #define arguments_BDK_BGXX_GMP_PCS_INTX_W1S(a,b) (a),(b),-1,-1
10595 
10596 /**
10597  * Register (RSL) bgx#_gmp_pcs_link#_timer
10598  *
10599  * BGX GMP PCS Link Timer Registers
10600  * This is the 1.6 ms nominal link timer register.
10601  */
10602 union bdk_bgxx_gmp_pcs_linkx_timer
10603 {
10604     uint64_t u;
10605     struct bdk_bgxx_gmp_pcs_linkx_timer_s
10606     {
10607 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10608         uint64_t reserved_16_63        : 48;
10609         uint64_t count                 : 16; /**< [ 15:  0](R/W) (Coprocessor clock period * 1024) * [COUNT] should be 1.6 ms for SGMII/QSGMII and 10 ms
10610                                                                  otherwise,
10611                                                                  which is the link timer used in autonegotiation. Reset assumes a 700 MHz coprocessor
10612                                                                  clock for 1.6 ms link timer. */
10613 #else /* Word 0 - Little Endian */
10614         uint64_t count                 : 16; /**< [ 15:  0](R/W) (Coprocessor clock period * 1024) * [COUNT] should be 1.6 ms for SGMII/QSGMII and 10 ms
10615                                                                  otherwise,
10616                                                                  which is the link timer used in autonegotiation. Reset assumes a 700 MHz coprocessor
10617                                                                  clock for 1.6 ms link timer. */
10618         uint64_t reserved_16_63        : 48;
10619 #endif /* Word 0 - End */
10620     } s;
10621     /* struct bdk_bgxx_gmp_pcs_linkx_timer_s cn81xx; */
10622     struct bdk_bgxx_gmp_pcs_linkx_timer_cn88xx
10623     {
10624 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10625         uint64_t reserved_16_63        : 48;
10626         uint64_t count                 : 16; /**< [ 15:  0](R/W) (Coprocessor clock period * 1024) * COUNT should be 1.6 ms for SGMII and 10 ms otherwise,
10627                                                                  which is the link timer used in autonegotiation. Reset assumes a 700 MHz coprocessor
10628                                                                  clock for 1.6 ms link timer. */
10629 #else /* Word 0 - Little Endian */
10630         uint64_t count                 : 16; /**< [ 15:  0](R/W) (Coprocessor clock period * 1024) * COUNT should be 1.6 ms for SGMII and 10 ms otherwise,
10631                                                                  which is the link timer used in autonegotiation. Reset assumes a 700 MHz coprocessor
10632                                                                  clock for 1.6 ms link timer. */
10633         uint64_t reserved_16_63        : 48;
10634 #endif /* Word 0 - End */
10635     } cn88xx;
10636     /* struct bdk_bgxx_gmp_pcs_linkx_timer_s cn83xx; */
10637 };
10638 typedef union bdk_bgxx_gmp_pcs_linkx_timer bdk_bgxx_gmp_pcs_linkx_timer_t;
10639 
10640 static inline uint64_t BDK_BGXX_GMP_PCS_LINKX_TIMER(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_LINKX_TIMER(unsigned long a,unsigned long b)10641 static inline uint64_t BDK_BGXX_GMP_PCS_LINKX_TIMER(unsigned long a, unsigned long b)
10642 {
10643     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
10644         return 0x87e0e0030040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10645     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
10646         return 0x87e0e0030040ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
10647     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
10648         return 0x87e0e0030040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10649     __bdk_csr_fatal("BGXX_GMP_PCS_LINKX_TIMER", 2, a, b, 0, 0);
10650 }
10651 
10652 #define typedef_BDK_BGXX_GMP_PCS_LINKX_TIMER(a,b) bdk_bgxx_gmp_pcs_linkx_timer_t
10653 #define bustype_BDK_BGXX_GMP_PCS_LINKX_TIMER(a,b) BDK_CSR_TYPE_RSL
10654 #define basename_BDK_BGXX_GMP_PCS_LINKX_TIMER(a,b) "BGXX_GMP_PCS_LINKX_TIMER"
10655 #define device_bar_BDK_BGXX_GMP_PCS_LINKX_TIMER(a,b) 0x0 /* PF_BAR0 */
10656 #define busnum_BDK_BGXX_GMP_PCS_LINKX_TIMER(a,b) (a)
10657 #define arguments_BDK_BGXX_GMP_PCS_LINKX_TIMER(a,b) (a),(b),-1,-1
10658 
10659 /**
10660  * Register (RSL) bgx#_gmp_pcs_misc#_ctl
10661  *
10662  * BGX GMP SGMII Miscellaneous Control Registers
10663  * Internal:
10664  * SGMII bit [12] is really a misnomer, it is a decode  of pi_qlm_cfg pins to indicate SGMII or
10665  * 1000Base-X modes.
10666  *
10667  * Note: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if
10668  * [MAC_PHY] is set (1=PHY mode). If the bit is not set (0=MAC mode), the
10669  * tx_Config_Reg\<14\> becomes ACK bit and tx_Config_Reg\<0\> is always 1.
10670  * All other bits in tx_Config_Reg sent will be 0. The PHY dictates the Auto Negotiation results.
10671  */
10672 union bdk_bgxx_gmp_pcs_miscx_ctl
10673 {
10674     uint64_t u;
10675     struct bdk_bgxx_gmp_pcs_miscx_ctl_s
10676     {
10677 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10678         uint64_t reserved_33_63        : 31;
10679         uint64_t qsgmii_comma_wd_en    : 1;  /**< [ 32: 32](R/W) QSGMII comma watchdog byte counter enable. */
10680         uint64_t qsgmii_comma_wd       : 16; /**< [ 31: 16](R/W) QSGMII comma watchdog byte counter. This counter is used in QSGMII mode and
10681                                                                  counts incoming bytes to ensure state transitions in the PCS receive side state
10682                                                                  machine when disparity enable is turned off and bad code groups and commas are
10683                                                                  not communicated from the code group processor after code group lock. */
10684         uint64_t reserved_14_15        : 2;
10685         uint64_t disp_en               : 1;  /**< [ 13: 13](R/W) Disparity check enable.  When LMAC_TYPE=QSGMII the running disparity check should be
10686                                                                  disabled
10687                                                                  to
10688                                                                  prevent propogation across ports.
10689                                                                  0 = disable disparity check
10690                                                                  1 = enable disparity checking
10691 
10692                                                                  See GSER()_LANE_MODE[LMODE]. */
10693         uint64_t sgmii                 : 1;  /**< [ 12: 12](RO/H) Reserved. Always 1. */
10694         uint64_t gmxeno                : 1;  /**< [ 11: 11](R/W) GMI enable override. When set, forces GMI to appear disabled. The enable/disable status of
10695                                                                  GMI is checked only at SOP of every packet. */
10696         uint64_t loopbck2              : 1;  /**< [ 10: 10](R/W) Sets external loopback mode to return RX data back out via the TX data path. 0 = No
10697                                                                  loopback. 1 = Loopback.
10698                                                                  LOOPBCK1 and LOOPBCK2 modes may not be supported simultaneously. */
10699         uint64_t mac_phy               : 1;  /**< [  9:  9](R/W) MAC/PHY.
10700                                                                  0 = MAC.
10701                                                                  1 = PHY decides the tx_Config_Reg value to be sent during autonegotiation. */
10702         uint64_t mode                  : 1;  /**< [  8:  8](R/W) Mode bit.
10703 
10704                                                                  _ 0 = SGMII mode is selected and the following note applies.
10705                                                                  The SGMII AN advertisement register (BGX()_GMP_PCS_SGM()_AN_ADV) is sent during
10706                                                                  autonegotiation if BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] = 1 (PHY mode). If [MAC_PHY]
10707                                                                  = 0 (MAC mode), the tx_Config_Reg\<14\> becomes ACK bit and \<0\> is always 1. All other bits
10708                                                                  in tx_Config_Reg sent are 0. The PHY dictates the autonegotiation results.
10709 
10710                                                                  _ 1 = 1000Base-X mode is selected. Autonegotiation follows IEEE 802.3 clause 37. */
10711         uint64_t an_ovrd               : 1;  /**< [  7:  7](R/W) Autonegotiation results override:
10712                                                                  0 = Disable.
10713                                                                  1 = Enable override. Autonegotiation is allowed to happen but the results are ignored
10714                                                                  when this bit is set.  Duplex and Link speed values are set from BGX()_GMP_PCS_MISC()_CTL. */
10715         uint64_t samp_pt               : 7;  /**< [  6:  0](R/W) Byte number in elongated frames for 10/100 Mb/s operation for data sampling on RX side in
10716                                                                  PCS. Recommended values are 0x5 for 100 Mb/s operation and 0x32 for 10 Mb/s operation.
10717 
10718                                                                  For 10 Mb/s operation, this field should be set to a value less than 99 and greater than
10719                                                                  0.
10720                                                                  If set out of this range, a value of 50 is used for actual sampling internally without
10721                                                                  affecting the CSR field.
10722 
10723                                                                  For 100 Mb/s operation this field should be set to a value less than 9 and greater than 0.
10724                                                                  If set out of this range, a value of 5 is used for actual sampling internally without
10725                                                                  affecting the CSR field. */
10726 #else /* Word 0 - Little Endian */
10727         uint64_t samp_pt               : 7;  /**< [  6:  0](R/W) Byte number in elongated frames for 10/100 Mb/s operation for data sampling on RX side in
10728                                                                  PCS. Recommended values are 0x5 for 100 Mb/s operation and 0x32 for 10 Mb/s operation.
10729 
10730                                                                  For 10 Mb/s operation, this field should be set to a value less than 99 and greater than
10731                                                                  0.
10732                                                                  If set out of this range, a value of 50 is used for actual sampling internally without
10733                                                                  affecting the CSR field.
10734 
10735                                                                  For 100 Mb/s operation this field should be set to a value less than 9 and greater than 0.
10736                                                                  If set out of this range, a value of 5 is used for actual sampling internally without
10737                                                                  affecting the CSR field. */
10738         uint64_t an_ovrd               : 1;  /**< [  7:  7](R/W) Autonegotiation results override:
10739                                                                  0 = Disable.
10740                                                                  1 = Enable override. Autonegotiation is allowed to happen but the results are ignored
10741                                                                  when this bit is set.  Duplex and Link speed values are set from BGX()_GMP_PCS_MISC()_CTL. */
10742         uint64_t mode                  : 1;  /**< [  8:  8](R/W) Mode bit.
10743 
10744                                                                  _ 0 = SGMII mode is selected and the following note applies.
10745                                                                  The SGMII AN advertisement register (BGX()_GMP_PCS_SGM()_AN_ADV) is sent during
10746                                                                  autonegotiation if BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] = 1 (PHY mode). If [MAC_PHY]
10747                                                                  = 0 (MAC mode), the tx_Config_Reg\<14\> becomes ACK bit and \<0\> is always 1. All other bits
10748                                                                  in tx_Config_Reg sent are 0. The PHY dictates the autonegotiation results.
10749 
10750                                                                  _ 1 = 1000Base-X mode is selected. Autonegotiation follows IEEE 802.3 clause 37. */
10751         uint64_t mac_phy               : 1;  /**< [  9:  9](R/W) MAC/PHY.
10752                                                                  0 = MAC.
10753                                                                  1 = PHY decides the tx_Config_Reg value to be sent during autonegotiation. */
10754         uint64_t loopbck2              : 1;  /**< [ 10: 10](R/W) Sets external loopback mode to return RX data back out via the TX data path. 0 = No
10755                                                                  loopback. 1 = Loopback.
10756                                                                  LOOPBCK1 and LOOPBCK2 modes may not be supported simultaneously. */
10757         uint64_t gmxeno                : 1;  /**< [ 11: 11](R/W) GMI enable override. When set, forces GMI to appear disabled. The enable/disable status of
10758                                                                  GMI is checked only at SOP of every packet. */
10759         uint64_t sgmii                 : 1;  /**< [ 12: 12](RO/H) Reserved. Always 1. */
10760         uint64_t disp_en               : 1;  /**< [ 13: 13](R/W) Disparity check enable.  When LMAC_TYPE=QSGMII the running disparity check should be
10761                                                                  disabled
10762                                                                  to
10763                                                                  prevent propogation across ports.
10764                                                                  0 = disable disparity check
10765                                                                  1 = enable disparity checking
10766 
10767                                                                  See GSER()_LANE_MODE[LMODE]. */
10768         uint64_t reserved_14_15        : 2;
10769         uint64_t qsgmii_comma_wd       : 16; /**< [ 31: 16](R/W) QSGMII comma watchdog byte counter. This counter is used in QSGMII mode and
10770                                                                  counts incoming bytes to ensure state transitions in the PCS receive side state
10771                                                                  machine when disparity enable is turned off and bad code groups and commas are
10772                                                                  not communicated from the code group processor after code group lock. */
10773         uint64_t qsgmii_comma_wd_en    : 1;  /**< [ 32: 32](R/W) QSGMII comma watchdog byte counter enable. */
10774         uint64_t reserved_33_63        : 31;
10775 #endif /* Word 0 - End */
10776     } s;
10777     /* struct bdk_bgxx_gmp_pcs_miscx_ctl_s cn81xx; */
10778     struct bdk_bgxx_gmp_pcs_miscx_ctl_cn88xx
10779     {
10780 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10781         uint64_t reserved_13_63        : 51;
10782         uint64_t sgmii                 : 1;  /**< [ 12: 12](RO/H) Reserved. Always 1. */
10783         uint64_t gmxeno                : 1;  /**< [ 11: 11](R/W) GMI enable override. When set, forces GMI to appear disabled. The enable/disable status of
10784                                                                  GMI is checked only at SOP of every packet. */
10785         uint64_t loopbck2              : 1;  /**< [ 10: 10](R/W) Sets external loopback mode to return RX data back out via the TX data path. 0 = No
10786                                                                  loopback. 1 = Loopback.
10787                                                                  LOOPBCK1 and LOOPBCK2 modes may not be supported simultaneously. */
10788         uint64_t mac_phy               : 1;  /**< [  9:  9](R/W) MAC/PHY.
10789                                                                  0 = MAC.
10790                                                                  1 = PHY decides the tx_Config_Reg value to be sent during autonegotiation. */
10791         uint64_t mode                  : 1;  /**< [  8:  8](R/W) Mode bit.
10792 
10793                                                                  _ 0 = SGMII mode is selected and the following note applies.
10794                                                                  The SGMII AN advertisement register (BGX()_GMP_PCS_SGM()_AN_ADV) is sent during
10795                                                                  autonegotiation if BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] = 1 (PHY mode). If [MAC_PHY]
10796                                                                  = 0 (MAC mode), the tx_Config_Reg\<14\> becomes ACK bit and \<0\> is always 1. All other bits
10797                                                                  in tx_Config_Reg sent are 0. The PHY dictates the autonegotiation results.
10798 
10799                                                                  _ 1 = 1000Base-X mode is selected. Autonegotiation follows IEEE 802.3 clause 37. */
10800         uint64_t an_ovrd               : 1;  /**< [  7:  7](R/W) Autonegotiation results override:
10801                                                                  0 = Disable.
10802                                                                  1 = Enable override. Autonegotiation is allowed to happen but the results are ignored
10803                                                                  when this bit is set.  Duplex and Link speed values are set from BGX()_GMP_PCS_MISC()_CTL. */
10804         uint64_t samp_pt               : 7;  /**< [  6:  0](R/W) Byte number in elongated frames for 10/100 Mb/s operation for data sampling on RX side in
10805                                                                  PCS. Recommended values are 0x5 for 100 Mb/s operation and 0x32 for 10 Mb/s operation.
10806 
10807                                                                  For 10 Mb/s operation, this field should be set to a value less than 99 and greater than
10808                                                                  0.
10809                                                                  If set out of this range, a value of 50 is used for actual sampling internally without
10810                                                                  affecting the CSR field.
10811 
10812                                                                  For 100 Mb/s operation this field should be set to a value less than 9 and greater than 0.
10813                                                                  If set out of this range, a value of 5 is used for actual sampling internally without
10814                                                                  affecting the CSR field. */
10815 #else /* Word 0 - Little Endian */
10816         uint64_t samp_pt               : 7;  /**< [  6:  0](R/W) Byte number in elongated frames for 10/100 Mb/s operation for data sampling on RX side in
10817                                                                  PCS. Recommended values are 0x5 for 100 Mb/s operation and 0x32 for 10 Mb/s operation.
10818 
10819                                                                  For 10 Mb/s operation, this field should be set to a value less than 99 and greater than
10820                                                                  0.
10821                                                                  If set out of this range, a value of 50 is used for actual sampling internally without
10822                                                                  affecting the CSR field.
10823 
10824                                                                  For 100 Mb/s operation this field should be set to a value less than 9 and greater than 0.
10825                                                                  If set out of this range, a value of 5 is used for actual sampling internally without
10826                                                                  affecting the CSR field. */
10827         uint64_t an_ovrd               : 1;  /**< [  7:  7](R/W) Autonegotiation results override:
10828                                                                  0 = Disable.
10829                                                                  1 = Enable override. Autonegotiation is allowed to happen but the results are ignored
10830                                                                  when this bit is set.  Duplex and Link speed values are set from BGX()_GMP_PCS_MISC()_CTL. */
10831         uint64_t mode                  : 1;  /**< [  8:  8](R/W) Mode bit.
10832 
10833                                                                  _ 0 = SGMII mode is selected and the following note applies.
10834                                                                  The SGMII AN advertisement register (BGX()_GMP_PCS_SGM()_AN_ADV) is sent during
10835                                                                  autonegotiation if BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] = 1 (PHY mode). If [MAC_PHY]
10836                                                                  = 0 (MAC mode), the tx_Config_Reg\<14\> becomes ACK bit and \<0\> is always 1. All other bits
10837                                                                  in tx_Config_Reg sent are 0. The PHY dictates the autonegotiation results.
10838 
10839                                                                  _ 1 = 1000Base-X mode is selected. Autonegotiation follows IEEE 802.3 clause 37. */
10840         uint64_t mac_phy               : 1;  /**< [  9:  9](R/W) MAC/PHY.
10841                                                                  0 = MAC.
10842                                                                  1 = PHY decides the tx_Config_Reg value to be sent during autonegotiation. */
10843         uint64_t loopbck2              : 1;  /**< [ 10: 10](R/W) Sets external loopback mode to return RX data back out via the TX data path. 0 = No
10844                                                                  loopback. 1 = Loopback.
10845                                                                  LOOPBCK1 and LOOPBCK2 modes may not be supported simultaneously. */
10846         uint64_t gmxeno                : 1;  /**< [ 11: 11](R/W) GMI enable override. When set, forces GMI to appear disabled. The enable/disable status of
10847                                                                  GMI is checked only at SOP of every packet. */
10848         uint64_t sgmii                 : 1;  /**< [ 12: 12](RO/H) Reserved. Always 1. */
10849         uint64_t reserved_13_63        : 51;
10850 #endif /* Word 0 - End */
10851     } cn88xx;
10852     /* struct bdk_bgxx_gmp_pcs_miscx_ctl_s cn83xx; */
10853 };
10854 typedef union bdk_bgxx_gmp_pcs_miscx_ctl bdk_bgxx_gmp_pcs_miscx_ctl_t;
10855 
10856 static inline uint64_t BDK_BGXX_GMP_PCS_MISCX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_MISCX_CTL(unsigned long a,unsigned long b)10857 static inline uint64_t BDK_BGXX_GMP_PCS_MISCX_CTL(unsigned long a, unsigned long b)
10858 {
10859     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
10860         return 0x87e0e0030078ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10861     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
10862         return 0x87e0e0030078ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
10863     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
10864         return 0x87e0e0030078ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
10865     __bdk_csr_fatal("BGXX_GMP_PCS_MISCX_CTL", 2, a, b, 0, 0);
10866 }
10867 
10868 #define typedef_BDK_BGXX_GMP_PCS_MISCX_CTL(a,b) bdk_bgxx_gmp_pcs_miscx_ctl_t
10869 #define bustype_BDK_BGXX_GMP_PCS_MISCX_CTL(a,b) BDK_CSR_TYPE_RSL
10870 #define basename_BDK_BGXX_GMP_PCS_MISCX_CTL(a,b) "BGXX_GMP_PCS_MISCX_CTL"
10871 #define device_bar_BDK_BGXX_GMP_PCS_MISCX_CTL(a,b) 0x0 /* PF_BAR0 */
10872 #define busnum_BDK_BGXX_GMP_PCS_MISCX_CTL(a,b) (a)
10873 #define arguments_BDK_BGXX_GMP_PCS_MISCX_CTL(a,b) (a),(b),-1,-1
10874 
10875 /**
10876  * Register (RSL) bgx#_gmp_pcs_mr#_control
10877  *
10878  * BGX GMP PCS Control Registers
10879  */
10880 union bdk_bgxx_gmp_pcs_mrx_control
10881 {
10882     uint64_t u;
10883     struct bdk_bgxx_gmp_pcs_mrx_control_s
10884     {
10885 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10886         uint64_t reserved_16_63        : 48;
10887         uint64_t reset                 : 1;  /**< [ 15: 15](R/W/H) Set to reset.
10888                                                                  0 = Normal operation.
10889                                                                  1 = Software PCS reset.
10890 
10891                                                                  The bit returns to 0 after PCS has been reset. Takes 32 coprocessor-clock cycles to reset
10892                                                                  PCS.   This bit, when set, also drains the tx gmi fifo and can be used as a fifo draining
10893                                                                  mechanism for both SerDes reset conditions and for XCV reset conditions. */
10894         uint64_t loopbck1              : 1;  /**< [ 14: 14](R/W) Enable loopback:
10895                                                                    0 = Normal operation.
10896                                                                    1 = Internal loopback mode.
10897 
10898                                                                  The loopback mode returns loopback TX data from GMII TX back to GMII RX interface. The
10899                                                                  loopback happens in the PCS module. Autonegotiation is disabled even if [AN_EN] is set
10900                                                                  during loopback. */
10901         uint64_t spdlsb                : 1;  /**< [ 13: 13](R/W) Least-significant bit of the link-speed field, i.e. SPD\<0\>. Refer to SPDMSB. */
10902         uint64_t an_en                 : 1;  /**< [ 12: 12](R/W) Autonegotiation enable. */
10903         uint64_t pwr_dn                : 1;  /**< [ 11: 11](R/W) Power down:
10904                                                                    0 = Normal operation.
10905                                                                    1 = Power down (hardware reset). */
10906         uint64_t reserved_10           : 1;
10907         uint64_t rst_an                : 1;  /**< [  9:  9](R/W/H) Reset autonegotiation. When set, if [AN_EN] = 1 and
10908                                                                  BGX()_GMP_PCS_MR()_STATUS[AN_ABIL] = 1, autonegotiation begins. Otherwise,
10909                                                                  software write requests are ignored and this bit remains at 0. This bit clears itself to
10910                                                                  0, when autonegotiation starts. */
10911         uint64_t dup                   : 1;  /**< [  8:  8](R/W) Duplex mode:
10912                                                                    0 = half duplex; effective only if autonegotiation is disabled.
10913                                                                    1 = full duplex.
10914 
10915                                                                  If BGX()_GMP_PCS_MR()_STATUS \<15:9\> and
10916                                                                  BGX()_GMP_PCS_AN()_ADV\<15:12\> allow only one duplex mode, this bit corresponds to
10917                                                                  that value and any attempts to write are ignored. */
10918         uint64_t coltst                : 1;  /**< [  7:  7](R/W) Enable COL signal test.
10919                                                                  During COL test, the COL signal reflects the GMII TX_EN signal with less than 16BT delay. */
10920         uint64_t spdmsb                : 1;  /**< [  6:  6](R/W) Link speed most-significant bit, i.e SPD\<1\>; effective only if autonegotiation is
10921                                                                  disabled.
10922 
10923                                                                  \<pre\>
10924                                                                  [SPDMSB]   [SPDLSB]   Link Speed
10925                                                                   0          0         10 Mb/s
10926                                                                   0          1         100 Mb/s
10927                                                                   1          0         1000 Mb/s
10928                                                                   1          1         reserved
10929                                                                  \</pre\> */
10930         uint64_t uni                   : 1;  /**< [  5:  5](R/W) Unidirectional (IEEE 802.3-2005, Clause 66.2). When set to 1, this bit overrides [AN_EN]
10931                                                                  and
10932                                                                  disables the autonegotiation variable mr_an_enable. Used in both 1000BASE-X and
10933                                                                  SGMII/QSGMII
10934                                                                  modes. */
10935         uint64_t reserved_0_4          : 5;
10936 #else /* Word 0 - Little Endian */
10937         uint64_t reserved_0_4          : 5;
10938         uint64_t uni                   : 1;  /**< [  5:  5](R/W) Unidirectional (IEEE 802.3-2005, Clause 66.2). When set to 1, this bit overrides [AN_EN]
10939                                                                  and
10940                                                                  disables the autonegotiation variable mr_an_enable. Used in both 1000BASE-X and
10941                                                                  SGMII/QSGMII
10942                                                                  modes. */
10943         uint64_t spdmsb                : 1;  /**< [  6:  6](R/W) Link speed most-significant bit, i.e SPD\<1\>; effective only if autonegotiation is
10944                                                                  disabled.
10945 
10946                                                                  \<pre\>
10947                                                                  [SPDMSB]   [SPDLSB]   Link Speed
10948                                                                   0          0         10 Mb/s
10949                                                                   0          1         100 Mb/s
10950                                                                   1          0         1000 Mb/s
10951                                                                   1          1         reserved
10952                                                                  \</pre\> */
10953         uint64_t coltst                : 1;  /**< [  7:  7](R/W) Enable COL signal test.
10954                                                                  During COL test, the COL signal reflects the GMII TX_EN signal with less than 16BT delay. */
10955         uint64_t dup                   : 1;  /**< [  8:  8](R/W) Duplex mode:
10956                                                                    0 = half duplex; effective only if autonegotiation is disabled.
10957                                                                    1 = full duplex.
10958 
10959                                                                  If BGX()_GMP_PCS_MR()_STATUS \<15:9\> and
10960                                                                  BGX()_GMP_PCS_AN()_ADV\<15:12\> allow only one duplex mode, this bit corresponds to
10961                                                                  that value and any attempts to write are ignored. */
10962         uint64_t rst_an                : 1;  /**< [  9:  9](R/W/H) Reset autonegotiation. When set, if [AN_EN] = 1 and
10963                                                                  BGX()_GMP_PCS_MR()_STATUS[AN_ABIL] = 1, autonegotiation begins. Otherwise,
10964                                                                  software write requests are ignored and this bit remains at 0. This bit clears itself to
10965                                                                  0, when autonegotiation starts. */
10966         uint64_t reserved_10           : 1;
10967         uint64_t pwr_dn                : 1;  /**< [ 11: 11](R/W) Power down:
10968                                                                    0 = Normal operation.
10969                                                                    1 = Power down (hardware reset). */
10970         uint64_t an_en                 : 1;  /**< [ 12: 12](R/W) Autonegotiation enable. */
10971         uint64_t spdlsb                : 1;  /**< [ 13: 13](R/W) Least-significant bit of the link-speed field, i.e. SPD\<0\>. Refer to SPDMSB. */
10972         uint64_t loopbck1              : 1;  /**< [ 14: 14](R/W) Enable loopback:
10973                                                                    0 = Normal operation.
10974                                                                    1 = Internal loopback mode.
10975 
10976                                                                  The loopback mode returns loopback TX data from GMII TX back to GMII RX interface. The
10977                                                                  loopback happens in the PCS module. Autonegotiation is disabled even if [AN_EN] is set
10978                                                                  during loopback. */
10979         uint64_t reset                 : 1;  /**< [ 15: 15](R/W/H) Set to reset.
10980                                                                  0 = Normal operation.
10981                                                                  1 = Software PCS reset.
10982 
10983                                                                  The bit returns to 0 after PCS has been reset. Takes 32 coprocessor-clock cycles to reset
10984                                                                  PCS.   This bit, when set, also drains the tx gmi fifo and can be used as a fifo draining
10985                                                                  mechanism for both SerDes reset conditions and for XCV reset conditions. */
10986         uint64_t reserved_16_63        : 48;
10987 #endif /* Word 0 - End */
10988     } s;
10989     /* struct bdk_bgxx_gmp_pcs_mrx_control_s cn81xx; */
10990     struct bdk_bgxx_gmp_pcs_mrx_control_cn88xx
10991     {
10992 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10993         uint64_t reserved_16_63        : 48;
10994         uint64_t reset                 : 1;  /**< [ 15: 15](R/W/H) Set to reset.
10995                                                                  0 = Normal operation.
10996                                                                  1 = Software PCS reset.
10997 
10998                                                                  The bit returns to 0 after PCS has been reset. Takes 32 coprocessor-clock cycles to reset
10999                                                                  PCS.   This bit, when set, also drains the tx gmi fifo and can be used as a fifo draining
11000                                                                  mechanism for both SerDes reset conditions and for XCV reset conditions. */
11001         uint64_t loopbck1              : 1;  /**< [ 14: 14](R/W) Enable loopback:
11002                                                                    0 = Normal operation.
11003                                                                    1 = Internal loopback mode.
11004 
11005                                                                  The loopback mode returns loopback TX data from GMII TX back to GMII RX interface. The
11006                                                                  loopback happens in the PCS module. Autonegotiation is disabled even if [AN_EN] is set
11007                                                                  during loopback. */
11008         uint64_t spdlsb                : 1;  /**< [ 13: 13](R/W) Least-significant bit of the link-speed field, i.e. SPD\<0\>. Refer to SPDMSB. */
11009         uint64_t an_en                 : 1;  /**< [ 12: 12](R/W) Autonegotiation enable. */
11010         uint64_t pwr_dn                : 1;  /**< [ 11: 11](R/W) Power down:
11011                                                                    0 = Normal operation.
11012                                                                    1 = Power down (hardware reset). */
11013         uint64_t reserved_10           : 1;
11014         uint64_t rst_an                : 1;  /**< [  9:  9](R/W/H) Reset autonegotiation. When set, if [AN_EN] = 1 and
11015                                                                  BGX()_GMP_PCS_MR()_STATUS[AN_ABIL] = 1, autonegotiation begins. Otherwise,
11016                                                                  software write requests are ignored and this bit remains at 0. This bit clears itself to
11017                                                                  0, when autonegotiation starts. */
11018         uint64_t dup                   : 1;  /**< [  8:  8](R/W) Duplex mode:
11019                                                                    0 = half duplex; effective only if autonegotiation is disabled.
11020                                                                    1 = full duplex.
11021 
11022                                                                  If BGX()_GMP_PCS_MR()_STATUS \<15:9\> and
11023                                                                  BGX()_GMP_PCS_AN()_ADV\<15:12\> allow only one duplex mode, this bit corresponds to
11024                                                                  that value and any attempts to write are ignored. */
11025         uint64_t coltst                : 1;  /**< [  7:  7](R/W) Enable COL signal test.
11026                                                                  During COL test, the COL signal reflects the GMII TX_EN signal with less than 16BT delay. */
11027         uint64_t spdmsb                : 1;  /**< [  6:  6](R/W) Link speed most-significant bit, i.e SPD\<1\>; effective only if autonegotiation is
11028                                                                  disabled.
11029 
11030                                                                  \<pre\>
11031                                                                  [SPDMSB]   [SPDLSB]   Link Speed
11032                                                                   0          0         10 Mb/s
11033                                                                   0          1         100 Mb/s
11034                                                                   1          0         1000 Mb/s
11035                                                                   1          1         reserved
11036                                                                  \</pre\> */
11037         uint64_t uni                   : 1;  /**< [  5:  5](R/W) Unidirectional (IEEE 802.3-2005, Clause 66.2). When set to 1, this bit overrides [AN_EN]
11038                                                                  and
11039                                                                  disables the autonegotiation variable mr_an_enable. Used in both 1000BASE-X and SGMII
11040                                                                  modes. */
11041         uint64_t reserved_0_4          : 5;
11042 #else /* Word 0 - Little Endian */
11043         uint64_t reserved_0_4          : 5;
11044         uint64_t uni                   : 1;  /**< [  5:  5](R/W) Unidirectional (IEEE 802.3-2005, Clause 66.2). When set to 1, this bit overrides [AN_EN]
11045                                                                  and
11046                                                                  disables the autonegotiation variable mr_an_enable. Used in both 1000BASE-X and SGMII
11047                                                                  modes. */
11048         uint64_t spdmsb                : 1;  /**< [  6:  6](R/W) Link speed most-significant bit, i.e SPD\<1\>; effective only if autonegotiation is
11049                                                                  disabled.
11050 
11051                                                                  \<pre\>
11052                                                                  [SPDMSB]   [SPDLSB]   Link Speed
11053                                                                   0          0         10 Mb/s
11054                                                                   0          1         100 Mb/s
11055                                                                   1          0         1000 Mb/s
11056                                                                   1          1         reserved
11057                                                                  \</pre\> */
11058         uint64_t coltst                : 1;  /**< [  7:  7](R/W) Enable COL signal test.
11059                                                                  During COL test, the COL signal reflects the GMII TX_EN signal with less than 16BT delay. */
11060         uint64_t dup                   : 1;  /**< [  8:  8](R/W) Duplex mode:
11061                                                                    0 = half duplex; effective only if autonegotiation is disabled.
11062                                                                    1 = full duplex.
11063 
11064                                                                  If BGX()_GMP_PCS_MR()_STATUS \<15:9\> and
11065                                                                  BGX()_GMP_PCS_AN()_ADV\<15:12\> allow only one duplex mode, this bit corresponds to
11066                                                                  that value and any attempts to write are ignored. */
11067         uint64_t rst_an                : 1;  /**< [  9:  9](R/W/H) Reset autonegotiation. When set, if [AN_EN] = 1 and
11068                                                                  BGX()_GMP_PCS_MR()_STATUS[AN_ABIL] = 1, autonegotiation begins. Otherwise,
11069                                                                  software write requests are ignored and this bit remains at 0. This bit clears itself to
11070                                                                  0, when autonegotiation starts. */
11071         uint64_t reserved_10           : 1;
11072         uint64_t pwr_dn                : 1;  /**< [ 11: 11](R/W) Power down:
11073                                                                    0 = Normal operation.
11074                                                                    1 = Power down (hardware reset). */
11075         uint64_t an_en                 : 1;  /**< [ 12: 12](R/W) Autonegotiation enable. */
11076         uint64_t spdlsb                : 1;  /**< [ 13: 13](R/W) Least-significant bit of the link-speed field, i.e. SPD\<0\>. Refer to SPDMSB. */
11077         uint64_t loopbck1              : 1;  /**< [ 14: 14](R/W) Enable loopback:
11078                                                                    0 = Normal operation.
11079                                                                    1 = Internal loopback mode.
11080 
11081                                                                  The loopback mode returns loopback TX data from GMII TX back to GMII RX interface. The
11082                                                                  loopback happens in the PCS module. Autonegotiation is disabled even if [AN_EN] is set
11083                                                                  during loopback. */
11084         uint64_t reset                 : 1;  /**< [ 15: 15](R/W/H) Set to reset.
11085                                                                  0 = Normal operation.
11086                                                                  1 = Software PCS reset.
11087 
11088                                                                  The bit returns to 0 after PCS has been reset. Takes 32 coprocessor-clock cycles to reset
11089                                                                  PCS.   This bit, when set, also drains the tx gmi fifo and can be used as a fifo draining
11090                                                                  mechanism for both SerDes reset conditions and for XCV reset conditions. */
11091         uint64_t reserved_16_63        : 48;
11092 #endif /* Word 0 - End */
11093     } cn88xx;
11094     /* struct bdk_bgxx_gmp_pcs_mrx_control_s cn83xx; */
11095 };
11096 typedef union bdk_bgxx_gmp_pcs_mrx_control bdk_bgxx_gmp_pcs_mrx_control_t;
11097 
11098 static inline uint64_t BDK_BGXX_GMP_PCS_MRX_CONTROL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_MRX_CONTROL(unsigned long a,unsigned long b)11099 static inline uint64_t BDK_BGXX_GMP_PCS_MRX_CONTROL(unsigned long a, unsigned long b)
11100 {
11101     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11102         return 0x87e0e0030000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11103     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11104         return 0x87e0e0030000ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11105     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11106         return 0x87e0e0030000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11107     __bdk_csr_fatal("BGXX_GMP_PCS_MRX_CONTROL", 2, a, b, 0, 0);
11108 }
11109 
11110 #define typedef_BDK_BGXX_GMP_PCS_MRX_CONTROL(a,b) bdk_bgxx_gmp_pcs_mrx_control_t
11111 #define bustype_BDK_BGXX_GMP_PCS_MRX_CONTROL(a,b) BDK_CSR_TYPE_RSL
11112 #define basename_BDK_BGXX_GMP_PCS_MRX_CONTROL(a,b) "BGXX_GMP_PCS_MRX_CONTROL"
11113 #define device_bar_BDK_BGXX_GMP_PCS_MRX_CONTROL(a,b) 0x0 /* PF_BAR0 */
11114 #define busnum_BDK_BGXX_GMP_PCS_MRX_CONTROL(a,b) (a)
11115 #define arguments_BDK_BGXX_GMP_PCS_MRX_CONTROL(a,b) (a),(b),-1,-1
11116 
11117 /**
11118  * Register (RSL) bgx#_gmp_pcs_mr#_status
11119  *
11120  * BGX GMP PCS Status Registers
11121  * Bits \<15:9\> in this register indicate the ability to operate when
11122  * BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] is set to MAC mode. Bits \<15:9\> are always read as
11123  * 0, indicating that the chip cannot operate in the corresponding modes. The field [RM_FLT] is a
11124  * 'don't care' when the selected mode is SGMII.
11125  */
11126 union bdk_bgxx_gmp_pcs_mrx_status
11127 {
11128     uint64_t u;
11129     struct bdk_bgxx_gmp_pcs_mrx_status_s
11130     {
11131 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11132         uint64_t reserved_16_63        : 48;
11133         uint64_t hun_t4                : 1;  /**< [ 15: 15](RO/H) Indicates 100BASE-T4 capable. */
11134         uint64_t hun_xfd               : 1;  /**< [ 14: 14](RO/H) Indicates 100BASE-X full duplex. */
11135         uint64_t hun_xhd               : 1;  /**< [ 13: 13](RO/H) Indicates 100BASE-X half duplex. */
11136         uint64_t ten_fd                : 1;  /**< [ 12: 12](RO/H) Indicates 10Mb/s full duplex. */
11137         uint64_t ten_hd                : 1;  /**< [ 11: 11](RO/H) Indicates 10Mb/s half duplex. */
11138         uint64_t hun_t2fd              : 1;  /**< [ 10: 10](RO/H) Indicates 100BASE-T2 full duplex. */
11139         uint64_t hun_t2hd              : 1;  /**< [  9:  9](RO/H) Indicates 100BASE-T2 half duplex. */
11140         uint64_t ext_st                : 1;  /**< [  8:  8](RO/H) Extended status information. When set to 1, indicates that additional status data is
11141                                                                  available in BGX()_GMP_PCS_AN()_EXT_ST. */
11142         uint64_t reserved_7            : 1;
11143         uint64_t prb_sup               : 1;  /**< [  6:  6](RO/H) Preamble not needed.
11144                                                                  0 = Cannot accept frames without preamble bytes.
11145                                                                  1 = Can work without preamble bytes at the beginning of frames. */
11146         uint64_t an_cpt                : 1;  /**< [  5:  5](RO/H) Indicates autonegotiation is complete; the contents of the
11147                                                                  BGX()_GMP_PCS_AN()_RESULTS are valid. */
11148         uint64_t rm_flt                : 1;  /**< [  4:  4](RO/H) Indicates remote fault condition occurred. This bit implements a latching-high behavior.
11149                                                                  It is cleared when software reads this register or when
11150                                                                  BGX()_GMP_PCS_MR()_CONTROL[RESET] is asserted.
11151                                                                  See BGX()_GMP_PCS_AN()_ADV[REM_FLT] for fault conditions. */
11152         uint64_t an_abil               : 1;  /**< [  3:  3](RO/H) Indicates autonegotiation capable. */
11153         uint64_t lnk_st                : 1;  /**< [  2:  2](RO/H) Link state:
11154                                                                    0 = link down.
11155                                                                    1 = link up.
11156 
11157                                                                  Set during autonegotiation process. Set whenever XMIT = DATA. Latching-low behavior when
11158                                                                  link goes down. Link down value of the bit stays low until software reads the register. */
11159         uint64_t reserved_1            : 1;
11160         uint64_t extnd                 : 1;  /**< [  0:  0](RO/H) This field is always 0, extended capability registers not present. */
11161 #else /* Word 0 - Little Endian */
11162         uint64_t extnd                 : 1;  /**< [  0:  0](RO/H) This field is always 0, extended capability registers not present. */
11163         uint64_t reserved_1            : 1;
11164         uint64_t lnk_st                : 1;  /**< [  2:  2](RO/H) Link state:
11165                                                                    0 = link down.
11166                                                                    1 = link up.
11167 
11168                                                                  Set during autonegotiation process. Set whenever XMIT = DATA. Latching-low behavior when
11169                                                                  link goes down. Link down value of the bit stays low until software reads the register. */
11170         uint64_t an_abil               : 1;  /**< [  3:  3](RO/H) Indicates autonegotiation capable. */
11171         uint64_t rm_flt                : 1;  /**< [  4:  4](RO/H) Indicates remote fault condition occurred. This bit implements a latching-high behavior.
11172                                                                  It is cleared when software reads this register or when
11173                                                                  BGX()_GMP_PCS_MR()_CONTROL[RESET] is asserted.
11174                                                                  See BGX()_GMP_PCS_AN()_ADV[REM_FLT] for fault conditions. */
11175         uint64_t an_cpt                : 1;  /**< [  5:  5](RO/H) Indicates autonegotiation is complete; the contents of the
11176                                                                  BGX()_GMP_PCS_AN()_RESULTS are valid. */
11177         uint64_t prb_sup               : 1;  /**< [  6:  6](RO/H) Preamble not needed.
11178                                                                  0 = Cannot accept frames without preamble bytes.
11179                                                                  1 = Can work without preamble bytes at the beginning of frames. */
11180         uint64_t reserved_7            : 1;
11181         uint64_t ext_st                : 1;  /**< [  8:  8](RO/H) Extended status information. When set to 1, indicates that additional status data is
11182                                                                  available in BGX()_GMP_PCS_AN()_EXT_ST. */
11183         uint64_t hun_t2hd              : 1;  /**< [  9:  9](RO/H) Indicates 100BASE-T2 half duplex. */
11184         uint64_t hun_t2fd              : 1;  /**< [ 10: 10](RO/H) Indicates 100BASE-T2 full duplex. */
11185         uint64_t ten_hd                : 1;  /**< [ 11: 11](RO/H) Indicates 10Mb/s half duplex. */
11186         uint64_t ten_fd                : 1;  /**< [ 12: 12](RO/H) Indicates 10Mb/s full duplex. */
11187         uint64_t hun_xhd               : 1;  /**< [ 13: 13](RO/H) Indicates 100BASE-X half duplex. */
11188         uint64_t hun_xfd               : 1;  /**< [ 14: 14](RO/H) Indicates 100BASE-X full duplex. */
11189         uint64_t hun_t4                : 1;  /**< [ 15: 15](RO/H) Indicates 100BASE-T4 capable. */
11190         uint64_t reserved_16_63        : 48;
11191 #endif /* Word 0 - End */
11192     } s;
11193     /* struct bdk_bgxx_gmp_pcs_mrx_status_s cn; */
11194 };
11195 typedef union bdk_bgxx_gmp_pcs_mrx_status bdk_bgxx_gmp_pcs_mrx_status_t;
11196 
11197 static inline uint64_t BDK_BGXX_GMP_PCS_MRX_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_MRX_STATUS(unsigned long a,unsigned long b)11198 static inline uint64_t BDK_BGXX_GMP_PCS_MRX_STATUS(unsigned long a, unsigned long b)
11199 {
11200     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11201         return 0x87e0e0030008ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11202     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11203         return 0x87e0e0030008ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11204     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11205         return 0x87e0e0030008ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11206     __bdk_csr_fatal("BGXX_GMP_PCS_MRX_STATUS", 2, a, b, 0, 0);
11207 }
11208 
11209 #define typedef_BDK_BGXX_GMP_PCS_MRX_STATUS(a,b) bdk_bgxx_gmp_pcs_mrx_status_t
11210 #define bustype_BDK_BGXX_GMP_PCS_MRX_STATUS(a,b) BDK_CSR_TYPE_RSL
11211 #define basename_BDK_BGXX_GMP_PCS_MRX_STATUS(a,b) "BGXX_GMP_PCS_MRX_STATUS"
11212 #define device_bar_BDK_BGXX_GMP_PCS_MRX_STATUS(a,b) 0x0 /* PF_BAR0 */
11213 #define busnum_BDK_BGXX_GMP_PCS_MRX_STATUS(a,b) (a)
11214 #define arguments_BDK_BGXX_GMP_PCS_MRX_STATUS(a,b) (a),(b),-1,-1
11215 
11216 /**
11217  * Register (RSL) bgx#_gmp_pcs_rx#_states
11218  *
11219  * BGX GMP PCS RX State-Machines States Registers
11220  */
11221 union bdk_bgxx_gmp_pcs_rxx_states
11222 {
11223     uint64_t u;
11224     struct bdk_bgxx_gmp_pcs_rxx_states_s
11225     {
11226 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11227         uint64_t reserved_16_63        : 48;
11228         uint64_t rx_bad                : 1;  /**< [ 15: 15](RO/H) Receive state machine is in an illegal state. */
11229         uint64_t rx_st                 : 5;  /**< [ 14: 10](RO/H) Receive state-machine state. */
11230         uint64_t sync_bad              : 1;  /**< [  9:  9](RO/H) Receive synchronization state machine is in an illegal state. */
11231         uint64_t sync                  : 4;  /**< [  8:  5](RO/H) Receive synchronization state-machine state. */
11232         uint64_t an_bad                : 1;  /**< [  4:  4](RO/H) Autonegotiation state machine is in an illegal state. */
11233         uint64_t an_st                 : 4;  /**< [  3:  0](RO/H) Autonegotiation state-machine state. */
11234 #else /* Word 0 - Little Endian */
11235         uint64_t an_st                 : 4;  /**< [  3:  0](RO/H) Autonegotiation state-machine state. */
11236         uint64_t an_bad                : 1;  /**< [  4:  4](RO/H) Autonegotiation state machine is in an illegal state. */
11237         uint64_t sync                  : 4;  /**< [  8:  5](RO/H) Receive synchronization state-machine state. */
11238         uint64_t sync_bad              : 1;  /**< [  9:  9](RO/H) Receive synchronization state machine is in an illegal state. */
11239         uint64_t rx_st                 : 5;  /**< [ 14: 10](RO/H) Receive state-machine state. */
11240         uint64_t rx_bad                : 1;  /**< [ 15: 15](RO/H) Receive state machine is in an illegal state. */
11241         uint64_t reserved_16_63        : 48;
11242 #endif /* Word 0 - End */
11243     } s;
11244     /* struct bdk_bgxx_gmp_pcs_rxx_states_s cn; */
11245 };
11246 typedef union bdk_bgxx_gmp_pcs_rxx_states bdk_bgxx_gmp_pcs_rxx_states_t;
11247 
11248 static inline uint64_t BDK_BGXX_GMP_PCS_RXX_STATES(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_RXX_STATES(unsigned long a,unsigned long b)11249 static inline uint64_t BDK_BGXX_GMP_PCS_RXX_STATES(unsigned long a, unsigned long b)
11250 {
11251     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11252         return 0x87e0e0030058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11253     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11254         return 0x87e0e0030058ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11255     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11256         return 0x87e0e0030058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11257     __bdk_csr_fatal("BGXX_GMP_PCS_RXX_STATES", 2, a, b, 0, 0);
11258 }
11259 
11260 #define typedef_BDK_BGXX_GMP_PCS_RXX_STATES(a,b) bdk_bgxx_gmp_pcs_rxx_states_t
11261 #define bustype_BDK_BGXX_GMP_PCS_RXX_STATES(a,b) BDK_CSR_TYPE_RSL
11262 #define basename_BDK_BGXX_GMP_PCS_RXX_STATES(a,b) "BGXX_GMP_PCS_RXX_STATES"
11263 #define device_bar_BDK_BGXX_GMP_PCS_RXX_STATES(a,b) 0x0 /* PF_BAR0 */
11264 #define busnum_BDK_BGXX_GMP_PCS_RXX_STATES(a,b) (a)
11265 #define arguments_BDK_BGXX_GMP_PCS_RXX_STATES(a,b) (a),(b),-1,-1
11266 
11267 /**
11268  * Register (RSL) bgx#_gmp_pcs_rx#_sync
11269  *
11270  * BGX GMP PCS Code Group Synchronization Registers
11271  */
11272 union bdk_bgxx_gmp_pcs_rxx_sync
11273 {
11274     uint64_t u;
11275     struct bdk_bgxx_gmp_pcs_rxx_sync_s
11276     {
11277 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11278         uint64_t reserved_2_63         : 62;
11279         uint64_t sync                  : 1;  /**< [  1:  1](RO/H) When set, code group synchronization achieved. */
11280         uint64_t bit_lock              : 1;  /**< [  0:  0](RO/H) When set, bit lock achieved. */
11281 #else /* Word 0 - Little Endian */
11282         uint64_t bit_lock              : 1;  /**< [  0:  0](RO/H) When set, bit lock achieved. */
11283         uint64_t sync                  : 1;  /**< [  1:  1](RO/H) When set, code group synchronization achieved. */
11284         uint64_t reserved_2_63         : 62;
11285 #endif /* Word 0 - End */
11286     } s;
11287     /* struct bdk_bgxx_gmp_pcs_rxx_sync_s cn; */
11288 };
11289 typedef union bdk_bgxx_gmp_pcs_rxx_sync bdk_bgxx_gmp_pcs_rxx_sync_t;
11290 
11291 static inline uint64_t BDK_BGXX_GMP_PCS_RXX_SYNC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_RXX_SYNC(unsigned long a,unsigned long b)11292 static inline uint64_t BDK_BGXX_GMP_PCS_RXX_SYNC(unsigned long a, unsigned long b)
11293 {
11294     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11295         return 0x87e0e0030050ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11296     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11297         return 0x87e0e0030050ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11298     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11299         return 0x87e0e0030050ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11300     __bdk_csr_fatal("BGXX_GMP_PCS_RXX_SYNC", 2, a, b, 0, 0);
11301 }
11302 
11303 #define typedef_BDK_BGXX_GMP_PCS_RXX_SYNC(a,b) bdk_bgxx_gmp_pcs_rxx_sync_t
11304 #define bustype_BDK_BGXX_GMP_PCS_RXX_SYNC(a,b) BDK_CSR_TYPE_RSL
11305 #define basename_BDK_BGXX_GMP_PCS_RXX_SYNC(a,b) "BGXX_GMP_PCS_RXX_SYNC"
11306 #define device_bar_BDK_BGXX_GMP_PCS_RXX_SYNC(a,b) 0x0 /* PF_BAR0 */
11307 #define busnum_BDK_BGXX_GMP_PCS_RXX_SYNC(a,b) (a)
11308 #define arguments_BDK_BGXX_GMP_PCS_RXX_SYNC(a,b) (a),(b),-1,-1
11309 
11310 /**
11311  * Register (RSL) bgx#_gmp_pcs_sgm#_an_adv
11312  *
11313  * BGX GMP PCS SGMII Autonegotiation Advertisement Registers
11314  * This is the SGMII autonegotiation advertisement register (sent out as tx_Config_Reg\<15:0\> as
11315  * defined in IEEE 802.3 clause 37). This register is sent during autonegotiation if
11316  * BGX()_GMP_PCS_MISC()_CTL[MAC_PHY] is set (1 = PHY mode). If the bit is not set (0 =
11317  * MAC mode), then tx_Config_Reg\<14\> becomes ACK bit and tx_Config_Reg\<0\> is always 1. All other
11318  * bits in tx_Config_Reg sent will be 0. The PHY dictates the autonegotiation results.
11319  */
11320 union bdk_bgxx_gmp_pcs_sgmx_an_adv
11321 {
11322     uint64_t u;
11323     struct bdk_bgxx_gmp_pcs_sgmx_an_adv_s
11324     {
11325 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11326         uint64_t reserved_16_63        : 48;
11327         uint64_t link                  : 1;  /**< [ 15: 15](R/W) Link status: 1 = Link up. 0 = Link down. */
11328         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Autonegotiation acknowledgement. */
11329         uint64_t reserved_13           : 1;
11330         uint64_t dup                   : 1;  /**< [ 12: 12](R/W) Duplex mode: 1 = full duplex, 0 = half duplex. */
11331         uint64_t speed                 : 2;  /**< [ 11: 10](R/W) Link speed:
11332                                                                  0x0 = 10 Mb/s.
11333                                                                  0x1 = 100 Mb/s.
11334                                                                  0x2 = 1000 Mb/s.
11335                                                                  0x3 = Reserved. */
11336         uint64_t reserved_1_9          : 9;
11337         uint64_t one                   : 1;  /**< [  0:  0](RO/H) Always set to match tx_Config_Reg\<0\>. */
11338 #else /* Word 0 - Little Endian */
11339         uint64_t one                   : 1;  /**< [  0:  0](RO/H) Always set to match tx_Config_Reg\<0\>. */
11340         uint64_t reserved_1_9          : 9;
11341         uint64_t speed                 : 2;  /**< [ 11: 10](R/W) Link speed:
11342                                                                  0x0 = 10 Mb/s.
11343                                                                  0x1 = 100 Mb/s.
11344                                                                  0x2 = 1000 Mb/s.
11345                                                                  0x3 = Reserved. */
11346         uint64_t dup                   : 1;  /**< [ 12: 12](R/W) Duplex mode: 1 = full duplex, 0 = half duplex. */
11347         uint64_t reserved_13           : 1;
11348         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Autonegotiation acknowledgement. */
11349         uint64_t link                  : 1;  /**< [ 15: 15](R/W) Link status: 1 = Link up. 0 = Link down. */
11350         uint64_t reserved_16_63        : 48;
11351 #endif /* Word 0 - End */
11352     } s;
11353     /* struct bdk_bgxx_gmp_pcs_sgmx_an_adv_s cn; */
11354 };
11355 typedef union bdk_bgxx_gmp_pcs_sgmx_an_adv bdk_bgxx_gmp_pcs_sgmx_an_adv_t;
11356 
11357 static inline uint64_t BDK_BGXX_GMP_PCS_SGMX_AN_ADV(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_SGMX_AN_ADV(unsigned long a,unsigned long b)11358 static inline uint64_t BDK_BGXX_GMP_PCS_SGMX_AN_ADV(unsigned long a, unsigned long b)
11359 {
11360     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11361         return 0x87e0e0030068ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11362     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11363         return 0x87e0e0030068ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11364     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11365         return 0x87e0e0030068ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11366     __bdk_csr_fatal("BGXX_GMP_PCS_SGMX_AN_ADV", 2, a, b, 0, 0);
11367 }
11368 
11369 #define typedef_BDK_BGXX_GMP_PCS_SGMX_AN_ADV(a,b) bdk_bgxx_gmp_pcs_sgmx_an_adv_t
11370 #define bustype_BDK_BGXX_GMP_PCS_SGMX_AN_ADV(a,b) BDK_CSR_TYPE_RSL
11371 #define basename_BDK_BGXX_GMP_PCS_SGMX_AN_ADV(a,b) "BGXX_GMP_PCS_SGMX_AN_ADV"
11372 #define device_bar_BDK_BGXX_GMP_PCS_SGMX_AN_ADV(a,b) 0x0 /* PF_BAR0 */
11373 #define busnum_BDK_BGXX_GMP_PCS_SGMX_AN_ADV(a,b) (a)
11374 #define arguments_BDK_BGXX_GMP_PCS_SGMX_AN_ADV(a,b) (a),(b),-1,-1
11375 
11376 /**
11377  * Register (RSL) bgx#_gmp_pcs_sgm#_lp_adv
11378  *
11379  * BGX GMP PCS SGMII Link-Partner-Advertisement Registers
11380  * This is the SGMII link partner advertisement register (received as rx_Config_Reg\<15:0\> as
11381  * defined in IEEE 802.3 clause 37).
11382  */
11383 union bdk_bgxx_gmp_pcs_sgmx_lp_adv
11384 {
11385     uint64_t u;
11386     struct bdk_bgxx_gmp_pcs_sgmx_lp_adv_s
11387     {
11388 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11389         uint64_t reserved_16_63        : 48;
11390         uint64_t link                  : 1;  /**< [ 15: 15](RO/H) Link status: 1 = Link up. 0 = Link down. */
11391         uint64_t reserved_13_14        : 2;
11392         uint64_t dup                   : 1;  /**< [ 12: 12](RO/H) Duplex mode: 1 = Full duplex, 0 = Half duplex. */
11393         uint64_t speed                 : 2;  /**< [ 11: 10](RO/H) Link speed:
11394                                                                  0x0 = 10 Mb/s.
11395                                                                  0x1 = 100 Mb/s.
11396                                                                  0x2 = 1000 Mb/s.
11397                                                                  0x3 = Reserved. */
11398         uint64_t reserved_1_9          : 9;
11399         uint64_t one                   : 1;  /**< [  0:  0](RO/H) Always set to match tx_Config_Reg\<0\> */
11400 #else /* Word 0 - Little Endian */
11401         uint64_t one                   : 1;  /**< [  0:  0](RO/H) Always set to match tx_Config_Reg\<0\> */
11402         uint64_t reserved_1_9          : 9;
11403         uint64_t speed                 : 2;  /**< [ 11: 10](RO/H) Link speed:
11404                                                                  0x0 = 10 Mb/s.
11405                                                                  0x1 = 100 Mb/s.
11406                                                                  0x2 = 1000 Mb/s.
11407                                                                  0x3 = Reserved. */
11408         uint64_t dup                   : 1;  /**< [ 12: 12](RO/H) Duplex mode: 1 = Full duplex, 0 = Half duplex. */
11409         uint64_t reserved_13_14        : 2;
11410         uint64_t link                  : 1;  /**< [ 15: 15](RO/H) Link status: 1 = Link up. 0 = Link down. */
11411         uint64_t reserved_16_63        : 48;
11412 #endif /* Word 0 - End */
11413     } s;
11414     struct bdk_bgxx_gmp_pcs_sgmx_lp_adv_cn
11415     {
11416 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11417         uint64_t reserved_16_63        : 48;
11418         uint64_t link                  : 1;  /**< [ 15: 15](RO/H) Link status: 1 = Link up. 0 = Link down. */
11419         uint64_t reserved_14           : 1;
11420         uint64_t reserved_13           : 1;
11421         uint64_t dup                   : 1;  /**< [ 12: 12](RO/H) Duplex mode: 1 = Full duplex, 0 = Half duplex. */
11422         uint64_t speed                 : 2;  /**< [ 11: 10](RO/H) Link speed:
11423                                                                  0x0 = 10 Mb/s.
11424                                                                  0x1 = 100 Mb/s.
11425                                                                  0x2 = 1000 Mb/s.
11426                                                                  0x3 = Reserved. */
11427         uint64_t reserved_1_9          : 9;
11428         uint64_t one                   : 1;  /**< [  0:  0](RO/H) Always set to match tx_Config_Reg\<0\> */
11429 #else /* Word 0 - Little Endian */
11430         uint64_t one                   : 1;  /**< [  0:  0](RO/H) Always set to match tx_Config_Reg\<0\> */
11431         uint64_t reserved_1_9          : 9;
11432         uint64_t speed                 : 2;  /**< [ 11: 10](RO/H) Link speed:
11433                                                                  0x0 = 10 Mb/s.
11434                                                                  0x1 = 100 Mb/s.
11435                                                                  0x2 = 1000 Mb/s.
11436                                                                  0x3 = Reserved. */
11437         uint64_t dup                   : 1;  /**< [ 12: 12](RO/H) Duplex mode: 1 = Full duplex, 0 = Half duplex. */
11438         uint64_t reserved_13           : 1;
11439         uint64_t reserved_14           : 1;
11440         uint64_t link                  : 1;  /**< [ 15: 15](RO/H) Link status: 1 = Link up. 0 = Link down. */
11441         uint64_t reserved_16_63        : 48;
11442 #endif /* Word 0 - End */
11443     } cn;
11444 };
11445 typedef union bdk_bgxx_gmp_pcs_sgmx_lp_adv bdk_bgxx_gmp_pcs_sgmx_lp_adv_t;
11446 
11447 static inline uint64_t BDK_BGXX_GMP_PCS_SGMX_LP_ADV(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_SGMX_LP_ADV(unsigned long a,unsigned long b)11448 static inline uint64_t BDK_BGXX_GMP_PCS_SGMX_LP_ADV(unsigned long a, unsigned long b)
11449 {
11450     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11451         return 0x87e0e0030070ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11452     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11453         return 0x87e0e0030070ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11454     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11455         return 0x87e0e0030070ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11456     __bdk_csr_fatal("BGXX_GMP_PCS_SGMX_LP_ADV", 2, a, b, 0, 0);
11457 }
11458 
11459 #define typedef_BDK_BGXX_GMP_PCS_SGMX_LP_ADV(a,b) bdk_bgxx_gmp_pcs_sgmx_lp_adv_t
11460 #define bustype_BDK_BGXX_GMP_PCS_SGMX_LP_ADV(a,b) BDK_CSR_TYPE_RSL
11461 #define basename_BDK_BGXX_GMP_PCS_SGMX_LP_ADV(a,b) "BGXX_GMP_PCS_SGMX_LP_ADV"
11462 #define device_bar_BDK_BGXX_GMP_PCS_SGMX_LP_ADV(a,b) 0x0 /* PF_BAR0 */
11463 #define busnum_BDK_BGXX_GMP_PCS_SGMX_LP_ADV(a,b) (a)
11464 #define arguments_BDK_BGXX_GMP_PCS_SGMX_LP_ADV(a,b) (a),(b),-1,-1
11465 
11466 /**
11467  * Register (RSL) bgx#_gmp_pcs_tx#_states
11468  *
11469  * BGX GMP PCS TX State-Machines States Registers
11470  */
11471 union bdk_bgxx_gmp_pcs_txx_states
11472 {
11473     uint64_t u;
11474     struct bdk_bgxx_gmp_pcs_txx_states_s
11475     {
11476 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11477         uint64_t reserved_7_63         : 57;
11478         uint64_t xmit                  : 2;  /**< [  6:  5](RO/H) 0x0 = Undefined.
11479                                                                  0x1 = Config.
11480                                                                  0x2 = Idle.
11481                                                                  0x3 = Data. */
11482         uint64_t tx_bad                : 1;  /**< [  4:  4](RO/H) Transmit state machine in an illegal state. */
11483         uint64_t ord_st                : 4;  /**< [  3:  0](RO/H) Transmit ordered set state-machine state. */
11484 #else /* Word 0 - Little Endian */
11485         uint64_t ord_st                : 4;  /**< [  3:  0](RO/H) Transmit ordered set state-machine state. */
11486         uint64_t tx_bad                : 1;  /**< [  4:  4](RO/H) Transmit state machine in an illegal state. */
11487         uint64_t xmit                  : 2;  /**< [  6:  5](RO/H) 0x0 = Undefined.
11488                                                                  0x1 = Config.
11489                                                                  0x2 = Idle.
11490                                                                  0x3 = Data. */
11491         uint64_t reserved_7_63         : 57;
11492 #endif /* Word 0 - End */
11493     } s;
11494     /* struct bdk_bgxx_gmp_pcs_txx_states_s cn; */
11495 };
11496 typedef union bdk_bgxx_gmp_pcs_txx_states bdk_bgxx_gmp_pcs_txx_states_t;
11497 
11498 static inline uint64_t BDK_BGXX_GMP_PCS_TXX_STATES(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_TXX_STATES(unsigned long a,unsigned long b)11499 static inline uint64_t BDK_BGXX_GMP_PCS_TXX_STATES(unsigned long a, unsigned long b)
11500 {
11501     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11502         return 0x87e0e0030060ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11503     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11504         return 0x87e0e0030060ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11505     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11506         return 0x87e0e0030060ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11507     __bdk_csr_fatal("BGXX_GMP_PCS_TXX_STATES", 2, a, b, 0, 0);
11508 }
11509 
11510 #define typedef_BDK_BGXX_GMP_PCS_TXX_STATES(a,b) bdk_bgxx_gmp_pcs_txx_states_t
11511 #define bustype_BDK_BGXX_GMP_PCS_TXX_STATES(a,b) BDK_CSR_TYPE_RSL
11512 #define basename_BDK_BGXX_GMP_PCS_TXX_STATES(a,b) "BGXX_GMP_PCS_TXX_STATES"
11513 #define device_bar_BDK_BGXX_GMP_PCS_TXX_STATES(a,b) 0x0 /* PF_BAR0 */
11514 #define busnum_BDK_BGXX_GMP_PCS_TXX_STATES(a,b) (a)
11515 #define arguments_BDK_BGXX_GMP_PCS_TXX_STATES(a,b) (a),(b),-1,-1
11516 
11517 /**
11518  * Register (RSL) bgx#_gmp_pcs_tx_rx#_polarity
11519  *
11520  * BGX GMP PCS TX/RX Polarity Registers
11521  * BGX()_GMP_PCS_TX_RX()_POLARITY[AUTORXPL] shows correct polarity needed on the link
11522  * receive path after code group synchronization is achieved.
11523  */
11524 union bdk_bgxx_gmp_pcs_tx_rxx_polarity
11525 {
11526     uint64_t u;
11527     struct bdk_bgxx_gmp_pcs_tx_rxx_polarity_s
11528     {
11529 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11530         uint64_t reserved_4_63         : 60;
11531         uint64_t rxovrd                : 1;  /**< [  3:  3](R/W) RX polarity override.
11532                                                                  0 = AUTORXPL determines polarity.
11533                                                                  1 = [RXPLRT] determines polarity. */
11534         uint64_t autorxpl              : 1;  /**< [  2:  2](RO/H) Auto RX polarity detected:
11535                                                                  0 = Normal polarity.
11536                                                                  1 = Inverted polarity.
11537 
11538                                                                  This bit always represents the correct RX polarity setting needed for successful RX path
11539                                                                  operation, once a successful code group sync is obtained. */
11540         uint64_t rxplrt                : 1;  /**< [  1:  1](R/W) RX polarity: 0 = Normal polarity, 1 = Inverted polarity. */
11541         uint64_t txplrt                : 1;  /**< [  0:  0](R/W) TX polarity: 0 = Normal polarity, 1 = Inverted polarity. */
11542 #else /* Word 0 - Little Endian */
11543         uint64_t txplrt                : 1;  /**< [  0:  0](R/W) TX polarity: 0 = Normal polarity, 1 = Inverted polarity. */
11544         uint64_t rxplrt                : 1;  /**< [  1:  1](R/W) RX polarity: 0 = Normal polarity, 1 = Inverted polarity. */
11545         uint64_t autorxpl              : 1;  /**< [  2:  2](RO/H) Auto RX polarity detected:
11546                                                                  0 = Normal polarity.
11547                                                                  1 = Inverted polarity.
11548 
11549                                                                  This bit always represents the correct RX polarity setting needed for successful RX path
11550                                                                  operation, once a successful code group sync is obtained. */
11551         uint64_t rxovrd                : 1;  /**< [  3:  3](R/W) RX polarity override.
11552                                                                  0 = AUTORXPL determines polarity.
11553                                                                  1 = [RXPLRT] determines polarity. */
11554         uint64_t reserved_4_63         : 60;
11555 #endif /* Word 0 - End */
11556     } s;
11557     /* struct bdk_bgxx_gmp_pcs_tx_rxx_polarity_s cn; */
11558 };
11559 typedef union bdk_bgxx_gmp_pcs_tx_rxx_polarity bdk_bgxx_gmp_pcs_tx_rxx_polarity_t;
11560 
11561 static inline uint64_t BDK_BGXX_GMP_PCS_TX_RXX_POLARITY(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_GMP_PCS_TX_RXX_POLARITY(unsigned long a,unsigned long b)11562 static inline uint64_t BDK_BGXX_GMP_PCS_TX_RXX_POLARITY(unsigned long a, unsigned long b)
11563 {
11564     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11565         return 0x87e0e0030048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11566     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11567         return 0x87e0e0030048ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11568     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11569         return 0x87e0e0030048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11570     __bdk_csr_fatal("BGXX_GMP_PCS_TX_RXX_POLARITY", 2, a, b, 0, 0);
11571 }
11572 
11573 #define typedef_BDK_BGXX_GMP_PCS_TX_RXX_POLARITY(a,b) bdk_bgxx_gmp_pcs_tx_rxx_polarity_t
11574 #define bustype_BDK_BGXX_GMP_PCS_TX_RXX_POLARITY(a,b) BDK_CSR_TYPE_RSL
11575 #define basename_BDK_BGXX_GMP_PCS_TX_RXX_POLARITY(a,b) "BGXX_GMP_PCS_TX_RXX_POLARITY"
11576 #define device_bar_BDK_BGXX_GMP_PCS_TX_RXX_POLARITY(a,b) 0x0 /* PF_BAR0 */
11577 #define busnum_BDK_BGXX_GMP_PCS_TX_RXX_POLARITY(a,b) (a)
11578 #define arguments_BDK_BGXX_GMP_PCS_TX_RXX_POLARITY(a,b) (a),(b),-1,-1
11579 
11580 /**
11581  * Register (RSL) bgx#_msix_pba#
11582  *
11583  * BGX MSI-X Pending Bit Array Registers
11584  * This register is the MSI-X PBA table, the bit number is indexed by the BGX_INT_VEC_E
11585  * enumeration.
11586  */
11587 union bdk_bgxx_msix_pbax
11588 {
11589     uint64_t u;
11590     struct bdk_bgxx_msix_pbax_s
11591     {
11592 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11593         uint64_t pend                  : 64; /**< [ 63:  0](RO/H) Pending message for the associated BGX()_MSIX_VEC()_CTL, enumerated by BGX_INT_VEC_E.
11594                                                                  Bits that have no associated BGX_INT_VEC_E are zero. */
11595 #else /* Word 0 - Little Endian */
11596         uint64_t pend                  : 64; /**< [ 63:  0](RO/H) Pending message for the associated BGX()_MSIX_VEC()_CTL, enumerated by BGX_INT_VEC_E.
11597                                                                  Bits that have no associated BGX_INT_VEC_E are zero. */
11598 #endif /* Word 0 - End */
11599     } s;
11600     /* struct bdk_bgxx_msix_pbax_s cn; */
11601 };
11602 typedef union bdk_bgxx_msix_pbax bdk_bgxx_msix_pbax_t;
11603 
11604 static inline uint64_t BDK_BGXX_MSIX_PBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_MSIX_PBAX(unsigned long a,unsigned long b)11605 static inline uint64_t BDK_BGXX_MSIX_PBAX(unsigned long a, unsigned long b)
11606 {
11607     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b==0)))
11608         return 0x87e0e04f0000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
11609     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b==0)))
11610         return 0x87e0e04f0000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x0);
11611     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b==0)))
11612         return 0x87e0e04f0000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
11613     __bdk_csr_fatal("BGXX_MSIX_PBAX", 2, a, b, 0, 0);
11614 }
11615 
11616 #define typedef_BDK_BGXX_MSIX_PBAX(a,b) bdk_bgxx_msix_pbax_t
11617 #define bustype_BDK_BGXX_MSIX_PBAX(a,b) BDK_CSR_TYPE_RSL
11618 #define basename_BDK_BGXX_MSIX_PBAX(a,b) "BGXX_MSIX_PBAX"
11619 #define device_bar_BDK_BGXX_MSIX_PBAX(a,b) 0x4 /* PF_BAR4 */
11620 #define busnum_BDK_BGXX_MSIX_PBAX(a,b) (a)
11621 #define arguments_BDK_BGXX_MSIX_PBAX(a,b) (a),(b),-1,-1
11622 
11623 /**
11624  * Register (RSL) bgx#_msix_vec#_addr
11625  *
11626  * BGX MSI-X Vector Table Address Registers
11627  * This register is the MSI-X vector table, indexed by the BGX_INT_VEC_E enumeration.
11628  */
11629 union bdk_bgxx_msix_vecx_addr
11630 {
11631     uint64_t u;
11632     struct bdk_bgxx_msix_vecx_addr_s
11633     {
11634 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11635         uint64_t reserved_49_63        : 15;
11636         uint64_t addr                  : 47; /**< [ 48:  2](R/W) IOVA to use for MSI-X delivery of this vector. */
11637         uint64_t reserved_1            : 1;
11638         uint64_t secvec                : 1;  /**< [  0:  0](SR/W) Secure vector.
11639                                                                  0 = This vector may be read or written by either secure or nonsecure states.
11640                                                                  1 = This vector's BGX()_MSIX_VEC()_ADDR, BGX()_MSIX_VEC()_CTL, and corresponding
11641                                                                  bit of BGX()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
11642                                                                  by the nonsecure world.
11643 
11644                                                                  If PCCPF_BGX()_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
11645                                                                  is set, all vectors are secure and function as if [SECVEC] was set. */
11646 #else /* Word 0 - Little Endian */
11647         uint64_t secvec                : 1;  /**< [  0:  0](SR/W) Secure vector.
11648                                                                  0 = This vector may be read or written by either secure or nonsecure states.
11649                                                                  1 = This vector's BGX()_MSIX_VEC()_ADDR, BGX()_MSIX_VEC()_CTL, and corresponding
11650                                                                  bit of BGX()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
11651                                                                  by the nonsecure world.
11652 
11653                                                                  If PCCPF_BGX()_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
11654                                                                  is set, all vectors are secure and function as if [SECVEC] was set. */
11655         uint64_t reserved_1            : 1;
11656         uint64_t addr                  : 47; /**< [ 48:  2](R/W) IOVA to use for MSI-X delivery of this vector. */
11657         uint64_t reserved_49_63        : 15;
11658 #endif /* Word 0 - End */
11659     } s;
11660     /* struct bdk_bgxx_msix_vecx_addr_s cn; */
11661 };
11662 typedef union bdk_bgxx_msix_vecx_addr bdk_bgxx_msix_vecx_addr_t;
11663 
11664 static inline uint64_t BDK_BGXX_MSIX_VECX_ADDR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_MSIX_VECX_ADDR(unsigned long a,unsigned long b)11665 static inline uint64_t BDK_BGXX_MSIX_VECX_ADDR(unsigned long a, unsigned long b)
11666 {
11667     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=29)))
11668         return 0x87e0e0400000ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1f);
11669     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=29)))
11670         return 0x87e0e0400000ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x1f);
11671     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=29)))
11672         return 0x87e0e0400000ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1f);
11673     __bdk_csr_fatal("BGXX_MSIX_VECX_ADDR", 2, a, b, 0, 0);
11674 }
11675 
11676 #define typedef_BDK_BGXX_MSIX_VECX_ADDR(a,b) bdk_bgxx_msix_vecx_addr_t
11677 #define bustype_BDK_BGXX_MSIX_VECX_ADDR(a,b) BDK_CSR_TYPE_RSL
11678 #define basename_BDK_BGXX_MSIX_VECX_ADDR(a,b) "BGXX_MSIX_VECX_ADDR"
11679 #define device_bar_BDK_BGXX_MSIX_VECX_ADDR(a,b) 0x4 /* PF_BAR4 */
11680 #define busnum_BDK_BGXX_MSIX_VECX_ADDR(a,b) (a)
11681 #define arguments_BDK_BGXX_MSIX_VECX_ADDR(a,b) (a),(b),-1,-1
11682 
11683 /**
11684  * Register (RSL) bgx#_msix_vec#_ctl
11685  *
11686  * BGX MSI-X Vector Table Control and Data Registers
11687  * This register is the MSI-X vector table, indexed by the BGX_INT_VEC_E enumeration.
11688  */
11689 union bdk_bgxx_msix_vecx_ctl
11690 {
11691     uint64_t u;
11692     struct bdk_bgxx_msix_vecx_ctl_s
11693     {
11694 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11695         uint64_t reserved_33_63        : 31;
11696         uint64_t mask                  : 1;  /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
11697         uint64_t reserved_20_31        : 12;
11698         uint64_t data                  : 20; /**< [ 19:  0](R/W) Data to use for MSI-X delivery of this vector. */
11699 #else /* Word 0 - Little Endian */
11700         uint64_t data                  : 20; /**< [ 19:  0](R/W) Data to use for MSI-X delivery of this vector. */
11701         uint64_t reserved_20_31        : 12;
11702         uint64_t mask                  : 1;  /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
11703         uint64_t reserved_33_63        : 31;
11704 #endif /* Word 0 - End */
11705     } s;
11706     /* struct bdk_bgxx_msix_vecx_ctl_s cn; */
11707 };
11708 typedef union bdk_bgxx_msix_vecx_ctl bdk_bgxx_msix_vecx_ctl_t;
11709 
11710 static inline uint64_t BDK_BGXX_MSIX_VECX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_MSIX_VECX_CTL(unsigned long a,unsigned long b)11711 static inline uint64_t BDK_BGXX_MSIX_VECX_CTL(unsigned long a, unsigned long b)
11712 {
11713     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=29)))
11714         return 0x87e0e0400008ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1f);
11715     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=29)))
11716         return 0x87e0e0400008ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x1f);
11717     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=29)))
11718         return 0x87e0e0400008ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x1f);
11719     __bdk_csr_fatal("BGXX_MSIX_VECX_CTL", 2, a, b, 0, 0);
11720 }
11721 
11722 #define typedef_BDK_BGXX_MSIX_VECX_CTL(a,b) bdk_bgxx_msix_vecx_ctl_t
11723 #define bustype_BDK_BGXX_MSIX_VECX_CTL(a,b) BDK_CSR_TYPE_RSL
11724 #define basename_BDK_BGXX_MSIX_VECX_CTL(a,b) "BGXX_MSIX_VECX_CTL"
11725 #define device_bar_BDK_BGXX_MSIX_VECX_CTL(a,b) 0x4 /* PF_BAR4 */
11726 #define busnum_BDK_BGXX_MSIX_VECX_CTL(a,b) (a)
11727 #define arguments_BDK_BGXX_MSIX_VECX_CTL(a,b) (a),(b),-1,-1
11728 
11729 /**
11730  * Register (RSL) bgx#_smu#_cbfc_ctl
11731  *
11732  * BGX SMU PFC Control Registers
11733  * Internal:
11734  * INTERNAL: XOFF for a specific class/channel \<i\> is XOFF\<i\> = ([PHYS_EN]\<i\> & cmr_rx_phys_bp) |
11735  * ([LOGL_EN]\<i\> & cmr_rx_logl_xoff\<i\>).
11736  */
11737 union bdk_bgxx_smux_cbfc_ctl
11738 {
11739     uint64_t u;
11740     struct bdk_bgxx_smux_cbfc_ctl_s
11741     {
11742 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11743         uint64_t phys_en               : 16; /**< [ 63: 48](R/W) Physical backpressure enable. Determines which classes/channels in the class enable vector
11744                                                                  field of a transmitted PFC packet can be asserted due to RX physical backpressure. */
11745         uint64_t logl_en               : 16; /**< [ 47: 32](R/W) Logical backpressure enable. Determines which classes/channels in the class enable vector
11746                                                                  field of a transmitted PFC packet can be asserted due to RX logical backpressure. */
11747         uint64_t reserved_4_31         : 28;
11748         uint64_t bck_en                : 1;  /**< [  3:  3](R/W) Forward PFC information to the backpressure block. */
11749         uint64_t drp_en                : 1;  /**< [  2:  2](R/W) Drop-control enable. When set, drop PFC frames. */
11750         uint64_t tx_en                 : 1;  /**< [  1:  1](R/W) Transmit enable. When set, allow for PFC packets. Must be clear in HiGig2 mode
11751                                                                  i.e. when BGX()_SMU()_TX_CTL[HG_EN] = 1 and BGX()_SMU()_RX_UDD_SKP[LEN] =
11752                                                                  16. */
11753         uint64_t rx_en                 : 1;  /**< [  0:  0](R/W) Receive enable. When set, allow for PFC packets. Must be clear in HiGig2 mode
11754                                                                  i.e. when BGX()_SMU()_TX_CTL[HG_EN] = 1 and BGX()_SMU()_RX_UDD_SKP[LEN] =
11755                                                                  16. */
11756 #else /* Word 0 - Little Endian */
11757         uint64_t rx_en                 : 1;  /**< [  0:  0](R/W) Receive enable. When set, allow for PFC packets. Must be clear in HiGig2 mode
11758                                                                  i.e. when BGX()_SMU()_TX_CTL[HG_EN] = 1 and BGX()_SMU()_RX_UDD_SKP[LEN] =
11759                                                                  16. */
11760         uint64_t tx_en                 : 1;  /**< [  1:  1](R/W) Transmit enable. When set, allow for PFC packets. Must be clear in HiGig2 mode
11761                                                                  i.e. when BGX()_SMU()_TX_CTL[HG_EN] = 1 and BGX()_SMU()_RX_UDD_SKP[LEN] =
11762                                                                  16. */
11763         uint64_t drp_en                : 1;  /**< [  2:  2](R/W) Drop-control enable. When set, drop PFC frames. */
11764         uint64_t bck_en                : 1;  /**< [  3:  3](R/W) Forward PFC information to the backpressure block. */
11765         uint64_t reserved_4_31         : 28;
11766         uint64_t logl_en               : 16; /**< [ 47: 32](R/W) Logical backpressure enable. Determines which classes/channels in the class enable vector
11767                                                                  field of a transmitted PFC packet can be asserted due to RX logical backpressure. */
11768         uint64_t phys_en               : 16; /**< [ 63: 48](R/W) Physical backpressure enable. Determines which classes/channels in the class enable vector
11769                                                                  field of a transmitted PFC packet can be asserted due to RX physical backpressure. */
11770 #endif /* Word 0 - End */
11771     } s;
11772     /* struct bdk_bgxx_smux_cbfc_ctl_s cn; */
11773 };
11774 typedef union bdk_bgxx_smux_cbfc_ctl bdk_bgxx_smux_cbfc_ctl_t;
11775 
11776 static inline uint64_t BDK_BGXX_SMUX_CBFC_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_CBFC_CTL(unsigned long a,unsigned long b)11777 static inline uint64_t BDK_BGXX_SMUX_CBFC_CTL(unsigned long a, unsigned long b)
11778 {
11779     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11780         return 0x87e0e0020218ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11781     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11782         return 0x87e0e0020218ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11783     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11784         return 0x87e0e0020218ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11785     __bdk_csr_fatal("BGXX_SMUX_CBFC_CTL", 2, a, b, 0, 0);
11786 }
11787 
11788 #define typedef_BDK_BGXX_SMUX_CBFC_CTL(a,b) bdk_bgxx_smux_cbfc_ctl_t
11789 #define bustype_BDK_BGXX_SMUX_CBFC_CTL(a,b) BDK_CSR_TYPE_RSL
11790 #define basename_BDK_BGXX_SMUX_CBFC_CTL(a,b) "BGXX_SMUX_CBFC_CTL"
11791 #define device_bar_BDK_BGXX_SMUX_CBFC_CTL(a,b) 0x0 /* PF_BAR0 */
11792 #define busnum_BDK_BGXX_SMUX_CBFC_CTL(a,b) (a)
11793 #define arguments_BDK_BGXX_SMUX_CBFC_CTL(a,b) (a),(b),-1,-1
11794 
11795 /**
11796  * Register (RSL) bgx#_smu#_ctrl
11797  *
11798  * BGX SMU Control Registers
11799  */
11800 union bdk_bgxx_smux_ctrl
11801 {
11802     uint64_t u;
11803     struct bdk_bgxx_smux_ctrl_s
11804     {
11805 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11806         uint64_t reserved_2_63         : 62;
11807         uint64_t tx_idle               : 1;  /**< [  1:  1](RO/H) TX machine is idle. This indication pertains to the framer FSM and ignores the effects on
11808                                                                  the data-path controls or values which occur when BGX()_SMU()_TX_CTL[LS_BYP] is
11809                                                                  set. */
11810         uint64_t rx_idle               : 1;  /**< [  0:  0](RO/H) RX machine is idle. */
11811 #else /* Word 0 - Little Endian */
11812         uint64_t rx_idle               : 1;  /**< [  0:  0](RO/H) RX machine is idle. */
11813         uint64_t tx_idle               : 1;  /**< [  1:  1](RO/H) TX machine is idle. This indication pertains to the framer FSM and ignores the effects on
11814                                                                  the data-path controls or values which occur when BGX()_SMU()_TX_CTL[LS_BYP] is
11815                                                                  set. */
11816         uint64_t reserved_2_63         : 62;
11817 #endif /* Word 0 - End */
11818     } s;
11819     /* struct bdk_bgxx_smux_ctrl_s cn; */
11820 };
11821 typedef union bdk_bgxx_smux_ctrl bdk_bgxx_smux_ctrl_t;
11822 
11823 static inline uint64_t BDK_BGXX_SMUX_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_CTRL(unsigned long a,unsigned long b)11824 static inline uint64_t BDK_BGXX_SMUX_CTRL(unsigned long a, unsigned long b)
11825 {
11826     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11827         return 0x87e0e0020200ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11828     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11829         return 0x87e0e0020200ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11830     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11831         return 0x87e0e0020200ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11832     __bdk_csr_fatal("BGXX_SMUX_CTRL", 2, a, b, 0, 0);
11833 }
11834 
11835 #define typedef_BDK_BGXX_SMUX_CTRL(a,b) bdk_bgxx_smux_ctrl_t
11836 #define bustype_BDK_BGXX_SMUX_CTRL(a,b) BDK_CSR_TYPE_RSL
11837 #define basename_BDK_BGXX_SMUX_CTRL(a,b) "BGXX_SMUX_CTRL"
11838 #define device_bar_BDK_BGXX_SMUX_CTRL(a,b) 0x0 /* PF_BAR0 */
11839 #define busnum_BDK_BGXX_SMUX_CTRL(a,b) (a)
11840 #define arguments_BDK_BGXX_SMUX_CTRL(a,b) (a),(b),-1,-1
11841 
11842 /**
11843  * Register (RSL) bgx#_smu#_ext_loopback
11844  *
11845  * BGX SMU External Loopback Registers
11846  * In loopback mode, the IFG1+IFG2 of local and remote parties must match exactly; otherwise one
11847  * of the two sides' loopback FIFO will overrun: BGX()_SMU()_TX_INT[LB_OVRFLW].
11848  */
11849 union bdk_bgxx_smux_ext_loopback
11850 {
11851     uint64_t u;
11852     struct bdk_bgxx_smux_ext_loopback_s
11853     {
11854 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11855         uint64_t reserved_5_63         : 59;
11856         uint64_t en                    : 1;  /**< [  4:  4](R/W) Loopback enable. Puts the packet interface in external loopback mode where the RX lines
11857                                                                  are reflected on the TX lines. */
11858         uint64_t thresh                : 4;  /**< [  3:  0](R/W) Threshold on the TX FIFO. Software must only write the typical value. Any other value
11859                                                                  causes loopback mode not to function correctly. */
11860 #else /* Word 0 - Little Endian */
11861         uint64_t thresh                : 4;  /**< [  3:  0](R/W) Threshold on the TX FIFO. Software must only write the typical value. Any other value
11862                                                                  causes loopback mode not to function correctly. */
11863         uint64_t en                    : 1;  /**< [  4:  4](R/W) Loopback enable. Puts the packet interface in external loopback mode where the RX lines
11864                                                                  are reflected on the TX lines. */
11865         uint64_t reserved_5_63         : 59;
11866 #endif /* Word 0 - End */
11867     } s;
11868     /* struct bdk_bgxx_smux_ext_loopback_s cn; */
11869 };
11870 typedef union bdk_bgxx_smux_ext_loopback bdk_bgxx_smux_ext_loopback_t;
11871 
11872 static inline uint64_t BDK_BGXX_SMUX_EXT_LOOPBACK(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_EXT_LOOPBACK(unsigned long a,unsigned long b)11873 static inline uint64_t BDK_BGXX_SMUX_EXT_LOOPBACK(unsigned long a, unsigned long b)
11874 {
11875     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11876         return 0x87e0e0020208ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11877     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11878         return 0x87e0e0020208ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11879     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11880         return 0x87e0e0020208ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11881     __bdk_csr_fatal("BGXX_SMUX_EXT_LOOPBACK", 2, a, b, 0, 0);
11882 }
11883 
11884 #define typedef_BDK_BGXX_SMUX_EXT_LOOPBACK(a,b) bdk_bgxx_smux_ext_loopback_t
11885 #define bustype_BDK_BGXX_SMUX_EXT_LOOPBACK(a,b) BDK_CSR_TYPE_RSL
11886 #define basename_BDK_BGXX_SMUX_EXT_LOOPBACK(a,b) "BGXX_SMUX_EXT_LOOPBACK"
11887 #define device_bar_BDK_BGXX_SMUX_EXT_LOOPBACK(a,b) 0x0 /* PF_BAR0 */
11888 #define busnum_BDK_BGXX_SMUX_EXT_LOOPBACK(a,b) (a)
11889 #define arguments_BDK_BGXX_SMUX_EXT_LOOPBACK(a,b) (a),(b),-1,-1
11890 
11891 /**
11892  * Register (RSL) bgx#_smu#_hg2_control
11893  *
11894  * BGX SMU HiGig2 Control Registers
11895  * HiGig2 TX- and RX-enable are normally set together for HiGig2 messaging. Setting just the TX
11896  * or RX bit results in only the HG2 message transmit or receive capability.
11897  *
11898  * Setting [PHYS_EN] and [LOGL_EN] to 1 allows link PAUSE or backpressure to TNS/NIC as per the
11899  * received HiGig2 message. Setting these fields to 0 disables link PAUSE and backpressure to
11900  * TNS/NIC
11901  * in response to received messages.
11902  *
11903  * BGX()_SMU()_TX_CTL[HG_EN] must be set (to enable HiGig) whenever either [HG2TX_EN] or
11904  * [HG2RX_EN] are set. BGX()_SMU()_RX_UDD_SKP[LEN] must be set to 16 (to select HiGig2)
11905  * whenever either [HG2TX_EN] or [HG2RX_EN] are set.
11906  *
11907  * BGX()_CMR_RX_OVR_BP[EN]\<0\> must be set and BGX()_CMR_RX_OVR_BP[BP]\<0\> must be cleared
11908  * to 0 (to forcibly disable hardware-automatic 802.3 PAUSE packet generation) with the HiGig2
11909  * Protocol when [HG2TX_EN] = 0. (The HiGig2 protocol is indicated
11910  * by BGX()_SMU()_TX_CTL[HG_EN] = 1 and BGX()_SMU()_RX_UDD_SKP[LEN]=16.) Hardware
11911  * can only autogenerate backpressure via HiGig2 messages (optionally, when [HG2TX_EN] = 1) with
11912  * the HiGig2 protocol.
11913  */
11914 union bdk_bgxx_smux_hg2_control
11915 {
11916     uint64_t u;
11917     struct bdk_bgxx_smux_hg2_control_s
11918     {
11919 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11920         uint64_t reserved_19_63        : 45;
11921         uint64_t hg2tx_en              : 1;  /**< [ 18: 18](R/W) Enable transmission of HG2 physical and logical messages. When set, also disables hardware
11922                                                                  autogenerated 802.3 PAUSE and PFC frames. (CNXXXX cannot generate proper 802.3 or
11923                                                                  PFC frames in HiGig2 mode.) */
11924         uint64_t hg2rx_en              : 1;  /**< [ 17: 17](R/W) Enable extraction and processing of HG2 message packet from RX flow. Physical and logical
11925                                                                  PAUSE information is used to PAUSE physical-link, backpressure PKO. This field must be set
11926                                                                  when HiGig2 messages are present in the receive stream. This bit is also forwarded to CMR
11927                                                                  so it can generate the required deferring signals to SMU TX and backpressure signals to
11928                                                                  PKO. */
11929         uint64_t phys_en               : 1;  /**< [ 16: 16](R/W) Physical-link backpressure enable for received physical HiGig2 messages. This bit enables
11930                                                                  the SMU TX to CMR HG2 deferring counter to be set every time SMU RX receives and filters
11931                                                                  out a valid physical HG2 message. */
11932         uint64_t logl_en               : 16; /**< [ 15:  0](R/W) 16-bit logical-link backpressure enables for received HiGig2 messages or PFC packets. */
11933 #else /* Word 0 - Little Endian */
11934         uint64_t logl_en               : 16; /**< [ 15:  0](R/W) 16-bit logical-link backpressure enables for received HiGig2 messages or PFC packets. */
11935         uint64_t phys_en               : 1;  /**< [ 16: 16](R/W) Physical-link backpressure enable for received physical HiGig2 messages. This bit enables
11936                                                                  the SMU TX to CMR HG2 deferring counter to be set every time SMU RX receives and filters
11937                                                                  out a valid physical HG2 message. */
11938         uint64_t hg2rx_en              : 1;  /**< [ 17: 17](R/W) Enable extraction and processing of HG2 message packet from RX flow. Physical and logical
11939                                                                  PAUSE information is used to PAUSE physical-link, backpressure PKO. This field must be set
11940                                                                  when HiGig2 messages are present in the receive stream. This bit is also forwarded to CMR
11941                                                                  so it can generate the required deferring signals to SMU TX and backpressure signals to
11942                                                                  PKO. */
11943         uint64_t hg2tx_en              : 1;  /**< [ 18: 18](R/W) Enable transmission of HG2 physical and logical messages. When set, also disables hardware
11944                                                                  autogenerated 802.3 PAUSE and PFC frames. (CNXXXX cannot generate proper 802.3 or
11945                                                                  PFC frames in HiGig2 mode.) */
11946         uint64_t reserved_19_63        : 45;
11947 #endif /* Word 0 - End */
11948     } s;
11949     /* struct bdk_bgxx_smux_hg2_control_s cn81xx; */
11950     struct bdk_bgxx_smux_hg2_control_cn88xx
11951     {
11952 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11953         uint64_t reserved_19_63        : 45;
11954         uint64_t hg2tx_en              : 1;  /**< [ 18: 18](R/W) Enable transmission of HG2 physical and logical messages. When set, also disables hardware
11955                                                                  autogenerated 802.3 PAUSE and PFC frames. (CNXXXX cannot generate proper 802.3 or
11956                                                                  PFC frames in HiGig2 mode.) */
11957         uint64_t hg2rx_en              : 1;  /**< [ 17: 17](R/W) Enable extraction and processing of HG2 message packet from RX flow. Physical and logical
11958                                                                  PAUSE information is used to PAUSE physical-link, backpressure TNS/NIC. This field must be
11959                                                                  set
11960                                                                  when HiGig2 messages are present in the receive stream. This bit is also forwarded to CMR
11961                                                                  so it can generate the required deferring signals to SMU TX and backpressure signals to
11962                                                                  TNS/NIC. */
11963         uint64_t phys_en               : 1;  /**< [ 16: 16](R/W) Physical-link backpressure enable for received physical HiGig2 messages. This bit enables
11964                                                                  the SMU TX to CMR HG2 deferring counter to be set every time SMU RX receives and filters
11965                                                                  out a valid physical HG2 message. */
11966         uint64_t logl_en               : 16; /**< [ 15:  0](R/W) 16-bit logical-link backpressure enables for received HiGig2 messages or PFC packets. */
11967 #else /* Word 0 - Little Endian */
11968         uint64_t logl_en               : 16; /**< [ 15:  0](R/W) 16-bit logical-link backpressure enables for received HiGig2 messages or PFC packets. */
11969         uint64_t phys_en               : 1;  /**< [ 16: 16](R/W) Physical-link backpressure enable for received physical HiGig2 messages. This bit enables
11970                                                                  the SMU TX to CMR HG2 deferring counter to be set every time SMU RX receives and filters
11971                                                                  out a valid physical HG2 message. */
11972         uint64_t hg2rx_en              : 1;  /**< [ 17: 17](R/W) Enable extraction and processing of HG2 message packet from RX flow. Physical and logical
11973                                                                  PAUSE information is used to PAUSE physical-link, backpressure TNS/NIC. This field must be
11974                                                                  set
11975                                                                  when HiGig2 messages are present in the receive stream. This bit is also forwarded to CMR
11976                                                                  so it can generate the required deferring signals to SMU TX and backpressure signals to
11977                                                                  TNS/NIC. */
11978         uint64_t hg2tx_en              : 1;  /**< [ 18: 18](R/W) Enable transmission of HG2 physical and logical messages. When set, also disables hardware
11979                                                                  autogenerated 802.3 PAUSE and PFC frames. (CNXXXX cannot generate proper 802.3 or
11980                                                                  PFC frames in HiGig2 mode.) */
11981         uint64_t reserved_19_63        : 45;
11982 #endif /* Word 0 - End */
11983     } cn88xx;
11984     /* struct bdk_bgxx_smux_hg2_control_s cn83xx; */
11985 };
11986 typedef union bdk_bgxx_smux_hg2_control bdk_bgxx_smux_hg2_control_t;
11987 
11988 static inline uint64_t BDK_BGXX_SMUX_HG2_CONTROL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_HG2_CONTROL(unsigned long a,unsigned long b)11989 static inline uint64_t BDK_BGXX_SMUX_HG2_CONTROL(unsigned long a, unsigned long b)
11990 {
11991     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
11992         return 0x87e0e0020210ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11993     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
11994         return 0x87e0e0020210ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
11995     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
11996         return 0x87e0e0020210ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
11997     __bdk_csr_fatal("BGXX_SMUX_HG2_CONTROL", 2, a, b, 0, 0);
11998 }
11999 
12000 #define typedef_BDK_BGXX_SMUX_HG2_CONTROL(a,b) bdk_bgxx_smux_hg2_control_t
12001 #define bustype_BDK_BGXX_SMUX_HG2_CONTROL(a,b) BDK_CSR_TYPE_RSL
12002 #define basename_BDK_BGXX_SMUX_HG2_CONTROL(a,b) "BGXX_SMUX_HG2_CONTROL"
12003 #define device_bar_BDK_BGXX_SMUX_HG2_CONTROL(a,b) 0x0 /* PF_BAR0 */
12004 #define busnum_BDK_BGXX_SMUX_HG2_CONTROL(a,b) (a)
12005 #define arguments_BDK_BGXX_SMUX_HG2_CONTROL(a,b) (a),(b),-1,-1
12006 
12007 /**
12008  * Register (RSL) bgx#_smu#_rx_bad_col_hi
12009  *
12010  * BGX SMU RX Bad Column High Registers
12011  */
12012 union bdk_bgxx_smux_rx_bad_col_hi
12013 {
12014     uint64_t u;
12015     struct bdk_bgxx_smux_rx_bad_col_hi_s
12016     {
12017 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12018         uint64_t reserved_17_63        : 47;
12019         uint64_t val                   : 1;  /**< [ 16: 16](R/W1C/H) Set when BGX()_SMU()_RX_INT[PCTERR] is set. */
12020         uint64_t state                 : 8;  /**< [ 15:  8](RO/H) When BGX()_SMU()_RX_INT[PCTERR] is set, contains the receive state at the time of
12021                                                                  the error. */
12022         uint64_t lane_rxc              : 8;  /**< [  7:  0](RO/H) When BGX()_SMU()_RX_INT[PCTERR] is set, contains the column at the time of the error. */
12023 #else /* Word 0 - Little Endian */
12024         uint64_t lane_rxc              : 8;  /**< [  7:  0](RO/H) When BGX()_SMU()_RX_INT[PCTERR] is set, contains the column at the time of the error. */
12025         uint64_t state                 : 8;  /**< [ 15:  8](RO/H) When BGX()_SMU()_RX_INT[PCTERR] is set, contains the receive state at the time of
12026                                                                  the error. */
12027         uint64_t val                   : 1;  /**< [ 16: 16](R/W1C/H) Set when BGX()_SMU()_RX_INT[PCTERR] is set. */
12028         uint64_t reserved_17_63        : 47;
12029 #endif /* Word 0 - End */
12030     } s;
12031     /* struct bdk_bgxx_smux_rx_bad_col_hi_s cn; */
12032 };
12033 typedef union bdk_bgxx_smux_rx_bad_col_hi bdk_bgxx_smux_rx_bad_col_hi_t;
12034 
12035 static inline uint64_t BDK_BGXX_SMUX_RX_BAD_COL_HI(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_BAD_COL_HI(unsigned long a,unsigned long b)12036 static inline uint64_t BDK_BGXX_SMUX_RX_BAD_COL_HI(unsigned long a, unsigned long b)
12037 {
12038     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12039         return 0x87e0e0020058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12040     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12041         return 0x87e0e0020058ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12042     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12043         return 0x87e0e0020058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12044     __bdk_csr_fatal("BGXX_SMUX_RX_BAD_COL_HI", 2, a, b, 0, 0);
12045 }
12046 
12047 #define typedef_BDK_BGXX_SMUX_RX_BAD_COL_HI(a,b) bdk_bgxx_smux_rx_bad_col_hi_t
12048 #define bustype_BDK_BGXX_SMUX_RX_BAD_COL_HI(a,b) BDK_CSR_TYPE_RSL
12049 #define basename_BDK_BGXX_SMUX_RX_BAD_COL_HI(a,b) "BGXX_SMUX_RX_BAD_COL_HI"
12050 #define device_bar_BDK_BGXX_SMUX_RX_BAD_COL_HI(a,b) 0x0 /* PF_BAR0 */
12051 #define busnum_BDK_BGXX_SMUX_RX_BAD_COL_HI(a,b) (a)
12052 #define arguments_BDK_BGXX_SMUX_RX_BAD_COL_HI(a,b) (a),(b),-1,-1
12053 
12054 /**
12055  * Register (RSL) bgx#_smu#_rx_bad_col_lo
12056  *
12057  * BGX SMU RX Bad Column Low Registers
12058  */
12059 union bdk_bgxx_smux_rx_bad_col_lo
12060 {
12061     uint64_t u;
12062     struct bdk_bgxx_smux_rx_bad_col_lo_s
12063     {
12064 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12065         uint64_t lane_rxd              : 64; /**< [ 63:  0](RO/H) When BGX()_SMU()_RX_INT[PCTERR] is set, [LANE_RXD] contains the XAUI/RXAUI column at
12066                                                                  the time of the error. */
12067 #else /* Word 0 - Little Endian */
12068         uint64_t lane_rxd              : 64; /**< [ 63:  0](RO/H) When BGX()_SMU()_RX_INT[PCTERR] is set, [LANE_RXD] contains the XAUI/RXAUI column at
12069                                                                  the time of the error. */
12070 #endif /* Word 0 - End */
12071     } s;
12072     /* struct bdk_bgxx_smux_rx_bad_col_lo_s cn; */
12073 };
12074 typedef union bdk_bgxx_smux_rx_bad_col_lo bdk_bgxx_smux_rx_bad_col_lo_t;
12075 
12076 static inline uint64_t BDK_BGXX_SMUX_RX_BAD_COL_LO(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_BAD_COL_LO(unsigned long a,unsigned long b)12077 static inline uint64_t BDK_BGXX_SMUX_RX_BAD_COL_LO(unsigned long a, unsigned long b)
12078 {
12079     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12080         return 0x87e0e0020050ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12081     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12082         return 0x87e0e0020050ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12083     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12084         return 0x87e0e0020050ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12085     __bdk_csr_fatal("BGXX_SMUX_RX_BAD_COL_LO", 2, a, b, 0, 0);
12086 }
12087 
12088 #define typedef_BDK_BGXX_SMUX_RX_BAD_COL_LO(a,b) bdk_bgxx_smux_rx_bad_col_lo_t
12089 #define bustype_BDK_BGXX_SMUX_RX_BAD_COL_LO(a,b) BDK_CSR_TYPE_RSL
12090 #define basename_BDK_BGXX_SMUX_RX_BAD_COL_LO(a,b) "BGXX_SMUX_RX_BAD_COL_LO"
12091 #define device_bar_BDK_BGXX_SMUX_RX_BAD_COL_LO(a,b) 0x0 /* PF_BAR0 */
12092 #define busnum_BDK_BGXX_SMUX_RX_BAD_COL_LO(a,b) (a)
12093 #define arguments_BDK_BGXX_SMUX_RX_BAD_COL_LO(a,b) (a),(b),-1,-1
12094 
12095 /**
12096  * Register (RSL) bgx#_smu#_rx_ctl
12097  *
12098  * BGX SMU RX Control Registers
12099  */
12100 union bdk_bgxx_smux_rx_ctl
12101 {
12102     uint64_t u;
12103     struct bdk_bgxx_smux_rx_ctl_s
12104     {
12105 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12106         uint64_t reserved_2_63         : 62;
12107         uint64_t status                : 2;  /**< [  1:  0](RO/H) Link status.
12108                                                                  0x0 = Link OK.
12109                                                                  0x1 = Local fault.
12110                                                                  0x2 = Remote fault.
12111                                                                  0x3 = Reserved. */
12112 #else /* Word 0 - Little Endian */
12113         uint64_t status                : 2;  /**< [  1:  0](RO/H) Link status.
12114                                                                  0x0 = Link OK.
12115                                                                  0x1 = Local fault.
12116                                                                  0x2 = Remote fault.
12117                                                                  0x3 = Reserved. */
12118         uint64_t reserved_2_63         : 62;
12119 #endif /* Word 0 - End */
12120     } s;
12121     /* struct bdk_bgxx_smux_rx_ctl_s cn; */
12122 };
12123 typedef union bdk_bgxx_smux_rx_ctl bdk_bgxx_smux_rx_ctl_t;
12124 
12125 static inline uint64_t BDK_BGXX_SMUX_RX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_CTL(unsigned long a,unsigned long b)12126 static inline uint64_t BDK_BGXX_SMUX_RX_CTL(unsigned long a, unsigned long b)
12127 {
12128     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12129         return 0x87e0e0020048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12130     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12131         return 0x87e0e0020048ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12132     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12133         return 0x87e0e0020048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12134     __bdk_csr_fatal("BGXX_SMUX_RX_CTL", 2, a, b, 0, 0);
12135 }
12136 
12137 #define typedef_BDK_BGXX_SMUX_RX_CTL(a,b) bdk_bgxx_smux_rx_ctl_t
12138 #define bustype_BDK_BGXX_SMUX_RX_CTL(a,b) BDK_CSR_TYPE_RSL
12139 #define basename_BDK_BGXX_SMUX_RX_CTL(a,b) "BGXX_SMUX_RX_CTL"
12140 #define device_bar_BDK_BGXX_SMUX_RX_CTL(a,b) 0x0 /* PF_BAR0 */
12141 #define busnum_BDK_BGXX_SMUX_RX_CTL(a,b) (a)
12142 #define arguments_BDK_BGXX_SMUX_RX_CTL(a,b) (a),(b),-1,-1
12143 
12144 /**
12145  * Register (RSL) bgx#_smu#_rx_decision
12146  *
12147  * BGX SMU Packet Decision Registers
12148  * This register specifies the byte count used to determine when to accept or to filter a packet.
12149  * As each byte in a packet is received by BGX, the L2 byte count (i.e. the number of bytes from
12150  * the beginning of the L2 header (DMAC)) is compared against CNT. In normal operation, the L2
12151  * header begins after the PREAMBLE + SFD (BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 1) and any
12152  * optional UDD skip data (BGX()_SMU()_RX_UDD_SKP[LEN]).
12153  */
12154 union bdk_bgxx_smux_rx_decision
12155 {
12156     uint64_t u;
12157     struct bdk_bgxx_smux_rx_decision_s
12158     {
12159 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12160         uint64_t reserved_5_63         : 59;
12161         uint64_t cnt                   : 5;  /**< [  4:  0](R/W) The byte count to decide when to accept or filter a packet. */
12162 #else /* Word 0 - Little Endian */
12163         uint64_t cnt                   : 5;  /**< [  4:  0](R/W) The byte count to decide when to accept or filter a packet. */
12164         uint64_t reserved_5_63         : 59;
12165 #endif /* Word 0 - End */
12166     } s;
12167     /* struct bdk_bgxx_smux_rx_decision_s cn; */
12168 };
12169 typedef union bdk_bgxx_smux_rx_decision bdk_bgxx_smux_rx_decision_t;
12170 
12171 static inline uint64_t BDK_BGXX_SMUX_RX_DECISION(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_DECISION(unsigned long a,unsigned long b)12172 static inline uint64_t BDK_BGXX_SMUX_RX_DECISION(unsigned long a, unsigned long b)
12173 {
12174     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12175         return 0x87e0e0020038ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12176     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12177         return 0x87e0e0020038ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12178     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12179         return 0x87e0e0020038ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12180     __bdk_csr_fatal("BGXX_SMUX_RX_DECISION", 2, a, b, 0, 0);
12181 }
12182 
12183 #define typedef_BDK_BGXX_SMUX_RX_DECISION(a,b) bdk_bgxx_smux_rx_decision_t
12184 #define bustype_BDK_BGXX_SMUX_RX_DECISION(a,b) BDK_CSR_TYPE_RSL
12185 #define basename_BDK_BGXX_SMUX_RX_DECISION(a,b) "BGXX_SMUX_RX_DECISION"
12186 #define device_bar_BDK_BGXX_SMUX_RX_DECISION(a,b) 0x0 /* PF_BAR0 */
12187 #define busnum_BDK_BGXX_SMUX_RX_DECISION(a,b) (a)
12188 #define arguments_BDK_BGXX_SMUX_RX_DECISION(a,b) (a),(b),-1,-1
12189 
12190 /**
12191  * Register (RSL) bgx#_smu#_rx_frm_chk
12192  *
12193  * BGX SMU RX Frame Check Registers
12194  * The CSRs provide the enable bits for a subset of errors passed to CMR encoded.
12195  */
12196 union bdk_bgxx_smux_rx_frm_chk
12197 {
12198     uint64_t u;
12199     struct bdk_bgxx_smux_rx_frm_chk_s
12200     {
12201 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12202         uint64_t reserved_9_63         : 55;
12203         uint64_t skperr                : 1;  /**< [  8:  8](R/W) Skipper error. */
12204         uint64_t rcverr                : 1;  /**< [  7:  7](R/W) Frame was received with data-reception error. */
12205         uint64_t reserved_6            : 1;
12206         uint64_t fcserr_c              : 1;  /**< [  5:  5](R/W) Control frame was received with FCS/CRC error. */
12207         uint64_t fcserr_d              : 1;  /**< [  4:  4](R/W) Data frame was received with FCS/CRC error. */
12208         uint64_t jabber                : 1;  /**< [  3:  3](R/W) Frame was received with length \> sys_length. */
12209         uint64_t reserved_0_2          : 3;
12210 #else /* Word 0 - Little Endian */
12211         uint64_t reserved_0_2          : 3;
12212         uint64_t jabber                : 1;  /**< [  3:  3](R/W) Frame was received with length \> sys_length. */
12213         uint64_t fcserr_d              : 1;  /**< [  4:  4](R/W) Data frame was received with FCS/CRC error. */
12214         uint64_t fcserr_c              : 1;  /**< [  5:  5](R/W) Control frame was received with FCS/CRC error. */
12215         uint64_t reserved_6            : 1;
12216         uint64_t rcverr                : 1;  /**< [  7:  7](R/W) Frame was received with data-reception error. */
12217         uint64_t skperr                : 1;  /**< [  8:  8](R/W) Skipper error. */
12218         uint64_t reserved_9_63         : 55;
12219 #endif /* Word 0 - End */
12220     } s;
12221     /* struct bdk_bgxx_smux_rx_frm_chk_s cn; */
12222 };
12223 typedef union bdk_bgxx_smux_rx_frm_chk bdk_bgxx_smux_rx_frm_chk_t;
12224 
12225 static inline uint64_t BDK_BGXX_SMUX_RX_FRM_CHK(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_FRM_CHK(unsigned long a,unsigned long b)12226 static inline uint64_t BDK_BGXX_SMUX_RX_FRM_CHK(unsigned long a, unsigned long b)
12227 {
12228     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12229         return 0x87e0e0020028ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12230     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12231         return 0x87e0e0020028ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12232     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12233         return 0x87e0e0020028ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12234     __bdk_csr_fatal("BGXX_SMUX_RX_FRM_CHK", 2, a, b, 0, 0);
12235 }
12236 
12237 #define typedef_BDK_BGXX_SMUX_RX_FRM_CHK(a,b) bdk_bgxx_smux_rx_frm_chk_t
12238 #define bustype_BDK_BGXX_SMUX_RX_FRM_CHK(a,b) BDK_CSR_TYPE_RSL
12239 #define basename_BDK_BGXX_SMUX_RX_FRM_CHK(a,b) "BGXX_SMUX_RX_FRM_CHK"
12240 #define device_bar_BDK_BGXX_SMUX_RX_FRM_CHK(a,b) 0x0 /* PF_BAR0 */
12241 #define busnum_BDK_BGXX_SMUX_RX_FRM_CHK(a,b) (a)
12242 #define arguments_BDK_BGXX_SMUX_RX_FRM_CHK(a,b) (a),(b),-1,-1
12243 
12244 /**
12245  * Register (RSL) bgx#_smu#_rx_frm_ctl
12246  *
12247  * BGX SMU RX Frame Control Registers
12248  * This register controls the handling of the frames.
12249  * The [CTL_BCK] and [CTL_DRP] bits control how the hardware handles incoming PAUSE packets. The
12250  * most
12251  * common modes of operation:
12252  * _ [CTL_BCK] = 1, [CTL_DRP] = 1: hardware handles everything
12253  * _ [CTL_BCK] = 0, [CTL_DRP] = 0: software sees all PAUSE frames
12254  * _ [CTL_BCK] = 0, [CTL_DRP] = 1: all PAUSE frames are completely ignored
12255  *
12256  * These control bits should be set to [CTL_BCK] = 0, [CTL_DRP] = 0 in half-duplex mode. Since
12257  * PAUSE
12258  * packets only apply to full duplex operation, any PAUSE packet would constitute an exception
12259  * which should be handled by the processing cores. PAUSE packets should not be forwarded.
12260  */
12261 union bdk_bgxx_smux_rx_frm_ctl
12262 {
12263     uint64_t u;
12264     struct bdk_bgxx_smux_rx_frm_ctl_s
12265     {
12266 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12267         uint64_t reserved_13_63        : 51;
12268         uint64_t ptp_mode              : 1;  /**< [ 12: 12](R/W) Timestamp mode. When [PTP_MODE] is set, a 64-bit timestamp is prepended to every incoming
12269                                                                  packet.
12270 
12271                                                                  The timestamp bytes are added to the packet in such a way as to not modify the packet's
12272                                                                  receive byte count. This implies that the BGX()_SMU()_RX_JABBER,
12273                                                                  BGX()_SMU()_RX_DECISION, and BGX()_SMU()_RX_UDD_SKP do not require any
12274                                                                  adjustment as they operate on the received packet size. When the packet reaches NIC, its
12275                                                                  size reflects the additional bytes. */
12276         uint64_t reserved_6_11         : 6;
12277         uint64_t ctl_smac              : 1;  /**< [  5:  5](R/W) Control PAUSE frames can match station SMAC. */
12278         uint64_t ctl_mcst              : 1;  /**< [  4:  4](R/W) Control PAUSE frames can match globally assigned multicast address. */
12279         uint64_t ctl_bck               : 1;  /**< [  3:  3](R/W) Forward PAUSE information to TX block. */
12280         uint64_t ctl_drp               : 1;  /**< [  2:  2](R/W) Drop control PAUSE frames. */
12281         uint64_t pre_strp              : 1;  /**< [  1:  1](R/W) Strip off the preamble (when present).
12282 
12283                                                                  0 = PREAMBLE + SFD is sent to core as part of frame.
12284                                                                  1 = PREAMBLE + SFD is dropped.
12285                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features.
12286 
12287                                                                  If [PTP_MODE] = 1 and [PRE_CHK] = 1, [PRE_STRP] must be 1.
12288 
12289                                                                  When [PRE_CHK] is set (indicating that the PREAMBLE will be sent), [PRE_STRP] determines
12290                                                                  if
12291                                                                  the PREAMBLE+SFD bytes are thrown away or sent to the core as part of the packet. In
12292                                                                  either mode, the PREAMBLE+SFD bytes are not counted toward the packet size when checking
12293                                                                  against the MIN and MAX bounds. Furthermore, the bytes are skipped when locating the start
12294                                                                  of the L2 header for DMAC and control frame recognition. */
12295         uint64_t pre_chk               : 1;  /**< [  0:  0](R/W) Check the preamble for correctness.
12296                                                                  This port is configured to send a valid 802.3 PREAMBLE to begin every frame. BGX checks
12297                                                                  that a valid PREAMBLE is received. When a problem does occur within
12298                                                                  the PREAMBLE sequence, the frame is marked as bad and not sent into the core. The
12299                                                                  BGX()_SMU()_RX_INT[PCTERR] interrupt is also raised.
12300 
12301                                                                  When BGX()_SMU()_TX_CTL[HG_EN] is set, [PRE_CHK] must be 0.
12302 
12303                                                                  If [PTP_MODE] = 1 and [PRE_CHK] = 1, [PRE_STRP] must be 1. */
12304 #else /* Word 0 - Little Endian */
12305         uint64_t pre_chk               : 1;  /**< [  0:  0](R/W) Check the preamble for correctness.
12306                                                                  This port is configured to send a valid 802.3 PREAMBLE to begin every frame. BGX checks
12307                                                                  that a valid PREAMBLE is received. When a problem does occur within
12308                                                                  the PREAMBLE sequence, the frame is marked as bad and not sent into the core. The
12309                                                                  BGX()_SMU()_RX_INT[PCTERR] interrupt is also raised.
12310 
12311                                                                  When BGX()_SMU()_TX_CTL[HG_EN] is set, [PRE_CHK] must be 0.
12312 
12313                                                                  If [PTP_MODE] = 1 and [PRE_CHK] = 1, [PRE_STRP] must be 1. */
12314         uint64_t pre_strp              : 1;  /**< [  1:  1](R/W) Strip off the preamble (when present).
12315 
12316                                                                  0 = PREAMBLE + SFD is sent to core as part of frame.
12317                                                                  1 = PREAMBLE + SFD is dropped.
12318                                                                  [PRE_CHK] must be set to enable this and all PREAMBLE features.
12319 
12320                                                                  If [PTP_MODE] = 1 and [PRE_CHK] = 1, [PRE_STRP] must be 1.
12321 
12322                                                                  When [PRE_CHK] is set (indicating that the PREAMBLE will be sent), [PRE_STRP] determines
12323                                                                  if
12324                                                                  the PREAMBLE+SFD bytes are thrown away or sent to the core as part of the packet. In
12325                                                                  either mode, the PREAMBLE+SFD bytes are not counted toward the packet size when checking
12326                                                                  against the MIN and MAX bounds. Furthermore, the bytes are skipped when locating the start
12327                                                                  of the L2 header for DMAC and control frame recognition. */
12328         uint64_t ctl_drp               : 1;  /**< [  2:  2](R/W) Drop control PAUSE frames. */
12329         uint64_t ctl_bck               : 1;  /**< [  3:  3](R/W) Forward PAUSE information to TX block. */
12330         uint64_t ctl_mcst              : 1;  /**< [  4:  4](R/W) Control PAUSE frames can match globally assigned multicast address. */
12331         uint64_t ctl_smac              : 1;  /**< [  5:  5](R/W) Control PAUSE frames can match station SMAC. */
12332         uint64_t reserved_6_11         : 6;
12333         uint64_t ptp_mode              : 1;  /**< [ 12: 12](R/W) Timestamp mode. When [PTP_MODE] is set, a 64-bit timestamp is prepended to every incoming
12334                                                                  packet.
12335 
12336                                                                  The timestamp bytes are added to the packet in such a way as to not modify the packet's
12337                                                                  receive byte count. This implies that the BGX()_SMU()_RX_JABBER,
12338                                                                  BGX()_SMU()_RX_DECISION, and BGX()_SMU()_RX_UDD_SKP do not require any
12339                                                                  adjustment as they operate on the received packet size. When the packet reaches NIC, its
12340                                                                  size reflects the additional bytes. */
12341         uint64_t reserved_13_63        : 51;
12342 #endif /* Word 0 - End */
12343     } s;
12344     /* struct bdk_bgxx_smux_rx_frm_ctl_s cn; */
12345 };
12346 typedef union bdk_bgxx_smux_rx_frm_ctl bdk_bgxx_smux_rx_frm_ctl_t;
12347 
12348 static inline uint64_t BDK_BGXX_SMUX_RX_FRM_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_FRM_CTL(unsigned long a,unsigned long b)12349 static inline uint64_t BDK_BGXX_SMUX_RX_FRM_CTL(unsigned long a, unsigned long b)
12350 {
12351     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12352         return 0x87e0e0020020ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12353     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12354         return 0x87e0e0020020ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12355     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12356         return 0x87e0e0020020ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12357     __bdk_csr_fatal("BGXX_SMUX_RX_FRM_CTL", 2, a, b, 0, 0);
12358 }
12359 
12360 #define typedef_BDK_BGXX_SMUX_RX_FRM_CTL(a,b) bdk_bgxx_smux_rx_frm_ctl_t
12361 #define bustype_BDK_BGXX_SMUX_RX_FRM_CTL(a,b) BDK_CSR_TYPE_RSL
12362 #define basename_BDK_BGXX_SMUX_RX_FRM_CTL(a,b) "BGXX_SMUX_RX_FRM_CTL"
12363 #define device_bar_BDK_BGXX_SMUX_RX_FRM_CTL(a,b) 0x0 /* PF_BAR0 */
12364 #define busnum_BDK_BGXX_SMUX_RX_FRM_CTL(a,b) (a)
12365 #define arguments_BDK_BGXX_SMUX_RX_FRM_CTL(a,b) (a),(b),-1,-1
12366 
12367 /**
12368  * Register (RSL) bgx#_smu#_rx_int
12369  *
12370  * BGX SMU Receive Interrupt Registers
12371  * SMU Interrupt Register.
12372  * Internal:
12373  * Exception conditions \<9\> and \<4:0\> can also set the rcv/opcode in the received packet's work
12374  * queue entry. BGX()_SMU()_RX_FRM_CHK provides a bit mask for configuring which
12375  * conditions set the error.
12376  */
12377 union bdk_bgxx_smux_rx_int
12378 {
12379     uint64_t u;
12380     struct bdk_bgxx_smux_rx_int_s
12381     {
12382 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12383         uint64_t reserved_12_63        : 52;
12384         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1C/H) HiGig2 received message CRC or control-character error. Set when either a CRC8 error is
12385                                                                  detected, or when a control character is found in the message bytes after the K.SOM.
12386                                                                  HG2CC has higher priority than HG2FLD, which means that a HiGig2 message that results in
12387                                                                  HG2CC getting set never sets HG2FLD. */
12388         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1C/H) HiGig2 received message field error:
12389 
12390                                                                  MSG_TYPE field not 0x0, i.e. it is not a flow-control message, which is the only defined
12391                                                                  type for HiGig2.
12392 
12393                                                                  FWD_TYPE field not 0x0, i.e. it is not a link-level message, which is the only defined
12394                                                                  type for HiGig2.
12395 
12396                                                                  FC_OBJECT field is neither 0x0 for physical link, nor 0x2 for logical link. Those are the
12397                                                                  only two defined types in HiGig2 */
12398         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1C/H) Frame is terminated by control character other than /T/. The error
12399                                                                  propagation control character /E/ will be included as part of the frame and does not cause
12400                                                                  a frame termination. */
12401         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1C/H) Detected reserved sequence. */
12402         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1C/H) Remote-fault sequence detected. */
12403         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1C/H) Local-fault sequence detected. */
12404         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1C/H) Detected reserved opcode. */
12405         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1C/H) Bad preamble/protocol. In XAUI/RXAUI mode, the column of data that was bad is logged in
12406                                                                  BGX()_SMU()_RX_BAD_COL_LO and BGX()_SMU()_RX_BAD_COL_HI.
12407                                                                  PCTERR checks that the frame begins with a valid
12408                                                                  PREAMBLE sequence. Does not check the number of PREAMBLE cycles. */
12409         uint64_t skperr                : 1;  /**< [  3:  3](R/W1C/H) Skipper error. */
12410         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1C/H) Frame was received with data-reception error. */
12411         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1C/H) Frame was received with FCS/CRC error */
12412         uint64_t jabber                : 1;  /**< [  0:  0](R/W1C/H) Frame was received with length \> sys_length. An RX Jabber error indicates that a packet
12413                                                                  was received which is longer than the maximum allowed packet as defined by the system. BGX
12414                                                                  terminates the packet with an EOP on the beat on which JABBER was exceeded. The beat on
12415                                                                  which JABBER was exceeded is left unchanged and all subsequent data beats are dropped.
12416                                                                  Failure to truncate could lead to system instability. */
12417 #else /* Word 0 - Little Endian */
12418         uint64_t jabber                : 1;  /**< [  0:  0](R/W1C/H) Frame was received with length \> sys_length. An RX Jabber error indicates that a packet
12419                                                                  was received which is longer than the maximum allowed packet as defined by the system. BGX
12420                                                                  terminates the packet with an EOP on the beat on which JABBER was exceeded. The beat on
12421                                                                  which JABBER was exceeded is left unchanged and all subsequent data beats are dropped.
12422                                                                  Failure to truncate could lead to system instability. */
12423         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1C/H) Frame was received with FCS/CRC error */
12424         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1C/H) Frame was received with data-reception error. */
12425         uint64_t skperr                : 1;  /**< [  3:  3](R/W1C/H) Skipper error. */
12426         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1C/H) Bad preamble/protocol. In XAUI/RXAUI mode, the column of data that was bad is logged in
12427                                                                  BGX()_SMU()_RX_BAD_COL_LO and BGX()_SMU()_RX_BAD_COL_HI.
12428                                                                  PCTERR checks that the frame begins with a valid
12429                                                                  PREAMBLE sequence. Does not check the number of PREAMBLE cycles. */
12430         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1C/H) Detected reserved opcode. */
12431         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1C/H) Local-fault sequence detected. */
12432         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1C/H) Remote-fault sequence detected. */
12433         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1C/H) Detected reserved sequence. */
12434         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1C/H) Frame is terminated by control character other than /T/. The error
12435                                                                  propagation control character /E/ will be included as part of the frame and does not cause
12436                                                                  a frame termination. */
12437         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1C/H) HiGig2 received message field error:
12438 
12439                                                                  MSG_TYPE field not 0x0, i.e. it is not a flow-control message, which is the only defined
12440                                                                  type for HiGig2.
12441 
12442                                                                  FWD_TYPE field not 0x0, i.e. it is not a link-level message, which is the only defined
12443                                                                  type for HiGig2.
12444 
12445                                                                  FC_OBJECT field is neither 0x0 for physical link, nor 0x2 for logical link. Those are the
12446                                                                  only two defined types in HiGig2 */
12447         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1C/H) HiGig2 received message CRC or control-character error. Set when either a CRC8 error is
12448                                                                  detected, or when a control character is found in the message bytes after the K.SOM.
12449                                                                  HG2CC has higher priority than HG2FLD, which means that a HiGig2 message that results in
12450                                                                  HG2CC getting set never sets HG2FLD. */
12451         uint64_t reserved_12_63        : 52;
12452 #endif /* Word 0 - End */
12453     } s;
12454     /* struct bdk_bgxx_smux_rx_int_s cn; */
12455 };
12456 typedef union bdk_bgxx_smux_rx_int bdk_bgxx_smux_rx_int_t;
12457 
12458 static inline uint64_t BDK_BGXX_SMUX_RX_INT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_INT(unsigned long a,unsigned long b)12459 static inline uint64_t BDK_BGXX_SMUX_RX_INT(unsigned long a, unsigned long b)
12460 {
12461     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12462         return 0x87e0e0020000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12463     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12464         return 0x87e0e0020000ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12465     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12466         return 0x87e0e0020000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12467     __bdk_csr_fatal("BGXX_SMUX_RX_INT", 2, a, b, 0, 0);
12468 }
12469 
12470 #define typedef_BDK_BGXX_SMUX_RX_INT(a,b) bdk_bgxx_smux_rx_int_t
12471 #define bustype_BDK_BGXX_SMUX_RX_INT(a,b) BDK_CSR_TYPE_RSL
12472 #define basename_BDK_BGXX_SMUX_RX_INT(a,b) "BGXX_SMUX_RX_INT"
12473 #define device_bar_BDK_BGXX_SMUX_RX_INT(a,b) 0x0 /* PF_BAR0 */
12474 #define busnum_BDK_BGXX_SMUX_RX_INT(a,b) (a)
12475 #define arguments_BDK_BGXX_SMUX_RX_INT(a,b) (a),(b),-1,-1
12476 
12477 /**
12478  * Register (RSL) bgx#_smu#_rx_int_ena_w1c
12479  *
12480  * BGX SMU Receive Interrupt Enable Clear Registers
12481  * This register clears interrupt enable bits.
12482  */
12483 union bdk_bgxx_smux_rx_int_ena_w1c
12484 {
12485     uint64_t u;
12486     struct bdk_bgxx_smux_rx_int_ena_w1c_s
12487     {
12488 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12489         uint64_t reserved_12_63        : 52;
12490         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[HG2CC]. */
12491         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[HG2FLD]. */
12492         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[BAD_TERM]. */
12493         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12494         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[REM_FAULT]. */
12495         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12496         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[RSVERR]. */
12497         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[PCTERR]. */
12498         uint64_t skperr                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[SKPERR]. */
12499         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[RCVERR]. */
12500         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[FCSERR]. */
12501         uint64_t jabber                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[JABBER]. */
12502 #else /* Word 0 - Little Endian */
12503         uint64_t jabber                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[JABBER]. */
12504         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[FCSERR]. */
12505         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[RCVERR]. */
12506         uint64_t skperr                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[SKPERR]. */
12507         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[PCTERR]. */
12508         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[RSVERR]. */
12509         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12510         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[REM_FAULT]. */
12511         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12512         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[BAD_TERM]. */
12513         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[HG2FLD]. */
12514         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_RX_INT[HG2CC]. */
12515         uint64_t reserved_12_63        : 52;
12516 #endif /* Word 0 - End */
12517     } s;
12518     /* struct bdk_bgxx_smux_rx_int_ena_w1c_s cn81xx; */
12519     /* struct bdk_bgxx_smux_rx_int_ena_w1c_s cn88xx; */
12520     struct bdk_bgxx_smux_rx_int_ena_w1c_cn83xx
12521     {
12522 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12523         uint64_t reserved_12_63        : 52;
12524         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[HG2CC]. */
12525         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[HG2FLD]. */
12526         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[BAD_TERM]. */
12527         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12528         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[REM_FAULT]. */
12529         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12530         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[RSVERR]. */
12531         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[PCTERR]. */
12532         uint64_t skperr                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[SKPERR]. */
12533         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[RCVERR]. */
12534         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[FCSERR]. */
12535         uint64_t jabber                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[JABBER]. */
12536 #else /* Word 0 - Little Endian */
12537         uint64_t jabber                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[JABBER]. */
12538         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[FCSERR]. */
12539         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[RCVERR]. */
12540         uint64_t skperr                : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[SKPERR]. */
12541         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[PCTERR]. */
12542         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[RSVERR]. */
12543         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12544         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[REM_FAULT]. */
12545         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12546         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[BAD_TERM]. */
12547         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[HG2FLD]. */
12548         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_RX_INT[HG2CC]. */
12549         uint64_t reserved_12_63        : 52;
12550 #endif /* Word 0 - End */
12551     } cn83xx;
12552 };
12553 typedef union bdk_bgxx_smux_rx_int_ena_w1c bdk_bgxx_smux_rx_int_ena_w1c_t;
12554 
12555 static inline uint64_t BDK_BGXX_SMUX_RX_INT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_INT_ENA_W1C(unsigned long a,unsigned long b)12556 static inline uint64_t BDK_BGXX_SMUX_RX_INT_ENA_W1C(unsigned long a, unsigned long b)
12557 {
12558     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12559         return 0x87e0e0020010ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12560     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12561         return 0x87e0e0020010ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12562     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12563         return 0x87e0e0020010ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12564     __bdk_csr_fatal("BGXX_SMUX_RX_INT_ENA_W1C", 2, a, b, 0, 0);
12565 }
12566 
12567 #define typedef_BDK_BGXX_SMUX_RX_INT_ENA_W1C(a,b) bdk_bgxx_smux_rx_int_ena_w1c_t
12568 #define bustype_BDK_BGXX_SMUX_RX_INT_ENA_W1C(a,b) BDK_CSR_TYPE_RSL
12569 #define basename_BDK_BGXX_SMUX_RX_INT_ENA_W1C(a,b) "BGXX_SMUX_RX_INT_ENA_W1C"
12570 #define device_bar_BDK_BGXX_SMUX_RX_INT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
12571 #define busnum_BDK_BGXX_SMUX_RX_INT_ENA_W1C(a,b) (a)
12572 #define arguments_BDK_BGXX_SMUX_RX_INT_ENA_W1C(a,b) (a),(b),-1,-1
12573 
12574 /**
12575  * Register (RSL) bgx#_smu#_rx_int_ena_w1s
12576  *
12577  * BGX SMU Receive Interrupt Enable Set Registers
12578  * This register sets interrupt enable bits.
12579  */
12580 union bdk_bgxx_smux_rx_int_ena_w1s
12581 {
12582     uint64_t u;
12583     struct bdk_bgxx_smux_rx_int_ena_w1s_s
12584     {
12585 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12586         uint64_t reserved_12_63        : 52;
12587         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[HG2CC]. */
12588         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[HG2FLD]. */
12589         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[BAD_TERM]. */
12590         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12591         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[REM_FAULT]. */
12592         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12593         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[RSVERR]. */
12594         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[PCTERR]. */
12595         uint64_t skperr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[SKPERR]. */
12596         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[RCVERR]. */
12597         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[FCSERR]. */
12598         uint64_t jabber                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[JABBER]. */
12599 #else /* Word 0 - Little Endian */
12600         uint64_t jabber                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[JABBER]. */
12601         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[FCSERR]. */
12602         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[RCVERR]. */
12603         uint64_t skperr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[SKPERR]. */
12604         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[PCTERR]. */
12605         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[RSVERR]. */
12606         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12607         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[REM_FAULT]. */
12608         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12609         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[BAD_TERM]. */
12610         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[HG2FLD]. */
12611         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_RX_INT[HG2CC]. */
12612         uint64_t reserved_12_63        : 52;
12613 #endif /* Word 0 - End */
12614     } s;
12615     /* struct bdk_bgxx_smux_rx_int_ena_w1s_s cn81xx; */
12616     /* struct bdk_bgxx_smux_rx_int_ena_w1s_s cn88xx; */
12617     struct bdk_bgxx_smux_rx_int_ena_w1s_cn83xx
12618     {
12619 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12620         uint64_t reserved_12_63        : 52;
12621         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[HG2CC]. */
12622         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[HG2FLD]. */
12623         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[BAD_TERM]. */
12624         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12625         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[REM_FAULT]. */
12626         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12627         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[RSVERR]. */
12628         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[PCTERR]. */
12629         uint64_t skperr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[SKPERR]. */
12630         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[RCVERR]. */
12631         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[FCSERR]. */
12632         uint64_t jabber                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[JABBER]. */
12633 #else /* Word 0 - Little Endian */
12634         uint64_t jabber                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[JABBER]. */
12635         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[FCSERR]. */
12636         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[RCVERR]. */
12637         uint64_t skperr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[SKPERR]. */
12638         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[PCTERR]. */
12639         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[RSVERR]. */
12640         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12641         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[REM_FAULT]. */
12642         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12643         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[BAD_TERM]. */
12644         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[HG2FLD]. */
12645         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_RX_INT[HG2CC]. */
12646         uint64_t reserved_12_63        : 52;
12647 #endif /* Word 0 - End */
12648     } cn83xx;
12649 };
12650 typedef union bdk_bgxx_smux_rx_int_ena_w1s bdk_bgxx_smux_rx_int_ena_w1s_t;
12651 
12652 static inline uint64_t BDK_BGXX_SMUX_RX_INT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_INT_ENA_W1S(unsigned long a,unsigned long b)12653 static inline uint64_t BDK_BGXX_SMUX_RX_INT_ENA_W1S(unsigned long a, unsigned long b)
12654 {
12655     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12656         return 0x87e0e0020018ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12657     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12658         return 0x87e0e0020018ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12659     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12660         return 0x87e0e0020018ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12661     __bdk_csr_fatal("BGXX_SMUX_RX_INT_ENA_W1S", 2, a, b, 0, 0);
12662 }
12663 
12664 #define typedef_BDK_BGXX_SMUX_RX_INT_ENA_W1S(a,b) bdk_bgxx_smux_rx_int_ena_w1s_t
12665 #define bustype_BDK_BGXX_SMUX_RX_INT_ENA_W1S(a,b) BDK_CSR_TYPE_RSL
12666 #define basename_BDK_BGXX_SMUX_RX_INT_ENA_W1S(a,b) "BGXX_SMUX_RX_INT_ENA_W1S"
12667 #define device_bar_BDK_BGXX_SMUX_RX_INT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
12668 #define busnum_BDK_BGXX_SMUX_RX_INT_ENA_W1S(a,b) (a)
12669 #define arguments_BDK_BGXX_SMUX_RX_INT_ENA_W1S(a,b) (a),(b),-1,-1
12670 
12671 /**
12672  * Register (RSL) bgx#_smu#_rx_int_w1s
12673  *
12674  * BGX SMU Receive Interrupt Set Registers
12675  * This register sets interrupt bits.
12676  */
12677 union bdk_bgxx_smux_rx_int_w1s
12678 {
12679     uint64_t u;
12680     struct bdk_bgxx_smux_rx_int_w1s_s
12681     {
12682 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12683         uint64_t reserved_12_63        : 52;
12684         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[HG2CC]. */
12685         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[HG2FLD]. */
12686         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[BAD_TERM]. */
12687         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12688         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[REM_FAULT]. */
12689         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12690         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[RSVERR]. */
12691         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[PCTERR]. */
12692         uint64_t skperr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[SKPERR]. */
12693         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[RCVERR]. */
12694         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[FCSERR]. */
12695         uint64_t jabber                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[JABBER]. */
12696 #else /* Word 0 - Little Endian */
12697         uint64_t jabber                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[JABBER]. */
12698         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[FCSERR]. */
12699         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[RCVERR]. */
12700         uint64_t skperr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[SKPERR]. */
12701         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[PCTERR]. */
12702         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[RSVERR]. */
12703         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12704         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[REM_FAULT]. */
12705         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12706         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[BAD_TERM]. */
12707         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[HG2FLD]. */
12708         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_RX_INT[HG2CC]. */
12709         uint64_t reserved_12_63        : 52;
12710 #endif /* Word 0 - End */
12711     } s;
12712     /* struct bdk_bgxx_smux_rx_int_w1s_s cn81xx; */
12713     /* struct bdk_bgxx_smux_rx_int_w1s_s cn88xx; */
12714     struct bdk_bgxx_smux_rx_int_w1s_cn83xx
12715     {
12716 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12717         uint64_t reserved_12_63        : 52;
12718         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[HG2CC]. */
12719         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[HG2FLD]. */
12720         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[BAD_TERM]. */
12721         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12722         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[REM_FAULT]. */
12723         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12724         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[RSVERR]. */
12725         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[PCTERR]. */
12726         uint64_t skperr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[SKPERR]. */
12727         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[RCVERR]. */
12728         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[FCSERR]. */
12729         uint64_t jabber                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[JABBER]. */
12730 #else /* Word 0 - Little Endian */
12731         uint64_t jabber                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[JABBER]. */
12732         uint64_t fcserr                : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[FCSERR]. */
12733         uint64_t rcverr                : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[RCVERR]. */
12734         uint64_t skperr                : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[SKPERR]. */
12735         uint64_t pcterr                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[PCTERR]. */
12736         uint64_t rsverr                : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[RSVERR]. */
12737         uint64_t loc_fault             : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[LOC_FAULT]. */
12738         uint64_t rem_fault             : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[REM_FAULT]. */
12739         uint64_t bad_seq               : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[BAD_SEQ]. */
12740         uint64_t bad_term              : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[BAD_TERM]. */
12741         uint64_t hg2fld                : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[HG2FLD]. */
12742         uint64_t hg2cc                 : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_RX_INT[HG2CC]. */
12743         uint64_t reserved_12_63        : 52;
12744 #endif /* Word 0 - End */
12745     } cn83xx;
12746 };
12747 typedef union bdk_bgxx_smux_rx_int_w1s bdk_bgxx_smux_rx_int_w1s_t;
12748 
12749 static inline uint64_t BDK_BGXX_SMUX_RX_INT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_INT_W1S(unsigned long a,unsigned long b)12750 static inline uint64_t BDK_BGXX_SMUX_RX_INT_W1S(unsigned long a, unsigned long b)
12751 {
12752     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12753         return 0x87e0e0020008ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12754     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12755         return 0x87e0e0020008ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12756     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12757         return 0x87e0e0020008ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12758     __bdk_csr_fatal("BGXX_SMUX_RX_INT_W1S", 2, a, b, 0, 0);
12759 }
12760 
12761 #define typedef_BDK_BGXX_SMUX_RX_INT_W1S(a,b) bdk_bgxx_smux_rx_int_w1s_t
12762 #define bustype_BDK_BGXX_SMUX_RX_INT_W1S(a,b) BDK_CSR_TYPE_RSL
12763 #define basename_BDK_BGXX_SMUX_RX_INT_W1S(a,b) "BGXX_SMUX_RX_INT_W1S"
12764 #define device_bar_BDK_BGXX_SMUX_RX_INT_W1S(a,b) 0x0 /* PF_BAR0 */
12765 #define busnum_BDK_BGXX_SMUX_RX_INT_W1S(a,b) (a)
12766 #define arguments_BDK_BGXX_SMUX_RX_INT_W1S(a,b) (a),(b),-1,-1
12767 
12768 /**
12769  * Register (RSL) bgx#_smu#_rx_jabber
12770  *
12771  * BGX SMU Maximum Packet-Size Registers
12772  * This register specifies the maximum size for packets, beyond which the SMU truncates. In
12773  * XAUI/RXAUI mode, port 0 is used for checking.
12774  *
12775  * Internal:
12776  * The packet that will be sent to the packet input logic will have an
12777  * additionl 8 bytes if BGX()_SMU()_RX_FRM_CTL[PRE_CHK] is set and
12778  * BGX()_SMU()_RX_FRM_CTL[PRE_STRP] is clear.  The max packet that will be sent is
12779  * defined as:
12780  *
12781  * _ max_sized_packet = BGX()_SMU()_RX_JABBER[CNT]+((BGX()_SMU()_RX_FRM_CTL[PRE_CHK] &
12782  * !BGX()_SMU()_RX_FRM_CTL[PRE_STRP])*8)
12783  */
12784 union bdk_bgxx_smux_rx_jabber
12785 {
12786     uint64_t u;
12787     struct bdk_bgxx_smux_rx_jabber_s
12788     {
12789 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12790         uint64_t reserved_16_63        : 48;
12791         uint64_t cnt                   : 16; /**< [ 15:  0](R/W) Byte count for jabber check. Failing packets set the JABBER interrupt and are optionally
12792                                                                  sent with opcode = JABBER. BGX truncates the packet to CNT+1 to CNT+8 bytes.
12793                                                                  CNT must be 8-byte aligned such that CNT\<2:0\> = 000. */
12794 #else /* Word 0 - Little Endian */
12795         uint64_t cnt                   : 16; /**< [ 15:  0](R/W) Byte count for jabber check. Failing packets set the JABBER interrupt and are optionally
12796                                                                  sent with opcode = JABBER. BGX truncates the packet to CNT+1 to CNT+8 bytes.
12797                                                                  CNT must be 8-byte aligned such that CNT\<2:0\> = 000. */
12798         uint64_t reserved_16_63        : 48;
12799 #endif /* Word 0 - End */
12800     } s;
12801     /* struct bdk_bgxx_smux_rx_jabber_s cn; */
12802 };
12803 typedef union bdk_bgxx_smux_rx_jabber bdk_bgxx_smux_rx_jabber_t;
12804 
12805 static inline uint64_t BDK_BGXX_SMUX_RX_JABBER(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_JABBER(unsigned long a,unsigned long b)12806 static inline uint64_t BDK_BGXX_SMUX_RX_JABBER(unsigned long a, unsigned long b)
12807 {
12808     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12809         return 0x87e0e0020030ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12810     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12811         return 0x87e0e0020030ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12812     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12813         return 0x87e0e0020030ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12814     __bdk_csr_fatal("BGXX_SMUX_RX_JABBER", 2, a, b, 0, 0);
12815 }
12816 
12817 #define typedef_BDK_BGXX_SMUX_RX_JABBER(a,b) bdk_bgxx_smux_rx_jabber_t
12818 #define bustype_BDK_BGXX_SMUX_RX_JABBER(a,b) BDK_CSR_TYPE_RSL
12819 #define basename_BDK_BGXX_SMUX_RX_JABBER(a,b) "BGXX_SMUX_RX_JABBER"
12820 #define device_bar_BDK_BGXX_SMUX_RX_JABBER(a,b) 0x0 /* PF_BAR0 */
12821 #define busnum_BDK_BGXX_SMUX_RX_JABBER(a,b) (a)
12822 #define arguments_BDK_BGXX_SMUX_RX_JABBER(a,b) (a),(b),-1,-1
12823 
12824 /**
12825  * Register (RSL) bgx#_smu#_rx_udd_skp
12826  *
12827  * BGX SMU User-Defined Data Skip Registers
12828  * Internal:
12829  * (1) The skip bytes are part of the packet and will be sent down the NCB
12830  * packet interface and will be handled by NIC.
12831  * (2) The system can determine if the UDD bytes are included in the FCS check
12832  * by using the FCSSEL field if the FCS check is enabled.
12833  *
12834  * (3) Assume that the preamble/sfd is always at the start of the frame even
12835  * before UDD bytes.  In most cases, there will be no preamble in these
12836  * cases since it will be packet interface in direct communication to
12837  * another packet interface (MAC to MAC) without a PHY involved.
12838  *
12839  * (4) We can still do address filtering and control packet filtering if the
12840  * user desires.
12841  *
12842  * (6) In all cases, the UDD bytes will be sent down the packet interface as
12843  * part of the packet.  The UDD bytes are never stripped from the actual
12844  * packet.
12845  */
12846 union bdk_bgxx_smux_rx_udd_skp
12847 {
12848     uint64_t u;
12849     struct bdk_bgxx_smux_rx_udd_skp_s
12850     {
12851 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12852         uint64_t reserved_9_63         : 55;
12853         uint64_t fcssel                : 1;  /**< [  8:  8](R/W) Include the skip bytes in the FCS calculation.
12854                                                                  0 = All skip bytes are included in FCS.
12855                                                                  1 = The skip bytes are not included in FCS.
12856 
12857                                                                  When BGX()_SMU()_TX_CTL[HG_EN] is set, this field must be 0.
12858                                                                  The skip bytes are part of the packet and are sent through the NCB packet interface and
12859                                                                  are handled by NIC. The system can determine if the UDD bytes are included in the FCS
12860                                                                  check by using the FCSSEL field, if the FCS check is enabled. */
12861         uint64_t reserved_7            : 1;
12862         uint64_t len                   : 7;  /**< [  6:  0](R/W) Amount of user-defined data before the start of the L2C data, in bytes.
12863                                                                  Setting to 0 means L2C comes first; maximum value is 64.
12864                                                                  LEN must be 0x0 in half-duplex operation.
12865 
12866                                                                  When BGX()_SMU()_TX_CTL[HG_EN] is set, this field must be set to 12 or 16
12867                                                                  (depending on HiGig header size) to account for the HiGig header.
12868                                                                  LEN = 12 selects HiGig/HiGig+; LEN = 16 selects HiGig2. */
12869 #else /* Word 0 - Little Endian */
12870         uint64_t len                   : 7;  /**< [  6:  0](R/W) Amount of user-defined data before the start of the L2C data, in bytes.
12871                                                                  Setting to 0 means L2C comes first; maximum value is 64.
12872                                                                  LEN must be 0x0 in half-duplex operation.
12873 
12874                                                                  When BGX()_SMU()_TX_CTL[HG_EN] is set, this field must be set to 12 or 16
12875                                                                  (depending on HiGig header size) to account for the HiGig header.
12876                                                                  LEN = 12 selects HiGig/HiGig+; LEN = 16 selects HiGig2. */
12877         uint64_t reserved_7            : 1;
12878         uint64_t fcssel                : 1;  /**< [  8:  8](R/W) Include the skip bytes in the FCS calculation.
12879                                                                  0 = All skip bytes are included in FCS.
12880                                                                  1 = The skip bytes are not included in FCS.
12881 
12882                                                                  When BGX()_SMU()_TX_CTL[HG_EN] is set, this field must be 0.
12883                                                                  The skip bytes are part of the packet and are sent through the NCB packet interface and
12884                                                                  are handled by NIC. The system can determine if the UDD bytes are included in the FCS
12885                                                                  check by using the FCSSEL field, if the FCS check is enabled. */
12886         uint64_t reserved_9_63         : 55;
12887 #endif /* Word 0 - End */
12888     } s;
12889     /* struct bdk_bgxx_smux_rx_udd_skp_s cn; */
12890 };
12891 typedef union bdk_bgxx_smux_rx_udd_skp bdk_bgxx_smux_rx_udd_skp_t;
12892 
12893 static inline uint64_t BDK_BGXX_SMUX_RX_UDD_SKP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_RX_UDD_SKP(unsigned long a,unsigned long b)12894 static inline uint64_t BDK_BGXX_SMUX_RX_UDD_SKP(unsigned long a, unsigned long b)
12895 {
12896     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12897         return 0x87e0e0020040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12898     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12899         return 0x87e0e0020040ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12900     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12901         return 0x87e0e0020040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12902     __bdk_csr_fatal("BGXX_SMUX_RX_UDD_SKP", 2, a, b, 0, 0);
12903 }
12904 
12905 #define typedef_BDK_BGXX_SMUX_RX_UDD_SKP(a,b) bdk_bgxx_smux_rx_udd_skp_t
12906 #define bustype_BDK_BGXX_SMUX_RX_UDD_SKP(a,b) BDK_CSR_TYPE_RSL
12907 #define basename_BDK_BGXX_SMUX_RX_UDD_SKP(a,b) "BGXX_SMUX_RX_UDD_SKP"
12908 #define device_bar_BDK_BGXX_SMUX_RX_UDD_SKP(a,b) 0x0 /* PF_BAR0 */
12909 #define busnum_BDK_BGXX_SMUX_RX_UDD_SKP(a,b) (a)
12910 #define arguments_BDK_BGXX_SMUX_RX_UDD_SKP(a,b) (a),(b),-1,-1
12911 
12912 /**
12913  * Register (RSL) bgx#_smu#_smac
12914  *
12915  * BGX SMU SMAC Registers
12916  */
12917 union bdk_bgxx_smux_smac
12918 {
12919     uint64_t u;
12920     struct bdk_bgxx_smux_smac_s
12921     {
12922 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12923         uint64_t reserved_48_63        : 16;
12924         uint64_t smac                  : 48; /**< [ 47:  0](R/W) The SMAC field is used for generating and accepting control PAUSE packets. */
12925 #else /* Word 0 - Little Endian */
12926         uint64_t smac                  : 48; /**< [ 47:  0](R/W) The SMAC field is used for generating and accepting control PAUSE packets. */
12927         uint64_t reserved_48_63        : 16;
12928 #endif /* Word 0 - End */
12929     } s;
12930     /* struct bdk_bgxx_smux_smac_s cn; */
12931 };
12932 typedef union bdk_bgxx_smux_smac bdk_bgxx_smux_smac_t;
12933 
12934 static inline uint64_t BDK_BGXX_SMUX_SMAC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_SMAC(unsigned long a,unsigned long b)12935 static inline uint64_t BDK_BGXX_SMUX_SMAC(unsigned long a, unsigned long b)
12936 {
12937     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12938         return 0x87e0e0020108ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12939     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12940         return 0x87e0e0020108ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12941     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12942         return 0x87e0e0020108ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12943     __bdk_csr_fatal("BGXX_SMUX_SMAC", 2, a, b, 0, 0);
12944 }
12945 
12946 #define typedef_BDK_BGXX_SMUX_SMAC(a,b) bdk_bgxx_smux_smac_t
12947 #define bustype_BDK_BGXX_SMUX_SMAC(a,b) BDK_CSR_TYPE_RSL
12948 #define basename_BDK_BGXX_SMUX_SMAC(a,b) "BGXX_SMUX_SMAC"
12949 #define device_bar_BDK_BGXX_SMUX_SMAC(a,b) 0x0 /* PF_BAR0 */
12950 #define busnum_BDK_BGXX_SMUX_SMAC(a,b) (a)
12951 #define arguments_BDK_BGXX_SMUX_SMAC(a,b) (a),(b),-1,-1
12952 
12953 /**
12954  * Register (RSL) bgx#_smu#_tx_append
12955  *
12956  * BGX SMU TX Append Control Registers
12957  * For more details on the interactions between FCS and PAD, see also the description of
12958  * BGX()_SMU()_TX_MIN_PKT[MIN_SIZE].
12959  */
12960 union bdk_bgxx_smux_tx_append
12961 {
12962     uint64_t u;
12963     struct bdk_bgxx_smux_tx_append_s
12964     {
12965 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12966         uint64_t reserved_4_63         : 60;
12967         uint64_t fcs_c                 : 1;  /**< [  3:  3](R/W) Append the Ethernet FCS on each PAUSE packet. PAUSE packets are normally padded to 60
12968                                                                  bytes. If BGX()_SMU()_TX_MIN_PKT[MIN_SIZE] exceeds 59, then [FCS_C] is not used. */
12969         uint64_t fcs_d                 : 1;  /**< [  2:  2](R/W) Append the Ethernet FCS on each data packet. */
12970         uint64_t pad                   : 1;  /**< [  1:  1](R/W) Append PAD bytes such that minimum-sized packet is transmitted. */
12971         uint64_t preamble              : 1;  /**< [  0:  0](R/W) Prepend the Ethernet preamble on each transfer. When BGX()_SMU()_TX_CTL[HG_EN] is
12972                                                                  set, PREAMBLE must be 0. */
12973 #else /* Word 0 - Little Endian */
12974         uint64_t preamble              : 1;  /**< [  0:  0](R/W) Prepend the Ethernet preamble on each transfer. When BGX()_SMU()_TX_CTL[HG_EN] is
12975                                                                  set, PREAMBLE must be 0. */
12976         uint64_t pad                   : 1;  /**< [  1:  1](R/W) Append PAD bytes such that minimum-sized packet is transmitted. */
12977         uint64_t fcs_d                 : 1;  /**< [  2:  2](R/W) Append the Ethernet FCS on each data packet. */
12978         uint64_t fcs_c                 : 1;  /**< [  3:  3](R/W) Append the Ethernet FCS on each PAUSE packet. PAUSE packets are normally padded to 60
12979                                                                  bytes. If BGX()_SMU()_TX_MIN_PKT[MIN_SIZE] exceeds 59, then [FCS_C] is not used. */
12980         uint64_t reserved_4_63         : 60;
12981 #endif /* Word 0 - End */
12982     } s;
12983     /* struct bdk_bgxx_smux_tx_append_s cn; */
12984 };
12985 typedef union bdk_bgxx_smux_tx_append bdk_bgxx_smux_tx_append_t;
12986 
12987 static inline uint64_t BDK_BGXX_SMUX_TX_APPEND(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_APPEND(unsigned long a,unsigned long b)12988 static inline uint64_t BDK_BGXX_SMUX_TX_APPEND(unsigned long a, unsigned long b)
12989 {
12990     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
12991         return 0x87e0e0020100ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12992     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
12993         return 0x87e0e0020100ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
12994     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
12995         return 0x87e0e0020100ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
12996     __bdk_csr_fatal("BGXX_SMUX_TX_APPEND", 2, a, b, 0, 0);
12997 }
12998 
12999 #define typedef_BDK_BGXX_SMUX_TX_APPEND(a,b) bdk_bgxx_smux_tx_append_t
13000 #define bustype_BDK_BGXX_SMUX_TX_APPEND(a,b) BDK_CSR_TYPE_RSL
13001 #define basename_BDK_BGXX_SMUX_TX_APPEND(a,b) "BGXX_SMUX_TX_APPEND"
13002 #define device_bar_BDK_BGXX_SMUX_TX_APPEND(a,b) 0x0 /* PF_BAR0 */
13003 #define busnum_BDK_BGXX_SMUX_TX_APPEND(a,b) (a)
13004 #define arguments_BDK_BGXX_SMUX_TX_APPEND(a,b) (a),(b),-1,-1
13005 
13006 /**
13007  * Register (RSL) bgx#_smu#_tx_ctl
13008  *
13009  * BGX SMU Transmit Control Registers
13010  */
13011 union bdk_bgxx_smux_tx_ctl
13012 {
13013     uint64_t u;
13014     struct bdk_bgxx_smux_tx_ctl_s
13015     {
13016 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13017         uint64_t reserved_31_63        : 33;
13018         uint64_t spu_mrk_cnt           : 20; /**< [ 30: 11](R/W) 40GBASE-R transmit marker interval count. Specifies the interval (number of 66-bit BASE-R
13019                                                                  blocks) at which the LMAC transmit logic inserts 40GBASE-R alignment markers. An internal
13020                                                                  counter in SMU is initialized to this value, counts down for each BASE-R block transmitted
13021                                                                  by the LMAC, and wraps back to the initial value from 0. The LMAC transmit logic inserts
13022                                                                  alignment markers for lanes 0, 1, 2 and 3, respectively, in the last four BASE-R blocks
13023                                                                  before the counter wraps (3, 2, 1, 0). The default value corresponds to an alignment
13024                                                                  marker period of 16363 blocks (exclusive) per lane, as specified in 802.3ba-2010. The
13025                                                                  default value should always be used for normal operation. */
13026         uint64_t hg_pause_hgi          : 2;  /**< [ 10:  9](R/W) HGI field for hardware-generated HiGig PAUSE packets. */
13027         uint64_t hg_en                 : 1;  /**< [  8:  8](R/W) Enable HiGig mode.
13028                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 12, the interface is in
13029                                                                  HiGig/HiGig+ mode and the following must be set:
13030                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13031                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13032                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 12.
13033                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13034 
13035                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 16, the interface is in
13036                                                                  HiGig2 mode and the following must be set:
13037                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13038                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13039                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 16.
13040                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13041                                                                  * BGX()_SMU()_CBFC_CTL[RX_EN] = 0.
13042                                                                  * BGX()_SMU()_CBFC_CTL[TX_EN] = 0. */
13043         uint64_t l2p_bp_conv           : 1;  /**< [  7:  7](R/W) If set, causes TX to generate 802.3 pause packets when CMR applies logical backpressure
13044                                                                  (XOFF), if and only if BGX()_SMU()_CBFC_CTL[TX_EN] is clear and
13045                                                                  BGX()_SMU()_HG2_CONTROL[HG2TX_EN] is clear. */
13046         uint64_t ls_byp                : 1;  /**< [  6:  6](R/W) Bypass the link status, as determined by the XGMII receiver, and set the link status of
13047                                                                  the transmitter to LS. */
13048         uint64_t ls                    : 2;  /**< [  5:  4](R/W) Link status.
13049                                                                  0 = Link OK; link runs normally. RS passes MAC data to PCS.
13050                                                                  1 = Local fault. RS layer sends continuous remote fault sequences.
13051                                                                  2 = Remote fault. RS layer sends continuous idle sequences.
13052                                                                  3 = Link drain. RS layer drops full packets to allow BGX and PKO to drain their FIFOs. */
13053         uint64_t reserved_3            : 1;
13054         uint64_t x4a_dis               : 1;  /**< [  2:  2](R/W) Disable 4-byte SOP align (effectively force 8-byte SOP align) for all 10G variants
13055                                                                  (XAUI, RXAUI, 10G). */
13056         uint64_t uni_en                : 1;  /**< [  1:  1](R/W) Enable unidirectional mode (IEEE Clause 66). */
13057         uint64_t dic_en                : 1;  /**< [  0:  0](R/W) Enable the deficit idle counter for IFG averaging. */
13058 #else /* Word 0 - Little Endian */
13059         uint64_t dic_en                : 1;  /**< [  0:  0](R/W) Enable the deficit idle counter for IFG averaging. */
13060         uint64_t uni_en                : 1;  /**< [  1:  1](R/W) Enable unidirectional mode (IEEE Clause 66). */
13061         uint64_t x4a_dis               : 1;  /**< [  2:  2](R/W) Disable 4-byte SOP align (effectively force 8-byte SOP align) for all 10G variants
13062                                                                  (XAUI, RXAUI, 10G). */
13063         uint64_t reserved_3            : 1;
13064         uint64_t ls                    : 2;  /**< [  5:  4](R/W) Link status.
13065                                                                  0 = Link OK; link runs normally. RS passes MAC data to PCS.
13066                                                                  1 = Local fault. RS layer sends continuous remote fault sequences.
13067                                                                  2 = Remote fault. RS layer sends continuous idle sequences.
13068                                                                  3 = Link drain. RS layer drops full packets to allow BGX and PKO to drain their FIFOs. */
13069         uint64_t ls_byp                : 1;  /**< [  6:  6](R/W) Bypass the link status, as determined by the XGMII receiver, and set the link status of
13070                                                                  the transmitter to LS. */
13071         uint64_t l2p_bp_conv           : 1;  /**< [  7:  7](R/W) If set, causes TX to generate 802.3 pause packets when CMR applies logical backpressure
13072                                                                  (XOFF), if and only if BGX()_SMU()_CBFC_CTL[TX_EN] is clear and
13073                                                                  BGX()_SMU()_HG2_CONTROL[HG2TX_EN] is clear. */
13074         uint64_t hg_en                 : 1;  /**< [  8:  8](R/W) Enable HiGig mode.
13075                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 12, the interface is in
13076                                                                  HiGig/HiGig+ mode and the following must be set:
13077                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13078                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13079                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 12.
13080                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13081 
13082                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 16, the interface is in
13083                                                                  HiGig2 mode and the following must be set:
13084                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13085                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13086                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 16.
13087                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13088                                                                  * BGX()_SMU()_CBFC_CTL[RX_EN] = 0.
13089                                                                  * BGX()_SMU()_CBFC_CTL[TX_EN] = 0. */
13090         uint64_t hg_pause_hgi          : 2;  /**< [ 10:  9](R/W) HGI field for hardware-generated HiGig PAUSE packets. */
13091         uint64_t spu_mrk_cnt           : 20; /**< [ 30: 11](R/W) 40GBASE-R transmit marker interval count. Specifies the interval (number of 66-bit BASE-R
13092                                                                  blocks) at which the LMAC transmit logic inserts 40GBASE-R alignment markers. An internal
13093                                                                  counter in SMU is initialized to this value, counts down for each BASE-R block transmitted
13094                                                                  by the LMAC, and wraps back to the initial value from 0. The LMAC transmit logic inserts
13095                                                                  alignment markers for lanes 0, 1, 2 and 3, respectively, in the last four BASE-R blocks
13096                                                                  before the counter wraps (3, 2, 1, 0). The default value corresponds to an alignment
13097                                                                  marker period of 16363 blocks (exclusive) per lane, as specified in 802.3ba-2010. The
13098                                                                  default value should always be used for normal operation. */
13099         uint64_t reserved_31_63        : 33;
13100 #endif /* Word 0 - End */
13101     } s;
13102     struct bdk_bgxx_smux_tx_ctl_cn88xxp1
13103     {
13104 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13105         uint64_t reserved_31_63        : 33;
13106         uint64_t spu_mrk_cnt           : 20; /**< [ 30: 11](R/W) 40GBASE-R transmit marker interval count. Specifies the interval (number of 66-bit BASE-R
13107                                                                  blocks) at which the LMAC transmit logic inserts 40GBASE-R alignment markers. An internal
13108                                                                  counter in SMU is initialized to this value, counts down for each BASE-R block transmitted
13109                                                                  by the LMAC, and wraps back to the initial value from 0. The LMAC transmit logic inserts
13110                                                                  alignment markers for lanes 0, 1, 2 and 3, respectively, in the last four BASE-R blocks
13111                                                                  before the counter wraps (3, 2, 1, 0). The default value corresponds to an alignment
13112                                                                  marker period of 16363 blocks (exclusive) per lane, as specified in 802.3ba-2010. The
13113                                                                  default value should always be used for normal operation. */
13114         uint64_t hg_pause_hgi          : 2;  /**< [ 10:  9](R/W) HGI field for hardware-generated HiGig PAUSE packets. */
13115         uint64_t hg_en                 : 1;  /**< [  8:  8](R/W) Enable HiGig mode.
13116                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 12, the interface is in
13117                                                                  HiGig/HiGig+ mode and the following must be set:
13118                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13119                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13120                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 12.
13121                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13122 
13123                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 16, the interface is in
13124                                                                  HiGig2 mode and the following must be set:
13125                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13126                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13127                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 16.
13128                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13129                                                                  * BGX()_SMU()_CBFC_CTL[RX_EN] = 0.
13130                                                                  * BGX()_SMU()_CBFC_CTL[TX_EN] = 0. */
13131         uint64_t l2p_bp_conv           : 1;  /**< [  7:  7](R/W) If set, causes TX to generate 802.3 pause packets when CMR applies logical backpressure
13132                                                                  (XOFF), if and only if BGX()_SMU()_CBFC_CTL[TX_EN] is clear and
13133                                                                  BGX()_SMU()_HG2_CONTROL[HG2TX_EN] is clear. */
13134         uint64_t ls_byp                : 1;  /**< [  6:  6](R/W) Bypass the link status, as determined by the XGMII receiver, and set the link status of
13135                                                                  the transmitter to LS. */
13136         uint64_t ls                    : 2;  /**< [  5:  4](R/W) Link status.
13137                                                                  0 = Link OK; link runs normally. RS passes MAC data to PCS.
13138                                                                  1 = Local fault. RS layer sends continuous remote fault sequences.
13139                                                                  2 = Remote fault. RS layer sends continuous idle sequences.
13140                                                                  3 = Link drain. RS layer drops full packets to allow BGX and TNS/NIC to drain their FIFOs. */
13141         uint64_t reserved_3            : 1;
13142         uint64_t x4a_dis               : 1;  /**< [  2:  2](RAZ) Reserved. */
13143         uint64_t uni_en                : 1;  /**< [  1:  1](R/W) Enable unidirectional mode (IEEE Clause 66). */
13144         uint64_t dic_en                : 1;  /**< [  0:  0](R/W) Enable the deficit idle counter for IFG averaging. */
13145 #else /* Word 0 - Little Endian */
13146         uint64_t dic_en                : 1;  /**< [  0:  0](R/W) Enable the deficit idle counter for IFG averaging. */
13147         uint64_t uni_en                : 1;  /**< [  1:  1](R/W) Enable unidirectional mode (IEEE Clause 66). */
13148         uint64_t x4a_dis               : 1;  /**< [  2:  2](RAZ) Reserved. */
13149         uint64_t reserved_3            : 1;
13150         uint64_t ls                    : 2;  /**< [  5:  4](R/W) Link status.
13151                                                                  0 = Link OK; link runs normally. RS passes MAC data to PCS.
13152                                                                  1 = Local fault. RS layer sends continuous remote fault sequences.
13153                                                                  2 = Remote fault. RS layer sends continuous idle sequences.
13154                                                                  3 = Link drain. RS layer drops full packets to allow BGX and TNS/NIC to drain their FIFOs. */
13155         uint64_t ls_byp                : 1;  /**< [  6:  6](R/W) Bypass the link status, as determined by the XGMII receiver, and set the link status of
13156                                                                  the transmitter to LS. */
13157         uint64_t l2p_bp_conv           : 1;  /**< [  7:  7](R/W) If set, causes TX to generate 802.3 pause packets when CMR applies logical backpressure
13158                                                                  (XOFF), if and only if BGX()_SMU()_CBFC_CTL[TX_EN] is clear and
13159                                                                  BGX()_SMU()_HG2_CONTROL[HG2TX_EN] is clear. */
13160         uint64_t hg_en                 : 1;  /**< [  8:  8](R/W) Enable HiGig mode.
13161                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 12, the interface is in
13162                                                                  HiGig/HiGig+ mode and the following must be set:
13163                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13164                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13165                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 12.
13166                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13167 
13168                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 16, the interface is in
13169                                                                  HiGig2 mode and the following must be set:
13170                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13171                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13172                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 16.
13173                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13174                                                                  * BGX()_SMU()_CBFC_CTL[RX_EN] = 0.
13175                                                                  * BGX()_SMU()_CBFC_CTL[TX_EN] = 0. */
13176         uint64_t hg_pause_hgi          : 2;  /**< [ 10:  9](R/W) HGI field for hardware-generated HiGig PAUSE packets. */
13177         uint64_t spu_mrk_cnt           : 20; /**< [ 30: 11](R/W) 40GBASE-R transmit marker interval count. Specifies the interval (number of 66-bit BASE-R
13178                                                                  blocks) at which the LMAC transmit logic inserts 40GBASE-R alignment markers. An internal
13179                                                                  counter in SMU is initialized to this value, counts down for each BASE-R block transmitted
13180                                                                  by the LMAC, and wraps back to the initial value from 0. The LMAC transmit logic inserts
13181                                                                  alignment markers for lanes 0, 1, 2 and 3, respectively, in the last four BASE-R blocks
13182                                                                  before the counter wraps (3, 2, 1, 0). The default value corresponds to an alignment
13183                                                                  marker period of 16363 blocks (exclusive) per lane, as specified in 802.3ba-2010. The
13184                                                                  default value should always be used for normal operation. */
13185         uint64_t reserved_31_63        : 33;
13186 #endif /* Word 0 - End */
13187     } cn88xxp1;
13188     /* struct bdk_bgxx_smux_tx_ctl_s cn81xx; */
13189     /* struct bdk_bgxx_smux_tx_ctl_s cn83xx; */
13190     struct bdk_bgxx_smux_tx_ctl_cn88xxp2
13191     {
13192 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13193         uint64_t reserved_31_63        : 33;
13194         uint64_t spu_mrk_cnt           : 20; /**< [ 30: 11](R/W) 40GBASE-R transmit marker interval count. Specifies the interval (number of 66-bit BASE-R
13195                                                                  blocks) at which the LMAC transmit logic inserts 40GBASE-R alignment markers. An internal
13196                                                                  counter in SMU is initialized to this value, counts down for each BASE-R block transmitted
13197                                                                  by the LMAC, and wraps back to the initial value from 0. The LMAC transmit logic inserts
13198                                                                  alignment markers for lanes 0, 1, 2 and 3, respectively, in the last four BASE-R blocks
13199                                                                  before the counter wraps (3, 2, 1, 0). The default value corresponds to an alignment
13200                                                                  marker period of 16363 blocks (exclusive) per lane, as specified in 802.3ba-2010. The
13201                                                                  default value should always be used for normal operation. */
13202         uint64_t hg_pause_hgi          : 2;  /**< [ 10:  9](R/W) HGI field for hardware-generated HiGig PAUSE packets. */
13203         uint64_t hg_en                 : 1;  /**< [  8:  8](R/W) Enable HiGig mode.
13204                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 12, the interface is in
13205                                                                  HiGig/HiGig+ mode and the following must be set:
13206                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13207                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13208                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 12.
13209                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13210 
13211                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 16, the interface is in
13212                                                                  HiGig2 mode and the following must be set:
13213                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13214                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13215                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 16.
13216                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13217                                                                  * BGX()_SMU()_CBFC_CTL[RX_EN] = 0.
13218                                                                  * BGX()_SMU()_CBFC_CTL[TX_EN] = 0. */
13219         uint64_t l2p_bp_conv           : 1;  /**< [  7:  7](R/W) If set, causes TX to generate 802.3 pause packets when CMR applies logical backpressure
13220                                                                  (XOFF), if and only if BGX()_SMU()_CBFC_CTL[TX_EN] is clear and
13221                                                                  BGX()_SMU()_HG2_CONTROL[HG2TX_EN] is clear. */
13222         uint64_t ls_byp                : 1;  /**< [  6:  6](R/W) Bypass the link status, as determined by the XGMII receiver, and set the link status of
13223                                                                  the transmitter to LS. */
13224         uint64_t ls                    : 2;  /**< [  5:  4](R/W) Link status.
13225                                                                  0 = Link OK; link runs normally. RS passes MAC data to PCS.
13226                                                                  1 = Local fault. RS layer sends continuous remote fault sequences.
13227                                                                  2 = Remote fault. RS layer sends continuous idle sequences.
13228                                                                  3 = Link drain. RS layer drops full packets to allow BGX and TNS/NIC to drain their FIFOs. */
13229         uint64_t reserved_3            : 1;
13230         uint64_t x4a_dis               : 1;  /**< [  2:  2](R/W) Disable 4-byte SOP align (effectively force 8-byte SOP align) for all 10G variants
13231                                                                  (XAUI, RXAUI, 10G). */
13232         uint64_t uni_en                : 1;  /**< [  1:  1](R/W) Enable unidirectional mode (IEEE Clause 66). */
13233         uint64_t dic_en                : 1;  /**< [  0:  0](R/W) Enable the deficit idle counter for IFG averaging. */
13234 #else /* Word 0 - Little Endian */
13235         uint64_t dic_en                : 1;  /**< [  0:  0](R/W) Enable the deficit idle counter for IFG averaging. */
13236         uint64_t uni_en                : 1;  /**< [  1:  1](R/W) Enable unidirectional mode (IEEE Clause 66). */
13237         uint64_t x4a_dis               : 1;  /**< [  2:  2](R/W) Disable 4-byte SOP align (effectively force 8-byte SOP align) for all 10G variants
13238                                                                  (XAUI, RXAUI, 10G). */
13239         uint64_t reserved_3            : 1;
13240         uint64_t ls                    : 2;  /**< [  5:  4](R/W) Link status.
13241                                                                  0 = Link OK; link runs normally. RS passes MAC data to PCS.
13242                                                                  1 = Local fault. RS layer sends continuous remote fault sequences.
13243                                                                  2 = Remote fault. RS layer sends continuous idle sequences.
13244                                                                  3 = Link drain. RS layer drops full packets to allow BGX and TNS/NIC to drain their FIFOs. */
13245         uint64_t ls_byp                : 1;  /**< [  6:  6](R/W) Bypass the link status, as determined by the XGMII receiver, and set the link status of
13246                                                                  the transmitter to LS. */
13247         uint64_t l2p_bp_conv           : 1;  /**< [  7:  7](R/W) If set, causes TX to generate 802.3 pause packets when CMR applies logical backpressure
13248                                                                  (XOFF), if and only if BGX()_SMU()_CBFC_CTL[TX_EN] is clear and
13249                                                                  BGX()_SMU()_HG2_CONTROL[HG2TX_EN] is clear. */
13250         uint64_t hg_en                 : 1;  /**< [  8:  8](R/W) Enable HiGig mode.
13251                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 12, the interface is in
13252                                                                  HiGig/HiGig+ mode and the following must be set:
13253                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13254                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13255                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 12.
13256                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13257 
13258                                                                  When this field is set and BGX()_SMU()_RX_UDD_SKP[LEN] = 16, the interface is in
13259                                                                  HiGig2 mode and the following must be set:
13260                                                                  * BGX()_SMU()_RX_FRM_CTL[PRE_CHK] = 0.
13261                                                                  * BGX()_SMU()_RX_UDD_SKP[FCSSEL] = 0.
13262                                                                  * BGX()_SMU()_RX_UDD_SKP[LEN] = 16.
13263                                                                  * BGX()_SMU()_TX_APPEND[PREAMBLE] = 0.
13264                                                                  * BGX()_SMU()_CBFC_CTL[RX_EN] = 0.
13265                                                                  * BGX()_SMU()_CBFC_CTL[TX_EN] = 0. */
13266         uint64_t hg_pause_hgi          : 2;  /**< [ 10:  9](R/W) HGI field for hardware-generated HiGig PAUSE packets. */
13267         uint64_t spu_mrk_cnt           : 20; /**< [ 30: 11](R/W) 40GBASE-R transmit marker interval count. Specifies the interval (number of 66-bit BASE-R
13268                                                                  blocks) at which the LMAC transmit logic inserts 40GBASE-R alignment markers. An internal
13269                                                                  counter in SMU is initialized to this value, counts down for each BASE-R block transmitted
13270                                                                  by the LMAC, and wraps back to the initial value from 0. The LMAC transmit logic inserts
13271                                                                  alignment markers for lanes 0, 1, 2 and 3, respectively, in the last four BASE-R blocks
13272                                                                  before the counter wraps (3, 2, 1, 0). The default value corresponds to an alignment
13273                                                                  marker period of 16363 blocks (exclusive) per lane, as specified in 802.3ba-2010. The
13274                                                                  default value should always be used for normal operation. */
13275         uint64_t reserved_31_63        : 33;
13276 #endif /* Word 0 - End */
13277     } cn88xxp2;
13278 };
13279 typedef union bdk_bgxx_smux_tx_ctl bdk_bgxx_smux_tx_ctl_t;
13280 
13281 static inline uint64_t BDK_BGXX_SMUX_TX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_CTL(unsigned long a,unsigned long b)13282 static inline uint64_t BDK_BGXX_SMUX_TX_CTL(unsigned long a, unsigned long b)
13283 {
13284     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13285         return 0x87e0e0020178ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13286     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13287         return 0x87e0e0020178ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13288     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13289         return 0x87e0e0020178ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13290     __bdk_csr_fatal("BGXX_SMUX_TX_CTL", 2, a, b, 0, 0);
13291 }
13292 
13293 #define typedef_BDK_BGXX_SMUX_TX_CTL(a,b) bdk_bgxx_smux_tx_ctl_t
13294 #define bustype_BDK_BGXX_SMUX_TX_CTL(a,b) BDK_CSR_TYPE_RSL
13295 #define basename_BDK_BGXX_SMUX_TX_CTL(a,b) "BGXX_SMUX_TX_CTL"
13296 #define device_bar_BDK_BGXX_SMUX_TX_CTL(a,b) 0x0 /* PF_BAR0 */
13297 #define busnum_BDK_BGXX_SMUX_TX_CTL(a,b) (a)
13298 #define arguments_BDK_BGXX_SMUX_TX_CTL(a,b) (a),(b),-1,-1
13299 
13300 /**
13301  * Register (RSL) bgx#_smu#_tx_ifg
13302  *
13303  * BGX SMU TX Interframe-Gap Cycles Registers
13304  * Programming IFG1 and IFG2:
13305  * * For XAUI/RXAUI/10Gbs/40Gbs systems that require IEEE 802.3 compatibility, the IFG1+IFG2 sum
13306  * must be 12.
13307  * * In loopback mode, the IFG1+IFG2 of local and remote parties must match exactly; otherwise
13308  * one of the two sides' loopback FIFO will overrun: BGX()_SMU()_TX_INT[LB_OVRFLW].
13309  */
13310 union bdk_bgxx_smux_tx_ifg
13311 {
13312     uint64_t u;
13313     struct bdk_bgxx_smux_tx_ifg_s
13314     {
13315 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13316         uint64_t reserved_8_63         : 56;
13317         uint64_t ifg2                  : 4;  /**< [  7:  4](R/W) 1/2 of the interframe gap timing (in IFG2*8 bits). */
13318         uint64_t ifg1                  : 4;  /**< [  3:  0](R/W) 1/2 of the interframe gap timing (in IFG1*8 bits). */
13319 #else /* Word 0 - Little Endian */
13320         uint64_t ifg1                  : 4;  /**< [  3:  0](R/W) 1/2 of the interframe gap timing (in IFG1*8 bits). */
13321         uint64_t ifg2                  : 4;  /**< [  7:  4](R/W) 1/2 of the interframe gap timing (in IFG2*8 bits). */
13322         uint64_t reserved_8_63         : 56;
13323 #endif /* Word 0 - End */
13324     } s;
13325     /* struct bdk_bgxx_smux_tx_ifg_s cn; */
13326 };
13327 typedef union bdk_bgxx_smux_tx_ifg bdk_bgxx_smux_tx_ifg_t;
13328 
13329 static inline uint64_t BDK_BGXX_SMUX_TX_IFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_IFG(unsigned long a,unsigned long b)13330 static inline uint64_t BDK_BGXX_SMUX_TX_IFG(unsigned long a, unsigned long b)
13331 {
13332     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13333         return 0x87e0e0020160ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13334     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13335         return 0x87e0e0020160ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13336     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13337         return 0x87e0e0020160ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13338     __bdk_csr_fatal("BGXX_SMUX_TX_IFG", 2, a, b, 0, 0);
13339 }
13340 
13341 #define typedef_BDK_BGXX_SMUX_TX_IFG(a,b) bdk_bgxx_smux_tx_ifg_t
13342 #define bustype_BDK_BGXX_SMUX_TX_IFG(a,b) BDK_CSR_TYPE_RSL
13343 #define basename_BDK_BGXX_SMUX_TX_IFG(a,b) "BGXX_SMUX_TX_IFG"
13344 #define device_bar_BDK_BGXX_SMUX_TX_IFG(a,b) 0x0 /* PF_BAR0 */
13345 #define busnum_BDK_BGXX_SMUX_TX_IFG(a,b) (a)
13346 #define arguments_BDK_BGXX_SMUX_TX_IFG(a,b) (a),(b),-1,-1
13347 
13348 /**
13349  * Register (RSL) bgx#_smu#_tx_int
13350  *
13351  * BGX SMU TX Interrupt Registers
13352  */
13353 union bdk_bgxx_smux_tx_int
13354 {
13355     uint64_t u;
13356     struct bdk_bgxx_smux_tx_int_s
13357     {
13358 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13359         uint64_t reserved_5_63         : 59;
13360         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1C/H) TX loopback overflow. */
13361         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1C/H) TX loopback underflow. */
13362         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1C/H) TX SMU started a packet with PTP on SOP and has not seen a commit for it from TX SPU after
13363                                                                  256 cycles so it faked a commit to CMR. */
13364         uint64_t xchange               : 1;  /**< [  1:  1](R/W1C/H) Link status changed. This denotes a change to BGX()_SMU()_RX_CTL[STATUS]. */
13365         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) TX underflow. */
13366 #else /* Word 0 - Little Endian */
13367         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) TX underflow. */
13368         uint64_t xchange               : 1;  /**< [  1:  1](R/W1C/H) Link status changed. This denotes a change to BGX()_SMU()_RX_CTL[STATUS]. */
13369         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1C/H) TX SMU started a packet with PTP on SOP and has not seen a commit for it from TX SPU after
13370                                                                  256 cycles so it faked a commit to CMR. */
13371         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1C/H) TX loopback underflow. */
13372         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1C/H) TX loopback overflow. */
13373         uint64_t reserved_5_63         : 59;
13374 #endif /* Word 0 - End */
13375     } s;
13376     /* struct bdk_bgxx_smux_tx_int_s cn; */
13377 };
13378 typedef union bdk_bgxx_smux_tx_int bdk_bgxx_smux_tx_int_t;
13379 
13380 static inline uint64_t BDK_BGXX_SMUX_TX_INT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_INT(unsigned long a,unsigned long b)13381 static inline uint64_t BDK_BGXX_SMUX_TX_INT(unsigned long a, unsigned long b)
13382 {
13383     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13384         return 0x87e0e0020140ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13385     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13386         return 0x87e0e0020140ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13387     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13388         return 0x87e0e0020140ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13389     __bdk_csr_fatal("BGXX_SMUX_TX_INT", 2, a, b, 0, 0);
13390 }
13391 
13392 #define typedef_BDK_BGXX_SMUX_TX_INT(a,b) bdk_bgxx_smux_tx_int_t
13393 #define bustype_BDK_BGXX_SMUX_TX_INT(a,b) BDK_CSR_TYPE_RSL
13394 #define basename_BDK_BGXX_SMUX_TX_INT(a,b) "BGXX_SMUX_TX_INT"
13395 #define device_bar_BDK_BGXX_SMUX_TX_INT(a,b) 0x0 /* PF_BAR0 */
13396 #define busnum_BDK_BGXX_SMUX_TX_INT(a,b) (a)
13397 #define arguments_BDK_BGXX_SMUX_TX_INT(a,b) (a),(b),-1,-1
13398 
13399 /**
13400  * Register (RSL) bgx#_smu#_tx_int_ena_w1c
13401  *
13402  * BGX SMU TX Interrupt Enable Clear Registers
13403  * This register clears interrupt enable bits.
13404  */
13405 union bdk_bgxx_smux_tx_int_ena_w1c
13406 {
13407     uint64_t u;
13408     struct bdk_bgxx_smux_tx_int_ena_w1c_s
13409     {
13410 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13411         uint64_t reserved_5_63         : 59;
13412         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13413         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13414         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13415         uint64_t xchange               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[XCHANGE]. */
13416         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[UNDFLW]. */
13417 #else /* Word 0 - Little Endian */
13418         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[UNDFLW]. */
13419         uint64_t xchange               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[XCHANGE]. */
13420         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13421         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13422         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13423         uint64_t reserved_5_63         : 59;
13424 #endif /* Word 0 - End */
13425     } s;
13426     /* struct bdk_bgxx_smux_tx_int_ena_w1c_s cn81xx; */
13427     /* struct bdk_bgxx_smux_tx_int_ena_w1c_s cn88xx; */
13428     struct bdk_bgxx_smux_tx_int_ena_w1c_cn83xx
13429     {
13430 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13431         uint64_t reserved_5_63         : 59;
13432         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13433         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13434         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13435         uint64_t xchange               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[XCHANGE]. */
13436         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[UNDFLW]. */
13437 #else /* Word 0 - Little Endian */
13438         uint64_t undflw                : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[UNDFLW]. */
13439         uint64_t xchange               : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[XCHANGE]. */
13440         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13441         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13442         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13443         uint64_t reserved_5_63         : 59;
13444 #endif /* Word 0 - End */
13445     } cn83xx;
13446 };
13447 typedef union bdk_bgxx_smux_tx_int_ena_w1c bdk_bgxx_smux_tx_int_ena_w1c_t;
13448 
13449 static inline uint64_t BDK_BGXX_SMUX_TX_INT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_INT_ENA_W1C(unsigned long a,unsigned long b)13450 static inline uint64_t BDK_BGXX_SMUX_TX_INT_ENA_W1C(unsigned long a, unsigned long b)
13451 {
13452     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13453         return 0x87e0e0020150ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13454     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13455         return 0x87e0e0020150ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13456     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13457         return 0x87e0e0020150ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13458     __bdk_csr_fatal("BGXX_SMUX_TX_INT_ENA_W1C", 2, a, b, 0, 0);
13459 }
13460 
13461 #define typedef_BDK_BGXX_SMUX_TX_INT_ENA_W1C(a,b) bdk_bgxx_smux_tx_int_ena_w1c_t
13462 #define bustype_BDK_BGXX_SMUX_TX_INT_ENA_W1C(a,b) BDK_CSR_TYPE_RSL
13463 #define basename_BDK_BGXX_SMUX_TX_INT_ENA_W1C(a,b) "BGXX_SMUX_TX_INT_ENA_W1C"
13464 #define device_bar_BDK_BGXX_SMUX_TX_INT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
13465 #define busnum_BDK_BGXX_SMUX_TX_INT_ENA_W1C(a,b) (a)
13466 #define arguments_BDK_BGXX_SMUX_TX_INT_ENA_W1C(a,b) (a),(b),-1,-1
13467 
13468 /**
13469  * Register (RSL) bgx#_smu#_tx_int_ena_w1s
13470  *
13471  * BGX SMU TX Interrupt Enable Set Registers
13472  * This register sets interrupt enable bits.
13473  */
13474 union bdk_bgxx_smux_tx_int_ena_w1s
13475 {
13476     uint64_t u;
13477     struct bdk_bgxx_smux_tx_int_ena_w1s_s
13478     {
13479 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13480         uint64_t reserved_5_63         : 59;
13481         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13482         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13483         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13484         uint64_t xchange               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[XCHANGE]. */
13485         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[UNDFLW]. */
13486 #else /* Word 0 - Little Endian */
13487         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[UNDFLW]. */
13488         uint64_t xchange               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[XCHANGE]. */
13489         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13490         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13491         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13492         uint64_t reserved_5_63         : 59;
13493 #endif /* Word 0 - End */
13494     } s;
13495     /* struct bdk_bgxx_smux_tx_int_ena_w1s_s cn81xx; */
13496     /* struct bdk_bgxx_smux_tx_int_ena_w1s_s cn88xx; */
13497     struct bdk_bgxx_smux_tx_int_ena_w1s_cn83xx
13498     {
13499 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13500         uint64_t reserved_5_63         : 59;
13501         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13502         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13503         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13504         uint64_t xchange               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[XCHANGE]. */
13505         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[UNDFLW]. */
13506 #else /* Word 0 - Little Endian */
13507         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[UNDFLW]. */
13508         uint64_t xchange               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[XCHANGE]. */
13509         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13510         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13511         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13512         uint64_t reserved_5_63         : 59;
13513 #endif /* Word 0 - End */
13514     } cn83xx;
13515 };
13516 typedef union bdk_bgxx_smux_tx_int_ena_w1s bdk_bgxx_smux_tx_int_ena_w1s_t;
13517 
13518 static inline uint64_t BDK_BGXX_SMUX_TX_INT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_INT_ENA_W1S(unsigned long a,unsigned long b)13519 static inline uint64_t BDK_BGXX_SMUX_TX_INT_ENA_W1S(unsigned long a, unsigned long b)
13520 {
13521     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13522         return 0x87e0e0020158ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13523     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13524         return 0x87e0e0020158ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13525     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13526         return 0x87e0e0020158ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13527     __bdk_csr_fatal("BGXX_SMUX_TX_INT_ENA_W1S", 2, a, b, 0, 0);
13528 }
13529 
13530 #define typedef_BDK_BGXX_SMUX_TX_INT_ENA_W1S(a,b) bdk_bgxx_smux_tx_int_ena_w1s_t
13531 #define bustype_BDK_BGXX_SMUX_TX_INT_ENA_W1S(a,b) BDK_CSR_TYPE_RSL
13532 #define basename_BDK_BGXX_SMUX_TX_INT_ENA_W1S(a,b) "BGXX_SMUX_TX_INT_ENA_W1S"
13533 #define device_bar_BDK_BGXX_SMUX_TX_INT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
13534 #define busnum_BDK_BGXX_SMUX_TX_INT_ENA_W1S(a,b) (a)
13535 #define arguments_BDK_BGXX_SMUX_TX_INT_ENA_W1S(a,b) (a),(b),-1,-1
13536 
13537 /**
13538  * Register (RSL) bgx#_smu#_tx_int_w1s
13539  *
13540  * BGX SMU TX Interrupt Set Registers
13541  * This register sets interrupt bits.
13542  */
13543 union bdk_bgxx_smux_tx_int_w1s
13544 {
13545     uint64_t u;
13546     struct bdk_bgxx_smux_tx_int_w1s_s
13547     {
13548 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13549         uint64_t reserved_5_63         : 59;
13550         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13551         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13552         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13553         uint64_t xchange               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[XCHANGE]. */
13554         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[UNDFLW]. */
13555 #else /* Word 0 - Little Endian */
13556         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[UNDFLW]. */
13557         uint64_t xchange               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[XCHANGE]. */
13558         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13559         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13560         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13561         uint64_t reserved_5_63         : 59;
13562 #endif /* Word 0 - End */
13563     } s;
13564     /* struct bdk_bgxx_smux_tx_int_w1s_s cn81xx; */
13565     /* struct bdk_bgxx_smux_tx_int_w1s_s cn88xx; */
13566     struct bdk_bgxx_smux_tx_int_w1s_cn83xx
13567     {
13568 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13569         uint64_t reserved_5_63         : 59;
13570         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13571         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13572         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13573         uint64_t xchange               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[XCHANGE]. */
13574         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[UNDFLW]. */
13575 #else /* Word 0 - Little Endian */
13576         uint64_t undflw                : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[UNDFLW]. */
13577         uint64_t xchange               : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[XCHANGE]. */
13578         uint64_t fake_commit           : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[FAKE_COMMIT]. */
13579         uint64_t lb_undflw             : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[LB_UNDFLW]. */
13580         uint64_t lb_ovrflw             : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_SMU(0..3)_TX_INT[LB_OVRFLW]. */
13581         uint64_t reserved_5_63         : 59;
13582 #endif /* Word 0 - End */
13583     } cn83xx;
13584 };
13585 typedef union bdk_bgxx_smux_tx_int_w1s bdk_bgxx_smux_tx_int_w1s_t;
13586 
13587 static inline uint64_t BDK_BGXX_SMUX_TX_INT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_INT_W1S(unsigned long a,unsigned long b)13588 static inline uint64_t BDK_BGXX_SMUX_TX_INT_W1S(unsigned long a, unsigned long b)
13589 {
13590     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13591         return 0x87e0e0020148ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13592     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13593         return 0x87e0e0020148ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13594     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13595         return 0x87e0e0020148ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13596     __bdk_csr_fatal("BGXX_SMUX_TX_INT_W1S", 2, a, b, 0, 0);
13597 }
13598 
13599 #define typedef_BDK_BGXX_SMUX_TX_INT_W1S(a,b) bdk_bgxx_smux_tx_int_w1s_t
13600 #define bustype_BDK_BGXX_SMUX_TX_INT_W1S(a,b) BDK_CSR_TYPE_RSL
13601 #define basename_BDK_BGXX_SMUX_TX_INT_W1S(a,b) "BGXX_SMUX_TX_INT_W1S"
13602 #define device_bar_BDK_BGXX_SMUX_TX_INT_W1S(a,b) 0x0 /* PF_BAR0 */
13603 #define busnum_BDK_BGXX_SMUX_TX_INT_W1S(a,b) (a)
13604 #define arguments_BDK_BGXX_SMUX_TX_INT_W1S(a,b) (a),(b),-1,-1
13605 
13606 /**
13607  * Register (RSL) bgx#_smu#_tx_min_pkt
13608  *
13609  * BGX SMU TX Minimum-Size-Packet Registers
13610  */
13611 union bdk_bgxx_smux_tx_min_pkt
13612 {
13613     uint64_t u;
13614     struct bdk_bgxx_smux_tx_min_pkt_s
13615     {
13616 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13617         uint64_t reserved_8_63         : 56;
13618         uint64_t min_size              : 8;  /**< [  7:  0](R/W) Min frame in bytes inclusive of FCS, if applied. Padding is only appended when
13619                                                                  BGX()_SMU()_TX_APPEND[PAD] for the corresponding port is set. When FCS is added to
13620                                                                  a packet which was padded, the FCS always appears in the four octets preceding /T/ or /E/. */
13621 #else /* Word 0 - Little Endian */
13622         uint64_t min_size              : 8;  /**< [  7:  0](R/W) Min frame in bytes inclusive of FCS, if applied. Padding is only appended when
13623                                                                  BGX()_SMU()_TX_APPEND[PAD] for the corresponding port is set. When FCS is added to
13624                                                                  a packet which was padded, the FCS always appears in the four octets preceding /T/ or /E/. */
13625         uint64_t reserved_8_63         : 56;
13626 #endif /* Word 0 - End */
13627     } s;
13628     /* struct bdk_bgxx_smux_tx_min_pkt_s cn; */
13629 };
13630 typedef union bdk_bgxx_smux_tx_min_pkt bdk_bgxx_smux_tx_min_pkt_t;
13631 
13632 static inline uint64_t BDK_BGXX_SMUX_TX_MIN_PKT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_MIN_PKT(unsigned long a,unsigned long b)13633 static inline uint64_t BDK_BGXX_SMUX_TX_MIN_PKT(unsigned long a, unsigned long b)
13634 {
13635     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13636         return 0x87e0e0020118ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13637     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13638         return 0x87e0e0020118ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13639     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13640         return 0x87e0e0020118ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13641     __bdk_csr_fatal("BGXX_SMUX_TX_MIN_PKT", 2, a, b, 0, 0);
13642 }
13643 
13644 #define typedef_BDK_BGXX_SMUX_TX_MIN_PKT(a,b) bdk_bgxx_smux_tx_min_pkt_t
13645 #define bustype_BDK_BGXX_SMUX_TX_MIN_PKT(a,b) BDK_CSR_TYPE_RSL
13646 #define basename_BDK_BGXX_SMUX_TX_MIN_PKT(a,b) "BGXX_SMUX_TX_MIN_PKT"
13647 #define device_bar_BDK_BGXX_SMUX_TX_MIN_PKT(a,b) 0x0 /* PF_BAR0 */
13648 #define busnum_BDK_BGXX_SMUX_TX_MIN_PKT(a,b) (a)
13649 #define arguments_BDK_BGXX_SMUX_TX_MIN_PKT(a,b) (a),(b),-1,-1
13650 
13651 /**
13652  * Register (RSL) bgx#_smu#_tx_pause_pkt_dmac
13653  *
13654  * BGX SMU TX PAUSE-Packet DMAC-Field Registers
13655  * This register provides the DMAC value that is placed in outbound PAUSE packets.
13656  */
13657 union bdk_bgxx_smux_tx_pause_pkt_dmac
13658 {
13659     uint64_t u;
13660     struct bdk_bgxx_smux_tx_pause_pkt_dmac_s
13661     {
13662 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13663         uint64_t reserved_48_63        : 16;
13664         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) The DMAC field that is placed in outbound PAUSE packets. */
13665 #else /* Word 0 - Little Endian */
13666         uint64_t dmac                  : 48; /**< [ 47:  0](R/W) The DMAC field that is placed in outbound PAUSE packets. */
13667         uint64_t reserved_48_63        : 16;
13668 #endif /* Word 0 - End */
13669     } s;
13670     /* struct bdk_bgxx_smux_tx_pause_pkt_dmac_s cn; */
13671 };
13672 typedef union bdk_bgxx_smux_tx_pause_pkt_dmac bdk_bgxx_smux_tx_pause_pkt_dmac_t;
13673 
13674 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_PKT_DMAC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_PAUSE_PKT_DMAC(unsigned long a,unsigned long b)13675 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_PKT_DMAC(unsigned long a, unsigned long b)
13676 {
13677     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13678         return 0x87e0e0020168ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13679     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13680         return 0x87e0e0020168ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13681     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13682         return 0x87e0e0020168ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13683     __bdk_csr_fatal("BGXX_SMUX_TX_PAUSE_PKT_DMAC", 2, a, b, 0, 0);
13684 }
13685 
13686 #define typedef_BDK_BGXX_SMUX_TX_PAUSE_PKT_DMAC(a,b) bdk_bgxx_smux_tx_pause_pkt_dmac_t
13687 #define bustype_BDK_BGXX_SMUX_TX_PAUSE_PKT_DMAC(a,b) BDK_CSR_TYPE_RSL
13688 #define basename_BDK_BGXX_SMUX_TX_PAUSE_PKT_DMAC(a,b) "BGXX_SMUX_TX_PAUSE_PKT_DMAC"
13689 #define device_bar_BDK_BGXX_SMUX_TX_PAUSE_PKT_DMAC(a,b) 0x0 /* PF_BAR0 */
13690 #define busnum_BDK_BGXX_SMUX_TX_PAUSE_PKT_DMAC(a,b) (a)
13691 #define arguments_BDK_BGXX_SMUX_TX_PAUSE_PKT_DMAC(a,b) (a),(b),-1,-1
13692 
13693 /**
13694  * Register (RSL) bgx#_smu#_tx_pause_pkt_interval
13695  *
13696  * BGX SMU TX PAUSE-Packet Transmission-Interval Registers
13697  * This register specifies how often PAUSE packets are sent.
13698  */
13699 union bdk_bgxx_smux_tx_pause_pkt_interval
13700 {
13701     uint64_t u;
13702     struct bdk_bgxx_smux_tx_pause_pkt_interval_s
13703     {
13704 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13705         uint64_t reserved_33_63        : 31;
13706         uint64_t hg2_intra_en          : 1;  /**< [ 32: 32](R/W) Allow intrapacket HiGig2 message generation. Relevant only if HiGig2 message generation is enabled. */
13707         uint64_t hg2_intra_interval    : 16; /**< [ 31: 16](R/W) Arbitrate for a HiGig2 message, every (INTERVAL*512) bit-times whilst sending regular
13708                                                                  packet data. Relevant only if HiGig2 message generation and [HG2_INTRA_EN] are both set.
13709                                                                  Normally, 0 \< INTERVAL \< BGX()_SMU()_TX_PAUSE_PKT_TIME.
13710 
13711                                                                  INTERVAL = 0 only sends a single PAUSE packet for each backpressure event. */
13712         uint64_t interval              : 16; /**< [ 15:  0](R/W) Arbitrate for a 802.3 PAUSE packet, HiGig2 message, or PFC packet every
13713                                                                  (INTERVAL * 512) bit-times.
13714                                                                  Normally, 0 \< INTERVAL \< BGX()_SMU()_TX_PAUSE_PKT_TIME[P_TIME].
13715 
13716                                                                  INTERVAL = 0 only sends a single PAUSE packet for each backpressure event. */
13717 #else /* Word 0 - Little Endian */
13718         uint64_t interval              : 16; /**< [ 15:  0](R/W) Arbitrate for a 802.3 PAUSE packet, HiGig2 message, or PFC packet every
13719                                                                  (INTERVAL * 512) bit-times.
13720                                                                  Normally, 0 \< INTERVAL \< BGX()_SMU()_TX_PAUSE_PKT_TIME[P_TIME].
13721 
13722                                                                  INTERVAL = 0 only sends a single PAUSE packet for each backpressure event. */
13723         uint64_t hg2_intra_interval    : 16; /**< [ 31: 16](R/W) Arbitrate for a HiGig2 message, every (INTERVAL*512) bit-times whilst sending regular
13724                                                                  packet data. Relevant only if HiGig2 message generation and [HG2_INTRA_EN] are both set.
13725                                                                  Normally, 0 \< INTERVAL \< BGX()_SMU()_TX_PAUSE_PKT_TIME.
13726 
13727                                                                  INTERVAL = 0 only sends a single PAUSE packet for each backpressure event. */
13728         uint64_t hg2_intra_en          : 1;  /**< [ 32: 32](R/W) Allow intrapacket HiGig2 message generation. Relevant only if HiGig2 message generation is enabled. */
13729         uint64_t reserved_33_63        : 31;
13730 #endif /* Word 0 - End */
13731     } s;
13732     /* struct bdk_bgxx_smux_tx_pause_pkt_interval_s cn; */
13733 };
13734 typedef union bdk_bgxx_smux_tx_pause_pkt_interval bdk_bgxx_smux_tx_pause_pkt_interval_t;
13735 
13736 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(unsigned long a,unsigned long b)13737 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(unsigned long a, unsigned long b)
13738 {
13739     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13740         return 0x87e0e0020120ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13741     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13742         return 0x87e0e0020120ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13743     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13744         return 0x87e0e0020120ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13745     __bdk_csr_fatal("BGXX_SMUX_TX_PAUSE_PKT_INTERVAL", 2, a, b, 0, 0);
13746 }
13747 
13748 #define typedef_BDK_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(a,b) bdk_bgxx_smux_tx_pause_pkt_interval_t
13749 #define bustype_BDK_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(a,b) BDK_CSR_TYPE_RSL
13750 #define basename_BDK_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(a,b) "BGXX_SMUX_TX_PAUSE_PKT_INTERVAL"
13751 #define device_bar_BDK_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(a,b) 0x0 /* PF_BAR0 */
13752 #define busnum_BDK_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(a,b) (a)
13753 #define arguments_BDK_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(a,b) (a),(b),-1,-1
13754 
13755 /**
13756  * Register (RSL) bgx#_smu#_tx_pause_pkt_time
13757  *
13758  * BGX SMU TX PAUSE Packet Time Registers
13759  */
13760 union bdk_bgxx_smux_tx_pause_pkt_time
13761 {
13762     uint64_t u;
13763     struct bdk_bgxx_smux_tx_pause_pkt_time_s
13764     {
13765 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13766         uint64_t reserved_16_63        : 48;
13767         uint64_t p_time                : 16; /**< [ 15:  0](R/W) Provides the pause_time field placed in outbound 802.3 PAUSE packets, HiGig2 messages, or
13768                                                                  PFC packets in 512 bit-times. Normally, [P_TIME] \>
13769                                                                  BGX()_SMU()_TX_PAUSE_PKT_INTERVAL[INTERVAL]. See programming notes in
13770                                                                  BGX()_SMU()_TX_PAUSE_PKT_INTERVAL. */
13771 #else /* Word 0 - Little Endian */
13772         uint64_t p_time                : 16; /**< [ 15:  0](R/W) Provides the pause_time field placed in outbound 802.3 PAUSE packets, HiGig2 messages, or
13773                                                                  PFC packets in 512 bit-times. Normally, [P_TIME] \>
13774                                                                  BGX()_SMU()_TX_PAUSE_PKT_INTERVAL[INTERVAL]. See programming notes in
13775                                                                  BGX()_SMU()_TX_PAUSE_PKT_INTERVAL. */
13776         uint64_t reserved_16_63        : 48;
13777 #endif /* Word 0 - End */
13778     } s;
13779     /* struct bdk_bgxx_smux_tx_pause_pkt_time_s cn; */
13780 };
13781 typedef union bdk_bgxx_smux_tx_pause_pkt_time bdk_bgxx_smux_tx_pause_pkt_time_t;
13782 
13783 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_PKT_TIME(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_PAUSE_PKT_TIME(unsigned long a,unsigned long b)13784 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_PKT_TIME(unsigned long a, unsigned long b)
13785 {
13786     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13787         return 0x87e0e0020110ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13788     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13789         return 0x87e0e0020110ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13790     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13791         return 0x87e0e0020110ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13792     __bdk_csr_fatal("BGXX_SMUX_TX_PAUSE_PKT_TIME", 2, a, b, 0, 0);
13793 }
13794 
13795 #define typedef_BDK_BGXX_SMUX_TX_PAUSE_PKT_TIME(a,b) bdk_bgxx_smux_tx_pause_pkt_time_t
13796 #define bustype_BDK_BGXX_SMUX_TX_PAUSE_PKT_TIME(a,b) BDK_CSR_TYPE_RSL
13797 #define basename_BDK_BGXX_SMUX_TX_PAUSE_PKT_TIME(a,b) "BGXX_SMUX_TX_PAUSE_PKT_TIME"
13798 #define device_bar_BDK_BGXX_SMUX_TX_PAUSE_PKT_TIME(a,b) 0x0 /* PF_BAR0 */
13799 #define busnum_BDK_BGXX_SMUX_TX_PAUSE_PKT_TIME(a,b) (a)
13800 #define arguments_BDK_BGXX_SMUX_TX_PAUSE_PKT_TIME(a,b) (a),(b),-1,-1
13801 
13802 /**
13803  * Register (RSL) bgx#_smu#_tx_pause_pkt_type
13804  *
13805  * BGX SMU TX PAUSE-Packet P_TYPE-Field Registers
13806  * This register provides the P_TYPE field that is placed in outbound PAUSE packets.
13807  */
13808 union bdk_bgxx_smux_tx_pause_pkt_type
13809 {
13810     uint64_t u;
13811     struct bdk_bgxx_smux_tx_pause_pkt_type_s
13812     {
13813 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13814         uint64_t reserved_16_63        : 48;
13815         uint64_t p_type                : 16; /**< [ 15:  0](R/W) The P_TYPE field that is placed in outbound PAUSE packets. */
13816 #else /* Word 0 - Little Endian */
13817         uint64_t p_type                : 16; /**< [ 15:  0](R/W) The P_TYPE field that is placed in outbound PAUSE packets. */
13818         uint64_t reserved_16_63        : 48;
13819 #endif /* Word 0 - End */
13820     } s;
13821     /* struct bdk_bgxx_smux_tx_pause_pkt_type_s cn; */
13822 };
13823 typedef union bdk_bgxx_smux_tx_pause_pkt_type bdk_bgxx_smux_tx_pause_pkt_type_t;
13824 
13825 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_PKT_TYPE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_PAUSE_PKT_TYPE(unsigned long a,unsigned long b)13826 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_PKT_TYPE(unsigned long a, unsigned long b)
13827 {
13828     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13829         return 0x87e0e0020170ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13830     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13831         return 0x87e0e0020170ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13832     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13833         return 0x87e0e0020170ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13834     __bdk_csr_fatal("BGXX_SMUX_TX_PAUSE_PKT_TYPE", 2, a, b, 0, 0);
13835 }
13836 
13837 #define typedef_BDK_BGXX_SMUX_TX_PAUSE_PKT_TYPE(a,b) bdk_bgxx_smux_tx_pause_pkt_type_t
13838 #define bustype_BDK_BGXX_SMUX_TX_PAUSE_PKT_TYPE(a,b) BDK_CSR_TYPE_RSL
13839 #define basename_BDK_BGXX_SMUX_TX_PAUSE_PKT_TYPE(a,b) "BGXX_SMUX_TX_PAUSE_PKT_TYPE"
13840 #define device_bar_BDK_BGXX_SMUX_TX_PAUSE_PKT_TYPE(a,b) 0x0 /* PF_BAR0 */
13841 #define busnum_BDK_BGXX_SMUX_TX_PAUSE_PKT_TYPE(a,b) (a)
13842 #define arguments_BDK_BGXX_SMUX_TX_PAUSE_PKT_TYPE(a,b) (a),(b),-1,-1
13843 
13844 /**
13845  * Register (RSL) bgx#_smu#_tx_pause_togo
13846  *
13847  * BGX SMU TX Time-to-Backpressure Registers
13848  */
13849 union bdk_bgxx_smux_tx_pause_togo
13850 {
13851     uint64_t u;
13852     struct bdk_bgxx_smux_tx_pause_togo_s
13853     {
13854 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13855         uint64_t reserved_32_63        : 32;
13856         uint64_t msg_time              : 16; /**< [ 31: 16](RO/H) Amount of time remaining to backpressure, from the HiGig2 physical message PAUSE timer
13857                                                                  (only valid on port0). */
13858         uint64_t p_time                : 16; /**< [ 15:  0](RO/H) Amount of time remaining to backpressure, from the standard 802.3 PAUSE timer. */
13859 #else /* Word 0 - Little Endian */
13860         uint64_t p_time                : 16; /**< [ 15:  0](RO/H) Amount of time remaining to backpressure, from the standard 802.3 PAUSE timer. */
13861         uint64_t msg_time              : 16; /**< [ 31: 16](RO/H) Amount of time remaining to backpressure, from the HiGig2 physical message PAUSE timer
13862                                                                  (only valid on port0). */
13863         uint64_t reserved_32_63        : 32;
13864 #endif /* Word 0 - End */
13865     } s;
13866     /* struct bdk_bgxx_smux_tx_pause_togo_s cn; */
13867 };
13868 typedef union bdk_bgxx_smux_tx_pause_togo bdk_bgxx_smux_tx_pause_togo_t;
13869 
13870 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_TOGO(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_PAUSE_TOGO(unsigned long a,unsigned long b)13871 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_TOGO(unsigned long a, unsigned long b)
13872 {
13873     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13874         return 0x87e0e0020130ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13875     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13876         return 0x87e0e0020130ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13877     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13878         return 0x87e0e0020130ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13879     __bdk_csr_fatal("BGXX_SMUX_TX_PAUSE_TOGO", 2, a, b, 0, 0);
13880 }
13881 
13882 #define typedef_BDK_BGXX_SMUX_TX_PAUSE_TOGO(a,b) bdk_bgxx_smux_tx_pause_togo_t
13883 #define bustype_BDK_BGXX_SMUX_TX_PAUSE_TOGO(a,b) BDK_CSR_TYPE_RSL
13884 #define basename_BDK_BGXX_SMUX_TX_PAUSE_TOGO(a,b) "BGXX_SMUX_TX_PAUSE_TOGO"
13885 #define device_bar_BDK_BGXX_SMUX_TX_PAUSE_TOGO(a,b) 0x0 /* PF_BAR0 */
13886 #define busnum_BDK_BGXX_SMUX_TX_PAUSE_TOGO(a,b) (a)
13887 #define arguments_BDK_BGXX_SMUX_TX_PAUSE_TOGO(a,b) (a),(b),-1,-1
13888 
13889 /**
13890  * Register (RSL) bgx#_smu#_tx_pause_zero
13891  *
13892  * BGX SMU TX PAUSE Zero Registers
13893  */
13894 union bdk_bgxx_smux_tx_pause_zero
13895 {
13896     uint64_t u;
13897     struct bdk_bgxx_smux_tx_pause_zero_s
13898     {
13899 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13900         uint64_t reserved_1_63         : 63;
13901         uint64_t send                  : 1;  /**< [  0:  0](R/W) Send PAUSE-zero enable. When this bit is set, and the backpressure condition is clear, it
13902                                                                  allows sending a PAUSE packet with pause_time of 0 to enable the channel. */
13903 #else /* Word 0 - Little Endian */
13904         uint64_t send                  : 1;  /**< [  0:  0](R/W) Send PAUSE-zero enable. When this bit is set, and the backpressure condition is clear, it
13905                                                                  allows sending a PAUSE packet with pause_time of 0 to enable the channel. */
13906         uint64_t reserved_1_63         : 63;
13907 #endif /* Word 0 - End */
13908     } s;
13909     /* struct bdk_bgxx_smux_tx_pause_zero_s cn; */
13910 };
13911 typedef union bdk_bgxx_smux_tx_pause_zero bdk_bgxx_smux_tx_pause_zero_t;
13912 
13913 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_ZERO(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_PAUSE_ZERO(unsigned long a,unsigned long b)13914 static inline uint64_t BDK_BGXX_SMUX_TX_PAUSE_ZERO(unsigned long a, unsigned long b)
13915 {
13916     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13917         return 0x87e0e0020138ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13918     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13919         return 0x87e0e0020138ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13920     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13921         return 0x87e0e0020138ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13922     __bdk_csr_fatal("BGXX_SMUX_TX_PAUSE_ZERO", 2, a, b, 0, 0);
13923 }
13924 
13925 #define typedef_BDK_BGXX_SMUX_TX_PAUSE_ZERO(a,b) bdk_bgxx_smux_tx_pause_zero_t
13926 #define bustype_BDK_BGXX_SMUX_TX_PAUSE_ZERO(a,b) BDK_CSR_TYPE_RSL
13927 #define basename_BDK_BGXX_SMUX_TX_PAUSE_ZERO(a,b) "BGXX_SMUX_TX_PAUSE_ZERO"
13928 #define device_bar_BDK_BGXX_SMUX_TX_PAUSE_ZERO(a,b) 0x0 /* PF_BAR0 */
13929 #define busnum_BDK_BGXX_SMUX_TX_PAUSE_ZERO(a,b) (a)
13930 #define arguments_BDK_BGXX_SMUX_TX_PAUSE_ZERO(a,b) (a),(b),-1,-1
13931 
13932 /**
13933  * Register (RSL) bgx#_smu#_tx_soft_pause
13934  *
13935  * BGX SMU TX Soft PAUSE Registers
13936  */
13937 union bdk_bgxx_smux_tx_soft_pause
13938 {
13939     uint64_t u;
13940     struct bdk_bgxx_smux_tx_soft_pause_s
13941     {
13942 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13943         uint64_t reserved_16_63        : 48;
13944         uint64_t p_time                : 16; /**< [ 15:  0](R/W) Back off the TX bus for ([P_TIME] * 512) bit-times */
13945 #else /* Word 0 - Little Endian */
13946         uint64_t p_time                : 16; /**< [ 15:  0](R/W) Back off the TX bus for ([P_TIME] * 512) bit-times */
13947         uint64_t reserved_16_63        : 48;
13948 #endif /* Word 0 - End */
13949     } s;
13950     /* struct bdk_bgxx_smux_tx_soft_pause_s cn; */
13951 };
13952 typedef union bdk_bgxx_smux_tx_soft_pause bdk_bgxx_smux_tx_soft_pause_t;
13953 
13954 static inline uint64_t BDK_BGXX_SMUX_TX_SOFT_PAUSE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_SOFT_PAUSE(unsigned long a,unsigned long b)13955 static inline uint64_t BDK_BGXX_SMUX_TX_SOFT_PAUSE(unsigned long a, unsigned long b)
13956 {
13957     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
13958         return 0x87e0e0020128ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13959     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
13960         return 0x87e0e0020128ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
13961     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
13962         return 0x87e0e0020128ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
13963     __bdk_csr_fatal("BGXX_SMUX_TX_SOFT_PAUSE", 2, a, b, 0, 0);
13964 }
13965 
13966 #define typedef_BDK_BGXX_SMUX_TX_SOFT_PAUSE(a,b) bdk_bgxx_smux_tx_soft_pause_t
13967 #define bustype_BDK_BGXX_SMUX_TX_SOFT_PAUSE(a,b) BDK_CSR_TYPE_RSL
13968 #define basename_BDK_BGXX_SMUX_TX_SOFT_PAUSE(a,b) "BGXX_SMUX_TX_SOFT_PAUSE"
13969 #define device_bar_BDK_BGXX_SMUX_TX_SOFT_PAUSE(a,b) 0x0 /* PF_BAR0 */
13970 #define busnum_BDK_BGXX_SMUX_TX_SOFT_PAUSE(a,b) (a)
13971 #define arguments_BDK_BGXX_SMUX_TX_SOFT_PAUSE(a,b) (a),(b),-1,-1
13972 
13973 /**
13974  * Register (RSL) bgx#_smu#_tx_thresh
13975  *
13976  * BGX SMU TX Threshold Registers
13977  */
13978 union bdk_bgxx_smux_tx_thresh
13979 {
13980     uint64_t u;
13981     struct bdk_bgxx_smux_tx_thresh_s
13982     {
13983 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13984         uint64_t reserved_11_63        : 53;
13985         uint64_t cnt                   : 11; /**< [ 10:  0](R/W) Number of 128-bit words to accumulate in the TX FIFO before sending on the packet
13986                                                                  interface. This field should be large enough to prevent underflow on the packet interface
13987                                                                  and must never be set to 0x0.
13988 
13989                                                                  In all modes, this register cannot exceed the TX FIFO depth configured by
13990                                                                  BGX()_CMR_TX_LMACS[LMACS]. */
13991 #else /* Word 0 - Little Endian */
13992         uint64_t cnt                   : 11; /**< [ 10:  0](R/W) Number of 128-bit words to accumulate in the TX FIFO before sending on the packet
13993                                                                  interface. This field should be large enough to prevent underflow on the packet interface
13994                                                                  and must never be set to 0x0.
13995 
13996                                                                  In all modes, this register cannot exceed the TX FIFO depth configured by
13997                                                                  BGX()_CMR_TX_LMACS[LMACS]. */
13998         uint64_t reserved_11_63        : 53;
13999 #endif /* Word 0 - End */
14000     } s;
14001     /* struct bdk_bgxx_smux_tx_thresh_s cn; */
14002 };
14003 typedef union bdk_bgxx_smux_tx_thresh bdk_bgxx_smux_tx_thresh_t;
14004 
14005 static inline uint64_t BDK_BGXX_SMUX_TX_THRESH(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SMUX_TX_THRESH(unsigned long a,unsigned long b)14006 static inline uint64_t BDK_BGXX_SMUX_TX_THRESH(unsigned long a, unsigned long b)
14007 {
14008     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14009         return 0x87e0e0020180ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14010     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14011         return 0x87e0e0020180ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14012     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14013         return 0x87e0e0020180ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14014     __bdk_csr_fatal("BGXX_SMUX_TX_THRESH", 2, a, b, 0, 0);
14015 }
14016 
14017 #define typedef_BDK_BGXX_SMUX_TX_THRESH(a,b) bdk_bgxx_smux_tx_thresh_t
14018 #define bustype_BDK_BGXX_SMUX_TX_THRESH(a,b) BDK_CSR_TYPE_RSL
14019 #define basename_BDK_BGXX_SMUX_TX_THRESH(a,b) "BGXX_SMUX_TX_THRESH"
14020 #define device_bar_BDK_BGXX_SMUX_TX_THRESH(a,b) 0x0 /* PF_BAR0 */
14021 #define busnum_BDK_BGXX_SMUX_TX_THRESH(a,b) (a)
14022 #define arguments_BDK_BGXX_SMUX_TX_THRESH(a,b) (a),(b),-1,-1
14023 
14024 /**
14025  * Register (RSL) bgx#_spu#_an_adv
14026  *
14027  * BGX SPU Autonegotiation Advertisement Registers
14028  * Software programs this register with the contents of the AN-link code word base page to be
14029  * transmitted during autonegotiation. (See IEEE 802.3 section 73.6 for details.) Any write
14030  * operations to this register prior to completion of autonegotiation, as indicated by
14031  * BGX()_SPU()_AN_STATUS[AN_COMPLETE], should be followed by a renegotiation in order for
14032  * the new values to take effect. Renegotiation is initiated by setting
14033  * BGX()_SPU()_AN_CONTROL[AN_RESTART]. Once autonegotiation has completed, software can
14034  * examine this register along with BGX()_SPU()_AN_LP_BASE to determine the highest
14035  * common denominator technology.
14036  */
14037 union bdk_bgxx_spux_an_adv
14038 {
14039     uint64_t u;
14040     struct bdk_bgxx_spux_an_adv_s
14041     {
14042 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14043         uint64_t reserved_48_63        : 16;
14044         uint64_t fec_req               : 1;  /**< [ 47: 47](R/W) FEC requested. */
14045         uint64_t fec_able              : 1;  /**< [ 46: 46](R/W) FEC ability. */
14046         uint64_t arsv                  : 19; /**< [ 45: 27](R/W) Technology ability. Reserved bits, should always be 0. */
14047         uint64_t a100g_cr10            : 1;  /**< [ 26: 26](R/W) 100GBASE-CR10 ability. Should always be 0; 100GBASE-R is not supported. */
14048         uint64_t a40g_cr4              : 1;  /**< [ 25: 25](R/W) 40GBASE-CR4 ability. */
14049         uint64_t a40g_kr4              : 1;  /**< [ 24: 24](R/W) 40GBASE-KR4 ability. */
14050         uint64_t a10g_kr               : 1;  /**< [ 23: 23](R/W) 10GBASE-KR ability. */
14051         uint64_t a10g_kx4              : 1;  /**< [ 22: 22](R/W) 10GBASE-KX4 ability. */
14052         uint64_t a1g_kx                : 1;  /**< [ 21: 21](R/W) 1000BASE-KX ability. Should always be 0; autonegotiation is not supported for 1000Base-KX. */
14053         uint64_t t                     : 5;  /**< [ 20: 16](R/W/H) Transmitted nonce. This field is automatically updated with a pseudo-random value on entry
14054                                                                  to the AN ability detect state. */
14055         uint64_t np                    : 1;  /**< [ 15: 15](R/W) Next page. Always 0; extended next pages are not used for 10G+ autonegotiation. */
14056         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Acknowledge. Always 0 in this register. */
14057         uint64_t rf                    : 1;  /**< [ 13: 13](R/W) Remote fault. */
14058         uint64_t xnp_able              : 1;  /**< [ 12: 12](R/W) Extended next page ability. */
14059         uint64_t asm_dir               : 1;  /**< [ 11: 11](R/W) Asymmetric PAUSE. */
14060         uint64_t pause                 : 1;  /**< [ 10: 10](R/W) PAUSE ability. */
14061         uint64_t e                     : 5;  /**< [  9:  5](R/W) Echoed nonce. Provides the echoed-nonce value to use when ACK = 0 in transmitted DME page.
14062                                                                  Should always be 0x0. */
14063         uint64_t s                     : 5;  /**< [  4:  0](R/W) Selector. Should be 0x1 (encoding for IEEE 802.3). */
14064 #else /* Word 0 - Little Endian */
14065         uint64_t s                     : 5;  /**< [  4:  0](R/W) Selector. Should be 0x1 (encoding for IEEE 802.3). */
14066         uint64_t e                     : 5;  /**< [  9:  5](R/W) Echoed nonce. Provides the echoed-nonce value to use when ACK = 0 in transmitted DME page.
14067                                                                  Should always be 0x0. */
14068         uint64_t pause                 : 1;  /**< [ 10: 10](R/W) PAUSE ability. */
14069         uint64_t asm_dir               : 1;  /**< [ 11: 11](R/W) Asymmetric PAUSE. */
14070         uint64_t xnp_able              : 1;  /**< [ 12: 12](R/W) Extended next page ability. */
14071         uint64_t rf                    : 1;  /**< [ 13: 13](R/W) Remote fault. */
14072         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Acknowledge. Always 0 in this register. */
14073         uint64_t np                    : 1;  /**< [ 15: 15](R/W) Next page. Always 0; extended next pages are not used for 10G+ autonegotiation. */
14074         uint64_t t                     : 5;  /**< [ 20: 16](R/W/H) Transmitted nonce. This field is automatically updated with a pseudo-random value on entry
14075                                                                  to the AN ability detect state. */
14076         uint64_t a1g_kx                : 1;  /**< [ 21: 21](R/W) 1000BASE-KX ability. Should always be 0; autonegotiation is not supported for 1000Base-KX. */
14077         uint64_t a10g_kx4              : 1;  /**< [ 22: 22](R/W) 10GBASE-KX4 ability. */
14078         uint64_t a10g_kr               : 1;  /**< [ 23: 23](R/W) 10GBASE-KR ability. */
14079         uint64_t a40g_kr4              : 1;  /**< [ 24: 24](R/W) 40GBASE-KR4 ability. */
14080         uint64_t a40g_cr4              : 1;  /**< [ 25: 25](R/W) 40GBASE-CR4 ability. */
14081         uint64_t a100g_cr10            : 1;  /**< [ 26: 26](R/W) 100GBASE-CR10 ability. Should always be 0; 100GBASE-R is not supported. */
14082         uint64_t arsv                  : 19; /**< [ 45: 27](R/W) Technology ability. Reserved bits, should always be 0. */
14083         uint64_t fec_able              : 1;  /**< [ 46: 46](R/W) FEC ability. */
14084         uint64_t fec_req               : 1;  /**< [ 47: 47](R/W) FEC requested. */
14085         uint64_t reserved_48_63        : 16;
14086 #endif /* Word 0 - End */
14087     } s;
14088     /* struct bdk_bgxx_spux_an_adv_s cn; */
14089 };
14090 typedef union bdk_bgxx_spux_an_adv bdk_bgxx_spux_an_adv_t;
14091 
14092 static inline uint64_t BDK_BGXX_SPUX_AN_ADV(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_AN_ADV(unsigned long a,unsigned long b)14093 static inline uint64_t BDK_BGXX_SPUX_AN_ADV(unsigned long a, unsigned long b)
14094 {
14095     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14096         return 0x87e0e00100d8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14097     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14098         return 0x87e0e00100d8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14099     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14100         return 0x87e0e00100d8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14101     __bdk_csr_fatal("BGXX_SPUX_AN_ADV", 2, a, b, 0, 0);
14102 }
14103 
14104 #define typedef_BDK_BGXX_SPUX_AN_ADV(a,b) bdk_bgxx_spux_an_adv_t
14105 #define bustype_BDK_BGXX_SPUX_AN_ADV(a,b) BDK_CSR_TYPE_RSL
14106 #define basename_BDK_BGXX_SPUX_AN_ADV(a,b) "BGXX_SPUX_AN_ADV"
14107 #define device_bar_BDK_BGXX_SPUX_AN_ADV(a,b) 0x0 /* PF_BAR0 */
14108 #define busnum_BDK_BGXX_SPUX_AN_ADV(a,b) (a)
14109 #define arguments_BDK_BGXX_SPUX_AN_ADV(a,b) (a),(b),-1,-1
14110 
14111 /**
14112  * Register (RSL) bgx#_spu#_an_bp_status
14113  *
14114  * BGX SPU Autonegotiation Backplane Ethernet & BASE-R Copper Status Registers
14115  * The contents of this register are updated
14116  * during autonegotiation and are valid when BGX()_SPU()_AN_STATUS[AN_COMPLETE] is set.
14117  * At that time, one of the port type bits ([N100G_CR10], [N40G_CR4], [N40G_KR4], [N10G_KR],
14118  * [N10G_KX4],
14119  * [N1G_KX]) will be set depending on the AN priority resolution. If a BASE-R type is negotiated,
14120  * then [FEC] will be set to indicate that FEC operation has been negotiated, and will be
14121  * clear otherwise.
14122  */
14123 union bdk_bgxx_spux_an_bp_status
14124 {
14125     uint64_t u;
14126     struct bdk_bgxx_spux_an_bp_status_s
14127     {
14128 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14129         uint64_t reserved_9_63         : 55;
14130         uint64_t n100g_cr10            : 1;  /**< [  8:  8](RO/H) 100GBASE-CR10 negotiated; expected to always be 0; 100GBASE-R is not supported. */
14131         uint64_t reserved_7            : 1;
14132         uint64_t n40g_cr4              : 1;  /**< [  6:  6](RO/H) 40GBASE-CR4 negotiated. */
14133         uint64_t n40g_kr4              : 1;  /**< [  5:  5](RO/H) 40GBASE-KR4 negotiated. */
14134         uint64_t fec                   : 1;  /**< [  4:  4](RO/H) BASE-R FEC negotiated. */
14135         uint64_t n10g_kr               : 1;  /**< [  3:  3](RO/H) 10GBASE-KR negotiated. */
14136         uint64_t n10g_kx4              : 1;  /**< [  2:  2](RO/H) 10GBASE-KX4 or CX4 negotiated (XAUI). */
14137         uint64_t n1g_kx                : 1;  /**< [  1:  1](RO/H) 1000BASE-KX negotiated. */
14138         uint64_t bp_an_able            : 1;  /**< [  0:  0](RO) Backplane or BASE-R copper AN Ability; always 1. */
14139 #else /* Word 0 - Little Endian */
14140         uint64_t bp_an_able            : 1;  /**< [  0:  0](RO) Backplane or BASE-R copper AN Ability; always 1. */
14141         uint64_t n1g_kx                : 1;  /**< [  1:  1](RO/H) 1000BASE-KX negotiated. */
14142         uint64_t n10g_kx4              : 1;  /**< [  2:  2](RO/H) 10GBASE-KX4 or CX4 negotiated (XAUI). */
14143         uint64_t n10g_kr               : 1;  /**< [  3:  3](RO/H) 10GBASE-KR negotiated. */
14144         uint64_t fec                   : 1;  /**< [  4:  4](RO/H) BASE-R FEC negotiated. */
14145         uint64_t n40g_kr4              : 1;  /**< [  5:  5](RO/H) 40GBASE-KR4 negotiated. */
14146         uint64_t n40g_cr4              : 1;  /**< [  6:  6](RO/H) 40GBASE-CR4 negotiated. */
14147         uint64_t reserved_7            : 1;
14148         uint64_t n100g_cr10            : 1;  /**< [  8:  8](RO/H) 100GBASE-CR10 negotiated; expected to always be 0; 100GBASE-R is not supported. */
14149         uint64_t reserved_9_63         : 55;
14150 #endif /* Word 0 - End */
14151     } s;
14152     /* struct bdk_bgxx_spux_an_bp_status_s cn; */
14153 };
14154 typedef union bdk_bgxx_spux_an_bp_status bdk_bgxx_spux_an_bp_status_t;
14155 
14156 static inline uint64_t BDK_BGXX_SPUX_AN_BP_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_AN_BP_STATUS(unsigned long a,unsigned long b)14157 static inline uint64_t BDK_BGXX_SPUX_AN_BP_STATUS(unsigned long a, unsigned long b)
14158 {
14159     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14160         return 0x87e0e00100f8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14161     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14162         return 0x87e0e00100f8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14163     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14164         return 0x87e0e00100f8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14165     __bdk_csr_fatal("BGXX_SPUX_AN_BP_STATUS", 2, a, b, 0, 0);
14166 }
14167 
14168 #define typedef_BDK_BGXX_SPUX_AN_BP_STATUS(a,b) bdk_bgxx_spux_an_bp_status_t
14169 #define bustype_BDK_BGXX_SPUX_AN_BP_STATUS(a,b) BDK_CSR_TYPE_RSL
14170 #define basename_BDK_BGXX_SPUX_AN_BP_STATUS(a,b) "BGXX_SPUX_AN_BP_STATUS"
14171 #define device_bar_BDK_BGXX_SPUX_AN_BP_STATUS(a,b) 0x0 /* PF_BAR0 */
14172 #define busnum_BDK_BGXX_SPUX_AN_BP_STATUS(a,b) (a)
14173 #define arguments_BDK_BGXX_SPUX_AN_BP_STATUS(a,b) (a),(b),-1,-1
14174 
14175 /**
14176  * Register (RSL) bgx#_spu#_an_control
14177  *
14178  * BGX SPU Autonegotiation Control Registers
14179  */
14180 union bdk_bgxx_spux_an_control
14181 {
14182     uint64_t u;
14183     struct bdk_bgxx_spux_an_control_s
14184     {
14185 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14186         uint64_t reserved_16_63        : 48;
14187         uint64_t an_reset              : 1;  /**< [ 15: 15](R/W1S/H) Autonegotiation reset. Setting this bit or BGX()_SPU()_CONTROL1[RESET] to 1
14188                                                                  causes the following to happen:
14189                                                                  * Resets the logical PCS (LPCS)
14190                                                                  * Sets the IEEE 802.3 PCS, FEC and AN registers for the LPCS to their default states
14191                                                                  * Resets the associated SerDes lanes.
14192 
14193                                                                  It takes up to 32 coprocessor-clock cycles to reset the LPCS, after which RESET is
14194                                                                  automatically cleared. */
14195         uint64_t reserved_14           : 1;
14196         uint64_t xnp_en                : 1;  /**< [ 13: 13](R/W) Extended next-page enable. */
14197         uint64_t an_en                 : 1;  /**< [ 12: 12](R/W) Autonegotiation enable. This bit should not be set when
14198                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is set to RXAUI; autonegotiation is not supported
14199                                                                  in RXAUI mode. */
14200         uint64_t reserved_10_11        : 2;
14201         uint64_t an_restart            : 1;  /**< [  9:  9](R/W1S/H) Autonegotiation restart. Writing a 1 to this bit restarts the autonegotiation process if
14202                                                                  [AN_EN] is also set. This is a self-clearing bit. */
14203         uint64_t reserved_0_8          : 9;
14204 #else /* Word 0 - Little Endian */
14205         uint64_t reserved_0_8          : 9;
14206         uint64_t an_restart            : 1;  /**< [  9:  9](R/W1S/H) Autonegotiation restart. Writing a 1 to this bit restarts the autonegotiation process if
14207                                                                  [AN_EN] is also set. This is a self-clearing bit. */
14208         uint64_t reserved_10_11        : 2;
14209         uint64_t an_en                 : 1;  /**< [ 12: 12](R/W) Autonegotiation enable. This bit should not be set when
14210                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is set to RXAUI; autonegotiation is not supported
14211                                                                  in RXAUI mode. */
14212         uint64_t xnp_en                : 1;  /**< [ 13: 13](R/W) Extended next-page enable. */
14213         uint64_t reserved_14           : 1;
14214         uint64_t an_reset              : 1;  /**< [ 15: 15](R/W1S/H) Autonegotiation reset. Setting this bit or BGX()_SPU()_CONTROL1[RESET] to 1
14215                                                                  causes the following to happen:
14216                                                                  * Resets the logical PCS (LPCS)
14217                                                                  * Sets the IEEE 802.3 PCS, FEC and AN registers for the LPCS to their default states
14218                                                                  * Resets the associated SerDes lanes.
14219 
14220                                                                  It takes up to 32 coprocessor-clock cycles to reset the LPCS, after which RESET is
14221                                                                  automatically cleared. */
14222         uint64_t reserved_16_63        : 48;
14223 #endif /* Word 0 - End */
14224     } s;
14225     /* struct bdk_bgxx_spux_an_control_s cn; */
14226 };
14227 typedef union bdk_bgxx_spux_an_control bdk_bgxx_spux_an_control_t;
14228 
14229 static inline uint64_t BDK_BGXX_SPUX_AN_CONTROL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_AN_CONTROL(unsigned long a,unsigned long b)14230 static inline uint64_t BDK_BGXX_SPUX_AN_CONTROL(unsigned long a, unsigned long b)
14231 {
14232     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14233         return 0x87e0e00100c8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14234     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14235         return 0x87e0e00100c8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14236     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14237         return 0x87e0e00100c8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14238     __bdk_csr_fatal("BGXX_SPUX_AN_CONTROL", 2, a, b, 0, 0);
14239 }
14240 
14241 #define typedef_BDK_BGXX_SPUX_AN_CONTROL(a,b) bdk_bgxx_spux_an_control_t
14242 #define bustype_BDK_BGXX_SPUX_AN_CONTROL(a,b) BDK_CSR_TYPE_RSL
14243 #define basename_BDK_BGXX_SPUX_AN_CONTROL(a,b) "BGXX_SPUX_AN_CONTROL"
14244 #define device_bar_BDK_BGXX_SPUX_AN_CONTROL(a,b) 0x0 /* PF_BAR0 */
14245 #define busnum_BDK_BGXX_SPUX_AN_CONTROL(a,b) (a)
14246 #define arguments_BDK_BGXX_SPUX_AN_CONTROL(a,b) (a),(b),-1,-1
14247 
14248 /**
14249  * Register (RSL) bgx#_spu#_an_lp_base
14250  *
14251  * BGX SPU Autonegotiation Link-Partner Base-Page Ability Registers
14252  * This register captures the contents of the latest AN link code word base page received from
14253  * the link partner during autonegotiation. (See IEEE 802.3 section 73.6 for details.)
14254  * BGX()_SPU()_AN_STATUS[PAGE_RX] is set when this register is updated by hardware.
14255  */
14256 union bdk_bgxx_spux_an_lp_base
14257 {
14258     uint64_t u;
14259     struct bdk_bgxx_spux_an_lp_base_s
14260     {
14261 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14262         uint64_t reserved_48_63        : 16;
14263         uint64_t fec_req               : 1;  /**< [ 47: 47](RO/H) FEC requested. */
14264         uint64_t fec_able              : 1;  /**< [ 46: 46](RO/H) FEC ability. */
14265         uint64_t arsv                  : 19; /**< [ 45: 27](RO/H) Technology ability. Reserved bits, should always be 0. */
14266         uint64_t a100g_cr10            : 1;  /**< [ 26: 26](RO/H) 100GBASE-CR10 ability. */
14267         uint64_t a40g_cr4              : 1;  /**< [ 25: 25](RO/H) 40GBASE-CR4 ability. */
14268         uint64_t a40g_kr4              : 1;  /**< [ 24: 24](RO/H) 40GBASE-KR4 ability. */
14269         uint64_t a10g_kr               : 1;  /**< [ 23: 23](RO/H) 10GBASE-KR ability. */
14270         uint64_t a10g_kx4              : 1;  /**< [ 22: 22](RO/H) 10GBASE-KX4 ability. */
14271         uint64_t a1g_kx                : 1;  /**< [ 21: 21](RO/H) 1000BASE-KX ability. */
14272         uint64_t t                     : 5;  /**< [ 20: 16](RO/H) Transmitted nonce. */
14273         uint64_t np                    : 1;  /**< [ 15: 15](RO/H) Next page. */
14274         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Acknowledge. */
14275         uint64_t rf                    : 1;  /**< [ 13: 13](RO/H) Remote fault. */
14276         uint64_t xnp_able              : 1;  /**< [ 12: 12](RO/H) Extended next page ability. */
14277         uint64_t asm_dir               : 1;  /**< [ 11: 11](RO/H) Asymmetric PAUSE. */
14278         uint64_t pause                 : 1;  /**< [ 10: 10](RO/H) PAUSE ability. */
14279         uint64_t e                     : 5;  /**< [  9:  5](RO/H) Echoed nonce. */
14280         uint64_t s                     : 5;  /**< [  4:  0](RO/H) Selector. */
14281 #else /* Word 0 - Little Endian */
14282         uint64_t s                     : 5;  /**< [  4:  0](RO/H) Selector. */
14283         uint64_t e                     : 5;  /**< [  9:  5](RO/H) Echoed nonce. */
14284         uint64_t pause                 : 1;  /**< [ 10: 10](RO/H) PAUSE ability. */
14285         uint64_t asm_dir               : 1;  /**< [ 11: 11](RO/H) Asymmetric PAUSE. */
14286         uint64_t xnp_able              : 1;  /**< [ 12: 12](RO/H) Extended next page ability. */
14287         uint64_t rf                    : 1;  /**< [ 13: 13](RO/H) Remote fault. */
14288         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Acknowledge. */
14289         uint64_t np                    : 1;  /**< [ 15: 15](RO/H) Next page. */
14290         uint64_t t                     : 5;  /**< [ 20: 16](RO/H) Transmitted nonce. */
14291         uint64_t a1g_kx                : 1;  /**< [ 21: 21](RO/H) 1000BASE-KX ability. */
14292         uint64_t a10g_kx4              : 1;  /**< [ 22: 22](RO/H) 10GBASE-KX4 ability. */
14293         uint64_t a10g_kr               : 1;  /**< [ 23: 23](RO/H) 10GBASE-KR ability. */
14294         uint64_t a40g_kr4              : 1;  /**< [ 24: 24](RO/H) 40GBASE-KR4 ability. */
14295         uint64_t a40g_cr4              : 1;  /**< [ 25: 25](RO/H) 40GBASE-CR4 ability. */
14296         uint64_t a100g_cr10            : 1;  /**< [ 26: 26](RO/H) 100GBASE-CR10 ability. */
14297         uint64_t arsv                  : 19; /**< [ 45: 27](RO/H) Technology ability. Reserved bits, should always be 0. */
14298         uint64_t fec_able              : 1;  /**< [ 46: 46](RO/H) FEC ability. */
14299         uint64_t fec_req               : 1;  /**< [ 47: 47](RO/H) FEC requested. */
14300         uint64_t reserved_48_63        : 16;
14301 #endif /* Word 0 - End */
14302     } s;
14303     /* struct bdk_bgxx_spux_an_lp_base_s cn; */
14304 };
14305 typedef union bdk_bgxx_spux_an_lp_base bdk_bgxx_spux_an_lp_base_t;
14306 
14307 static inline uint64_t BDK_BGXX_SPUX_AN_LP_BASE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_AN_LP_BASE(unsigned long a,unsigned long b)14308 static inline uint64_t BDK_BGXX_SPUX_AN_LP_BASE(unsigned long a, unsigned long b)
14309 {
14310     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14311         return 0x87e0e00100e0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14312     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14313         return 0x87e0e00100e0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14314     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14315         return 0x87e0e00100e0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14316     __bdk_csr_fatal("BGXX_SPUX_AN_LP_BASE", 2, a, b, 0, 0);
14317 }
14318 
14319 #define typedef_BDK_BGXX_SPUX_AN_LP_BASE(a,b) bdk_bgxx_spux_an_lp_base_t
14320 #define bustype_BDK_BGXX_SPUX_AN_LP_BASE(a,b) BDK_CSR_TYPE_RSL
14321 #define basename_BDK_BGXX_SPUX_AN_LP_BASE(a,b) "BGXX_SPUX_AN_LP_BASE"
14322 #define device_bar_BDK_BGXX_SPUX_AN_LP_BASE(a,b) 0x0 /* PF_BAR0 */
14323 #define busnum_BDK_BGXX_SPUX_AN_LP_BASE(a,b) (a)
14324 #define arguments_BDK_BGXX_SPUX_AN_LP_BASE(a,b) (a),(b),-1,-1
14325 
14326 /**
14327  * Register (RSL) bgx#_spu#_an_lp_xnp
14328  *
14329  * BGX SPU Autonegotiation Link Partner Extended Next Page Ability Registers
14330  * This register captures the contents of the latest next page code word received from the link
14331  * partner during autonegotiation, if any. See section 802.3 section 73.7.7 for details.
14332  */
14333 union bdk_bgxx_spux_an_lp_xnp
14334 {
14335     uint64_t u;
14336     struct bdk_bgxx_spux_an_lp_xnp_s
14337     {
14338 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14339         uint64_t reserved_48_63        : 16;
14340         uint64_t u                     : 32; /**< [ 47: 16](RO/H) Unformatted code field. */
14341         uint64_t np                    : 1;  /**< [ 15: 15](RO/H) Next page. */
14342         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Acknowledge. */
14343         uint64_t mp                    : 1;  /**< [ 13: 13](RO/H) Message page. */
14344         uint64_t ack2                  : 1;  /**< [ 12: 12](RO/H) Acknowledge 2. */
14345         uint64_t toggle                : 1;  /**< [ 11: 11](RO/H) Toggle. */
14346         uint64_t m_u                   : 11; /**< [ 10:  0](RO/H) Message/unformatted code field. */
14347 #else /* Word 0 - Little Endian */
14348         uint64_t m_u                   : 11; /**< [ 10:  0](RO/H) Message/unformatted code field. */
14349         uint64_t toggle                : 1;  /**< [ 11: 11](RO/H) Toggle. */
14350         uint64_t ack2                  : 1;  /**< [ 12: 12](RO/H) Acknowledge 2. */
14351         uint64_t mp                    : 1;  /**< [ 13: 13](RO/H) Message page. */
14352         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Acknowledge. */
14353         uint64_t np                    : 1;  /**< [ 15: 15](RO/H) Next page. */
14354         uint64_t u                     : 32; /**< [ 47: 16](RO/H) Unformatted code field. */
14355         uint64_t reserved_48_63        : 16;
14356 #endif /* Word 0 - End */
14357     } s;
14358     /* struct bdk_bgxx_spux_an_lp_xnp_s cn; */
14359 };
14360 typedef union bdk_bgxx_spux_an_lp_xnp bdk_bgxx_spux_an_lp_xnp_t;
14361 
14362 static inline uint64_t BDK_BGXX_SPUX_AN_LP_XNP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_AN_LP_XNP(unsigned long a,unsigned long b)14363 static inline uint64_t BDK_BGXX_SPUX_AN_LP_XNP(unsigned long a, unsigned long b)
14364 {
14365     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14366         return 0x87e0e00100f0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14367     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14368         return 0x87e0e00100f0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14369     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14370         return 0x87e0e00100f0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14371     __bdk_csr_fatal("BGXX_SPUX_AN_LP_XNP", 2, a, b, 0, 0);
14372 }
14373 
14374 #define typedef_BDK_BGXX_SPUX_AN_LP_XNP(a,b) bdk_bgxx_spux_an_lp_xnp_t
14375 #define bustype_BDK_BGXX_SPUX_AN_LP_XNP(a,b) BDK_CSR_TYPE_RSL
14376 #define basename_BDK_BGXX_SPUX_AN_LP_XNP(a,b) "BGXX_SPUX_AN_LP_XNP"
14377 #define device_bar_BDK_BGXX_SPUX_AN_LP_XNP(a,b) 0x0 /* PF_BAR0 */
14378 #define busnum_BDK_BGXX_SPUX_AN_LP_XNP(a,b) (a)
14379 #define arguments_BDK_BGXX_SPUX_AN_LP_XNP(a,b) (a),(b),-1,-1
14380 
14381 /**
14382  * Register (RSL) bgx#_spu#_an_status
14383  *
14384  * BGX SPU Autonegotiation Status Registers
14385  */
14386 union bdk_bgxx_spux_an_status
14387 {
14388     uint64_t u;
14389     struct bdk_bgxx_spux_an_status_s
14390     {
14391 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14392         uint64_t reserved_10_63        : 54;
14393         uint64_t prl_flt               : 1;  /**< [  9:  9](RO) Parallel detection fault. Always 0; SPU does not support parallel detection as part of the
14394                                                                  autonegotiation protocol. */
14395         uint64_t reserved_8            : 1;
14396         uint64_t xnp_stat              : 1;  /**< [  7:  7](RO/H) Extended next-page status. */
14397         uint64_t page_rx               : 1;  /**< [  6:  6](R/W1C/H) Page received. This latching-high bit is set when a new page has been received and stored
14398                                                                  in BGX()_SPU()_AN_LP_BASE or BGX()_SPU()_AN_LP_XNP; stays set until a 1 is
14399                                                                  written by software, autonegotiation is disabled or restarted, or next page exchange is
14400                                                                  initiated. Note that in order to avoid read side effects, this is implemented as a
14401                                                                  write-1-to-clear bit, rather than latching high read-only as specified in 802.3. */
14402         uint64_t an_complete           : 1;  /**< [  5:  5](RO/H) Autonegotiation complete. Set when the autonegotiation process has been completed and
14403                                                                  the link is up and running using the negotiated highest common denominator (HCD)
14404                                                                  technology. If AN is enabled (BGX()_SPU()_AN_CONTROL[AN_EN] = 1) and this bit is
14405                                                                  read as a zero, it indicates that the AN process has not been completed, and the contents
14406                                                                  of BGX()_SPU()_AN_LP_BASE, BGX()_SPU()_AN_XNP_TX, and
14407                                                                  BGX()_SPU()_AN_LP_XNP are as defined by the current state of the autonegotiation
14408                                                                  protocol, or as written for manual configuration. This bit is always zero when AN is
14409                                                                  disabled (BGX()_SPU()_AN_CONTROL[AN_EN] = 0). */
14410         uint64_t rmt_flt               : 1;  /**< [  4:  4](RO) Remote fault: Always 0. */
14411         uint64_t an_able               : 1;  /**< [  3:  3](RO) Autonegotiation ability: Always 1. */
14412         uint64_t link_status           : 1;  /**< [  2:  2](R/W1S/H) Link status. This bit captures the state of the link_status variable as defined in 802.3
14413                                                                  section 73.9.1. When set, indicates that a valid link has been established. When clear,
14414                                                                  indicates that the link has been invalid after this bit was last set by software. Latching
14415                                                                  low bit; stays clear until a 1 is written by software. Note that in order to avoid read
14416                                                                  side effects, this is implemented as a write-1-to-set bit, rather than latching low read-
14417                                                                  only as specified in 802.3. */
14418         uint64_t reserved_1            : 1;
14419         uint64_t lp_an_able            : 1;  /**< [  0:  0](RO/H) Link partner autonegotiation ability. Set to indicate that the link partner is able to
14420                                                                  participate in the autonegotiation function, and cleared otherwise. */
14421 #else /* Word 0 - Little Endian */
14422         uint64_t lp_an_able            : 1;  /**< [  0:  0](RO/H) Link partner autonegotiation ability. Set to indicate that the link partner is able to
14423                                                                  participate in the autonegotiation function, and cleared otherwise. */
14424         uint64_t reserved_1            : 1;
14425         uint64_t link_status           : 1;  /**< [  2:  2](R/W1S/H) Link status. This bit captures the state of the link_status variable as defined in 802.3
14426                                                                  section 73.9.1. When set, indicates that a valid link has been established. When clear,
14427                                                                  indicates that the link has been invalid after this bit was last set by software. Latching
14428                                                                  low bit; stays clear until a 1 is written by software. Note that in order to avoid read
14429                                                                  side effects, this is implemented as a write-1-to-set bit, rather than latching low read-
14430                                                                  only as specified in 802.3. */
14431         uint64_t an_able               : 1;  /**< [  3:  3](RO) Autonegotiation ability: Always 1. */
14432         uint64_t rmt_flt               : 1;  /**< [  4:  4](RO) Remote fault: Always 0. */
14433         uint64_t an_complete           : 1;  /**< [  5:  5](RO/H) Autonegotiation complete. Set when the autonegotiation process has been completed and
14434                                                                  the link is up and running using the negotiated highest common denominator (HCD)
14435                                                                  technology. If AN is enabled (BGX()_SPU()_AN_CONTROL[AN_EN] = 1) and this bit is
14436                                                                  read as a zero, it indicates that the AN process has not been completed, and the contents
14437                                                                  of BGX()_SPU()_AN_LP_BASE, BGX()_SPU()_AN_XNP_TX, and
14438                                                                  BGX()_SPU()_AN_LP_XNP are as defined by the current state of the autonegotiation
14439                                                                  protocol, or as written for manual configuration. This bit is always zero when AN is
14440                                                                  disabled (BGX()_SPU()_AN_CONTROL[AN_EN] = 0). */
14441         uint64_t page_rx               : 1;  /**< [  6:  6](R/W1C/H) Page received. This latching-high bit is set when a new page has been received and stored
14442                                                                  in BGX()_SPU()_AN_LP_BASE or BGX()_SPU()_AN_LP_XNP; stays set until a 1 is
14443                                                                  written by software, autonegotiation is disabled or restarted, or next page exchange is
14444                                                                  initiated. Note that in order to avoid read side effects, this is implemented as a
14445                                                                  write-1-to-clear bit, rather than latching high read-only as specified in 802.3. */
14446         uint64_t xnp_stat              : 1;  /**< [  7:  7](RO/H) Extended next-page status. */
14447         uint64_t reserved_8            : 1;
14448         uint64_t prl_flt               : 1;  /**< [  9:  9](RO) Parallel detection fault. Always 0; SPU does not support parallel detection as part of the
14449                                                                  autonegotiation protocol. */
14450         uint64_t reserved_10_63        : 54;
14451 #endif /* Word 0 - End */
14452     } s;
14453     /* struct bdk_bgxx_spux_an_status_s cn; */
14454 };
14455 typedef union bdk_bgxx_spux_an_status bdk_bgxx_spux_an_status_t;
14456 
14457 static inline uint64_t BDK_BGXX_SPUX_AN_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_AN_STATUS(unsigned long a,unsigned long b)14458 static inline uint64_t BDK_BGXX_SPUX_AN_STATUS(unsigned long a, unsigned long b)
14459 {
14460     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14461         return 0x87e0e00100d0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14462     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14463         return 0x87e0e00100d0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14464     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14465         return 0x87e0e00100d0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14466     __bdk_csr_fatal("BGXX_SPUX_AN_STATUS", 2, a, b, 0, 0);
14467 }
14468 
14469 #define typedef_BDK_BGXX_SPUX_AN_STATUS(a,b) bdk_bgxx_spux_an_status_t
14470 #define bustype_BDK_BGXX_SPUX_AN_STATUS(a,b) BDK_CSR_TYPE_RSL
14471 #define basename_BDK_BGXX_SPUX_AN_STATUS(a,b) "BGXX_SPUX_AN_STATUS"
14472 #define device_bar_BDK_BGXX_SPUX_AN_STATUS(a,b) 0x0 /* PF_BAR0 */
14473 #define busnum_BDK_BGXX_SPUX_AN_STATUS(a,b) (a)
14474 #define arguments_BDK_BGXX_SPUX_AN_STATUS(a,b) (a),(b),-1,-1
14475 
14476 /**
14477  * Register (RSL) bgx#_spu#_an_xnp_tx
14478  *
14479  * BGX SPU Autonegotiation Extended Next Page Transmit Registers
14480  * Software programs this register with the contents of the AN message next page or unformatted
14481  * next page link code word to be transmitted during autonegotiation. Next page exchange occurs
14482  * after the base link code words have been exchanged if either end of the link segment sets the
14483  * NP bit to 1, indicating that it has at least one next page to send. Once initiated, next page
14484  * exchange continues until both ends of the link segment set their NP bits to 0. See section
14485  * 802.3 section 73.7.7 for details.
14486  */
14487 union bdk_bgxx_spux_an_xnp_tx
14488 {
14489     uint64_t u;
14490     struct bdk_bgxx_spux_an_xnp_tx_s
14491     {
14492 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14493         uint64_t reserved_48_63        : 16;
14494         uint64_t u                     : 32; /**< [ 47: 16](R/W) Unformatted code field. When the MP bit is set, this field contains the 32-bit unformatted
14495                                                                  code field of the message next page. When MP is clear, this field contains the upper 32
14496                                                                  bits of the 43-bit unformatted code field of the unformatted next page. */
14497         uint64_t np                    : 1;  /**< [ 15: 15](R/W) Next page. */
14498         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Acknowledge: Always 0 in this register. */
14499         uint64_t mp                    : 1;  /**< [ 13: 13](R/W) Message page. Set to indicate that this register contains a message next page. Clear to
14500                                                                  indicate that the register contains an unformatted next page. */
14501         uint64_t ack2                  : 1;  /**< [ 12: 12](R/W) Acknowledge 2. Indicates that the receiver is able to act on the information (or perform
14502                                                                  the task) defined in the message. */
14503         uint64_t toggle                : 1;  /**< [ 11: 11](R/W) This bit is ignored by hardware. The value of the TOGGLE bit in transmitted next pages is
14504                                                                  automatically generated by hardware. */
14505         uint64_t m_u                   : 11; /**< [ 10:  0](R/W) Message/unformatted code field: When the MP bit is set, this field contains the message
14506                                                                  code field (M) of the message next page. When MP is clear, this field contains the lower
14507                                                                  11 bits of the 43-bit unformatted code field of the unformatted next page. */
14508 #else /* Word 0 - Little Endian */
14509         uint64_t m_u                   : 11; /**< [ 10:  0](R/W) Message/unformatted code field: When the MP bit is set, this field contains the message
14510                                                                  code field (M) of the message next page. When MP is clear, this field contains the lower
14511                                                                  11 bits of the 43-bit unformatted code field of the unformatted next page. */
14512         uint64_t toggle                : 1;  /**< [ 11: 11](R/W) This bit is ignored by hardware. The value of the TOGGLE bit in transmitted next pages is
14513                                                                  automatically generated by hardware. */
14514         uint64_t ack2                  : 1;  /**< [ 12: 12](R/W) Acknowledge 2. Indicates that the receiver is able to act on the information (or perform
14515                                                                  the task) defined in the message. */
14516         uint64_t mp                    : 1;  /**< [ 13: 13](R/W) Message page. Set to indicate that this register contains a message next page. Clear to
14517                                                                  indicate that the register contains an unformatted next page. */
14518         uint64_t ack                   : 1;  /**< [ 14: 14](RO/H) Acknowledge: Always 0 in this register. */
14519         uint64_t np                    : 1;  /**< [ 15: 15](R/W) Next page. */
14520         uint64_t u                     : 32; /**< [ 47: 16](R/W) Unformatted code field. When the MP bit is set, this field contains the 32-bit unformatted
14521                                                                  code field of the message next page. When MP is clear, this field contains the upper 32
14522                                                                  bits of the 43-bit unformatted code field of the unformatted next page. */
14523         uint64_t reserved_48_63        : 16;
14524 #endif /* Word 0 - End */
14525     } s;
14526     /* struct bdk_bgxx_spux_an_xnp_tx_s cn; */
14527 };
14528 typedef union bdk_bgxx_spux_an_xnp_tx bdk_bgxx_spux_an_xnp_tx_t;
14529 
14530 static inline uint64_t BDK_BGXX_SPUX_AN_XNP_TX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_AN_XNP_TX(unsigned long a,unsigned long b)14531 static inline uint64_t BDK_BGXX_SPUX_AN_XNP_TX(unsigned long a, unsigned long b)
14532 {
14533     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14534         return 0x87e0e00100e8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14535     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14536         return 0x87e0e00100e8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14537     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14538         return 0x87e0e00100e8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14539     __bdk_csr_fatal("BGXX_SPUX_AN_XNP_TX", 2, a, b, 0, 0);
14540 }
14541 
14542 #define typedef_BDK_BGXX_SPUX_AN_XNP_TX(a,b) bdk_bgxx_spux_an_xnp_tx_t
14543 #define bustype_BDK_BGXX_SPUX_AN_XNP_TX(a,b) BDK_CSR_TYPE_RSL
14544 #define basename_BDK_BGXX_SPUX_AN_XNP_TX(a,b) "BGXX_SPUX_AN_XNP_TX"
14545 #define device_bar_BDK_BGXX_SPUX_AN_XNP_TX(a,b) 0x0 /* PF_BAR0 */
14546 #define busnum_BDK_BGXX_SPUX_AN_XNP_TX(a,b) (a)
14547 #define arguments_BDK_BGXX_SPUX_AN_XNP_TX(a,b) (a),(b),-1,-1
14548 
14549 /**
14550  * Register (RSL) bgx#_spu#_br_algn_status
14551  *
14552  * BGX SPU Multilane BASE-R PCS Alignment-Status Registers
14553  * This register implements the IEEE 802.3 multilane BASE-R PCS alignment status 1-4 registers
14554  * (3.50-3.53). It is valid only when the LPCS type is 40GBASE-R
14555  * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), and always returns 0x0 for all other LPCS
14556  * types. IEEE 802.3 bits that are not applicable to 40GBASE-R (e.g. status bits for PCS lanes
14557  * 19-4) are not implemented and marked as reserved. PCS lanes 3-0 are valid and are mapped to
14558  * physical SerDes lanes based on the programming of BGX()_CMR()_CONFIG[LANE_TO_SDS].
14559  */
14560 union bdk_bgxx_spux_br_algn_status
14561 {
14562     uint64_t u;
14563     struct bdk_bgxx_spux_br_algn_status_s
14564     {
14565 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14566         uint64_t reserved_36_63        : 28;
14567         uint64_t marker_lock           : 4;  /**< [ 35: 32](RO/H) Marker-locked status for PCS lanes 3-0.
14568                                                                  0 = Not locked.
14569                                                                  1 = Locked. */
14570         uint64_t reserved_13_31        : 19;
14571         uint64_t alignd                : 1;  /**< [ 12: 12](RO/H) All lanes are locked and aligned. This bit returns 1 when the logical PCS has locked and
14572                                                                  aligned all associated receive lanes; returns 0 otherwise. For all other PCS types, this
14573                                                                  bit always returns 0. */
14574         uint64_t reserved_4_11         : 8;
14575         uint64_t block_lock            : 4;  /**< [  3:  0](RO/H) Block-lock status for PCS lanes 3-0:
14576                                                                    0 = Not locked.
14577                                                                    1 = Locked. */
14578 #else /* Word 0 - Little Endian */
14579         uint64_t block_lock            : 4;  /**< [  3:  0](RO/H) Block-lock status for PCS lanes 3-0:
14580                                                                    0 = Not locked.
14581                                                                    1 = Locked. */
14582         uint64_t reserved_4_11         : 8;
14583         uint64_t alignd                : 1;  /**< [ 12: 12](RO/H) All lanes are locked and aligned. This bit returns 1 when the logical PCS has locked and
14584                                                                  aligned all associated receive lanes; returns 0 otherwise. For all other PCS types, this
14585                                                                  bit always returns 0. */
14586         uint64_t reserved_13_31        : 19;
14587         uint64_t marker_lock           : 4;  /**< [ 35: 32](RO/H) Marker-locked status for PCS lanes 3-0.
14588                                                                  0 = Not locked.
14589                                                                  1 = Locked. */
14590         uint64_t reserved_36_63        : 28;
14591 #endif /* Word 0 - End */
14592     } s;
14593     /* struct bdk_bgxx_spux_br_algn_status_s cn; */
14594 };
14595 typedef union bdk_bgxx_spux_br_algn_status bdk_bgxx_spux_br_algn_status_t;
14596 
14597 static inline uint64_t BDK_BGXX_SPUX_BR_ALGN_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_ALGN_STATUS(unsigned long a,unsigned long b)14598 static inline uint64_t BDK_BGXX_SPUX_BR_ALGN_STATUS(unsigned long a, unsigned long b)
14599 {
14600     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14601         return 0x87e0e0010050ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14602     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14603         return 0x87e0e0010050ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14604     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14605         return 0x87e0e0010050ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14606     __bdk_csr_fatal("BGXX_SPUX_BR_ALGN_STATUS", 2, a, b, 0, 0);
14607 }
14608 
14609 #define typedef_BDK_BGXX_SPUX_BR_ALGN_STATUS(a,b) bdk_bgxx_spux_br_algn_status_t
14610 #define bustype_BDK_BGXX_SPUX_BR_ALGN_STATUS(a,b) BDK_CSR_TYPE_RSL
14611 #define basename_BDK_BGXX_SPUX_BR_ALGN_STATUS(a,b) "BGXX_SPUX_BR_ALGN_STATUS"
14612 #define device_bar_BDK_BGXX_SPUX_BR_ALGN_STATUS(a,b) 0x0 /* PF_BAR0 */
14613 #define busnum_BDK_BGXX_SPUX_BR_ALGN_STATUS(a,b) (a)
14614 #define arguments_BDK_BGXX_SPUX_BR_ALGN_STATUS(a,b) (a),(b),-1,-1
14615 
14616 /**
14617  * Register (RSL) bgx#_spu#_br_bip_err_cnt
14618  *
14619  * BGX SPU 40GBASE-R BIP Error-Counter Registers
14620  * This register implements the IEEE 802.3 BIP error-counter registers for PCS lanes 0-3
14621  * (3.200-3.203). It is valid only when the LPCS type is 40GBASE-R
14622  * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), and always returns 0x0 for all other LPCS
14623  * types. The counters are indexed by the RX PCS lane number based on the Alignment Marker
14624  * detected on each lane and captured in BGX()_SPU()_BR_LANE_MAP. Each counter counts the
14625  * BIP errors for its PCS lane, and is held at all ones in case of overflow. The counters are
14626  * reset to all 0s when this register is read by software.
14627  *
14628  * The reset operation takes precedence over the increment operation; if the register is read on
14629  * the same clock cycle as an increment operation, the counter is reset to all 0s and the
14630  * increment operation is lost. The counters are writable for test purposes, rather than read-
14631  * only as specified in IEEE 802.3.
14632  */
14633 union bdk_bgxx_spux_br_bip_err_cnt
14634 {
14635     uint64_t u;
14636     struct bdk_bgxx_spux_br_bip_err_cnt_s
14637     {
14638 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14639         uint64_t bip_err_cnt_ln3       : 16; /**< [ 63: 48](RC/W/H) BIP error counter for lane on which PCS lane 3 markers are received. */
14640         uint64_t bip_err_cnt_ln2       : 16; /**< [ 47: 32](RC/W/H) BIP error counter for lane on which PCS lane 2 markers are received. */
14641         uint64_t bip_err_cnt_ln1       : 16; /**< [ 31: 16](RC/W/H) BIP error counter for lane on which PCS lane 1 markers are received. */
14642         uint64_t bip_err_cnt_ln0       : 16; /**< [ 15:  0](RC/W/H) BIP error counter for lane on which PCS lane 0 markers are received. */
14643 #else /* Word 0 - Little Endian */
14644         uint64_t bip_err_cnt_ln0       : 16; /**< [ 15:  0](RC/W/H) BIP error counter for lane on which PCS lane 0 markers are received. */
14645         uint64_t bip_err_cnt_ln1       : 16; /**< [ 31: 16](RC/W/H) BIP error counter for lane on which PCS lane 1 markers are received. */
14646         uint64_t bip_err_cnt_ln2       : 16; /**< [ 47: 32](RC/W/H) BIP error counter for lane on which PCS lane 2 markers are received. */
14647         uint64_t bip_err_cnt_ln3       : 16; /**< [ 63: 48](RC/W/H) BIP error counter for lane on which PCS lane 3 markers are received. */
14648 #endif /* Word 0 - End */
14649     } s;
14650     /* struct bdk_bgxx_spux_br_bip_err_cnt_s cn; */
14651 };
14652 typedef union bdk_bgxx_spux_br_bip_err_cnt bdk_bgxx_spux_br_bip_err_cnt_t;
14653 
14654 static inline uint64_t BDK_BGXX_SPUX_BR_BIP_ERR_CNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_BIP_ERR_CNT(unsigned long a,unsigned long b)14655 static inline uint64_t BDK_BGXX_SPUX_BR_BIP_ERR_CNT(unsigned long a, unsigned long b)
14656 {
14657     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14658         return 0x87e0e0010058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14659     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14660         return 0x87e0e0010058ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14661     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14662         return 0x87e0e0010058ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14663     __bdk_csr_fatal("BGXX_SPUX_BR_BIP_ERR_CNT", 2, a, b, 0, 0);
14664 }
14665 
14666 #define typedef_BDK_BGXX_SPUX_BR_BIP_ERR_CNT(a,b) bdk_bgxx_spux_br_bip_err_cnt_t
14667 #define bustype_BDK_BGXX_SPUX_BR_BIP_ERR_CNT(a,b) BDK_CSR_TYPE_RSL
14668 #define basename_BDK_BGXX_SPUX_BR_BIP_ERR_CNT(a,b) "BGXX_SPUX_BR_BIP_ERR_CNT"
14669 #define device_bar_BDK_BGXX_SPUX_BR_BIP_ERR_CNT(a,b) 0x0 /* PF_BAR0 */
14670 #define busnum_BDK_BGXX_SPUX_BR_BIP_ERR_CNT(a,b) (a)
14671 #define arguments_BDK_BGXX_SPUX_BR_BIP_ERR_CNT(a,b) (a),(b),-1,-1
14672 
14673 /**
14674  * Register (RSL) bgx#_spu#_br_lane_map
14675  *
14676  * BGX SPU 40GBASE-R Lane-Mapping Registers
14677  * This register implements the IEEE 802.3 lane 0-3 mapping registers (3.400-3.403). It is valid
14678  * only when the LPCS type is 40GBASE-R (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), and always
14679  * returns 0x0 for all other LPCS types. The LNx_MAPPING field for each programmed PCS lane
14680  * (called service interface in 802.3ba-2010) is valid when that lane has achieved alignment
14681  * marker lock on the receive side (i.e. the associated
14682  * BGX()_SPU()_BR_ALGN_STATUS[MARKER_LOCK] = 1), and is invalid otherwise. When valid, it
14683  * returns the actual detected receive PCS lane number based on the received alignment marker
14684  * contents received on that service interface.
14685  *
14686  * The mapping is flexible because IEEE 802.3 allows multilane BASE-R receive lanes to be re-
14687  * ordered. Note that for the transmit side, each PCS lane is mapped to a physical SerDes lane
14688  * based on the programming of BGX()_CMR()_CONFIG[LANE_TO_SDS]. For the receive side,
14689  * BGX()_CMR()_CONFIG[LANE_TO_SDS] specifies the service interface to physical SerDes
14690  * lane mapping, and this register specifies the service interface to PCS lane mapping.
14691  */
14692 union bdk_bgxx_spux_br_lane_map
14693 {
14694     uint64_t u;
14695     struct bdk_bgxx_spux_br_lane_map_s
14696     {
14697 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14698         uint64_t reserved_54_63        : 10;
14699         uint64_t ln3_mapping           : 6;  /**< [ 53: 48](RO/H) PCS lane number received on service interface 3 */
14700         uint64_t reserved_38_47        : 10;
14701         uint64_t ln2_mapping           : 6;  /**< [ 37: 32](RO/H) PCS lane number received on service interface 2 */
14702         uint64_t reserved_22_31        : 10;
14703         uint64_t ln1_mapping           : 6;  /**< [ 21: 16](RO/H) PCS lane number received on service interface 1 */
14704         uint64_t reserved_6_15         : 10;
14705         uint64_t ln0_mapping           : 6;  /**< [  5:  0](RO/H) PCS lane number received on service interface 0 */
14706 #else /* Word 0 - Little Endian */
14707         uint64_t ln0_mapping           : 6;  /**< [  5:  0](RO/H) PCS lane number received on service interface 0 */
14708         uint64_t reserved_6_15         : 10;
14709         uint64_t ln1_mapping           : 6;  /**< [ 21: 16](RO/H) PCS lane number received on service interface 1 */
14710         uint64_t reserved_22_31        : 10;
14711         uint64_t ln2_mapping           : 6;  /**< [ 37: 32](RO/H) PCS lane number received on service interface 2 */
14712         uint64_t reserved_38_47        : 10;
14713         uint64_t ln3_mapping           : 6;  /**< [ 53: 48](RO/H) PCS lane number received on service interface 3 */
14714         uint64_t reserved_54_63        : 10;
14715 #endif /* Word 0 - End */
14716     } s;
14717     /* struct bdk_bgxx_spux_br_lane_map_s cn; */
14718 };
14719 typedef union bdk_bgxx_spux_br_lane_map bdk_bgxx_spux_br_lane_map_t;
14720 
14721 static inline uint64_t BDK_BGXX_SPUX_BR_LANE_MAP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_LANE_MAP(unsigned long a,unsigned long b)14722 static inline uint64_t BDK_BGXX_SPUX_BR_LANE_MAP(unsigned long a, unsigned long b)
14723 {
14724     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14725         return 0x87e0e0010060ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14726     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14727         return 0x87e0e0010060ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14728     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14729         return 0x87e0e0010060ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14730     __bdk_csr_fatal("BGXX_SPUX_BR_LANE_MAP", 2, a, b, 0, 0);
14731 }
14732 
14733 #define typedef_BDK_BGXX_SPUX_BR_LANE_MAP(a,b) bdk_bgxx_spux_br_lane_map_t
14734 #define bustype_BDK_BGXX_SPUX_BR_LANE_MAP(a,b) BDK_CSR_TYPE_RSL
14735 #define basename_BDK_BGXX_SPUX_BR_LANE_MAP(a,b) "BGXX_SPUX_BR_LANE_MAP"
14736 #define device_bar_BDK_BGXX_SPUX_BR_LANE_MAP(a,b) 0x0 /* PF_BAR0 */
14737 #define busnum_BDK_BGXX_SPUX_BR_LANE_MAP(a,b) (a)
14738 #define arguments_BDK_BGXX_SPUX_BR_LANE_MAP(a,b) (a),(b),-1,-1
14739 
14740 /**
14741  * Register (RSL) bgx#_spu#_br_pmd_control
14742  *
14743  * BGX SPU 40GBASE-R PMD Control Registers
14744  */
14745 union bdk_bgxx_spux_br_pmd_control
14746 {
14747     uint64_t u;
14748     struct bdk_bgxx_spux_br_pmd_control_s
14749     {
14750 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14751         uint64_t reserved_2_63         : 62;
14752         uint64_t train_en              : 1;  /**< [  1:  1](R/W) BASE-R training enable. */
14753         uint64_t train_restart         : 1;  /**< [  0:  0](R/W1S/H) BASE-R training restart. Writing a 1 to this bit restarts the training process if
14754                                                                  [TRAIN_EN] is also set. This is a self-clearing bit. Software should
14755                                                                  wait a minimum of 1.7ms after BGX()_SPU()_INT[TRAINING_FAILURE] is set before
14756                                                                  restarting the training process. */
14757 #else /* Word 0 - Little Endian */
14758         uint64_t train_restart         : 1;  /**< [  0:  0](R/W1S/H) BASE-R training restart. Writing a 1 to this bit restarts the training process if
14759                                                                  [TRAIN_EN] is also set. This is a self-clearing bit. Software should
14760                                                                  wait a minimum of 1.7ms after BGX()_SPU()_INT[TRAINING_FAILURE] is set before
14761                                                                  restarting the training process. */
14762         uint64_t train_en              : 1;  /**< [  1:  1](R/W) BASE-R training enable. */
14763         uint64_t reserved_2_63         : 62;
14764 #endif /* Word 0 - End */
14765     } s;
14766     /* struct bdk_bgxx_spux_br_pmd_control_s cn; */
14767 };
14768 typedef union bdk_bgxx_spux_br_pmd_control bdk_bgxx_spux_br_pmd_control_t;
14769 
14770 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_CONTROL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_PMD_CONTROL(unsigned long a,unsigned long b)14771 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_CONTROL(unsigned long a, unsigned long b)
14772 {
14773     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14774         return 0x87e0e0010068ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14775     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14776         return 0x87e0e0010068ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14777     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14778         return 0x87e0e0010068ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14779     __bdk_csr_fatal("BGXX_SPUX_BR_PMD_CONTROL", 2, a, b, 0, 0);
14780 }
14781 
14782 #define typedef_BDK_BGXX_SPUX_BR_PMD_CONTROL(a,b) bdk_bgxx_spux_br_pmd_control_t
14783 #define bustype_BDK_BGXX_SPUX_BR_PMD_CONTROL(a,b) BDK_CSR_TYPE_RSL
14784 #define basename_BDK_BGXX_SPUX_BR_PMD_CONTROL(a,b) "BGXX_SPUX_BR_PMD_CONTROL"
14785 #define device_bar_BDK_BGXX_SPUX_BR_PMD_CONTROL(a,b) 0x0 /* PF_BAR0 */
14786 #define busnum_BDK_BGXX_SPUX_BR_PMD_CONTROL(a,b) (a)
14787 #define arguments_BDK_BGXX_SPUX_BR_PMD_CONTROL(a,b) (a),(b),-1,-1
14788 
14789 /**
14790  * Register (RSL) bgx#_spu#_br_pmd_ld_cup
14791  *
14792  * BGX SPU 40GBASE-R PMD Local Device Coefficient Update Registers
14793  * This register implements 802.3 MDIO register 1.153 for 10GBASE-R (when
14794  * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R)
14795  * and MDIO registers 1.1300-1.1303 for 40GBASE-R (when
14796  * BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of training.
14797  * When link training
14798  * is in progress, each field reflects the contents of the coefficient update field in the
14799  * associated lane's outgoing training frame. The fields in this register are read/write even
14800  * though they are specified as read-only in 802.3.
14801  *
14802  * If BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is set, then this register must be updated
14803  * by software during link training and hardware updates are disabled. If
14804  * BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is clear, this register is automatically
14805  * updated by hardware, and it should not be written by software. The lane fields in this
14806  * register are indexed by logical PCS lane ID.
14807  *
14808  * The lane 0 field (LN0_*) is valid for both
14809  * 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*, LN3_*) are only valid for
14810  * 40GBASE-R.
14811  */
14812 union bdk_bgxx_spux_br_pmd_ld_cup
14813 {
14814     uint64_t u;
14815     struct bdk_bgxx_spux_br_pmd_ld_cup_s
14816     {
14817 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14818         uint64_t ln3_cup               : 16; /**< [ 63: 48](R/W/H) PCS lane 3 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14819                                                                  10GBASE-R. */
14820         uint64_t ln2_cup               : 16; /**< [ 47: 32](R/W/H) PCS lane 2 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14821                                                                  10GBASE-R. */
14822         uint64_t ln1_cup               : 16; /**< [ 31: 16](R/W/H) PCS lane 1 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14823                                                                  10GBASE-R. */
14824         uint64_t ln0_cup               : 16; /**< [ 15:  0](R/W/H) PCS lane 0 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. */
14825 #else /* Word 0 - Little Endian */
14826         uint64_t ln0_cup               : 16; /**< [ 15:  0](R/W/H) PCS lane 0 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. */
14827         uint64_t ln1_cup               : 16; /**< [ 31: 16](R/W/H) PCS lane 1 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14828                                                                  10GBASE-R. */
14829         uint64_t ln2_cup               : 16; /**< [ 47: 32](R/W/H) PCS lane 2 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14830                                                                  10GBASE-R. */
14831         uint64_t ln3_cup               : 16; /**< [ 63: 48](R/W/H) PCS lane 3 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14832                                                                  10GBASE-R. */
14833 #endif /* Word 0 - End */
14834     } s;
14835     /* struct bdk_bgxx_spux_br_pmd_ld_cup_s cn; */
14836 };
14837 typedef union bdk_bgxx_spux_br_pmd_ld_cup bdk_bgxx_spux_br_pmd_ld_cup_t;
14838 
14839 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_LD_CUP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_PMD_LD_CUP(unsigned long a,unsigned long b)14840 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_LD_CUP(unsigned long a, unsigned long b)
14841 {
14842     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14843         return 0x87e0e0010088ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14844     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14845         return 0x87e0e0010088ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14846     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14847         return 0x87e0e0010088ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14848     __bdk_csr_fatal("BGXX_SPUX_BR_PMD_LD_CUP", 2, a, b, 0, 0);
14849 }
14850 
14851 #define typedef_BDK_BGXX_SPUX_BR_PMD_LD_CUP(a,b) bdk_bgxx_spux_br_pmd_ld_cup_t
14852 #define bustype_BDK_BGXX_SPUX_BR_PMD_LD_CUP(a,b) BDK_CSR_TYPE_RSL
14853 #define basename_BDK_BGXX_SPUX_BR_PMD_LD_CUP(a,b) "BGXX_SPUX_BR_PMD_LD_CUP"
14854 #define device_bar_BDK_BGXX_SPUX_BR_PMD_LD_CUP(a,b) 0x0 /* PF_BAR0 */
14855 #define busnum_BDK_BGXX_SPUX_BR_PMD_LD_CUP(a,b) (a)
14856 #define arguments_BDK_BGXX_SPUX_BR_PMD_LD_CUP(a,b) (a),(b),-1,-1
14857 
14858 /**
14859  * Register (RSL) bgx#_spu#_br_pmd_ld_rep
14860  *
14861  * BGX SPU 40GBASE-R PMD Local Device Status Report Registers
14862  * This register implements 802.3 MDIO register 1.154 for 10GBASE-R (when
14863  * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R) and MDIO registers 1.1400-1.1403 for 40GBASE-R
14864  * (when BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of
14865  * training. Each field
14866  * reflects the contents of the status report field in the associated lane's outgoing training
14867  * frame. The fields in this register are read/write even though they are specified as read-only
14868  * in 802.3. If BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is set, then this register must
14869  * be updated by software during link training and hardware updates are disabled. If
14870  * BGX()_SPU_DBG_CONTROL[BR_PMD_TRAIN_SOFT_EN] is clear, this register is automatically
14871  * updated by hardware, and it should not be written by software. The lane fields in this
14872  * register are indexed by logical PCS lane ID.
14873  *
14874  * The lane 0 field (LN0_*) is valid for both
14875  * 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*, LN3_*) are only valid for
14876  * 40GBASE-R.
14877  */
14878 union bdk_bgxx_spux_br_pmd_ld_rep
14879 {
14880     uint64_t u;
14881     struct bdk_bgxx_spux_br_pmd_ld_rep_s
14882     {
14883 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14884         uint64_t ln3_rep               : 16; /**< [ 63: 48](R/W/H) PCS lane 3 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
14885                                                                  10GBASE-R. */
14886         uint64_t ln2_rep               : 16; /**< [ 47: 32](R/W/H) PCS lane 2 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
14887                                                                  10GBASE-R. */
14888         uint64_t ln1_rep               : 16; /**< [ 31: 16](R/W/H) PCS lane 1 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
14889                                                                  10GBASE-R. */
14890         uint64_t ln0_rep               : 16; /**< [ 15:  0](R/W/H) PCS lane 0 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. */
14891 #else /* Word 0 - Little Endian */
14892         uint64_t ln0_rep               : 16; /**< [ 15:  0](R/W/H) PCS lane 0 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. */
14893         uint64_t ln1_rep               : 16; /**< [ 31: 16](R/W/H) PCS lane 1 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
14894                                                                  10GBASE-R. */
14895         uint64_t ln2_rep               : 16; /**< [ 47: 32](R/W/H) PCS lane 2 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
14896                                                                  10GBASE-R. */
14897         uint64_t ln3_rep               : 16; /**< [ 63: 48](R/W/H) PCS lane 3 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
14898                                                                  10GBASE-R. */
14899 #endif /* Word 0 - End */
14900     } s;
14901     /* struct bdk_bgxx_spux_br_pmd_ld_rep_s cn; */
14902 };
14903 typedef union bdk_bgxx_spux_br_pmd_ld_rep bdk_bgxx_spux_br_pmd_ld_rep_t;
14904 
14905 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_LD_REP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_PMD_LD_REP(unsigned long a,unsigned long b)14906 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_LD_REP(unsigned long a, unsigned long b)
14907 {
14908     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14909         return 0x87e0e0010090ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14910     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14911         return 0x87e0e0010090ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14912     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14913         return 0x87e0e0010090ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14914     __bdk_csr_fatal("BGXX_SPUX_BR_PMD_LD_REP", 2, a, b, 0, 0);
14915 }
14916 
14917 #define typedef_BDK_BGXX_SPUX_BR_PMD_LD_REP(a,b) bdk_bgxx_spux_br_pmd_ld_rep_t
14918 #define bustype_BDK_BGXX_SPUX_BR_PMD_LD_REP(a,b) BDK_CSR_TYPE_RSL
14919 #define basename_BDK_BGXX_SPUX_BR_PMD_LD_REP(a,b) "BGXX_SPUX_BR_PMD_LD_REP"
14920 #define device_bar_BDK_BGXX_SPUX_BR_PMD_LD_REP(a,b) 0x0 /* PF_BAR0 */
14921 #define busnum_BDK_BGXX_SPUX_BR_PMD_LD_REP(a,b) (a)
14922 #define arguments_BDK_BGXX_SPUX_BR_PMD_LD_REP(a,b) (a),(b),-1,-1
14923 
14924 /**
14925  * Register (RSL) bgx#_spu#_br_pmd_lp_cup
14926  *
14927  * BGX SPU 40GBASE-R PMD Link Partner Coefficient Update Registers
14928  * This register implements 802.3 MDIO register 1.152 for 10GBASE-R (when
14929  * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R)
14930  * and MDIO registers 1.1100-1.1103 for 40GBASE-R (when
14931  * BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of training.
14932  * Each field reflects
14933  * the contents of the coefficient update field in the lane's most recently received training
14934  * frame. This register should not be written when link training is enabled, i.e. when
14935  * BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is set. The lane fields in this register are indexed by
14936  * logical PCS lane ID.
14937  *
14938  * The lane 0 field (LN0_*) is valid for both 10GBASE-R and 40GBASE-R. The remaining fields
14939  * (LN1_*, LN2_*, LN3_*) are only valid for 40GBASE-R.
14940  */
14941 union bdk_bgxx_spux_br_pmd_lp_cup
14942 {
14943     uint64_t u;
14944     struct bdk_bgxx_spux_br_pmd_lp_cup_s
14945     {
14946 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14947         uint64_t ln3_cup               : 16; /**< [ 63: 48](R/W/H) PCS lane 3 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14948                                                                  10GBASE-R. */
14949         uint64_t ln2_cup               : 16; /**< [ 47: 32](R/W/H) PCS lane 2 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14950                                                                  10GBASE-R. */
14951         uint64_t ln1_cup               : 16; /**< [ 31: 16](R/W/H) PCS lane 1 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14952                                                                  10GBASE-R. */
14953         uint64_t ln0_cup               : 16; /**< [ 15:  0](R/W/H) PCS lane 0 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. */
14954 #else /* Word 0 - Little Endian */
14955         uint64_t ln0_cup               : 16; /**< [ 15:  0](R/W/H) PCS lane 0 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. */
14956         uint64_t ln1_cup               : 16; /**< [ 31: 16](R/W/H) PCS lane 1 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14957                                                                  10GBASE-R. */
14958         uint64_t ln2_cup               : 16; /**< [ 47: 32](R/W/H) PCS lane 2 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14959                                                                  10GBASE-R. */
14960         uint64_t ln3_cup               : 16; /**< [ 63: 48](R/W/H) PCS lane 3 coefficient update: format defined by BGX_SPU_BR_TRAIN_CUP_S. Not valid for
14961                                                                  10GBASE-R. */
14962 #endif /* Word 0 - End */
14963     } s;
14964     /* struct bdk_bgxx_spux_br_pmd_lp_cup_s cn; */
14965 };
14966 typedef union bdk_bgxx_spux_br_pmd_lp_cup bdk_bgxx_spux_br_pmd_lp_cup_t;
14967 
14968 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_LP_CUP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_PMD_LP_CUP(unsigned long a,unsigned long b)14969 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_LP_CUP(unsigned long a, unsigned long b)
14970 {
14971     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
14972         return 0x87e0e0010078ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14973     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
14974         return 0x87e0e0010078ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
14975     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
14976         return 0x87e0e0010078ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
14977     __bdk_csr_fatal("BGXX_SPUX_BR_PMD_LP_CUP", 2, a, b, 0, 0);
14978 }
14979 
14980 #define typedef_BDK_BGXX_SPUX_BR_PMD_LP_CUP(a,b) bdk_bgxx_spux_br_pmd_lp_cup_t
14981 #define bustype_BDK_BGXX_SPUX_BR_PMD_LP_CUP(a,b) BDK_CSR_TYPE_RSL
14982 #define basename_BDK_BGXX_SPUX_BR_PMD_LP_CUP(a,b) "BGXX_SPUX_BR_PMD_LP_CUP"
14983 #define device_bar_BDK_BGXX_SPUX_BR_PMD_LP_CUP(a,b) 0x0 /* PF_BAR0 */
14984 #define busnum_BDK_BGXX_SPUX_BR_PMD_LP_CUP(a,b) (a)
14985 #define arguments_BDK_BGXX_SPUX_BR_PMD_LP_CUP(a,b) (a),(b),-1,-1
14986 
14987 /**
14988  * Register (RSL) bgx#_spu#_br_pmd_lp_rep
14989  *
14990  * BGX SPU 40GBASE-R PMD Link Partner Status Report Registers
14991  * This register implements 802.3 MDIO register 1.153 for 10GBASE-R (when
14992  * BGX()_CMR()_CONFIG[LMAC_TYPE] = 10G_R)
14993  * and MDIO registers 1.1200-1.1203 for 40GBASE-R (when
14994  * BGX()_CMR()_CONFIG[LMAC_TYPE] = 40G_R). It is automatically cleared at the start of training.
14995  * Each field reflects
14996  * the contents of the status report field in the associated lane's most recently received
14997  * training frame. The lane fields in this register are indexed by logical PCS lane ID.
14998  *
14999  * The lane
15000  * 0 field (LN0_*) is valid for both 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*,
15001  * LN3_*) are only valid for 40GBASE-R.
15002  */
15003 union bdk_bgxx_spux_br_pmd_lp_rep
15004 {
15005     uint64_t u;
15006     struct bdk_bgxx_spux_br_pmd_lp_rep_s
15007     {
15008 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15009         uint64_t ln3_rep               : 16; /**< [ 63: 48](RO/H) PCS lane 3 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
15010                                                                  10GBASE-R. */
15011         uint64_t ln2_rep               : 16; /**< [ 47: 32](RO/H) PCS lane 2 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
15012                                                                  10GBASE-R. */
15013         uint64_t ln1_rep               : 16; /**< [ 31: 16](RO/H) PCS lane 1 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
15014                                                                  10GBASE-R. */
15015         uint64_t ln0_rep               : 16; /**< [ 15:  0](RO/H) PCS lane 0 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. */
15016 #else /* Word 0 - Little Endian */
15017         uint64_t ln0_rep               : 16; /**< [ 15:  0](RO/H) PCS lane 0 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. */
15018         uint64_t ln1_rep               : 16; /**< [ 31: 16](RO/H) PCS lane 1 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
15019                                                                  10GBASE-R. */
15020         uint64_t ln2_rep               : 16; /**< [ 47: 32](RO/H) PCS lane 2 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
15021                                                                  10GBASE-R. */
15022         uint64_t ln3_rep               : 16; /**< [ 63: 48](RO/H) PCS lane 3 status report: format defined by BGX_SPU_BR_TRAIN_REP_S. Not valid for
15023                                                                  10GBASE-R. */
15024 #endif /* Word 0 - End */
15025     } s;
15026     /* struct bdk_bgxx_spux_br_pmd_lp_rep_s cn; */
15027 };
15028 typedef union bdk_bgxx_spux_br_pmd_lp_rep bdk_bgxx_spux_br_pmd_lp_rep_t;
15029 
15030 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_LP_REP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_PMD_LP_REP(unsigned long a,unsigned long b)15031 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_LP_REP(unsigned long a, unsigned long b)
15032 {
15033     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15034         return 0x87e0e0010080ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15035     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15036         return 0x87e0e0010080ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15037     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15038         return 0x87e0e0010080ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15039     __bdk_csr_fatal("BGXX_SPUX_BR_PMD_LP_REP", 2, a, b, 0, 0);
15040 }
15041 
15042 #define typedef_BDK_BGXX_SPUX_BR_PMD_LP_REP(a,b) bdk_bgxx_spux_br_pmd_lp_rep_t
15043 #define bustype_BDK_BGXX_SPUX_BR_PMD_LP_REP(a,b) BDK_CSR_TYPE_RSL
15044 #define basename_BDK_BGXX_SPUX_BR_PMD_LP_REP(a,b) "BGXX_SPUX_BR_PMD_LP_REP"
15045 #define device_bar_BDK_BGXX_SPUX_BR_PMD_LP_REP(a,b) 0x0 /* PF_BAR0 */
15046 #define busnum_BDK_BGXX_SPUX_BR_PMD_LP_REP(a,b) (a)
15047 #define arguments_BDK_BGXX_SPUX_BR_PMD_LP_REP(a,b) (a),(b),-1,-1
15048 
15049 /**
15050  * Register (RSL) bgx#_spu#_br_pmd_status
15051  *
15052  * BGX SPU 40GBASE-R PMD Status Registers
15053  * The lane fields in this register are indexed by logical PCS lane ID. The lane 0 field (LN0_*)
15054  * is valid for both 10GBASE-R and 40GBASE-R. The remaining fields (LN1_*, LN2_*, LN3_*) are only
15055  * valid for 40GBASE-R.
15056  */
15057 union bdk_bgxx_spux_br_pmd_status
15058 {
15059     uint64_t u;
15060     struct bdk_bgxx_spux_br_pmd_status_s
15061     {
15062 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15063         uint64_t reserved_16_63        : 48;
15064         uint64_t ln3_train_status      : 4;  /**< [ 15: 12](RO/H) PCS lane 3 link training status. Format defined by BGX_SPU_BR_LANE_TRAIN_STATUS_S. Not
15065                                                                  valid for 10GBASE-R. */
15066         uint64_t ln2_train_status      : 4;  /**< [ 11:  8](RO/H) PCS lane 2 link training status. Format defined by BGX_SPU_BR_LANE_TRAIN_STATUS_S. Not
15067                                                                  valid for 10GBASE-R. */
15068         uint64_t ln1_train_status      : 4;  /**< [  7:  4](RO/H) PCS lane 1 link training status. Format defined by BGX_SPU_BR_LANE_TRAIN_STATUS_S. Not
15069                                                                  valid for 10GBASE-R. */
15070         uint64_t ln0_train_status      : 4;  /**< [  3:  0](RO/H) PCS lane 0 link training status. Format defined by BGX_SPU_BR_LANE_TRAIN_STATUS_S. */
15071 #else /* Word 0 - Little Endian */
15072         uint64_t ln0_train_status      : 4;  /**< [  3:  0](RO/H) PCS lane 0 link training status. Format defined by BGX_SPU_BR_LANE_TRAIN_STATUS_S. */
15073         uint64_t ln1_train_status      : 4;  /**< [  7:  4](RO/H) PCS lane 1 link training status. Format defined by BGX_SPU_BR_LANE_TRAIN_STATUS_S. Not
15074                                                                  valid for 10GBASE-R. */
15075         uint64_t ln2_train_status      : 4;  /**< [ 11:  8](RO/H) PCS lane 2 link training status. Format defined by BGX_SPU_BR_LANE_TRAIN_STATUS_S. Not
15076                                                                  valid for 10GBASE-R. */
15077         uint64_t ln3_train_status      : 4;  /**< [ 15: 12](RO/H) PCS lane 3 link training status. Format defined by BGX_SPU_BR_LANE_TRAIN_STATUS_S. Not
15078                                                                  valid for 10GBASE-R. */
15079         uint64_t reserved_16_63        : 48;
15080 #endif /* Word 0 - End */
15081     } s;
15082     /* struct bdk_bgxx_spux_br_pmd_status_s cn; */
15083 };
15084 typedef union bdk_bgxx_spux_br_pmd_status bdk_bgxx_spux_br_pmd_status_t;
15085 
15086 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_PMD_STATUS(unsigned long a,unsigned long b)15087 static inline uint64_t BDK_BGXX_SPUX_BR_PMD_STATUS(unsigned long a, unsigned long b)
15088 {
15089     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15090         return 0x87e0e0010070ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15091     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15092         return 0x87e0e0010070ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15093     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15094         return 0x87e0e0010070ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15095     __bdk_csr_fatal("BGXX_SPUX_BR_PMD_STATUS", 2, a, b, 0, 0);
15096 }
15097 
15098 #define typedef_BDK_BGXX_SPUX_BR_PMD_STATUS(a,b) bdk_bgxx_spux_br_pmd_status_t
15099 #define bustype_BDK_BGXX_SPUX_BR_PMD_STATUS(a,b) BDK_CSR_TYPE_RSL
15100 #define basename_BDK_BGXX_SPUX_BR_PMD_STATUS(a,b) "BGXX_SPUX_BR_PMD_STATUS"
15101 #define device_bar_BDK_BGXX_SPUX_BR_PMD_STATUS(a,b) 0x0 /* PF_BAR0 */
15102 #define busnum_BDK_BGXX_SPUX_BR_PMD_STATUS(a,b) (a)
15103 #define arguments_BDK_BGXX_SPUX_BR_PMD_STATUS(a,b) (a),(b),-1,-1
15104 
15105 /**
15106  * Register (RSL) bgx#_spu#_br_status1
15107  *
15108  * BGX SPU BASE-R Status 1 Registers
15109  */
15110 union bdk_bgxx_spux_br_status1
15111 {
15112     uint64_t u;
15113     struct bdk_bgxx_spux_br_status1_s
15114     {
15115 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15116         uint64_t reserved_13_63        : 51;
15117         uint64_t rcv_lnk               : 1;  /**< [ 12: 12](RO/H) BASE-R receive link status.
15118                                                                  0 = BASE-R PCS receive-link down.
15119                                                                  1 = BASE-R PCS receive-link up.
15120 
15121                                                                  This bit is a reflection of the PCS_status variable defined in IEEE 802.3 sections
15122                                                                  49.2.14.1 and 82.3.1. */
15123         uint64_t reserved_4_11         : 8;
15124         uint64_t prbs9                 : 1;  /**< [  3:  3](RO) 10GBASE-R PRBS9 pattern testing ability. Always 0; PRBS9 pattern testing is not supported. */
15125         uint64_t prbs31                : 1;  /**< [  2:  2](RO) 10GBASE-R PRBS31 pattern testing ability. Always 0; PRBS31 pattern testing is not supported. */
15126         uint64_t hi_ber                : 1;  /**< [  1:  1](RO/H) BASE-R PCS high bit-error rate.
15127                                                                  0 = 64/66 bit receiver is detecting a bit-error rate of \< 10.4.
15128                                                                  1 = 64/66 bit receiver is detecting a bit-error rate of \>= 10.4.
15129 
15130                                                                  This bit is a direct reflection of the state of the HI_BER variable in the 64 B/66 B state
15131                                                                  diagram and is defined in IEEE 802.3 sections 49.2.13.2.2 and 82.2.18.2.2. */
15132         uint64_t blk_lock              : 1;  /**< [  0:  0](RO/H) BASE-R PCS block lock.
15133                                                                  0 = No block lock.
15134                                                                  1 = 64/66 bit receiver for BASE-R has block lock.
15135 
15136                                                                  This bit is a direct reflection of the state of the BLOCK_LOCK variable in the 64 B/66 B
15137                                                                  state diagram and is defined in IEEE 802.3 sections 49.2.13.2.2 and 82.2.18.2.2.
15138                                                                  For a multilane logical PCS (i.e. 40GBASE-R), this bit indicates that the receiver has
15139                                                                  both block lock and alignment for all lanes and is identical to
15140                                                                  BGX()_SPU()_BR_ALGN_STATUS[ALIGND]. */
15141 #else /* Word 0 - Little Endian */
15142         uint64_t blk_lock              : 1;  /**< [  0:  0](RO/H) BASE-R PCS block lock.
15143                                                                  0 = No block lock.
15144                                                                  1 = 64/66 bit receiver for BASE-R has block lock.
15145 
15146                                                                  This bit is a direct reflection of the state of the BLOCK_LOCK variable in the 64 B/66 B
15147                                                                  state diagram and is defined in IEEE 802.3 sections 49.2.13.2.2 and 82.2.18.2.2.
15148                                                                  For a multilane logical PCS (i.e. 40GBASE-R), this bit indicates that the receiver has
15149                                                                  both block lock and alignment for all lanes and is identical to
15150                                                                  BGX()_SPU()_BR_ALGN_STATUS[ALIGND]. */
15151         uint64_t hi_ber                : 1;  /**< [  1:  1](RO/H) BASE-R PCS high bit-error rate.
15152                                                                  0 = 64/66 bit receiver is detecting a bit-error rate of \< 10.4.
15153                                                                  1 = 64/66 bit receiver is detecting a bit-error rate of \>= 10.4.
15154 
15155                                                                  This bit is a direct reflection of the state of the HI_BER variable in the 64 B/66 B state
15156                                                                  diagram and is defined in IEEE 802.3 sections 49.2.13.2.2 and 82.2.18.2.2. */
15157         uint64_t prbs31                : 1;  /**< [  2:  2](RO) 10GBASE-R PRBS31 pattern testing ability. Always 0; PRBS31 pattern testing is not supported. */
15158         uint64_t prbs9                 : 1;  /**< [  3:  3](RO) 10GBASE-R PRBS9 pattern testing ability. Always 0; PRBS9 pattern testing is not supported. */
15159         uint64_t reserved_4_11         : 8;
15160         uint64_t rcv_lnk               : 1;  /**< [ 12: 12](RO/H) BASE-R receive link status.
15161                                                                  0 = BASE-R PCS receive-link down.
15162                                                                  1 = BASE-R PCS receive-link up.
15163 
15164                                                                  This bit is a reflection of the PCS_status variable defined in IEEE 802.3 sections
15165                                                                  49.2.14.1 and 82.3.1. */
15166         uint64_t reserved_13_63        : 51;
15167 #endif /* Word 0 - End */
15168     } s;
15169     /* struct bdk_bgxx_spux_br_status1_s cn; */
15170 };
15171 typedef union bdk_bgxx_spux_br_status1 bdk_bgxx_spux_br_status1_t;
15172 
15173 static inline uint64_t BDK_BGXX_SPUX_BR_STATUS1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_STATUS1(unsigned long a,unsigned long b)15174 static inline uint64_t BDK_BGXX_SPUX_BR_STATUS1(unsigned long a, unsigned long b)
15175 {
15176     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15177         return 0x87e0e0010030ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15178     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15179         return 0x87e0e0010030ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15180     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15181         return 0x87e0e0010030ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15182     __bdk_csr_fatal("BGXX_SPUX_BR_STATUS1", 2, a, b, 0, 0);
15183 }
15184 
15185 #define typedef_BDK_BGXX_SPUX_BR_STATUS1(a,b) bdk_bgxx_spux_br_status1_t
15186 #define bustype_BDK_BGXX_SPUX_BR_STATUS1(a,b) BDK_CSR_TYPE_RSL
15187 #define basename_BDK_BGXX_SPUX_BR_STATUS1(a,b) "BGXX_SPUX_BR_STATUS1"
15188 #define device_bar_BDK_BGXX_SPUX_BR_STATUS1(a,b) 0x0 /* PF_BAR0 */
15189 #define busnum_BDK_BGXX_SPUX_BR_STATUS1(a,b) (a)
15190 #define arguments_BDK_BGXX_SPUX_BR_STATUS1(a,b) (a),(b),-1,-1
15191 
15192 /**
15193  * Register (RSL) bgx#_spu#_br_status2
15194  *
15195  * BGX SPU BASE-R Status 2 Registers
15196  * This register implements a combination of the following IEEE 802.3 registers:
15197  * * BASE-R PCS status 2 (MDIO address 3.33).
15198  * * BASE-R BER high-order counter (MDIO address 3.44).
15199  * * Errored-blocks high-order counter (MDIO address 3.45).
15200  *
15201  * Note that the relative locations of some fields have been moved from IEEE 802.3 in order to
15202  * make the register layout more software friendly: the BER counter high-order and low-order bits
15203  * from sections 3.44 and 3.33 have been combined into the contiguous, 22-bit [BER_CNT] field;
15204  * likewise, the errored-blocks counter high-order and low-order bits from section 3.45 have been
15205  * combined into the contiguous, 22-bit [ERR_BLKS] field.
15206  */
15207 union bdk_bgxx_spux_br_status2
15208 {
15209     uint64_t u;
15210     struct bdk_bgxx_spux_br_status2_s
15211     {
15212 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15213         uint64_t reserved_62_63        : 2;
15214         uint64_t err_blks              : 22; /**< [ 61: 40](RC/W/H) Errored-blocks counter. This is the BASE-R errored-blocks counter as defined by the
15215                                                                  errored_block_count variable specified in IEEE 802.3 sections 49.2.14.2 and 82.2.18.2.4.
15216                                                                  It
15217                                                                  increments by one on each block for which the BASE-R receive state machine, specified in Std
15218                                                                  802.3 diagrams 49-15 and 82-15, enters the RX_E state.
15219                                                                  Back-to-back blocks in the RX_E state are counted as transitions from RX_E to RX_E and
15220                                                                  keep incrementing the counter. The counter is reset to all zeros after this register is read
15221                                                                  by software.
15222 
15223                                                                  The reset operation takes precedence over the increment operation: if the register is read
15224                                                                  on the same clock cycle as an increment operation, the counter is reset to all zeros and the
15225                                                                  increment operation is lost.
15226 
15227                                                                  This field is writable for test purposes, rather than read-only as specified in IEEE
15228                                                                  802.3. */
15229         uint64_t reserved_38_39        : 2;
15230         uint64_t ber_cnt               : 22; /**< [ 37: 16](RC/W/H) Bit-error-rate counter. This is the BASE-R BER counter as defined by the BER_COUNT
15231                                                                  variable in IEEE 802.3 sections 49.2.14.2 and 82.2.18.2.4. The counter is reset to all zeros
15232                                                                  after this register is read by software, and is held at all ones in case of overflow.
15233                                                                  The reset operation takes precedence over the increment operation: if the register is read
15234                                                                  on the same clock cycle an increment operation, the counter is reset to all zeros and the
15235                                                                  increment operation is lost.
15236 
15237                                                                  This field is writable for test purposes, rather than read-only as specified in IEEE
15238                                                                  802.3. */
15239         uint64_t latched_lock          : 1;  /**< [ 15: 15](R/W1S/H) Latched-block lock.
15240                                                                  0 = No block.
15241                                                                  1 = 64/66 bit receiver for BASE-R has block lock.
15242 
15243                                                                  This is a latching-low version of BGX()_SPU()_BR_STATUS1[BLK_LOCK]; it stays clear
15244                                                                  until a write-1-to-set by software. */
15245         uint64_t latched_ber           : 1;  /**< [ 14: 14](R/W1C/H) Latched-high bit-error rate.
15246                                                                  0 = Not a high BER.
15247                                                                  1 = 64/66 bit receiver is detecting a high BER.
15248 
15249                                                                  This is a latching-high version of BGX()_SPU()_BR_STATUS1[HI_BER]; it stays set until
15250                                                                  a write-1-to-clear by software. */
15251         uint64_t reserved_0_13         : 14;
15252 #else /* Word 0 - Little Endian */
15253         uint64_t reserved_0_13         : 14;
15254         uint64_t latched_ber           : 1;  /**< [ 14: 14](R/W1C/H) Latched-high bit-error rate.
15255                                                                  0 = Not a high BER.
15256                                                                  1 = 64/66 bit receiver is detecting a high BER.
15257 
15258                                                                  This is a latching-high version of BGX()_SPU()_BR_STATUS1[HI_BER]; it stays set until
15259                                                                  a write-1-to-clear by software. */
15260         uint64_t latched_lock          : 1;  /**< [ 15: 15](R/W1S/H) Latched-block lock.
15261                                                                  0 = No block.
15262                                                                  1 = 64/66 bit receiver for BASE-R has block lock.
15263 
15264                                                                  This is a latching-low version of BGX()_SPU()_BR_STATUS1[BLK_LOCK]; it stays clear
15265                                                                  until a write-1-to-set by software. */
15266         uint64_t ber_cnt               : 22; /**< [ 37: 16](RC/W/H) Bit-error-rate counter. This is the BASE-R BER counter as defined by the BER_COUNT
15267                                                                  variable in IEEE 802.3 sections 49.2.14.2 and 82.2.18.2.4. The counter is reset to all zeros
15268                                                                  after this register is read by software, and is held at all ones in case of overflow.
15269                                                                  The reset operation takes precedence over the increment operation: if the register is read
15270                                                                  on the same clock cycle an increment operation, the counter is reset to all zeros and the
15271                                                                  increment operation is lost.
15272 
15273                                                                  This field is writable for test purposes, rather than read-only as specified in IEEE
15274                                                                  802.3. */
15275         uint64_t reserved_38_39        : 2;
15276         uint64_t err_blks              : 22; /**< [ 61: 40](RC/W/H) Errored-blocks counter. This is the BASE-R errored-blocks counter as defined by the
15277                                                                  errored_block_count variable specified in IEEE 802.3 sections 49.2.14.2 and 82.2.18.2.4.
15278                                                                  It
15279                                                                  increments by one on each block for which the BASE-R receive state machine, specified in Std
15280                                                                  802.3 diagrams 49-15 and 82-15, enters the RX_E state.
15281                                                                  Back-to-back blocks in the RX_E state are counted as transitions from RX_E to RX_E and
15282                                                                  keep incrementing the counter. The counter is reset to all zeros after this register is read
15283                                                                  by software.
15284 
15285                                                                  The reset operation takes precedence over the increment operation: if the register is read
15286                                                                  on the same clock cycle as an increment operation, the counter is reset to all zeros and the
15287                                                                  increment operation is lost.
15288 
15289                                                                  This field is writable for test purposes, rather than read-only as specified in IEEE
15290                                                                  802.3. */
15291         uint64_t reserved_62_63        : 2;
15292 #endif /* Word 0 - End */
15293     } s;
15294     /* struct bdk_bgxx_spux_br_status2_s cn; */
15295 };
15296 typedef union bdk_bgxx_spux_br_status2 bdk_bgxx_spux_br_status2_t;
15297 
15298 static inline uint64_t BDK_BGXX_SPUX_BR_STATUS2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_STATUS2(unsigned long a,unsigned long b)15299 static inline uint64_t BDK_BGXX_SPUX_BR_STATUS2(unsigned long a, unsigned long b)
15300 {
15301     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15302         return 0x87e0e0010038ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15303     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15304         return 0x87e0e0010038ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15305     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15306         return 0x87e0e0010038ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15307     __bdk_csr_fatal("BGXX_SPUX_BR_STATUS2", 2, a, b, 0, 0);
15308 }
15309 
15310 #define typedef_BDK_BGXX_SPUX_BR_STATUS2(a,b) bdk_bgxx_spux_br_status2_t
15311 #define bustype_BDK_BGXX_SPUX_BR_STATUS2(a,b) BDK_CSR_TYPE_RSL
15312 #define basename_BDK_BGXX_SPUX_BR_STATUS2(a,b) "BGXX_SPUX_BR_STATUS2"
15313 #define device_bar_BDK_BGXX_SPUX_BR_STATUS2(a,b) 0x0 /* PF_BAR0 */
15314 #define busnum_BDK_BGXX_SPUX_BR_STATUS2(a,b) (a)
15315 #define arguments_BDK_BGXX_SPUX_BR_STATUS2(a,b) (a),(b),-1,-1
15316 
15317 /**
15318  * Register (RSL) bgx#_spu#_br_tp_control
15319  *
15320  * BGX SPU BASE-R Test-Pattern Control Registers
15321  * Refer to the test pattern methodology described in 802.3 sections 49.2.8 and 82.2.10.
15322  */
15323 union bdk_bgxx_spux_br_tp_control
15324 {
15325     uint64_t u;
15326     struct bdk_bgxx_spux_br_tp_control_s
15327     {
15328 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15329         uint64_t reserved_8_63         : 56;
15330         uint64_t scramble_tp           : 1;  /**< [  7:  7](R/W) Select scrambled idle test pattern. This bit selects the transmit test pattern used when
15331                                                                  [TX_TP_EN] is set:
15332                                                                  0 = Square wave test pattern.
15333                                                                  1 = Scrambled idle test pattern. */
15334         uint64_t prbs9_tx              : 1;  /**< [  6:  6](RO) 10GBASE-R PRBS9 TP transmit enable. Always 0; PRBS9 pattern testing is not supported. */
15335         uint64_t prbs31_rx             : 1;  /**< [  5:  5](RO) 10GBASE-R PRBS31 TP receive enable. Always 0; PRBS31 pattern testing is not supported. */
15336         uint64_t prbs31_tx             : 1;  /**< [  4:  4](RO) 10GBASE-R PRBS31 TP transmit enable. Always 0; PRBS31 pattern is not supported. */
15337         uint64_t tx_tp_en              : 1;  /**< [  3:  3](R/W) Transmit-test-pattern enable. */
15338         uint64_t rx_tp_en              : 1;  /**< [  2:  2](R/W) Receive-test-pattern enable. The only supported receive test pattern is the scrambled idle
15339                                                                  test pattern. Setting this bit enables checking of that receive pattern. */
15340         uint64_t tp_sel                : 1;  /**< [  1:  1](RO/H) Square/PRBS test pattern select. Always 1 to select square wave test pattern; PRBS test
15341                                                                  patterns are not supported. */
15342         uint64_t dp_sel                : 1;  /**< [  0:  0](RO) Data pattern select. Always 0; PRBS test patterns are not supported. */
15343 #else /* Word 0 - Little Endian */
15344         uint64_t dp_sel                : 1;  /**< [  0:  0](RO) Data pattern select. Always 0; PRBS test patterns are not supported. */
15345         uint64_t tp_sel                : 1;  /**< [  1:  1](RO/H) Square/PRBS test pattern select. Always 1 to select square wave test pattern; PRBS test
15346                                                                  patterns are not supported. */
15347         uint64_t rx_tp_en              : 1;  /**< [  2:  2](R/W) Receive-test-pattern enable. The only supported receive test pattern is the scrambled idle
15348                                                                  test pattern. Setting this bit enables checking of that receive pattern. */
15349         uint64_t tx_tp_en              : 1;  /**< [  3:  3](R/W) Transmit-test-pattern enable. */
15350         uint64_t prbs31_tx             : 1;  /**< [  4:  4](RO) 10GBASE-R PRBS31 TP transmit enable. Always 0; PRBS31 pattern is not supported. */
15351         uint64_t prbs31_rx             : 1;  /**< [  5:  5](RO) 10GBASE-R PRBS31 TP receive enable. Always 0; PRBS31 pattern testing is not supported. */
15352         uint64_t prbs9_tx              : 1;  /**< [  6:  6](RO) 10GBASE-R PRBS9 TP transmit enable. Always 0; PRBS9 pattern testing is not supported. */
15353         uint64_t scramble_tp           : 1;  /**< [  7:  7](R/W) Select scrambled idle test pattern. This bit selects the transmit test pattern used when
15354                                                                  [TX_TP_EN] is set:
15355                                                                  0 = Square wave test pattern.
15356                                                                  1 = Scrambled idle test pattern. */
15357         uint64_t reserved_8_63         : 56;
15358 #endif /* Word 0 - End */
15359     } s;
15360     /* struct bdk_bgxx_spux_br_tp_control_s cn; */
15361 };
15362 typedef union bdk_bgxx_spux_br_tp_control bdk_bgxx_spux_br_tp_control_t;
15363 
15364 static inline uint64_t BDK_BGXX_SPUX_BR_TP_CONTROL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_TP_CONTROL(unsigned long a,unsigned long b)15365 static inline uint64_t BDK_BGXX_SPUX_BR_TP_CONTROL(unsigned long a, unsigned long b)
15366 {
15367     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15368         return 0x87e0e0010040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15369     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15370         return 0x87e0e0010040ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15371     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15372         return 0x87e0e0010040ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15373     __bdk_csr_fatal("BGXX_SPUX_BR_TP_CONTROL", 2, a, b, 0, 0);
15374 }
15375 
15376 #define typedef_BDK_BGXX_SPUX_BR_TP_CONTROL(a,b) bdk_bgxx_spux_br_tp_control_t
15377 #define bustype_BDK_BGXX_SPUX_BR_TP_CONTROL(a,b) BDK_CSR_TYPE_RSL
15378 #define basename_BDK_BGXX_SPUX_BR_TP_CONTROL(a,b) "BGXX_SPUX_BR_TP_CONTROL"
15379 #define device_bar_BDK_BGXX_SPUX_BR_TP_CONTROL(a,b) 0x0 /* PF_BAR0 */
15380 #define busnum_BDK_BGXX_SPUX_BR_TP_CONTROL(a,b) (a)
15381 #define arguments_BDK_BGXX_SPUX_BR_TP_CONTROL(a,b) (a),(b),-1,-1
15382 
15383 /**
15384  * Register (RSL) bgx#_spu#_br_tp_err_cnt
15385  *
15386  * BGX SPU BASE-R Test-Pattern Error-Count Registers
15387  * This register provides the BASE-R PCS test-pattern error counter.
15388  */
15389 union bdk_bgxx_spux_br_tp_err_cnt
15390 {
15391     uint64_t u;
15392     struct bdk_bgxx_spux_br_tp_err_cnt_s
15393     {
15394 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15395         uint64_t reserved_16_63        : 48;
15396         uint64_t err_cnt               : 16; /**< [ 15:  0](RC/W/H) Error counter. This 16-bit counter contains the number of errors received during a pattern
15397                                                                  test. These bits are reset to all zeros when this register is read by software, and they are
15398                                                                  held at all ones in the case of overflow.
15399 
15400                                                                  The test pattern methodology is described in IEEE 802.3, Sections 49.2.12 and 82.2.10.
15401                                                                  This
15402                                                                  counter counts either block errors or bit errors dependent on the test mode (see Section
15403                                                                  49.2.12). The reset operation takes precedence over the increment operation; if the
15404                                                                  register is read on the same clock cycle as an increment operation, the counter is reset
15405                                                                  to all zeros and the increment operation is lost. This field is writable for test purposes,
15406                                                                  rather than read-only as specified in IEEE 802.3. */
15407 #else /* Word 0 - Little Endian */
15408         uint64_t err_cnt               : 16; /**< [ 15:  0](RC/W/H) Error counter. This 16-bit counter contains the number of errors received during a pattern
15409                                                                  test. These bits are reset to all zeros when this register is read by software, and they are
15410                                                                  held at all ones in the case of overflow.
15411 
15412                                                                  The test pattern methodology is described in IEEE 802.3, Sections 49.2.12 and 82.2.10.
15413                                                                  This
15414                                                                  counter counts either block errors or bit errors dependent on the test mode (see Section
15415                                                                  49.2.12). The reset operation takes precedence over the increment operation; if the
15416                                                                  register is read on the same clock cycle as an increment operation, the counter is reset
15417                                                                  to all zeros and the increment operation is lost. This field is writable for test purposes,
15418                                                                  rather than read-only as specified in IEEE 802.3. */
15419         uint64_t reserved_16_63        : 48;
15420 #endif /* Word 0 - End */
15421     } s;
15422     /* struct bdk_bgxx_spux_br_tp_err_cnt_s cn; */
15423 };
15424 typedef union bdk_bgxx_spux_br_tp_err_cnt bdk_bgxx_spux_br_tp_err_cnt_t;
15425 
15426 static inline uint64_t BDK_BGXX_SPUX_BR_TP_ERR_CNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BR_TP_ERR_CNT(unsigned long a,unsigned long b)15427 static inline uint64_t BDK_BGXX_SPUX_BR_TP_ERR_CNT(unsigned long a, unsigned long b)
15428 {
15429     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15430         return 0x87e0e0010048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15431     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15432         return 0x87e0e0010048ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15433     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15434         return 0x87e0e0010048ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15435     __bdk_csr_fatal("BGXX_SPUX_BR_TP_ERR_CNT", 2, a, b, 0, 0);
15436 }
15437 
15438 #define typedef_BDK_BGXX_SPUX_BR_TP_ERR_CNT(a,b) bdk_bgxx_spux_br_tp_err_cnt_t
15439 #define bustype_BDK_BGXX_SPUX_BR_TP_ERR_CNT(a,b) BDK_CSR_TYPE_RSL
15440 #define basename_BDK_BGXX_SPUX_BR_TP_ERR_CNT(a,b) "BGXX_SPUX_BR_TP_ERR_CNT"
15441 #define device_bar_BDK_BGXX_SPUX_BR_TP_ERR_CNT(a,b) 0x0 /* PF_BAR0 */
15442 #define busnum_BDK_BGXX_SPUX_BR_TP_ERR_CNT(a,b) (a)
15443 #define arguments_BDK_BGXX_SPUX_BR_TP_ERR_CNT(a,b) (a),(b),-1,-1
15444 
15445 /**
15446  * Register (RSL) bgx#_spu#_bx_status
15447  *
15448  * BGX SPU BASE-X Status Registers
15449  */
15450 union bdk_bgxx_spux_bx_status
15451 {
15452     uint64_t u;
15453     struct bdk_bgxx_spux_bx_status_s
15454     {
15455 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15456         uint64_t reserved_13_63        : 51;
15457         uint64_t alignd                : 1;  /**< [ 12: 12](RO/H) 10GBASE-X lane-alignment status.
15458                                                                  0 = receive lanes not aligned.
15459                                                                  1 = receive lanes aligned. */
15460         uint64_t pattst                : 1;  /**< [ 11: 11](RO) Pattern-testing ability. Always 0; 10GBASE-X pattern is testing not supported. */
15461         uint64_t reserved_4_10         : 7;
15462         uint64_t lsync                 : 4;  /**< [  3:  0](RO/H) Lane synchronization. BASE-X lane synchronization status for PCS lanes 3-0. Each bit is
15463                                                                  set when the associated lane is code-group synchronized, and clear otherwise. If the PCS
15464                                                                  type is RXAUI (i.e. the associated BGX()_CMR()_CONFIG[LMAC_TYPE] = RXAUI), then
15465                                                                  only lanes 1-0 are valid. */
15466 #else /* Word 0 - Little Endian */
15467         uint64_t lsync                 : 4;  /**< [  3:  0](RO/H) Lane synchronization. BASE-X lane synchronization status for PCS lanes 3-0. Each bit is
15468                                                                  set when the associated lane is code-group synchronized, and clear otherwise. If the PCS
15469                                                                  type is RXAUI (i.e. the associated BGX()_CMR()_CONFIG[LMAC_TYPE] = RXAUI), then
15470                                                                  only lanes 1-0 are valid. */
15471         uint64_t reserved_4_10         : 7;
15472         uint64_t pattst                : 1;  /**< [ 11: 11](RO) Pattern-testing ability. Always 0; 10GBASE-X pattern is testing not supported. */
15473         uint64_t alignd                : 1;  /**< [ 12: 12](RO/H) 10GBASE-X lane-alignment status.
15474                                                                  0 = receive lanes not aligned.
15475                                                                  1 = receive lanes aligned. */
15476         uint64_t reserved_13_63        : 51;
15477 #endif /* Word 0 - End */
15478     } s;
15479     /* struct bdk_bgxx_spux_bx_status_s cn; */
15480 };
15481 typedef union bdk_bgxx_spux_bx_status bdk_bgxx_spux_bx_status_t;
15482 
15483 static inline uint64_t BDK_BGXX_SPUX_BX_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_BX_STATUS(unsigned long a,unsigned long b)15484 static inline uint64_t BDK_BGXX_SPUX_BX_STATUS(unsigned long a, unsigned long b)
15485 {
15486     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15487         return 0x87e0e0010028ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15488     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15489         return 0x87e0e0010028ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15490     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15491         return 0x87e0e0010028ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15492     __bdk_csr_fatal("BGXX_SPUX_BX_STATUS", 2, a, b, 0, 0);
15493 }
15494 
15495 #define typedef_BDK_BGXX_SPUX_BX_STATUS(a,b) bdk_bgxx_spux_bx_status_t
15496 #define bustype_BDK_BGXX_SPUX_BX_STATUS(a,b) BDK_CSR_TYPE_RSL
15497 #define basename_BDK_BGXX_SPUX_BX_STATUS(a,b) "BGXX_SPUX_BX_STATUS"
15498 #define device_bar_BDK_BGXX_SPUX_BX_STATUS(a,b) 0x0 /* PF_BAR0 */
15499 #define busnum_BDK_BGXX_SPUX_BX_STATUS(a,b) (a)
15500 #define arguments_BDK_BGXX_SPUX_BX_STATUS(a,b) (a),(b),-1,-1
15501 
15502 /**
15503  * Register (RSL) bgx#_spu#_control1
15504  *
15505  * BGX SPU Control 1 Registers
15506  */
15507 union bdk_bgxx_spux_control1
15508 {
15509     uint64_t u;
15510     struct bdk_bgxx_spux_control1_s
15511     {
15512 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15513         uint64_t reserved_16_63        : 48;
15514         uint64_t reset                 : 1;  /**< [ 15: 15](R/W1S/H) Reset. Setting this bit or BGX()_SPU()_AN_CONTROL[AN_RESET] to 1 causes the
15515                                                                  following to happen:
15516                                                                  * Resets the logical PCS (LPCS)
15517                                                                  * Sets the IEEE 802.3 PCS, FEC and AN registers for the LPCS to their default states
15518                                                                  * Resets the associated SerDes lanes.
15519 
15520                                                                  It takes up to 32 coprocessor-clock cycles to reset the LPCS, after which RESET is
15521                                                                  automatically cleared. */
15522         uint64_t loopbck               : 1;  /**< [ 14: 14](R/W) TX-to-RX loopback enable. When set, transmit data for each SerDes lane is looped back as
15523                                                                  receive data. */
15524         uint64_t spdsel1               : 1;  /**< [ 13: 13](RO/H) Speed select 1: always 1. */
15525         uint64_t reserved_12           : 1;
15526         uint64_t lo_pwr                : 1;  /**< [ 11: 11](R/W) Low power enable. When set, the LPCS is disabled (overriding the associated
15527                                                                  BGX()_CMR()_CONFIG[ENABLE]), and the SerDes lanes associated with the LPCS are
15528                                                                  reset. */
15529         uint64_t reserved_7_10         : 4;
15530         uint64_t spdsel0               : 1;  /**< [  6:  6](RO/H) Speed select 0: always 1. */
15531         uint64_t spd                   : 4;  /**< [  5:  2](RO/H) '"Speed selection.
15532                                                                  Note that this is a read-only field rather than read/write as
15533                                                                  specified in 802.3.
15534                                                                  The LPCS speed is instead configured by the associated
15535                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. The read values returned by this field are as
15536                                                                  follows:
15537 
15538                                                                  \<pre\>
15539                                                                    LMAC_TYPE   Speed       SPD Read Value    Comment
15540                                                                    ------------------------------------------------------
15541                                                                    XAUI        10G/20G     0x0               20G if DXAUI
15542                                                                    RXAUI       10G         0x0
15543                                                                    10G_R       10G         0x0
15544                                                                    40G_R       40G         0x3
15545                                                                    Other       -           X
15546                                                                  \</pre\>' */
15547         uint64_t reserved_0_1          : 2;
15548 #else /* Word 0 - Little Endian */
15549         uint64_t reserved_0_1          : 2;
15550         uint64_t spd                   : 4;  /**< [  5:  2](RO/H) '"Speed selection.
15551                                                                  Note that this is a read-only field rather than read/write as
15552                                                                  specified in 802.3.
15553                                                                  The LPCS speed is instead configured by the associated
15554                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. The read values returned by this field are as
15555                                                                  follows:
15556 
15557                                                                  \<pre\>
15558                                                                    LMAC_TYPE   Speed       SPD Read Value    Comment
15559                                                                    ------------------------------------------------------
15560                                                                    XAUI        10G/20G     0x0               20G if DXAUI
15561                                                                    RXAUI       10G         0x0
15562                                                                    10G_R       10G         0x0
15563                                                                    40G_R       40G         0x3
15564                                                                    Other       -           X
15565                                                                  \</pre\>' */
15566         uint64_t spdsel0               : 1;  /**< [  6:  6](RO/H) Speed select 0: always 1. */
15567         uint64_t reserved_7_10         : 4;
15568         uint64_t lo_pwr                : 1;  /**< [ 11: 11](R/W) Low power enable. When set, the LPCS is disabled (overriding the associated
15569                                                                  BGX()_CMR()_CONFIG[ENABLE]), and the SerDes lanes associated with the LPCS are
15570                                                                  reset. */
15571         uint64_t reserved_12           : 1;
15572         uint64_t spdsel1               : 1;  /**< [ 13: 13](RO/H) Speed select 1: always 1. */
15573         uint64_t loopbck               : 1;  /**< [ 14: 14](R/W) TX-to-RX loopback enable. When set, transmit data for each SerDes lane is looped back as
15574                                                                  receive data. */
15575         uint64_t reset                 : 1;  /**< [ 15: 15](R/W1S/H) Reset. Setting this bit or BGX()_SPU()_AN_CONTROL[AN_RESET] to 1 causes the
15576                                                                  following to happen:
15577                                                                  * Resets the logical PCS (LPCS)
15578                                                                  * Sets the IEEE 802.3 PCS, FEC and AN registers for the LPCS to their default states
15579                                                                  * Resets the associated SerDes lanes.
15580 
15581                                                                  It takes up to 32 coprocessor-clock cycles to reset the LPCS, after which RESET is
15582                                                                  automatically cleared. */
15583         uint64_t reserved_16_63        : 48;
15584 #endif /* Word 0 - End */
15585     } s;
15586     /* struct bdk_bgxx_spux_control1_s cn; */
15587 };
15588 typedef union bdk_bgxx_spux_control1 bdk_bgxx_spux_control1_t;
15589 
15590 static inline uint64_t BDK_BGXX_SPUX_CONTROL1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_CONTROL1(unsigned long a,unsigned long b)15591 static inline uint64_t BDK_BGXX_SPUX_CONTROL1(unsigned long a, unsigned long b)
15592 {
15593     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15594         return 0x87e0e0010000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15595     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15596         return 0x87e0e0010000ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15597     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15598         return 0x87e0e0010000ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15599     __bdk_csr_fatal("BGXX_SPUX_CONTROL1", 2, a, b, 0, 0);
15600 }
15601 
15602 #define typedef_BDK_BGXX_SPUX_CONTROL1(a,b) bdk_bgxx_spux_control1_t
15603 #define bustype_BDK_BGXX_SPUX_CONTROL1(a,b) BDK_CSR_TYPE_RSL
15604 #define basename_BDK_BGXX_SPUX_CONTROL1(a,b) "BGXX_SPUX_CONTROL1"
15605 #define device_bar_BDK_BGXX_SPUX_CONTROL1(a,b) 0x0 /* PF_BAR0 */
15606 #define busnum_BDK_BGXX_SPUX_CONTROL1(a,b) (a)
15607 #define arguments_BDK_BGXX_SPUX_CONTROL1(a,b) (a),(b),-1,-1
15608 
15609 /**
15610  * Register (RSL) bgx#_spu#_control2
15611  *
15612  * BGX SPU Control 2 Registers
15613  */
15614 union bdk_bgxx_spux_control2
15615 {
15616     uint64_t u;
15617     struct bdk_bgxx_spux_control2_s
15618     {
15619 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15620         uint64_t reserved_3_63         : 61;
15621         uint64_t pcs_type              : 3;  /**< [  2:  0](RO/H) PCS type selection.
15622                                                                  Note that this is a read-only field rather than read/write as
15623                                                                  specified in 802.3.
15624                                                                  The LPCS speed is instead configured by the associated
15625                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. The read values returned by this field are as
15626                                                                  follows:
15627 
15628                                                                  \<pre\>
15629                                                                                [PCS_TYPE]
15630                                                                    LMAC_TYPE   Read Value      Comment
15631                                                                    -------------------------------------------------
15632                                                                    XAUI        0x1             10GBASE-X PCS type
15633                                                                    RXAUI       0x1             10GBASE-X PCS type
15634                                                                    10G_R       0x0             10GBASE-R PCS type
15635                                                                    40G_R       0x4             40GBASE-R PCS type
15636                                                                    Other       Undefined       Reserved
15637                                                                  \</pre\> */
15638 #else /* Word 0 - Little Endian */
15639         uint64_t pcs_type              : 3;  /**< [  2:  0](RO/H) PCS type selection.
15640                                                                  Note that this is a read-only field rather than read/write as
15641                                                                  specified in 802.3.
15642                                                                  The LPCS speed is instead configured by the associated
15643                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]. The read values returned by this field are as
15644                                                                  follows:
15645 
15646                                                                  \<pre\>
15647                                                                                [PCS_TYPE]
15648                                                                    LMAC_TYPE   Read Value      Comment
15649                                                                    -------------------------------------------------
15650                                                                    XAUI        0x1             10GBASE-X PCS type
15651                                                                    RXAUI       0x1             10GBASE-X PCS type
15652                                                                    10G_R       0x0             10GBASE-R PCS type
15653                                                                    40G_R       0x4             40GBASE-R PCS type
15654                                                                    Other       Undefined       Reserved
15655                                                                  \</pre\> */
15656         uint64_t reserved_3_63         : 61;
15657 #endif /* Word 0 - End */
15658     } s;
15659     /* struct bdk_bgxx_spux_control2_s cn; */
15660 };
15661 typedef union bdk_bgxx_spux_control2 bdk_bgxx_spux_control2_t;
15662 
15663 static inline uint64_t BDK_BGXX_SPUX_CONTROL2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_CONTROL2(unsigned long a,unsigned long b)15664 static inline uint64_t BDK_BGXX_SPUX_CONTROL2(unsigned long a, unsigned long b)
15665 {
15666     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15667         return 0x87e0e0010018ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15668     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15669         return 0x87e0e0010018ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15670     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15671         return 0x87e0e0010018ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15672     __bdk_csr_fatal("BGXX_SPUX_CONTROL2", 2, a, b, 0, 0);
15673 }
15674 
15675 #define typedef_BDK_BGXX_SPUX_CONTROL2(a,b) bdk_bgxx_spux_control2_t
15676 #define bustype_BDK_BGXX_SPUX_CONTROL2(a,b) BDK_CSR_TYPE_RSL
15677 #define basename_BDK_BGXX_SPUX_CONTROL2(a,b) "BGXX_SPUX_CONTROL2"
15678 #define device_bar_BDK_BGXX_SPUX_CONTROL2(a,b) 0x0 /* PF_BAR0 */
15679 #define busnum_BDK_BGXX_SPUX_CONTROL2(a,b) (a)
15680 #define arguments_BDK_BGXX_SPUX_CONTROL2(a,b) (a),(b),-1,-1
15681 
15682 /**
15683  * Register (RSL) bgx#_spu#_fec_abil
15684  *
15685  * BGX SPU Forward Error Correction Ability Registers
15686  */
15687 union bdk_bgxx_spux_fec_abil
15688 {
15689     uint64_t u;
15690     struct bdk_bgxx_spux_fec_abil_s
15691     {
15692 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15693         uint64_t reserved_2_63         : 62;
15694         uint64_t err_abil              : 1;  /**< [  1:  1](RO/H) BASE-R FEC error-indication ability. Always 1 when the LPCS type is BASE-R,
15695                                                                  i.e. BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4. Always 0 otherwise. */
15696         uint64_t fec_abil              : 1;  /**< [  0:  0](RO/H) BASE-R FEC ability. Always 1 when the LPCS type is BASE-R,
15697                                                                  i.e. BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4. Always 0 otherwise. */
15698 #else /* Word 0 - Little Endian */
15699         uint64_t fec_abil              : 1;  /**< [  0:  0](RO/H) BASE-R FEC ability. Always 1 when the LPCS type is BASE-R,
15700                                                                  i.e. BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4. Always 0 otherwise. */
15701         uint64_t err_abil              : 1;  /**< [  1:  1](RO/H) BASE-R FEC error-indication ability. Always 1 when the LPCS type is BASE-R,
15702                                                                  i.e. BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4. Always 0 otherwise. */
15703         uint64_t reserved_2_63         : 62;
15704 #endif /* Word 0 - End */
15705     } s;
15706     /* struct bdk_bgxx_spux_fec_abil_s cn; */
15707 };
15708 typedef union bdk_bgxx_spux_fec_abil bdk_bgxx_spux_fec_abil_t;
15709 
15710 static inline uint64_t BDK_BGXX_SPUX_FEC_ABIL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_FEC_ABIL(unsigned long a,unsigned long b)15711 static inline uint64_t BDK_BGXX_SPUX_FEC_ABIL(unsigned long a, unsigned long b)
15712 {
15713     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15714         return 0x87e0e0010098ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15715     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15716         return 0x87e0e0010098ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15717     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15718         return 0x87e0e0010098ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15719     __bdk_csr_fatal("BGXX_SPUX_FEC_ABIL", 2, a, b, 0, 0);
15720 }
15721 
15722 #define typedef_BDK_BGXX_SPUX_FEC_ABIL(a,b) bdk_bgxx_spux_fec_abil_t
15723 #define bustype_BDK_BGXX_SPUX_FEC_ABIL(a,b) BDK_CSR_TYPE_RSL
15724 #define basename_BDK_BGXX_SPUX_FEC_ABIL(a,b) "BGXX_SPUX_FEC_ABIL"
15725 #define device_bar_BDK_BGXX_SPUX_FEC_ABIL(a,b) 0x0 /* PF_BAR0 */
15726 #define busnum_BDK_BGXX_SPUX_FEC_ABIL(a,b) (a)
15727 #define arguments_BDK_BGXX_SPUX_FEC_ABIL(a,b) (a),(b),-1,-1
15728 
15729 /**
15730  * Register (RSL) bgx#_spu#_fec_control
15731  *
15732  * BGX SPU Forward Error Correction Control Registers
15733  */
15734 union bdk_bgxx_spux_fec_control
15735 {
15736     uint64_t u;
15737     struct bdk_bgxx_spux_fec_control_s
15738     {
15739 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15740         uint64_t reserved_2_63         : 62;
15741         uint64_t err_en                : 1;  /**< [  1:  1](R/W) BASE-R FEC error-indication enable. This bit corresponds to FEC_Enable_Error_to_PCS
15742                                                                  variable for BASE-R as defined in 802.3 Clause 74. When FEC is enabled ([FEC_EN] is set)
15743                                                                  and this bit is set, the FEC decoder on the receive side signals an
15744                                                                  uncorrectable FEC error to the BASE-R decoder by driving a value of 2'b11 on the sync bits
15745                                                                  for some of the 32 64/66 bit blocks belonging to the uncorrectable FEC block. See
15746                                                                  802.3-2008/802.3ba-2010 section 74.7.4.5.1 for more details. */
15747         uint64_t fec_en                : 1;  /**< [  0:  0](R/W) BASE-R FEC enable. When this bit is set and the LPCS type is BASE-R
15748                                                                  (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), forward error correction is enabled. FEC is
15749                                                                  disabled otherwise. Forward error correction is defined in IEEE Std
15750                                                                  802.3-2008/802.3ba-2010 Clause 74. */
15751 #else /* Word 0 - Little Endian */
15752         uint64_t fec_en                : 1;  /**< [  0:  0](R/W) BASE-R FEC enable. When this bit is set and the LPCS type is BASE-R
15753                                                                  (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4), forward error correction is enabled. FEC is
15754                                                                  disabled otherwise. Forward error correction is defined in IEEE Std
15755                                                                  802.3-2008/802.3ba-2010 Clause 74. */
15756         uint64_t err_en                : 1;  /**< [  1:  1](R/W) BASE-R FEC error-indication enable. This bit corresponds to FEC_Enable_Error_to_PCS
15757                                                                  variable for BASE-R as defined in 802.3 Clause 74. When FEC is enabled ([FEC_EN] is set)
15758                                                                  and this bit is set, the FEC decoder on the receive side signals an
15759                                                                  uncorrectable FEC error to the BASE-R decoder by driving a value of 2'b11 on the sync bits
15760                                                                  for some of the 32 64/66 bit blocks belonging to the uncorrectable FEC block. See
15761                                                                  802.3-2008/802.3ba-2010 section 74.7.4.5.1 for more details. */
15762         uint64_t reserved_2_63         : 62;
15763 #endif /* Word 0 - End */
15764     } s;
15765     /* struct bdk_bgxx_spux_fec_control_s cn; */
15766 };
15767 typedef union bdk_bgxx_spux_fec_control bdk_bgxx_spux_fec_control_t;
15768 
15769 static inline uint64_t BDK_BGXX_SPUX_FEC_CONTROL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_FEC_CONTROL(unsigned long a,unsigned long b)15770 static inline uint64_t BDK_BGXX_SPUX_FEC_CONTROL(unsigned long a, unsigned long b)
15771 {
15772     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15773         return 0x87e0e00100a0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15774     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15775         return 0x87e0e00100a0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15776     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15777         return 0x87e0e00100a0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15778     __bdk_csr_fatal("BGXX_SPUX_FEC_CONTROL", 2, a, b, 0, 0);
15779 }
15780 
15781 #define typedef_BDK_BGXX_SPUX_FEC_CONTROL(a,b) bdk_bgxx_spux_fec_control_t
15782 #define bustype_BDK_BGXX_SPUX_FEC_CONTROL(a,b) BDK_CSR_TYPE_RSL
15783 #define basename_BDK_BGXX_SPUX_FEC_CONTROL(a,b) "BGXX_SPUX_FEC_CONTROL"
15784 #define device_bar_BDK_BGXX_SPUX_FEC_CONTROL(a,b) 0x0 /* PF_BAR0 */
15785 #define busnum_BDK_BGXX_SPUX_FEC_CONTROL(a,b) (a)
15786 #define arguments_BDK_BGXX_SPUX_FEC_CONTROL(a,b) (a),(b),-1,-1
15787 
15788 /**
15789  * Register (RSL) bgx#_spu#_fec_corr_blks01
15790  *
15791  * BGX SPU FEC Corrected-Blocks Counters 0/1 Registers
15792  * This register is valid only when the LPCS type is BASE-R
15793  * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4). The FEC corrected-block counters are
15794  * defined in IEEE 802.3 section 74.8.4.1. Each corrected-blocks counter increments by 1 for a
15795  * corrected FEC block, i.e. an FEC block that has been received with invalid parity on the
15796  * associated PCS lane and has been corrected by the FEC decoder. The counter is reset to all 0s
15797  * when the register is read, and held at all 1s in case of overflow.
15798  *
15799  * The reset operation takes precedence over the increment operation; if the register is read on
15800  * the same clock cycle as an increment operation, the counter is reset to all 0s and the
15801  * increment operation is lost. The counters are writable for test purposes, rather than read-
15802  * only as specified in IEEE 802.3.
15803  */
15804 union bdk_bgxx_spux_fec_corr_blks01
15805 {
15806     uint64_t u;
15807     struct bdk_bgxx_spux_fec_corr_blks01_s
15808     {
15809 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15810         uint64_t ln1_corr_blks         : 32; /**< [ 63: 32](RC/W/H) PCS Lane 1 FEC corrected blocks.
15811                                                                  * For 10GBASE-R, reserved.
15812                                                                  * For 40GBASE-R, correspond to the IEEE 802.3 FEC_corrected_blocks_counter_1 variable
15813                                                                  (registers 1.302-1.303). */
15814         uint64_t ln0_corr_blks         : 32; /**< [ 31:  0](RC/W/H) PCS Lane 0 FEC corrected blocks.
15815                                                                  * For 10GBASE-R, corresponds to the IEEE 802.3 FEC_corrected_blocks_counter variable
15816                                                                  (registers 1.172-1.173).
15817                                                                  * For 40GBASE-R, correspond to the IEEE 802.3 FEC_corrected_blocks_counter_0 variable
15818                                                                  (registers 1.300-1.301). */
15819 #else /* Word 0 - Little Endian */
15820         uint64_t ln0_corr_blks         : 32; /**< [ 31:  0](RC/W/H) PCS Lane 0 FEC corrected blocks.
15821                                                                  * For 10GBASE-R, corresponds to the IEEE 802.3 FEC_corrected_blocks_counter variable
15822                                                                  (registers 1.172-1.173).
15823                                                                  * For 40GBASE-R, correspond to the IEEE 802.3 FEC_corrected_blocks_counter_0 variable
15824                                                                  (registers 1.300-1.301). */
15825         uint64_t ln1_corr_blks         : 32; /**< [ 63: 32](RC/W/H) PCS Lane 1 FEC corrected blocks.
15826                                                                  * For 10GBASE-R, reserved.
15827                                                                  * For 40GBASE-R, correspond to the IEEE 802.3 FEC_corrected_blocks_counter_1 variable
15828                                                                  (registers 1.302-1.303). */
15829 #endif /* Word 0 - End */
15830     } s;
15831     /* struct bdk_bgxx_spux_fec_corr_blks01_s cn; */
15832 };
15833 typedef union bdk_bgxx_spux_fec_corr_blks01 bdk_bgxx_spux_fec_corr_blks01_t;
15834 
15835 static inline uint64_t BDK_BGXX_SPUX_FEC_CORR_BLKS01(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_FEC_CORR_BLKS01(unsigned long a,unsigned long b)15836 static inline uint64_t BDK_BGXX_SPUX_FEC_CORR_BLKS01(unsigned long a, unsigned long b)
15837 {
15838     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15839         return 0x87e0e00100a8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15840     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15841         return 0x87e0e00100a8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15842     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15843         return 0x87e0e00100a8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15844     __bdk_csr_fatal("BGXX_SPUX_FEC_CORR_BLKS01", 2, a, b, 0, 0);
15845 }
15846 
15847 #define typedef_BDK_BGXX_SPUX_FEC_CORR_BLKS01(a,b) bdk_bgxx_spux_fec_corr_blks01_t
15848 #define bustype_BDK_BGXX_SPUX_FEC_CORR_BLKS01(a,b) BDK_CSR_TYPE_RSL
15849 #define basename_BDK_BGXX_SPUX_FEC_CORR_BLKS01(a,b) "BGXX_SPUX_FEC_CORR_BLKS01"
15850 #define device_bar_BDK_BGXX_SPUX_FEC_CORR_BLKS01(a,b) 0x0 /* PF_BAR0 */
15851 #define busnum_BDK_BGXX_SPUX_FEC_CORR_BLKS01(a,b) (a)
15852 #define arguments_BDK_BGXX_SPUX_FEC_CORR_BLKS01(a,b) (a),(b),-1,-1
15853 
15854 /**
15855  * Register (RSL) bgx#_spu#_fec_corr_blks23
15856  *
15857  * BGX SPU FEC Corrected-Blocks Counters 2/3 Registers
15858  * This register is valid only when the LPCS type is 40GBASE-R
15859  * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4). The FEC corrected-block counters are defined in
15860  * IEEE 802.3 section 74.8.4.1. Each corrected-blocks counter increments by 1 for a corrected FEC
15861  * block, i.e. an FEC block that has been received with invalid parity on the associated PCS lane
15862  * and has been corrected by the FEC decoder. The counter is reset to all 0s when the register is
15863  * read, and held at all 1s in case of overflow.
15864  *
15865  * The reset operation takes precedence over the increment operation; if the register is read on
15866  * the same clock cycle as an increment operation, the counter is reset to all 0s and the
15867  * increment operation is lost. The counters are writable for test purposes, rather than read-
15868  * only as specified in IEEE 802.3.
15869  */
15870 union bdk_bgxx_spux_fec_corr_blks23
15871 {
15872     uint64_t u;
15873     struct bdk_bgxx_spux_fec_corr_blks23_s
15874     {
15875 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15876         uint64_t ln3_corr_blks         : 32; /**< [ 63: 32](RC/W/H) PCS Lane 3 FEC corrected blocks. Correspond to the IEEE 802.3
15877                                                                  FEC_corrected_blocks_counter_3 variable (registers 1.306-1.307). */
15878         uint64_t ln2_corr_blks         : 32; /**< [ 31:  0](RC/W/H) PCS Lane 2 FEC corrected blocks. Correspond to the IEEE 802.3
15879                                                                  FEC_corrected_blocks_counter_3 variable (registers 1.304-1.305). */
15880 #else /* Word 0 - Little Endian */
15881         uint64_t ln2_corr_blks         : 32; /**< [ 31:  0](RC/W/H) PCS Lane 2 FEC corrected blocks. Correspond to the IEEE 802.3
15882                                                                  FEC_corrected_blocks_counter_3 variable (registers 1.304-1.305). */
15883         uint64_t ln3_corr_blks         : 32; /**< [ 63: 32](RC/W/H) PCS Lane 3 FEC corrected blocks. Correspond to the IEEE 802.3
15884                                                                  FEC_corrected_blocks_counter_3 variable (registers 1.306-1.307). */
15885 #endif /* Word 0 - End */
15886     } s;
15887     /* struct bdk_bgxx_spux_fec_corr_blks23_s cn; */
15888 };
15889 typedef union bdk_bgxx_spux_fec_corr_blks23 bdk_bgxx_spux_fec_corr_blks23_t;
15890 
15891 static inline uint64_t BDK_BGXX_SPUX_FEC_CORR_BLKS23(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_FEC_CORR_BLKS23(unsigned long a,unsigned long b)15892 static inline uint64_t BDK_BGXX_SPUX_FEC_CORR_BLKS23(unsigned long a, unsigned long b)
15893 {
15894     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15895         return 0x87e0e00100b0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15896     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15897         return 0x87e0e00100b0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15898     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15899         return 0x87e0e00100b0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15900     __bdk_csr_fatal("BGXX_SPUX_FEC_CORR_BLKS23", 2, a, b, 0, 0);
15901 }
15902 
15903 #define typedef_BDK_BGXX_SPUX_FEC_CORR_BLKS23(a,b) bdk_bgxx_spux_fec_corr_blks23_t
15904 #define bustype_BDK_BGXX_SPUX_FEC_CORR_BLKS23(a,b) BDK_CSR_TYPE_RSL
15905 #define basename_BDK_BGXX_SPUX_FEC_CORR_BLKS23(a,b) "BGXX_SPUX_FEC_CORR_BLKS23"
15906 #define device_bar_BDK_BGXX_SPUX_FEC_CORR_BLKS23(a,b) 0x0 /* PF_BAR0 */
15907 #define busnum_BDK_BGXX_SPUX_FEC_CORR_BLKS23(a,b) (a)
15908 #define arguments_BDK_BGXX_SPUX_FEC_CORR_BLKS23(a,b) (a),(b),-1,-1
15909 
15910 /**
15911  * Register (RSL) bgx#_spu#_fec_uncorr_blks01
15912  *
15913  * BGX SPU FEC Uncorrected-Blocks Counters 0/1 Registers
15914  * This register is valid only when the LPCS type is BASE-R
15915  * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x3 or 0x4). The FEC corrected-block counters are
15916  * defined in IEEE 802.3 section 74.8.4.2. Each uncorrected-blocks counter increments by 1 for an
15917  * uncorrected FEC block, i.e. an FEC block that has been received with invalid parity on the
15918  * associated PCS lane and has not been corrected by the FEC decoder. The counter is reset to all
15919  * 0s when the register is read, and held at all 1s in case of overflow.
15920  *
15921  * The reset operation takes precedence over the increment operation; if the register is read on
15922  * the same clock cycle as an increment operation, the counter is reset to all 0s and the
15923  * increment operation is lost. The counters are writable for test purposes, rather than read-
15924  * only as specified in IEEE 802.3.
15925  */
15926 union bdk_bgxx_spux_fec_uncorr_blks01
15927 {
15928     uint64_t u;
15929     struct bdk_bgxx_spux_fec_uncorr_blks01_s
15930     {
15931 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15932         uint64_t ln1_uncorr_blks       : 32; /**< [ 63: 32](RC/W/H) PCS Lane 1 FEC corrected blocks.
15933                                                                  * For 10GBASE-R, reserved.
15934                                                                  * For 40GBASE-R, corresponds to the IEEE 802.3 FEC_uncorrected_blocks_counter_1 variable
15935                                                                  (registers 1.702-1.703). */
15936         uint64_t ln0_uncorr_blks       : 32; /**< [ 31:  0](RC/W/H) PCS Lane 0 FEC uncorrected blocks.
15937                                                                  * For 10GBASE-R, corresponds to the IEEE 802.3 FEC_uncorrected_blocks_counter variable
15938                                                                  (registers 1.174-1.175).
15939                                                                  * For 40GBASE-R, correspond to the IEEE 802.3 FEC_uncorrected_blocks_counter_0 variable
15940                                                                  (registers 1.700-1.701). */
15941 #else /* Word 0 - Little Endian */
15942         uint64_t ln0_uncorr_blks       : 32; /**< [ 31:  0](RC/W/H) PCS Lane 0 FEC uncorrected blocks.
15943                                                                  * For 10GBASE-R, corresponds to the IEEE 802.3 FEC_uncorrected_blocks_counter variable
15944                                                                  (registers 1.174-1.175).
15945                                                                  * For 40GBASE-R, correspond to the IEEE 802.3 FEC_uncorrected_blocks_counter_0 variable
15946                                                                  (registers 1.700-1.701). */
15947         uint64_t ln1_uncorr_blks       : 32; /**< [ 63: 32](RC/W/H) PCS Lane 1 FEC corrected blocks.
15948                                                                  * For 10GBASE-R, reserved.
15949                                                                  * For 40GBASE-R, corresponds to the IEEE 802.3 FEC_uncorrected_blocks_counter_1 variable
15950                                                                  (registers 1.702-1.703). */
15951 #endif /* Word 0 - End */
15952     } s;
15953     /* struct bdk_bgxx_spux_fec_uncorr_blks01_s cn; */
15954 };
15955 typedef union bdk_bgxx_spux_fec_uncorr_blks01 bdk_bgxx_spux_fec_uncorr_blks01_t;
15956 
15957 static inline uint64_t BDK_BGXX_SPUX_FEC_UNCORR_BLKS01(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_FEC_UNCORR_BLKS01(unsigned long a,unsigned long b)15958 static inline uint64_t BDK_BGXX_SPUX_FEC_UNCORR_BLKS01(unsigned long a, unsigned long b)
15959 {
15960     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
15961         return 0x87e0e00100b8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15962     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
15963         return 0x87e0e00100b8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
15964     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
15965         return 0x87e0e00100b8ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
15966     __bdk_csr_fatal("BGXX_SPUX_FEC_UNCORR_BLKS01", 2, a, b, 0, 0);
15967 }
15968 
15969 #define typedef_BDK_BGXX_SPUX_FEC_UNCORR_BLKS01(a,b) bdk_bgxx_spux_fec_uncorr_blks01_t
15970 #define bustype_BDK_BGXX_SPUX_FEC_UNCORR_BLKS01(a,b) BDK_CSR_TYPE_RSL
15971 #define basename_BDK_BGXX_SPUX_FEC_UNCORR_BLKS01(a,b) "BGXX_SPUX_FEC_UNCORR_BLKS01"
15972 #define device_bar_BDK_BGXX_SPUX_FEC_UNCORR_BLKS01(a,b) 0x0 /* PF_BAR0 */
15973 #define busnum_BDK_BGXX_SPUX_FEC_UNCORR_BLKS01(a,b) (a)
15974 #define arguments_BDK_BGXX_SPUX_FEC_UNCORR_BLKS01(a,b) (a),(b),-1,-1
15975 
15976 /**
15977  * Register (RSL) bgx#_spu#_fec_uncorr_blks23
15978  *
15979  * BGX SPU FEC Uncorrected-Blocks Counters 2/3 Registers
15980  * This register is valid only when the LPCS type is 40GBASE-R
15981  * (BGX()_CMR()_CONFIG[LMAC_TYPE] = 0x4). The FEC uncorrected-block counters are defined
15982  * in IEEE 802.3 section 74.8.4.2. Each corrected-blocks counter increments by 1 for an
15983  * uncorrected FEC block, i.e. an FEC block that has been received with invalid parity on the
15984  * associated PCS lane and has not been corrected by the FEC decoder. The counter is reset to all
15985  * 0s when the register is read, and held at all 1s in case of overflow.
15986  *
15987  * The reset operation takes precedence over the increment operation; if the register is read on
15988  * the same clock cycle as an increment operation, the counter is reset to all 0s and the
15989  * increment operation is lost. The counters are writable for test purposes, rather than read-
15990  * only as specified in IEEE 802.3.
15991  */
15992 union bdk_bgxx_spux_fec_uncorr_blks23
15993 {
15994     uint64_t u;
15995     struct bdk_bgxx_spux_fec_uncorr_blks23_s
15996     {
15997 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15998         uint64_t ln3_uncorr_blks       : 32; /**< [ 63: 32](RC/W/H) PCS Lane 3 FEC uncorrected blocks. Corresponds to the IEEE 802.3
15999                                                                  FEC_uncorrected_blocks_counter_3 variable (registers 1.706-1.707). */
16000         uint64_t ln2_uncorr_blks       : 32; /**< [ 31:  0](RC/W/H) PCS Lane 2 FEC uncorrected blocks. Corresponds to the IEEE 802.3
16001                                                                  FEC_uncorrected_blocks_counter_3 variable (registers 1.704-1.705). */
16002 #else /* Word 0 - Little Endian */
16003         uint64_t ln2_uncorr_blks       : 32; /**< [ 31:  0](RC/W/H) PCS Lane 2 FEC uncorrected blocks. Corresponds to the IEEE 802.3
16004                                                                  FEC_uncorrected_blocks_counter_3 variable (registers 1.704-1.705). */
16005         uint64_t ln3_uncorr_blks       : 32; /**< [ 63: 32](RC/W/H) PCS Lane 3 FEC uncorrected blocks. Corresponds to the IEEE 802.3
16006                                                                  FEC_uncorrected_blocks_counter_3 variable (registers 1.706-1.707). */
16007 #endif /* Word 0 - End */
16008     } s;
16009     /* struct bdk_bgxx_spux_fec_uncorr_blks23_s cn; */
16010 };
16011 typedef union bdk_bgxx_spux_fec_uncorr_blks23 bdk_bgxx_spux_fec_uncorr_blks23_t;
16012 
16013 static inline uint64_t BDK_BGXX_SPUX_FEC_UNCORR_BLKS23(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_FEC_UNCORR_BLKS23(unsigned long a,unsigned long b)16014 static inline uint64_t BDK_BGXX_SPUX_FEC_UNCORR_BLKS23(unsigned long a, unsigned long b)
16015 {
16016     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16017         return 0x87e0e00100c0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16018     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16019         return 0x87e0e00100c0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16020     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16021         return 0x87e0e00100c0ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16022     __bdk_csr_fatal("BGXX_SPUX_FEC_UNCORR_BLKS23", 2, a, b, 0, 0);
16023 }
16024 
16025 #define typedef_BDK_BGXX_SPUX_FEC_UNCORR_BLKS23(a,b) bdk_bgxx_spux_fec_uncorr_blks23_t
16026 #define bustype_BDK_BGXX_SPUX_FEC_UNCORR_BLKS23(a,b) BDK_CSR_TYPE_RSL
16027 #define basename_BDK_BGXX_SPUX_FEC_UNCORR_BLKS23(a,b) "BGXX_SPUX_FEC_UNCORR_BLKS23"
16028 #define device_bar_BDK_BGXX_SPUX_FEC_UNCORR_BLKS23(a,b) 0x0 /* PF_BAR0 */
16029 #define busnum_BDK_BGXX_SPUX_FEC_UNCORR_BLKS23(a,b) (a)
16030 #define arguments_BDK_BGXX_SPUX_FEC_UNCORR_BLKS23(a,b) (a),(b),-1,-1
16031 
16032 /**
16033  * Register (RSL) bgx#_spu#_int
16034  *
16035  * BGX SPU Interrupt Registers
16036  */
16037 union bdk_bgxx_spux_int
16038 {
16039     uint64_t u;
16040     struct bdk_bgxx_spux_int_s
16041     {
16042 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16043         uint64_t reserved_15_63        : 49;
16044         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1C/H) BASE-R PMD training failure. Set when BASE-R PMD link training has failed on the 10GBASE-R
16045                                                                  lane or any 40GBASE-R lane. Valid if the LPCS type selected by
16046                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R and
16047                                                                  BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is 1, and never set otherwise. */
16048         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1C/H) BASE-R PMD training done. Set when the 10GBASE-R lane or all 40GBASE-R lanes have
16049                                                                  successfully completed BASE-R PMD link training. Valid if the LPCS type selected by
16050                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R and
16051                                                                  BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is 1, and never set otherwise. */
16052         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1C/H) Autonegotiation complete. Set when BGX()_SPU()_AN_STATUS[AN_COMPLETE] is set,
16053                                                                  indicating that the autonegotiation process has been completed and the link is up and
16054                                                                  running using the negotiated highest common denominator (HCD) technology. */
16055         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1C/H) Autonegotiation link good. Set when the an_link_good variable is set as defined in
16056                                                                  802.3-2008 Figure 73-11, indicating that autonegotiation has completed. */
16057         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1C/H) Autonegotiation page received. This bit is set along with
16058                                                                  BGX()_SPU()_AN_STATUS[PAGE_RX] when a new page has been received and stored in
16059                                                                  BGX()_SPU()_AN_LP_BASE or BGX()_SPU()_AN_LP_XNP. */
16060         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1C/H) Uncorrectable FEC error. Set when an FEC block with an uncorrectable error is received on
16061                                                                  the 10GBASE-R lane or any 40GBASE-R lane. Valid if the LPCS type selected by
16062                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R, and never set otherwise. */
16063         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1C/H) Correctable FEC error. Set when an FEC block with a correctable error is received on the
16064                                                                  10GBASE-R lane or any 40GBASE-R lane. Valid if the LPCS type selected by
16065                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R, and never set otherwise. */
16066         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1C/H) 40GBASE-R bit interleaved parity error. Set when a BIP error is detected on any lane.
16067                                                                  Valid if the LPCS type selected by BGX()_CMR()_CONFIG[LMAC_TYPE] is 40GBASE-R, and
16068                                                                  never set otherwise. */
16069         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1C/H) Sync failure debug. This interrupt is provided for link problem debugging help. It is set
16070                                                                  as follows based on the LPCS type selected by BGX()_CMR()_CONFIG[LMAC_TYPE], and
16071                                                                  whether FEC is enabled or disabled by BGX()_SPU()_FEC_CONTROL[FEC_EN]:
16072                                                                  * XAUI or RXAUI: Set when any lane's PCS synchronization state transitions from
16073                                                                  SYNC_ACQUIRED_1 to SYNC_ACQUIRED_2 (see 802.3-2008 Figure 48-7).
16074                                                                  * 10GBASE-R or 40GBASE-R with FEC disabled: Set when sh_invalid_cnt increments to 1 while
16075                                                                  BLOCK_LOCK is 1 (see 802.3-2008 Figure 49-12 and 802.3ba-2010 Figure 82-20).
16076                                                                  * 10GBASE-R or 40GBASE-R with FEC enabled: Set when parity_invalid_cnt increments to 1
16077                                                                  while fec_block_lock is 1 (see 802.3-2008 Figure 74-8). */
16078         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1C/H) Loss of lane alignment. Set when lane-to-lane alignment is lost. This is only valid if the
16079                                                                  logical PCS is a multilane type (i.e. XAUI, RXAUI or 40GBASE-R is selected by
16080                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]), and is never set otherwise. */
16081         uint64_t synlos                : 1;  /**< [  4:  4](R/W1C/H) Loss of lane sync. Lane code-group or block synchronization is lost on one or more lanes
16082                                                                  associated with the LMAC/LPCS. Set as follows based on the LPCS type selected by
16083                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE], and whether FEC is enabled or disabled by
16084                                                                  BGX()_SPU()_FEC_CONTROL[FEC_EN]:
16085                                                                  * XAUI or RXAUI: Set when any lane's PCS synchronization state transitions to LOSS_OF_SYNC
16086                                                                  (see 802.3-2008 Figure 48-7)
16087                                                                  * 10GBASE-R or 40GBASE-R with FEC disabled: set when the BLOCK_LOCK variable is cleared on
16088                                                                  the 10G lane or any 40G lane (see 802.3-2008 Figure 49-12 and 802.3ba-2010 Figure 82-20).
16089                                                                  * 10GBASE-R or 40GBASE-R with FEC enabled: set when the fec_block_lock variable is cleared
16090                                                                  on the 10G lane or any 40G lane (see 802.3-2008 Figure 74-8). */
16091         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1C/H) Bit lock lost on one or more lanes associated with the LMAC/LPCS. */
16092         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1C/H) Errored block received. Set when an errored BASE-R block is received as described for
16093                                                                  BGX()_SPU()_BR_STATUS2[ERR_BLKS]. Valid if the LPCS type selected by
16094                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R, and never set otherwise. */
16095         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1C/H) Set when the receive link goes down, which is the same condition that sets
16096                                                                  BGX()_SPU()_STATUS2[RCVFLT]. */
16097         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1C/H) Set when the receive link comes up, which is the same condition that allows the setting of
16098                                                                  BGX()_SPU()_STATUS1[RCV_LNK]. */
16099 #else /* Word 0 - Little Endian */
16100         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1C/H) Set when the receive link comes up, which is the same condition that allows the setting of
16101                                                                  BGX()_SPU()_STATUS1[RCV_LNK]. */
16102         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1C/H) Set when the receive link goes down, which is the same condition that sets
16103                                                                  BGX()_SPU()_STATUS2[RCVFLT]. */
16104         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1C/H) Errored block received. Set when an errored BASE-R block is received as described for
16105                                                                  BGX()_SPU()_BR_STATUS2[ERR_BLKS]. Valid if the LPCS type selected by
16106                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R, and never set otherwise. */
16107         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1C/H) Bit lock lost on one or more lanes associated with the LMAC/LPCS. */
16108         uint64_t synlos                : 1;  /**< [  4:  4](R/W1C/H) Loss of lane sync. Lane code-group or block synchronization is lost on one or more lanes
16109                                                                  associated with the LMAC/LPCS. Set as follows based on the LPCS type selected by
16110                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE], and whether FEC is enabled or disabled by
16111                                                                  BGX()_SPU()_FEC_CONTROL[FEC_EN]:
16112                                                                  * XAUI or RXAUI: Set when any lane's PCS synchronization state transitions to LOSS_OF_SYNC
16113                                                                  (see 802.3-2008 Figure 48-7)
16114                                                                  * 10GBASE-R or 40GBASE-R with FEC disabled: set when the BLOCK_LOCK variable is cleared on
16115                                                                  the 10G lane or any 40G lane (see 802.3-2008 Figure 49-12 and 802.3ba-2010 Figure 82-20).
16116                                                                  * 10GBASE-R or 40GBASE-R with FEC enabled: set when the fec_block_lock variable is cleared
16117                                                                  on the 10G lane or any 40G lane (see 802.3-2008 Figure 74-8). */
16118         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1C/H) Loss of lane alignment. Set when lane-to-lane alignment is lost. This is only valid if the
16119                                                                  logical PCS is a multilane type (i.e. XAUI, RXAUI or 40GBASE-R is selected by
16120                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE]), and is never set otherwise. */
16121         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1C/H) Sync failure debug. This interrupt is provided for link problem debugging help. It is set
16122                                                                  as follows based on the LPCS type selected by BGX()_CMR()_CONFIG[LMAC_TYPE], and
16123                                                                  whether FEC is enabled or disabled by BGX()_SPU()_FEC_CONTROL[FEC_EN]:
16124                                                                  * XAUI or RXAUI: Set when any lane's PCS synchronization state transitions from
16125                                                                  SYNC_ACQUIRED_1 to SYNC_ACQUIRED_2 (see 802.3-2008 Figure 48-7).
16126                                                                  * 10GBASE-R or 40GBASE-R with FEC disabled: Set when sh_invalid_cnt increments to 1 while
16127                                                                  BLOCK_LOCK is 1 (see 802.3-2008 Figure 49-12 and 802.3ba-2010 Figure 82-20).
16128                                                                  * 10GBASE-R or 40GBASE-R with FEC enabled: Set when parity_invalid_cnt increments to 1
16129                                                                  while fec_block_lock is 1 (see 802.3-2008 Figure 74-8). */
16130         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1C/H) 40GBASE-R bit interleaved parity error. Set when a BIP error is detected on any lane.
16131                                                                  Valid if the LPCS type selected by BGX()_CMR()_CONFIG[LMAC_TYPE] is 40GBASE-R, and
16132                                                                  never set otherwise. */
16133         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1C/H) Correctable FEC error. Set when an FEC block with a correctable error is received on the
16134                                                                  10GBASE-R lane or any 40GBASE-R lane. Valid if the LPCS type selected by
16135                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R, and never set otherwise. */
16136         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1C/H) Uncorrectable FEC error. Set when an FEC block with an uncorrectable error is received on
16137                                                                  the 10GBASE-R lane or any 40GBASE-R lane. Valid if the LPCS type selected by
16138                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R, and never set otherwise. */
16139         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1C/H) Autonegotiation page received. This bit is set along with
16140                                                                  BGX()_SPU()_AN_STATUS[PAGE_RX] when a new page has been received and stored in
16141                                                                  BGX()_SPU()_AN_LP_BASE or BGX()_SPU()_AN_LP_XNP. */
16142         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1C/H) Autonegotiation link good. Set when the an_link_good variable is set as defined in
16143                                                                  802.3-2008 Figure 73-11, indicating that autonegotiation has completed. */
16144         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1C/H) Autonegotiation complete. Set when BGX()_SPU()_AN_STATUS[AN_COMPLETE] is set,
16145                                                                  indicating that the autonegotiation process has been completed and the link is up and
16146                                                                  running using the negotiated highest common denominator (HCD) technology. */
16147         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1C/H) BASE-R PMD training done. Set when the 10GBASE-R lane or all 40GBASE-R lanes have
16148                                                                  successfully completed BASE-R PMD link training. Valid if the LPCS type selected by
16149                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R and
16150                                                                  BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is 1, and never set otherwise. */
16151         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1C/H) BASE-R PMD training failure. Set when BASE-R PMD link training has failed on the 10GBASE-R
16152                                                                  lane or any 40GBASE-R lane. Valid if the LPCS type selected by
16153                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE] is 10GBASE-R or 40GBASE-R and
16154                                                                  BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is 1, and never set otherwise. */
16155         uint64_t reserved_15_63        : 49;
16156 #endif /* Word 0 - End */
16157     } s;
16158     /* struct bdk_bgxx_spux_int_s cn; */
16159 };
16160 typedef union bdk_bgxx_spux_int bdk_bgxx_spux_int_t;
16161 
16162 static inline uint64_t BDK_BGXX_SPUX_INT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_INT(unsigned long a,unsigned long b)16163 static inline uint64_t BDK_BGXX_SPUX_INT(unsigned long a, unsigned long b)
16164 {
16165     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16166         return 0x87e0e0010220ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16167     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16168         return 0x87e0e0010220ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16169     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16170         return 0x87e0e0010220ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16171     __bdk_csr_fatal("BGXX_SPUX_INT", 2, a, b, 0, 0);
16172 }
16173 
16174 #define typedef_BDK_BGXX_SPUX_INT(a,b) bdk_bgxx_spux_int_t
16175 #define bustype_BDK_BGXX_SPUX_INT(a,b) BDK_CSR_TYPE_RSL
16176 #define basename_BDK_BGXX_SPUX_INT(a,b) "BGXX_SPUX_INT"
16177 #define device_bar_BDK_BGXX_SPUX_INT(a,b) 0x0 /* PF_BAR0 */
16178 #define busnum_BDK_BGXX_SPUX_INT(a,b) (a)
16179 #define arguments_BDK_BGXX_SPUX_INT(a,b) (a),(b),-1,-1
16180 
16181 /**
16182  * Register (RSL) bgx#_spu#_int_ena_w1c
16183  *
16184  * BGX SPU Interrupt Enable Clear Registers
16185  * This register clears interrupt enable bits.
16186  */
16187 union bdk_bgxx_spux_int_ena_w1c
16188 {
16189     uint64_t u;
16190     struct bdk_bgxx_spux_int_ena_w1c_s
16191     {
16192 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16193         uint64_t reserved_15_63        : 49;
16194         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16195         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[TRAINING_DONE]. */
16196         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[AN_COMPLETE]. */
16197         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16198         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[AN_PAGE_RX]. */
16199         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[FEC_UNCORR]. */
16200         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[FEC_CORR]. */
16201         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[BIP_ERR]. */
16202         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[DBG_SYNC]. */
16203         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[ALGNLOS]. */
16204         uint64_t synlos                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[SYNLOS]. */
16205         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[BITLCKLS]. */
16206         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[ERR_BLK]. */
16207         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16208         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[RX_LINK_UP]. */
16209 #else /* Word 0 - Little Endian */
16210         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[RX_LINK_UP]. */
16211         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16212         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[ERR_BLK]. */
16213         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[BITLCKLS]. */
16214         uint64_t synlos                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[SYNLOS]. */
16215         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[ALGNLOS]. */
16216         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[DBG_SYNC]. */
16217         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[BIP_ERR]. */
16218         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[FEC_CORR]. */
16219         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[FEC_UNCORR]. */
16220         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[AN_PAGE_RX]. */
16221         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16222         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[AN_COMPLETE]. */
16223         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[TRAINING_DONE]. */
16224         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16225         uint64_t reserved_15_63        : 49;
16226 #endif /* Word 0 - End */
16227     } s;
16228     /* struct bdk_bgxx_spux_int_ena_w1c_s cn81xx; */
16229     /* struct bdk_bgxx_spux_int_ena_w1c_s cn88xx; */
16230     struct bdk_bgxx_spux_int_ena_w1c_cn83xx
16231     {
16232 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16233         uint64_t reserved_15_63        : 49;
16234         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16235         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[TRAINING_DONE]. */
16236         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[AN_COMPLETE]. */
16237         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16238         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[AN_PAGE_RX]. */
16239         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[FEC_UNCORR]. */
16240         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[FEC_CORR]. */
16241         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[BIP_ERR]. */
16242         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[DBG_SYNC]. */
16243         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[ALGNLOS]. */
16244         uint64_t synlos                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[SYNLOS]. */
16245         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[BITLCKLS]. */
16246         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[ERR_BLK]. */
16247         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16248         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[RX_LINK_UP]. */
16249 #else /* Word 0 - Little Endian */
16250         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[RX_LINK_UP]. */
16251         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16252         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[ERR_BLK]. */
16253         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[BITLCKLS]. */
16254         uint64_t synlos                : 1;  /**< [  4:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[SYNLOS]. */
16255         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[ALGNLOS]. */
16256         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[DBG_SYNC]. */
16257         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[BIP_ERR]. */
16258         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[FEC_CORR]. */
16259         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[FEC_UNCORR]. */
16260         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[AN_PAGE_RX]. */
16261         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16262         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[AN_COMPLETE]. */
16263         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[TRAINING_DONE]. */
16264         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16265         uint64_t reserved_15_63        : 49;
16266 #endif /* Word 0 - End */
16267     } cn83xx;
16268 };
16269 typedef union bdk_bgxx_spux_int_ena_w1c bdk_bgxx_spux_int_ena_w1c_t;
16270 
16271 static inline uint64_t BDK_BGXX_SPUX_INT_ENA_W1C(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_INT_ENA_W1C(unsigned long a,unsigned long b)16272 static inline uint64_t BDK_BGXX_SPUX_INT_ENA_W1C(unsigned long a, unsigned long b)
16273 {
16274     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16275         return 0x87e0e0010230ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16276     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16277         return 0x87e0e0010230ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16278     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16279         return 0x87e0e0010230ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16280     __bdk_csr_fatal("BGXX_SPUX_INT_ENA_W1C", 2, a, b, 0, 0);
16281 }
16282 
16283 #define typedef_BDK_BGXX_SPUX_INT_ENA_W1C(a,b) bdk_bgxx_spux_int_ena_w1c_t
16284 #define bustype_BDK_BGXX_SPUX_INT_ENA_W1C(a,b) BDK_CSR_TYPE_RSL
16285 #define basename_BDK_BGXX_SPUX_INT_ENA_W1C(a,b) "BGXX_SPUX_INT_ENA_W1C"
16286 #define device_bar_BDK_BGXX_SPUX_INT_ENA_W1C(a,b) 0x0 /* PF_BAR0 */
16287 #define busnum_BDK_BGXX_SPUX_INT_ENA_W1C(a,b) (a)
16288 #define arguments_BDK_BGXX_SPUX_INT_ENA_W1C(a,b) (a),(b),-1,-1
16289 
16290 /**
16291  * Register (RSL) bgx#_spu#_int_ena_w1s
16292  *
16293  * BGX SPU Interrupt Enable Set Registers
16294  * This register sets interrupt enable bits.
16295  */
16296 union bdk_bgxx_spux_int_ena_w1s
16297 {
16298     uint64_t u;
16299     struct bdk_bgxx_spux_int_ena_w1s_s
16300     {
16301 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16302         uint64_t reserved_15_63        : 49;
16303         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16304         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[TRAINING_DONE]. */
16305         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[AN_COMPLETE]. */
16306         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16307         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[AN_PAGE_RX]. */
16308         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[FEC_UNCORR]. */
16309         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[FEC_CORR]. */
16310         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[BIP_ERR]. */
16311         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[DBG_SYNC]. */
16312         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[ALGNLOS]. */
16313         uint64_t synlos                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[SYNLOS]. */
16314         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[BITLCKLS]. */
16315         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[ERR_BLK]. */
16316         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16317         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[RX_LINK_UP]. */
16318 #else /* Word 0 - Little Endian */
16319         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[RX_LINK_UP]. */
16320         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16321         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[ERR_BLK]. */
16322         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[BITLCKLS]. */
16323         uint64_t synlos                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[SYNLOS]. */
16324         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[ALGNLOS]. */
16325         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[DBG_SYNC]. */
16326         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[BIP_ERR]. */
16327         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[FEC_CORR]. */
16328         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[FEC_UNCORR]. */
16329         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[AN_PAGE_RX]. */
16330         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16331         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[AN_COMPLETE]. */
16332         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[TRAINING_DONE]. */
16333         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16334         uint64_t reserved_15_63        : 49;
16335 #endif /* Word 0 - End */
16336     } s;
16337     /* struct bdk_bgxx_spux_int_ena_w1s_s cn81xx; */
16338     /* struct bdk_bgxx_spux_int_ena_w1s_s cn88xx; */
16339     struct bdk_bgxx_spux_int_ena_w1s_cn83xx
16340     {
16341 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16342         uint64_t reserved_15_63        : 49;
16343         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16344         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[TRAINING_DONE]. */
16345         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[AN_COMPLETE]. */
16346         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16347         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[AN_PAGE_RX]. */
16348         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[FEC_UNCORR]. */
16349         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[FEC_CORR]. */
16350         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[BIP_ERR]. */
16351         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[DBG_SYNC]. */
16352         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[ALGNLOS]. */
16353         uint64_t synlos                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[SYNLOS]. */
16354         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[BITLCKLS]. */
16355         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[ERR_BLK]. */
16356         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16357         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[RX_LINK_UP]. */
16358 #else /* Word 0 - Little Endian */
16359         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[RX_LINK_UP]. */
16360         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16361         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[ERR_BLK]. */
16362         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[BITLCKLS]. */
16363         uint64_t synlos                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[SYNLOS]. */
16364         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[ALGNLOS]. */
16365         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[DBG_SYNC]. */
16366         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[BIP_ERR]. */
16367         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[FEC_CORR]. */
16368         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[FEC_UNCORR]. */
16369         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[AN_PAGE_RX]. */
16370         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16371         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[AN_COMPLETE]. */
16372         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[TRAINING_DONE]. */
16373         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16374         uint64_t reserved_15_63        : 49;
16375 #endif /* Word 0 - End */
16376     } cn83xx;
16377 };
16378 typedef union bdk_bgxx_spux_int_ena_w1s bdk_bgxx_spux_int_ena_w1s_t;
16379 
16380 static inline uint64_t BDK_BGXX_SPUX_INT_ENA_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_INT_ENA_W1S(unsigned long a,unsigned long b)16381 static inline uint64_t BDK_BGXX_SPUX_INT_ENA_W1S(unsigned long a, unsigned long b)
16382 {
16383     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16384         return 0x87e0e0010238ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16385     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16386         return 0x87e0e0010238ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16387     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16388         return 0x87e0e0010238ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16389     __bdk_csr_fatal("BGXX_SPUX_INT_ENA_W1S", 2, a, b, 0, 0);
16390 }
16391 
16392 #define typedef_BDK_BGXX_SPUX_INT_ENA_W1S(a,b) bdk_bgxx_spux_int_ena_w1s_t
16393 #define bustype_BDK_BGXX_SPUX_INT_ENA_W1S(a,b) BDK_CSR_TYPE_RSL
16394 #define basename_BDK_BGXX_SPUX_INT_ENA_W1S(a,b) "BGXX_SPUX_INT_ENA_W1S"
16395 #define device_bar_BDK_BGXX_SPUX_INT_ENA_W1S(a,b) 0x0 /* PF_BAR0 */
16396 #define busnum_BDK_BGXX_SPUX_INT_ENA_W1S(a,b) (a)
16397 #define arguments_BDK_BGXX_SPUX_INT_ENA_W1S(a,b) (a),(b),-1,-1
16398 
16399 /**
16400  * Register (RSL) bgx#_spu#_int_w1s
16401  *
16402  * BGX SPU Interrupt Set Registers
16403  * This register sets interrupt bits.
16404  */
16405 union bdk_bgxx_spux_int_w1s
16406 {
16407     uint64_t u;
16408     struct bdk_bgxx_spux_int_w1s_s
16409     {
16410 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16411         uint64_t reserved_15_63        : 49;
16412         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16413         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[TRAINING_DONE]. */
16414         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[AN_COMPLETE]. */
16415         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16416         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[AN_PAGE_RX]. */
16417         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[FEC_UNCORR]. */
16418         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[FEC_CORR]. */
16419         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[BIP_ERR]. */
16420         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[DBG_SYNC]. */
16421         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[ALGNLOS]. */
16422         uint64_t synlos                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[SYNLOS]. */
16423         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[BITLCKLS]. */
16424         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[ERR_BLK]. */
16425         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16426         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[RX_LINK_UP]. */
16427 #else /* Word 0 - Little Endian */
16428         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[RX_LINK_UP]. */
16429         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16430         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[ERR_BLK]. */
16431         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[BITLCKLS]. */
16432         uint64_t synlos                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[SYNLOS]. */
16433         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[ALGNLOS]. */
16434         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[DBG_SYNC]. */
16435         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[BIP_ERR]. */
16436         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[FEC_CORR]. */
16437         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[FEC_UNCORR]. */
16438         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[AN_PAGE_RX]. */
16439         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16440         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[AN_COMPLETE]. */
16441         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[TRAINING_DONE]. */
16442         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..1)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16443         uint64_t reserved_15_63        : 49;
16444 #endif /* Word 0 - End */
16445     } s;
16446     /* struct bdk_bgxx_spux_int_w1s_s cn81xx; */
16447     /* struct bdk_bgxx_spux_int_w1s_s cn88xx; */
16448     struct bdk_bgxx_spux_int_w1s_cn83xx
16449     {
16450 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16451         uint64_t reserved_15_63        : 49;
16452         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16453         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[TRAINING_DONE]. */
16454         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[AN_COMPLETE]. */
16455         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16456         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[AN_PAGE_RX]. */
16457         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[FEC_UNCORR]. */
16458         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[FEC_CORR]. */
16459         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[BIP_ERR]. */
16460         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[DBG_SYNC]. */
16461         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[ALGNLOS]. */
16462         uint64_t synlos                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[SYNLOS]. */
16463         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[BITLCKLS]. */
16464         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[ERR_BLK]. */
16465         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16466         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[RX_LINK_UP]. */
16467 #else /* Word 0 - Little Endian */
16468         uint64_t rx_link_up            : 1;  /**< [  0:  0](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[RX_LINK_UP]. */
16469         uint64_t rx_link_down          : 1;  /**< [  1:  1](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[RX_LINK_DOWN]. */
16470         uint64_t err_blk               : 1;  /**< [  2:  2](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[ERR_BLK]. */
16471         uint64_t bitlckls              : 1;  /**< [  3:  3](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[BITLCKLS]. */
16472         uint64_t synlos                : 1;  /**< [  4:  4](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[SYNLOS]. */
16473         uint64_t algnlos               : 1;  /**< [  5:  5](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[ALGNLOS]. */
16474         uint64_t dbg_sync              : 1;  /**< [  6:  6](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[DBG_SYNC]. */
16475         uint64_t bip_err               : 1;  /**< [  7:  7](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[BIP_ERR]. */
16476         uint64_t fec_corr              : 1;  /**< [  8:  8](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[FEC_CORR]. */
16477         uint64_t fec_uncorr            : 1;  /**< [  9:  9](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[FEC_UNCORR]. */
16478         uint64_t an_page_rx            : 1;  /**< [ 10: 10](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[AN_PAGE_RX]. */
16479         uint64_t an_link_good          : 1;  /**< [ 11: 11](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[AN_LINK_GOOD]. */
16480         uint64_t an_complete           : 1;  /**< [ 12: 12](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[AN_COMPLETE]. */
16481         uint64_t training_done         : 1;  /**< [ 13: 13](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[TRAINING_DONE]. */
16482         uint64_t training_failure      : 1;  /**< [ 14: 14](R/W1S/H) Reads or sets BGX(0..3)_SPU(0..3)_INT[TRAINING_FAILURE]. */
16483         uint64_t reserved_15_63        : 49;
16484 #endif /* Word 0 - End */
16485     } cn83xx;
16486 };
16487 typedef union bdk_bgxx_spux_int_w1s bdk_bgxx_spux_int_w1s_t;
16488 
16489 static inline uint64_t BDK_BGXX_SPUX_INT_W1S(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_INT_W1S(unsigned long a,unsigned long b)16490 static inline uint64_t BDK_BGXX_SPUX_INT_W1S(unsigned long a, unsigned long b)
16491 {
16492     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16493         return 0x87e0e0010228ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16494     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16495         return 0x87e0e0010228ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16496     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16497         return 0x87e0e0010228ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16498     __bdk_csr_fatal("BGXX_SPUX_INT_W1S", 2, a, b, 0, 0);
16499 }
16500 
16501 #define typedef_BDK_BGXX_SPUX_INT_W1S(a,b) bdk_bgxx_spux_int_w1s_t
16502 #define bustype_BDK_BGXX_SPUX_INT_W1S(a,b) BDK_CSR_TYPE_RSL
16503 #define basename_BDK_BGXX_SPUX_INT_W1S(a,b) "BGXX_SPUX_INT_W1S"
16504 #define device_bar_BDK_BGXX_SPUX_INT_W1S(a,b) 0x0 /* PF_BAR0 */
16505 #define busnum_BDK_BGXX_SPUX_INT_W1S(a,b) (a)
16506 #define arguments_BDK_BGXX_SPUX_INT_W1S(a,b) (a),(b),-1,-1
16507 
16508 /**
16509  * Register (RSL) bgx#_spu#_lpcs_states
16510  *
16511  * BGX SPU BASE-X Transmit/Receive States Registers
16512  */
16513 union bdk_bgxx_spux_lpcs_states
16514 {
16515     uint64_t u;
16516     struct bdk_bgxx_spux_lpcs_states_s
16517     {
16518 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16519         uint64_t reserved_15_63        : 49;
16520         uint64_t br_rx_sm              : 3;  /**< [ 14: 12](RO/H) BASE-R receive state machine state */
16521         uint64_t reserved_10_11        : 2;
16522         uint64_t bx_rx_sm              : 2;  /**< [  9:  8](RO/H) BASE-X receive state machine state */
16523         uint64_t deskew_am_found       : 4;  /**< [  7:  4](RO/H) 40GBASE-R deskew state machine alignment marker found flag per logical PCS lane ID. */
16524         uint64_t reserved_3            : 1;
16525         uint64_t deskew_sm             : 3;  /**< [  2:  0](RO/H) BASE-X and 40GBASE-R deskew state machine state */
16526 #else /* Word 0 - Little Endian */
16527         uint64_t deskew_sm             : 3;  /**< [  2:  0](RO/H) BASE-X and 40GBASE-R deskew state machine state */
16528         uint64_t reserved_3            : 1;
16529         uint64_t deskew_am_found       : 4;  /**< [  7:  4](RO/H) 40GBASE-R deskew state machine alignment marker found flag per logical PCS lane ID. */
16530         uint64_t bx_rx_sm              : 2;  /**< [  9:  8](RO/H) BASE-X receive state machine state */
16531         uint64_t reserved_10_11        : 2;
16532         uint64_t br_rx_sm              : 3;  /**< [ 14: 12](RO/H) BASE-R receive state machine state */
16533         uint64_t reserved_15_63        : 49;
16534 #endif /* Word 0 - End */
16535     } s;
16536     /* struct bdk_bgxx_spux_lpcs_states_s cn; */
16537 };
16538 typedef union bdk_bgxx_spux_lpcs_states bdk_bgxx_spux_lpcs_states_t;
16539 
16540 static inline uint64_t BDK_BGXX_SPUX_LPCS_STATES(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_LPCS_STATES(unsigned long a,unsigned long b)16541 static inline uint64_t BDK_BGXX_SPUX_LPCS_STATES(unsigned long a, unsigned long b)
16542 {
16543     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16544         return 0x87e0e0010208ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16545     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16546         return 0x87e0e0010208ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16547     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16548         return 0x87e0e0010208ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16549     __bdk_csr_fatal("BGXX_SPUX_LPCS_STATES", 2, a, b, 0, 0);
16550 }
16551 
16552 #define typedef_BDK_BGXX_SPUX_LPCS_STATES(a,b) bdk_bgxx_spux_lpcs_states_t
16553 #define bustype_BDK_BGXX_SPUX_LPCS_STATES(a,b) BDK_CSR_TYPE_RSL
16554 #define basename_BDK_BGXX_SPUX_LPCS_STATES(a,b) "BGXX_SPUX_LPCS_STATES"
16555 #define device_bar_BDK_BGXX_SPUX_LPCS_STATES(a,b) 0x0 /* PF_BAR0 */
16556 #define busnum_BDK_BGXX_SPUX_LPCS_STATES(a,b) (a)
16557 #define arguments_BDK_BGXX_SPUX_LPCS_STATES(a,b) (a),(b),-1,-1
16558 
16559 /**
16560  * Register (RSL) bgx#_spu#_misc_control
16561  *
16562  * BGX SPU Miscellaneous Control Registers
16563  * "* RX logical PCS lane polarity vector \<3:0\> = [XOR_RXPLRT]\<3:0\> ^ {4{[RXPLRT]}}.
16564  * * TX logical PCS lane polarity vector \<3:0\> = [XOR_TXPLRT]\<3:0\> ^ {4{[TXPLRT]}}.
16565  *
16566  * In short, keep [RXPLRT] and [TXPLRT] cleared, and use [XOR_RXPLRT] and [XOR_TXPLRT] fields to
16567  * define
16568  * the polarity per logical PCS lane. Only bit 0 of vector is used for 10GBASE-R, and only bits
16569  * 1:0 of vector are used for RXAUI."
16570  */
16571 union bdk_bgxx_spux_misc_control
16572 {
16573     uint64_t u;
16574     struct bdk_bgxx_spux_misc_control_s
16575     {
16576 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16577         uint64_t reserved_13_63        : 51;
16578         uint64_t rx_packet_dis         : 1;  /**< [ 12: 12](R/W) Receive packet disable. Software can set or clear this bit at any time to gracefully
16579                                                                  disable or re-enable packet reception by the LPCS. If this bit is set while a packet is
16580                                                                  being received, the packet is completed and all subsequent received packets are discarded
16581                                                                  by the LPCS. Similarly, if this bit is cleared while a received packet is being discarded,
16582                                                                  packet reception resumes after the current packet is fully discarded. When set for a
16583                                                                  40GBASE-R or 10GBASE-R LMAC/LPCS type (selected by BGX()_CMR()_CONFIG[LMAC_TYPE]),
16584                                                                  received errors and faults will be ignored while receive packets are discarded; idles will
16585                                                                  be sent to the MAC layer (SMU) and the errored blocks counter
16586                                                                  (BGX()_SPU()_BR_STATUS2[ERR_BLKS]) will not increment. */
16587         uint64_t skip_after_term       : 1;  /**< [ 11: 11](R/W) Enable sending of idle skip after terminate. This bit is meaningful when the logical PCS
16588                                                                  type is XAUI or RXAUI (selected by BGX()_CMR()_CONFIG[LMAC_TYPE]), and has no
16589                                                                  effect otherwise. When set, the LMAC/LPCS transmits more idle skip columns for clock
16590                                                                  compensation. Typically set in HiGig/HiGig2 modes; clear otherwise. This field can be set
16591                                                                  to ensure sufficient density of XAUI idle skip (||R||) columns with a small transmit
16592                                                                  inter-frame gap (IFG) in order to allow the link partner's receiver to delete ||R||
16593                                                                  columns as needed for clock rate compensation. It is usually set when the LMAC's transmit
16594                                                                  IFG is set to eight bytes in HiGig/HiGig2 modes (i.e. BGX()_SMU()_TX_IFG[IFG1] +
16595                                                                  BGX()_SMU()_TX_IFG[IFG2] = 8), and should be cleared when the transmit IFG is
16596                                                                  greater than eight bytes. When this bit is set, the SPU will send an ||R|| column after a
16597                                                                  ||T0|| column (terminate in lane 0) if no ||R|| was sent in the previous IFG. This is a
16598                                                                  minor deviation from the functionality specified in 802.3-2008 Figure 48-6 (PCS transmit
16599                                                                  source state diagram), whereby the state will transition directly from SEND_DATA to
16600                                                                  SEND_RANDOM_R after ||T0|| if no ||R|| was transmitted in the previous IFG. Sending ||R||
16601                                                                  after ||T0|| only (and not ||T1||, |T2|| or ||T3||) ensures that the check_end function at
16602                                                                  the receiving end, as defined in 802.3-2008 sub-clause 48.2.6.1.4, does not detect an
16603                                                                  error due to this functional change. When this bit is clear, the LMAC will fully conform
16604                                                                  to the functionality specified in Figure 48-6. */
16605         uint64_t intlv_rdisp           : 1;  /**< [ 10: 10](R/W) RXAUI interleaved running disparity. This bit is meaningful when the logical PCS type is
16606                                                                  RXAUI (BGX()_CMR()_CONFIG[LMAC_TYPE] = RXAUI), and has no effect otherwise. It
16607                                                                  selects which disparity calculation to use when combining or splitting the RXAUI lanes, as
16608                                                                  follows:
16609 
16610                                                                  _ 0 = Common running disparity. Common running disparity is computed for even and odd
16611                                                                  code-
16612                                                                  groups of an RXAUI lane, i.e. interleave lanes before PCS layer as described in the Dune
16613                                                                  Networks/Broadcom RXAUI v2.1 specification. This obeys 6.25GHz SerDes disparity.
16614 
16615                                                                  _ 1 = Interleaved running disparity: Running disparity is computed separately for even and
16616                                                                  odd code-groups of an RXAUI lane, i.e. interleave lanes after PCS layer as described in
16617                                                                  the Marvell RXAUI Interface specification. This does not obey 6.25GHz SerDes disparity. */
16618         uint64_t xor_rxplrt            : 4;  /**< [  9:  6](R/W) RX polarity control per logical PCS lane */
16619         uint64_t xor_txplrt            : 4;  /**< [  5:  2](R/W) TX polarity control per logical PCS lane */
16620         uint64_t rxplrt                : 1;  /**< [  1:  1](R/W) Receive polarity. 1 = inverted polarity. 0 = normal polarity. */
16621         uint64_t txplrt                : 1;  /**< [  0:  0](R/W) Transmit polarity. 1 = inverted polarity. 0 = normal polarity. */
16622 #else /* Word 0 - Little Endian */
16623         uint64_t txplrt                : 1;  /**< [  0:  0](R/W) Transmit polarity. 1 = inverted polarity. 0 = normal polarity. */
16624         uint64_t rxplrt                : 1;  /**< [  1:  1](R/W) Receive polarity. 1 = inverted polarity. 0 = normal polarity. */
16625         uint64_t xor_txplrt            : 4;  /**< [  5:  2](R/W) TX polarity control per logical PCS lane */
16626         uint64_t xor_rxplrt            : 4;  /**< [  9:  6](R/W) RX polarity control per logical PCS lane */
16627         uint64_t intlv_rdisp           : 1;  /**< [ 10: 10](R/W) RXAUI interleaved running disparity. This bit is meaningful when the logical PCS type is
16628                                                                  RXAUI (BGX()_CMR()_CONFIG[LMAC_TYPE] = RXAUI), and has no effect otherwise. It
16629                                                                  selects which disparity calculation to use when combining or splitting the RXAUI lanes, as
16630                                                                  follows:
16631 
16632                                                                  _ 0 = Common running disparity. Common running disparity is computed for even and odd
16633                                                                  code-
16634                                                                  groups of an RXAUI lane, i.e. interleave lanes before PCS layer as described in the Dune
16635                                                                  Networks/Broadcom RXAUI v2.1 specification. This obeys 6.25GHz SerDes disparity.
16636 
16637                                                                  _ 1 = Interleaved running disparity: Running disparity is computed separately for even and
16638                                                                  odd code-groups of an RXAUI lane, i.e. interleave lanes after PCS layer as described in
16639                                                                  the Marvell RXAUI Interface specification. This does not obey 6.25GHz SerDes disparity. */
16640         uint64_t skip_after_term       : 1;  /**< [ 11: 11](R/W) Enable sending of idle skip after terminate. This bit is meaningful when the logical PCS
16641                                                                  type is XAUI or RXAUI (selected by BGX()_CMR()_CONFIG[LMAC_TYPE]), and has no
16642                                                                  effect otherwise. When set, the LMAC/LPCS transmits more idle skip columns for clock
16643                                                                  compensation. Typically set in HiGig/HiGig2 modes; clear otherwise. This field can be set
16644                                                                  to ensure sufficient density of XAUI idle skip (||R||) columns with a small transmit
16645                                                                  inter-frame gap (IFG) in order to allow the link partner's receiver to delete ||R||
16646                                                                  columns as needed for clock rate compensation. It is usually set when the LMAC's transmit
16647                                                                  IFG is set to eight bytes in HiGig/HiGig2 modes (i.e. BGX()_SMU()_TX_IFG[IFG1] +
16648                                                                  BGX()_SMU()_TX_IFG[IFG2] = 8), and should be cleared when the transmit IFG is
16649                                                                  greater than eight bytes. When this bit is set, the SPU will send an ||R|| column after a
16650                                                                  ||T0|| column (terminate in lane 0) if no ||R|| was sent in the previous IFG. This is a
16651                                                                  minor deviation from the functionality specified in 802.3-2008 Figure 48-6 (PCS transmit
16652                                                                  source state diagram), whereby the state will transition directly from SEND_DATA to
16653                                                                  SEND_RANDOM_R after ||T0|| if no ||R|| was transmitted in the previous IFG. Sending ||R||
16654                                                                  after ||T0|| only (and not ||T1||, |T2|| or ||T3||) ensures that the check_end function at
16655                                                                  the receiving end, as defined in 802.3-2008 sub-clause 48.2.6.1.4, does not detect an
16656                                                                  error due to this functional change. When this bit is clear, the LMAC will fully conform
16657                                                                  to the functionality specified in Figure 48-6. */
16658         uint64_t rx_packet_dis         : 1;  /**< [ 12: 12](R/W) Receive packet disable. Software can set or clear this bit at any time to gracefully
16659                                                                  disable or re-enable packet reception by the LPCS. If this bit is set while a packet is
16660                                                                  being received, the packet is completed and all subsequent received packets are discarded
16661                                                                  by the LPCS. Similarly, if this bit is cleared while a received packet is being discarded,
16662                                                                  packet reception resumes after the current packet is fully discarded. When set for a
16663                                                                  40GBASE-R or 10GBASE-R LMAC/LPCS type (selected by BGX()_CMR()_CONFIG[LMAC_TYPE]),
16664                                                                  received errors and faults will be ignored while receive packets are discarded; idles will
16665                                                                  be sent to the MAC layer (SMU) and the errored blocks counter
16666                                                                  (BGX()_SPU()_BR_STATUS2[ERR_BLKS]) will not increment. */
16667         uint64_t reserved_13_63        : 51;
16668 #endif /* Word 0 - End */
16669     } s;
16670     /* struct bdk_bgxx_spux_misc_control_s cn; */
16671 };
16672 typedef union bdk_bgxx_spux_misc_control bdk_bgxx_spux_misc_control_t;
16673 
16674 static inline uint64_t BDK_BGXX_SPUX_MISC_CONTROL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_MISC_CONTROL(unsigned long a,unsigned long b)16675 static inline uint64_t BDK_BGXX_SPUX_MISC_CONTROL(unsigned long a, unsigned long b)
16676 {
16677     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16678         return 0x87e0e0010218ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16679     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16680         return 0x87e0e0010218ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16681     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16682         return 0x87e0e0010218ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16683     __bdk_csr_fatal("BGXX_SPUX_MISC_CONTROL", 2, a, b, 0, 0);
16684 }
16685 
16686 #define typedef_BDK_BGXX_SPUX_MISC_CONTROL(a,b) bdk_bgxx_spux_misc_control_t
16687 #define bustype_BDK_BGXX_SPUX_MISC_CONTROL(a,b) BDK_CSR_TYPE_RSL
16688 #define basename_BDK_BGXX_SPUX_MISC_CONTROL(a,b) "BGXX_SPUX_MISC_CONTROL"
16689 #define device_bar_BDK_BGXX_SPUX_MISC_CONTROL(a,b) 0x0 /* PF_BAR0 */
16690 #define busnum_BDK_BGXX_SPUX_MISC_CONTROL(a,b) (a)
16691 #define arguments_BDK_BGXX_SPUX_MISC_CONTROL(a,b) (a),(b),-1,-1
16692 
16693 /**
16694  * Register (RSL) bgx#_spu#_spd_abil
16695  *
16696  * BGX SPU PCS Speed Ability Registers
16697  */
16698 union bdk_bgxx_spux_spd_abil
16699 {
16700     uint64_t u;
16701     struct bdk_bgxx_spux_spd_abil_s
16702     {
16703 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16704         uint64_t reserved_4_63         : 60;
16705         uint64_t hundredgb             : 1;  /**< [  3:  3](RO) 100G capable. Always 0. */
16706         uint64_t fortygb               : 1;  /**< [  2:  2](RO/H) 40G capable. Always 1. */
16707         uint64_t tenpasst              : 1;  /**< [  1:  1](RO) 10PASS-TS/2BASE-TL capable. Always 0. */
16708         uint64_t tengb                 : 1;  /**< [  0:  0](RO/H) 10G capable. Always 1. */
16709 #else /* Word 0 - Little Endian */
16710         uint64_t tengb                 : 1;  /**< [  0:  0](RO/H) 10G capable. Always 1. */
16711         uint64_t tenpasst              : 1;  /**< [  1:  1](RO) 10PASS-TS/2BASE-TL capable. Always 0. */
16712         uint64_t fortygb               : 1;  /**< [  2:  2](RO/H) 40G capable. Always 1. */
16713         uint64_t hundredgb             : 1;  /**< [  3:  3](RO) 100G capable. Always 0. */
16714         uint64_t reserved_4_63         : 60;
16715 #endif /* Word 0 - End */
16716     } s;
16717     /* struct bdk_bgxx_spux_spd_abil_s cn; */
16718 };
16719 typedef union bdk_bgxx_spux_spd_abil bdk_bgxx_spux_spd_abil_t;
16720 
16721 static inline uint64_t BDK_BGXX_SPUX_SPD_ABIL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_SPD_ABIL(unsigned long a,unsigned long b)16722 static inline uint64_t BDK_BGXX_SPUX_SPD_ABIL(unsigned long a, unsigned long b)
16723 {
16724     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16725         return 0x87e0e0010010ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16726     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16727         return 0x87e0e0010010ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16728     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16729         return 0x87e0e0010010ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16730     __bdk_csr_fatal("BGXX_SPUX_SPD_ABIL", 2, a, b, 0, 0);
16731 }
16732 
16733 #define typedef_BDK_BGXX_SPUX_SPD_ABIL(a,b) bdk_bgxx_spux_spd_abil_t
16734 #define bustype_BDK_BGXX_SPUX_SPD_ABIL(a,b) BDK_CSR_TYPE_RSL
16735 #define basename_BDK_BGXX_SPUX_SPD_ABIL(a,b) "BGXX_SPUX_SPD_ABIL"
16736 #define device_bar_BDK_BGXX_SPUX_SPD_ABIL(a,b) 0x0 /* PF_BAR0 */
16737 #define busnum_BDK_BGXX_SPUX_SPD_ABIL(a,b) (a)
16738 #define arguments_BDK_BGXX_SPUX_SPD_ABIL(a,b) (a),(b),-1,-1
16739 
16740 /**
16741  * Register (RSL) bgx#_spu#_status1
16742  *
16743  * BGX SPU Status 1 Registers
16744  */
16745 union bdk_bgxx_spux_status1
16746 {
16747     uint64_t u;
16748     struct bdk_bgxx_spux_status1_s
16749     {
16750 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16751         uint64_t reserved_8_63         : 56;
16752         uint64_t flt                   : 1;  /**< [  7:  7](RO/H) Fault condition detected.
16753                                                                  This bit is a logical OR of BGX()_SPU()_STATUS2[XMTFLT, RCVFLT]. */
16754         uint64_t reserved_3_6          : 4;
16755         uint64_t rcv_lnk               : 1;  /**< [  2:  2](R/W1S/H) PCS receive link status:
16756                                                                    0 = receive link down.
16757                                                                    1 = receive link up.
16758 
16759                                                                  This is a latching-low bit; it stays clear until a write-1-to-set by software.
16760 
16761                                                                  For a BASE-X logical PCS type (in the associated BGX()_CMR()_CONFIG[LMAC_TYPE] =
16762                                                                  XAUI or RXAUI), this is a latching-low version of BGX()_SPU()_BX_STATUS[ALIGND].
16763 
16764                                                                  For a BASE-R logical PCS type (in the associated BGX()_CMR()_CONFIG[LMAC_TYPE] =
16765                                                                  10G_R or 40G_R), this is a latching-low version of
16766                                                                  BGX()_SPU()_BR_STATUS1[RCV_LNK]. */
16767         uint64_t lpable                : 1;  /**< [  1:  1](RO) Low-power ability. Always returns 1 to indicate that the LPCS supports low-power mode. */
16768         uint64_t reserved_0            : 1;
16769 #else /* Word 0 - Little Endian */
16770         uint64_t reserved_0            : 1;
16771         uint64_t lpable                : 1;  /**< [  1:  1](RO) Low-power ability. Always returns 1 to indicate that the LPCS supports low-power mode. */
16772         uint64_t rcv_lnk               : 1;  /**< [  2:  2](R/W1S/H) PCS receive link status:
16773                                                                    0 = receive link down.
16774                                                                    1 = receive link up.
16775 
16776                                                                  This is a latching-low bit; it stays clear until a write-1-to-set by software.
16777 
16778                                                                  For a BASE-X logical PCS type (in the associated BGX()_CMR()_CONFIG[LMAC_TYPE] =
16779                                                                  XAUI or RXAUI), this is a latching-low version of BGX()_SPU()_BX_STATUS[ALIGND].
16780 
16781                                                                  For a BASE-R logical PCS type (in the associated BGX()_CMR()_CONFIG[LMAC_TYPE] =
16782                                                                  10G_R or 40G_R), this is a latching-low version of
16783                                                                  BGX()_SPU()_BR_STATUS1[RCV_LNK]. */
16784         uint64_t reserved_3_6          : 4;
16785         uint64_t flt                   : 1;  /**< [  7:  7](RO/H) Fault condition detected.
16786                                                                  This bit is a logical OR of BGX()_SPU()_STATUS2[XMTFLT, RCVFLT]. */
16787         uint64_t reserved_8_63         : 56;
16788 #endif /* Word 0 - End */
16789     } s;
16790     /* struct bdk_bgxx_spux_status1_s cn; */
16791 };
16792 typedef union bdk_bgxx_spux_status1 bdk_bgxx_spux_status1_t;
16793 
16794 static inline uint64_t BDK_BGXX_SPUX_STATUS1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_STATUS1(unsigned long a,unsigned long b)16795 static inline uint64_t BDK_BGXX_SPUX_STATUS1(unsigned long a, unsigned long b)
16796 {
16797     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16798         return 0x87e0e0010008ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16799     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16800         return 0x87e0e0010008ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16801     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16802         return 0x87e0e0010008ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16803     __bdk_csr_fatal("BGXX_SPUX_STATUS1", 2, a, b, 0, 0);
16804 }
16805 
16806 #define typedef_BDK_BGXX_SPUX_STATUS1(a,b) bdk_bgxx_spux_status1_t
16807 #define bustype_BDK_BGXX_SPUX_STATUS1(a,b) BDK_CSR_TYPE_RSL
16808 #define basename_BDK_BGXX_SPUX_STATUS1(a,b) "BGXX_SPUX_STATUS1"
16809 #define device_bar_BDK_BGXX_SPUX_STATUS1(a,b) 0x0 /* PF_BAR0 */
16810 #define busnum_BDK_BGXX_SPUX_STATUS1(a,b) (a)
16811 #define arguments_BDK_BGXX_SPUX_STATUS1(a,b) (a),(b),-1,-1
16812 
16813 /**
16814  * Register (RSL) bgx#_spu#_status2
16815  *
16816  * BGX SPU Status 2 Registers
16817  */
16818 union bdk_bgxx_spux_status2
16819 {
16820     uint64_t u;
16821     struct bdk_bgxx_spux_status2_s
16822     {
16823 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16824         uint64_t reserved_16_63        : 48;
16825         uint64_t dev                   : 2;  /**< [ 15: 14](RO/H) Device present. Always returns 0x2 to indicate a device is present at this address. */
16826         uint64_t reserved_12_13        : 2;
16827         uint64_t xmtflt                : 1;  /**< [ 11: 11](RO/H) Transmit fault. Always returns 0. */
16828         uint64_t rcvflt                : 1;  /**< [ 10: 10](R/W1C/H) Receive fault: 1 = receive fault. 0 = no receive fault. Latching high bit; stays set until
16829                                                                  a write-1-to-clear by software. */
16830         uint64_t reserved_6_9          : 4;
16831         uint64_t hundredgb_r           : 1;  /**< [  5:  5](RO) 100GBASE-R capable. Always 0. */
16832         uint64_t fortygb_r             : 1;  /**< [  4:  4](RO/H) 40GBASE-R capable. Always 1. */
16833         uint64_t tengb_t               : 1;  /**< [  3:  3](RO) 10GBASE-T capable. Always 0. */
16834         uint64_t tengb_w               : 1;  /**< [  2:  2](RO) 10GBASE-W capable. Always 0. */
16835         uint64_t tengb_x               : 1;  /**< [  1:  1](RO/H) 10GBASE-X capable. Always 1. */
16836         uint64_t tengb_r               : 1;  /**< [  0:  0](RO/H) 10GBASE-R capable. Always 1. */
16837 #else /* Word 0 - Little Endian */
16838         uint64_t tengb_r               : 1;  /**< [  0:  0](RO/H) 10GBASE-R capable. Always 1. */
16839         uint64_t tengb_x               : 1;  /**< [  1:  1](RO/H) 10GBASE-X capable. Always 1. */
16840         uint64_t tengb_w               : 1;  /**< [  2:  2](RO) 10GBASE-W capable. Always 0. */
16841         uint64_t tengb_t               : 1;  /**< [  3:  3](RO) 10GBASE-T capable. Always 0. */
16842         uint64_t fortygb_r             : 1;  /**< [  4:  4](RO/H) 40GBASE-R capable. Always 1. */
16843         uint64_t hundredgb_r           : 1;  /**< [  5:  5](RO) 100GBASE-R capable. Always 0. */
16844         uint64_t reserved_6_9          : 4;
16845         uint64_t rcvflt                : 1;  /**< [ 10: 10](R/W1C/H) Receive fault: 1 = receive fault. 0 = no receive fault. Latching high bit; stays set until
16846                                                                  a write-1-to-clear by software. */
16847         uint64_t xmtflt                : 1;  /**< [ 11: 11](RO/H) Transmit fault. Always returns 0. */
16848         uint64_t reserved_12_13        : 2;
16849         uint64_t dev                   : 2;  /**< [ 15: 14](RO/H) Device present. Always returns 0x2 to indicate a device is present at this address. */
16850         uint64_t reserved_16_63        : 48;
16851 #endif /* Word 0 - End */
16852     } s;
16853     /* struct bdk_bgxx_spux_status2_s cn; */
16854 };
16855 typedef union bdk_bgxx_spux_status2 bdk_bgxx_spux_status2_t;
16856 
16857 static inline uint64_t BDK_BGXX_SPUX_STATUS2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPUX_STATUS2(unsigned long a,unsigned long b)16858 static inline uint64_t BDK_BGXX_SPUX_STATUS2(unsigned long a, unsigned long b)
16859 {
16860     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
16861         return 0x87e0e0010020ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16862     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
16863         return 0x87e0e0010020ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x3);
16864     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
16865         return 0x87e0e0010020ll + 0x1000000ll * ((a) & 0x1) + 0x100000ll * ((b) & 0x3);
16866     __bdk_csr_fatal("BGXX_SPUX_STATUS2", 2, a, b, 0, 0);
16867 }
16868 
16869 #define typedef_BDK_BGXX_SPUX_STATUS2(a,b) bdk_bgxx_spux_status2_t
16870 #define bustype_BDK_BGXX_SPUX_STATUS2(a,b) BDK_CSR_TYPE_RSL
16871 #define basename_BDK_BGXX_SPUX_STATUS2(a,b) "BGXX_SPUX_STATUS2"
16872 #define device_bar_BDK_BGXX_SPUX_STATUS2(a,b) 0x0 /* PF_BAR0 */
16873 #define busnum_BDK_BGXX_SPUX_STATUS2(a,b) (a)
16874 #define arguments_BDK_BGXX_SPUX_STATUS2(a,b) (a),(b),-1,-1
16875 
16876 /**
16877  * Register (RSL) bgx#_spu_bist_status
16878  *
16879  * BGX SPU BIST Status Registers
16880  * This register provides memory BIST status from the SPU receive buffer lane FIFOs.
16881  */
16882 union bdk_bgxx_spu_bist_status
16883 {
16884     uint64_t u;
16885     struct bdk_bgxx_spu_bist_status_s
16886     {
16887 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16888         uint64_t reserved_4_63         : 60;
16889         uint64_t rx_buf_bist_status    : 4;  /**< [  3:  0](RO/H) SPU receive buffer BIST status for lanes 3-0. One bit per SerDes lane, set to indicate
16890                                                                  BIST
16891                                                                  failure for the associated receive buffer lane FIFO. */
16892 #else /* Word 0 - Little Endian */
16893         uint64_t rx_buf_bist_status    : 4;  /**< [  3:  0](RO/H) SPU receive buffer BIST status for lanes 3-0. One bit per SerDes lane, set to indicate
16894                                                                  BIST
16895                                                                  failure for the associated receive buffer lane FIFO. */
16896         uint64_t reserved_4_63         : 60;
16897 #endif /* Word 0 - End */
16898     } s;
16899     /* struct bdk_bgxx_spu_bist_status_s cn; */
16900 };
16901 typedef union bdk_bgxx_spu_bist_status bdk_bgxx_spu_bist_status_t;
16902 
16903 static inline uint64_t BDK_BGXX_SPU_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_SPU_BIST_STATUS(unsigned long a)16904 static inline uint64_t BDK_BGXX_SPU_BIST_STATUS(unsigned long a)
16905 {
16906     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
16907         return 0x87e0e0010330ll + 0x1000000ll * ((a) & 0x1);
16908     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
16909         return 0x87e0e0010330ll + 0x1000000ll * ((a) & 0x3);
16910     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
16911         return 0x87e0e0010330ll + 0x1000000ll * ((a) & 0x1);
16912     __bdk_csr_fatal("BGXX_SPU_BIST_STATUS", 1, a, 0, 0, 0);
16913 }
16914 
16915 #define typedef_BDK_BGXX_SPU_BIST_STATUS(a) bdk_bgxx_spu_bist_status_t
16916 #define bustype_BDK_BGXX_SPU_BIST_STATUS(a) BDK_CSR_TYPE_RSL
16917 #define basename_BDK_BGXX_SPU_BIST_STATUS(a) "BGXX_SPU_BIST_STATUS"
16918 #define device_bar_BDK_BGXX_SPU_BIST_STATUS(a) 0x0 /* PF_BAR0 */
16919 #define busnum_BDK_BGXX_SPU_BIST_STATUS(a) (a)
16920 #define arguments_BDK_BGXX_SPU_BIST_STATUS(a) (a),-1,-1,-1
16921 
16922 /**
16923  * Register (RSL) bgx#_spu_dbg_control
16924  *
16925  * BGX SPU Debug Control Registers
16926  */
16927 union bdk_bgxx_spu_dbg_control
16928 {
16929     uint64_t u;
16930     struct bdk_bgxx_spu_dbg_control_s
16931     {
16932 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16933         uint64_t reserved_56_63        : 8;
16934         uint64_t ms_clk_period         : 12; /**< [ 55: 44](R/W) Millisecond clock period. Specifies the number of microsecond clock ticks per millisecond,
16935                                                                  minus one. The default value of 999 (0x3E7) should be used during normal operation; other
16936                                                                  values may be used for test/debug purposes. */
16937         uint64_t us_clk_period         : 12; /**< [ 43: 32](R/W) Microsecond clock period. Specifies the number of SCLK cycles per microseconds, minus one.
16938                                                                  For example, if SCLK runs at 1.3 GHz, the number of SCLK cycles per microsecond is 1,300
16939                                                                  so the value of this field should be 1,299 (0x513). This is used by the BASE-R BER monitor
16940                                                                  timers. */
16941         uint64_t reserved_31           : 1;
16942         uint64_t br_ber_mon_dis        : 1;  /**< [ 30: 30](R/W) BASE-R bit error rate monitor disable. This bit should be clear for normal operation.
16943                                                                  Setting it disables the BASE-R BER monitor state machine defined in 802.3-2008 Figure
16944                                                                  49-13 for 10GBASE-R and 802.3ba-2010 Figure 82-13 for 40GBASE-R. */
16945         uint64_t an_nonce_match_dis    : 1;  /**< [ 29: 29](R/W) Autonegotiation nonce match disable. This bit should be clear for normal operation.
16946                                                                  Setting it disables Nonce Match check by forcing nonce_match variable to 0 in the
16947                                                                  autonegotiation arbitration state diagram, as defined in 802.3-2008 Figure 73-11. This bit
16948                                                                  can
16949                                                                  be set by software for test purposes, e.g. for running autonegotiation in loopback mode. */
16950         uint64_t timestamp_norm_dis    : 1;  /**< [ 28: 28](R/W) 40GBASE-R RX timestamp normalization disable. This bit controls the generation of the
16951                                                                  receive SOP timestamp passed to the SMU sub-block for a 40GBASE-R LMAC/LPCS. When this bit
16952                                                                  is clear, SPU normalizes the receive SOP timestamp in order to compensate for lane-to-lane
16953                                                                  skew on a 40GBASE-R link, as described below. When this bit is set, timestamp
16954                                                                  normalization is disabled and SPU directly passes the captured SOP timestamp values to
16955                                                                  SMU.
16956 
16957                                                                  In 40GBASE-R mode, a packet's SOP block can be transferred on any of the LMAC's lanes. In
16958                                                                  the presence of lane-to-lane skew, the SOP delay from transmit (by the link partner) to
16959                                                                  receive by SPU varies depending on which lane is used by the SOP block. This variation
16960                                                                  reduces the accuracy of the received SOP timestamp relative to when it was transmitted by
16961                                                                  the link partner.
16962 
16963                                                                  SPU captures the timestamp of the alignment marker received on each SerDes lane during
16964                                                                  align/skew detection; the captured value can be read from the SerDes lane's
16965                                                                  BGX()_SPU_SDS()_SKEW_STATUS[SKEW_STATUS] field (BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP]
16966                                                                  sub-field). If
16967                                                                  alignment markers are transmitted at about the same time on all lanes by the link partner,
16968                                                                  then the difference between the BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP] values for a pair
16969                                                                  of lanes represents the
16970                                                                  approximate skew between those lanes.
16971 
16972                                                                  SPU uses the 40GBASE-R LMAC's programmed PCS lane 0 as a reference and computes the
16973                                                                  BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP] delta of every other lane relative to PCS lane 0.
16974                                                                  When normalization is
16975                                                                  enabled, SPU adjusts the timestamp of a received SOP by subtracting the receiving lane's
16976                                                                  BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP] delta from the captured timestamp value. The
16977                                                                  adjusted/normalized timestamp
16978                                                                  value is then passed to SMU along with the SOP.
16979 
16980                                                                  Software can determine the actual maximum skew of a 40GBASE-R link by examining the
16981                                                                  BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP] values in the BGX()_SPU_SDS()_SKEW_STATUS
16982                                                                  registers, and decide if
16983                                                                  timestamp normalization should be enabled or disabled to improve PTP accuracy.
16984                                                                  Normalization improves accuracy for larger skew values but reduces the accuracy (due to
16985                                                                  timestamp measurement errors) for small skew values. */
16986         uint64_t rx_buf_flip_synd      : 8;  /**< [ 27: 20](R/W) Flip SPU receive buffer FIFO ECC bits. Two bits per SerDes lane; used to inject single-bit
16987                                                                  and
16988                                                                  double-bit errors into the ECC field on writes to the associated SPU receive buffer lane
16989                                                                  FIFO, as
16990                                                                  follows:
16991                                                                  0x0 = Normal operation.
16992                                                                  0x1 = SBE on ECC bit 0.
16993                                                                  0x2 = SBE on ECC bit 1.
16994                                                                  0x3 = DBE on ECC bits 1:0. */
16995         uint64_t br_pmd_train_soft_en  : 1;  /**< [ 19: 19](R/W) Enable BASE-R PMD software controlled link training. This bit configures the operation
16996                                                                  mode for BASE-R link training for all LMACs and lanes. When this bit is set along with
16997                                                                  BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] for a given LMAC, the BASE-R link training
16998                                                                  protocol for that LMAC is executed under software control, whereby the contents the
16999                                                                  BGX()_SPU()_BR_PMD_LD_CUP and BGX()_SPU()_BR_PMD_LD_REP registers are
17000                                                                  updated by software. When this bit is clear and
17001                                                                  BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is set, the link training protocol is fully
17002                                                                  automated in hardware, whereby the contents BGX()_SPU()_BR_PMD_LD_CUP and
17003                                                                  BGX()_SPU()_BR_PMD_LD_REP registers are automatically updated by hardware. */
17004         uint64_t an_arb_link_chk_en    : 1;  /**< [ 18: 18](R/W) Enable link status checking by autonegotiation arbitration state machine. When
17005                                                                  autonegotiation is enabled (BGX()_SPU()_AN_CONTROL[AN_EN] is set), this bit controls
17006                                                                  the behavior of the autonegotiation arbitration state machine when it reaches the AN GOOD
17007                                                                  CHECK state after DME pages are successfully exchanged, as defined in Figure 73-11 in
17008                                                                  802.3-2008.
17009 
17010                                                                  When this bit is set and the negotiated highest common denominator (HCD) technology
17011                                                                  matches BGX()_CMR()_CONFIG[LMAC_TYPE], the autonegotiation arbitration SM
17012                                                                  performs the actions defined for the AN GOOD CHECK state in Figure 73-11, i.e. run the
17013                                                                  link_fail_inhibit timer and eventually transition to the AN GOOD or TRANSMIT DISABLE
17014                                                                  state.
17015 
17016                                                                  When this bit is clear or the HCD technology does not match BGX()_CMR()_CONFIG[LMAC_TYPE],
17017                                                                  the AN arbitration
17018                                                                  SM stays in the AN GOOD CHECK state, with the expectation that software will perform the
17019                                                                  appropriate actions to complete the autonegotiation protocol, as follows:
17020 
17021                                                                  * If this bit is clear and the HCD technology matches BGX()_CMR()_CONFIG[LMAC_TYPE], clear
17022                                                                  BGX()_SPU()_AN_CONTROL[AN_EN].
17023 
17024                                                                  * Otherwise, disable the LPCS by clearing the BGX()_CMR()_CONFIG[ENABLE], clear
17025                                                                  BGX()_SPU()_AN_CONTROL[AN_EN], reconfigure the LPCS with the correct
17026                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE],
17027                                                                  and re-enable the LPCS by setting BGX()_CMR()_CONFIG[ENABLE].
17028 
17029                                                                  In both cases, software should implement the link_fail_inhibit timer and verify the link
17030                                                                  status as specified for the AN GOOD CHECK state. */
17031         uint64_t rx_buf_cor_dis        : 1;  /**< [ 17: 17](R/W) When set, disables ECC correction on all SPU receive buffer FIFOs. */
17032         uint64_t scramble_dis          : 1;  /**< [ 16: 16](R/W) BASE-R scrambler/descrambler disable. Setting this bit to 1 disables the BASE-R scrambler
17033                                                                  & descrambler functions and FEC PN-2112 scrambler & descrambler functions for debug
17034                                                                  purposes. */
17035         uint64_t reserved_15           : 1;
17036         uint64_t marker_rxp            : 15; /**< [ 14:  0](R/W) BASE-R alignment marker receive period. For a multilane BASE-R logical PCS (i.e.
17037                                                                  40GBASE-R), this field specifies the expected alignment marker receive period per lane,
17038                                                                  i.e. the expected number of received 66b non-marker blocks between consecutive markers on
17039                                                                  the same lane. The default value corresponds to a period of 16363 blocks (exclusive) as
17040                                                                  specified in 802.3ba-2010. Must be greater than 64. */
17041 #else /* Word 0 - Little Endian */
17042         uint64_t marker_rxp            : 15; /**< [ 14:  0](R/W) BASE-R alignment marker receive period. For a multilane BASE-R logical PCS (i.e.
17043                                                                  40GBASE-R), this field specifies the expected alignment marker receive period per lane,
17044                                                                  i.e. the expected number of received 66b non-marker blocks between consecutive markers on
17045                                                                  the same lane. The default value corresponds to a period of 16363 blocks (exclusive) as
17046                                                                  specified in 802.3ba-2010. Must be greater than 64. */
17047         uint64_t reserved_15           : 1;
17048         uint64_t scramble_dis          : 1;  /**< [ 16: 16](R/W) BASE-R scrambler/descrambler disable. Setting this bit to 1 disables the BASE-R scrambler
17049                                                                  & descrambler functions and FEC PN-2112 scrambler & descrambler functions for debug
17050                                                                  purposes. */
17051         uint64_t rx_buf_cor_dis        : 1;  /**< [ 17: 17](R/W) When set, disables ECC correction on all SPU receive buffer FIFOs. */
17052         uint64_t an_arb_link_chk_en    : 1;  /**< [ 18: 18](R/W) Enable link status checking by autonegotiation arbitration state machine. When
17053                                                                  autonegotiation is enabled (BGX()_SPU()_AN_CONTROL[AN_EN] is set), this bit controls
17054                                                                  the behavior of the autonegotiation arbitration state machine when it reaches the AN GOOD
17055                                                                  CHECK state after DME pages are successfully exchanged, as defined in Figure 73-11 in
17056                                                                  802.3-2008.
17057 
17058                                                                  When this bit is set and the negotiated highest common denominator (HCD) technology
17059                                                                  matches BGX()_CMR()_CONFIG[LMAC_TYPE], the autonegotiation arbitration SM
17060                                                                  performs the actions defined for the AN GOOD CHECK state in Figure 73-11, i.e. run the
17061                                                                  link_fail_inhibit timer and eventually transition to the AN GOOD or TRANSMIT DISABLE
17062                                                                  state.
17063 
17064                                                                  When this bit is clear or the HCD technology does not match BGX()_CMR()_CONFIG[LMAC_TYPE],
17065                                                                  the AN arbitration
17066                                                                  SM stays in the AN GOOD CHECK state, with the expectation that software will perform the
17067                                                                  appropriate actions to complete the autonegotiation protocol, as follows:
17068 
17069                                                                  * If this bit is clear and the HCD technology matches BGX()_CMR()_CONFIG[LMAC_TYPE], clear
17070                                                                  BGX()_SPU()_AN_CONTROL[AN_EN].
17071 
17072                                                                  * Otherwise, disable the LPCS by clearing the BGX()_CMR()_CONFIG[ENABLE], clear
17073                                                                  BGX()_SPU()_AN_CONTROL[AN_EN], reconfigure the LPCS with the correct
17074                                                                  BGX()_CMR()_CONFIG[LMAC_TYPE],
17075                                                                  and re-enable the LPCS by setting BGX()_CMR()_CONFIG[ENABLE].
17076 
17077                                                                  In both cases, software should implement the link_fail_inhibit timer and verify the link
17078                                                                  status as specified for the AN GOOD CHECK state. */
17079         uint64_t br_pmd_train_soft_en  : 1;  /**< [ 19: 19](R/W) Enable BASE-R PMD software controlled link training. This bit configures the operation
17080                                                                  mode for BASE-R link training for all LMACs and lanes. When this bit is set along with
17081                                                                  BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] for a given LMAC, the BASE-R link training
17082                                                                  protocol for that LMAC is executed under software control, whereby the contents the
17083                                                                  BGX()_SPU()_BR_PMD_LD_CUP and BGX()_SPU()_BR_PMD_LD_REP registers are
17084                                                                  updated by software. When this bit is clear and
17085                                                                  BGX()_SPU()_BR_PMD_CONTROL[TRAIN_EN] is set, the link training protocol is fully
17086                                                                  automated in hardware, whereby the contents BGX()_SPU()_BR_PMD_LD_CUP and
17087                                                                  BGX()_SPU()_BR_PMD_LD_REP registers are automatically updated by hardware. */
17088         uint64_t rx_buf_flip_synd      : 8;  /**< [ 27: 20](R/W) Flip SPU receive buffer FIFO ECC bits. Two bits per SerDes lane; used to inject single-bit
17089                                                                  and
17090                                                                  double-bit errors into the ECC field on writes to the associated SPU receive buffer lane
17091                                                                  FIFO, as
17092                                                                  follows:
17093                                                                  0x0 = Normal operation.
17094                                                                  0x1 = SBE on ECC bit 0.
17095                                                                  0x2 = SBE on ECC bit 1.
17096                                                                  0x3 = DBE on ECC bits 1:0. */
17097         uint64_t timestamp_norm_dis    : 1;  /**< [ 28: 28](R/W) 40GBASE-R RX timestamp normalization disable. This bit controls the generation of the
17098                                                                  receive SOP timestamp passed to the SMU sub-block for a 40GBASE-R LMAC/LPCS. When this bit
17099                                                                  is clear, SPU normalizes the receive SOP timestamp in order to compensate for lane-to-lane
17100                                                                  skew on a 40GBASE-R link, as described below. When this bit is set, timestamp
17101                                                                  normalization is disabled and SPU directly passes the captured SOP timestamp values to
17102                                                                  SMU.
17103 
17104                                                                  In 40GBASE-R mode, a packet's SOP block can be transferred on any of the LMAC's lanes. In
17105                                                                  the presence of lane-to-lane skew, the SOP delay from transmit (by the link partner) to
17106                                                                  receive by SPU varies depending on which lane is used by the SOP block. This variation
17107                                                                  reduces the accuracy of the received SOP timestamp relative to when it was transmitted by
17108                                                                  the link partner.
17109 
17110                                                                  SPU captures the timestamp of the alignment marker received on each SerDes lane during
17111                                                                  align/skew detection; the captured value can be read from the SerDes lane's
17112                                                                  BGX()_SPU_SDS()_SKEW_STATUS[SKEW_STATUS] field (BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP]
17113                                                                  sub-field). If
17114                                                                  alignment markers are transmitted at about the same time on all lanes by the link partner,
17115                                                                  then the difference between the BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP] values for a pair
17116                                                                  of lanes represents the
17117                                                                  approximate skew between those lanes.
17118 
17119                                                                  SPU uses the 40GBASE-R LMAC's programmed PCS lane 0 as a reference and computes the
17120                                                                  BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP] delta of every other lane relative to PCS lane 0.
17121                                                                  When normalization is
17122                                                                  enabled, SPU adjusts the timestamp of a received SOP by subtracting the receiving lane's
17123                                                                  BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP] delta from the captured timestamp value. The
17124                                                                  adjusted/normalized timestamp
17125                                                                  value is then passed to SMU along with the SOP.
17126 
17127                                                                  Software can determine the actual maximum skew of a 40GBASE-R link by examining the
17128                                                                  BGX_SPU_SDS_SKEW_STATUS_S[AM_TIMESTAMP] values in the BGX()_SPU_SDS()_SKEW_STATUS
17129                                                                  registers, and decide if
17130                                                                  timestamp normalization should be enabled or disabled to improve PTP accuracy.
17131                                                                  Normalization improves accuracy for larger skew values but reduces the accuracy (due to
17132                                                                  timestamp measurement errors) for small skew values. */
17133         uint64_t an_nonce_match_dis    : 1;  /**< [ 29: 29](R/W) Autonegotiation nonce match disable. This bit should be clear for normal operation.
17134                                                                  Setting it disables Nonce Match check by forcing nonce_match variable to 0 in the
17135                                                                  autonegotiation arbitration state diagram, as defined in 802.3-2008 Figure 73-11. This bit
17136                                                                  can
17137                                                                  be set by software for test purposes, e.g. for running autonegotiation in loopback mode. */
17138         uint64_t br_ber_mon_dis        : 1;  /**< [ 30: 30](R/W) BASE-R bit error rate monitor disable. This bit should be clear for normal operation.
17139                                                                  Setting it disables the BASE-R BER monitor state machine defined in 802.3-2008 Figure
17140                                                                  49-13 for 10GBASE-R and 802.3ba-2010 Figure 82-13 for 40GBASE-R. */
17141         uint64_t reserved_31           : 1;
17142         uint64_t us_clk_period         : 12; /**< [ 43: 32](R/W) Microsecond clock period. Specifies the number of SCLK cycles per microseconds, minus one.
17143                                                                  For example, if SCLK runs at 1.3 GHz, the number of SCLK cycles per microsecond is 1,300
17144                                                                  so the value of this field should be 1,299 (0x513). This is used by the BASE-R BER monitor
17145                                                                  timers. */
17146         uint64_t ms_clk_period         : 12; /**< [ 55: 44](R/W) Millisecond clock period. Specifies the number of microsecond clock ticks per millisecond,
17147                                                                  minus one. The default value of 999 (0x3E7) should be used during normal operation; other
17148                                                                  values may be used for test/debug purposes. */
17149         uint64_t reserved_56_63        : 8;
17150 #endif /* Word 0 - End */
17151     } s;
17152     /* struct bdk_bgxx_spu_dbg_control_s cn; */
17153 };
17154 typedef union bdk_bgxx_spu_dbg_control bdk_bgxx_spu_dbg_control_t;
17155 
17156 static inline uint64_t BDK_BGXX_SPU_DBG_CONTROL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_SPU_DBG_CONTROL(unsigned long a)17157 static inline uint64_t BDK_BGXX_SPU_DBG_CONTROL(unsigned long a)
17158 {
17159     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
17160         return 0x87e0e0010300ll + 0x1000000ll * ((a) & 0x1);
17161     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
17162         return 0x87e0e0010300ll + 0x1000000ll * ((a) & 0x3);
17163     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
17164         return 0x87e0e0010300ll + 0x1000000ll * ((a) & 0x1);
17165     __bdk_csr_fatal("BGXX_SPU_DBG_CONTROL", 1, a, 0, 0, 0);
17166 }
17167 
17168 #define typedef_BDK_BGXX_SPU_DBG_CONTROL(a) bdk_bgxx_spu_dbg_control_t
17169 #define bustype_BDK_BGXX_SPU_DBG_CONTROL(a) BDK_CSR_TYPE_RSL
17170 #define basename_BDK_BGXX_SPU_DBG_CONTROL(a) "BGXX_SPU_DBG_CONTROL"
17171 #define device_bar_BDK_BGXX_SPU_DBG_CONTROL(a) 0x0 /* PF_BAR0 */
17172 #define busnum_BDK_BGXX_SPU_DBG_CONTROL(a) (a)
17173 #define arguments_BDK_BGXX_SPU_DBG_CONTROL(a) (a),-1,-1,-1
17174 
17175 /**
17176  * Register (RSL) bgx#_spu_mem_int
17177  *
17178  * BGX SPU Memory Interrupt Registers
17179  */
17180 union bdk_bgxx_spu_mem_int
17181 {
17182     uint64_t u;
17183     struct bdk_bgxx_spu_mem_int_s
17184     {
17185 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17186         uint64_t reserved_8_63         : 56;
17187         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1C/H) SPU receive buffer single-bit error for lanes 3-0. One bit per physical SerDes lane. Each
17188                                                                  bit is set when the associated receive buffer lane FIFO detects a single-bit ECC error. */
17189         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1C/H) SPU receive buffer double-bit error for lanes 3-0. One bit per physical SerDes lane. Each
17190                                                                  bit is set when the associated receive buffer lane FIFO detects a double-bit ECC error. */
17191 #else /* Word 0 - Little Endian */
17192         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1C/H) SPU receive buffer double-bit error for lanes 3-0. One bit per physical SerDes lane. Each
17193                                                                  bit is set when the associated receive buffer lane FIFO detects a double-bit ECC error. */
17194         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1C/H) SPU receive buffer single-bit error for lanes 3-0. One bit per physical SerDes lane. Each
17195                                                                  bit is set when the associated receive buffer lane FIFO detects a single-bit ECC error. */
17196         uint64_t reserved_8_63         : 56;
17197 #endif /* Word 0 - End */
17198     } s;
17199     /* struct bdk_bgxx_spu_mem_int_s cn; */
17200 };
17201 typedef union bdk_bgxx_spu_mem_int bdk_bgxx_spu_mem_int_t;
17202 
17203 static inline uint64_t BDK_BGXX_SPU_MEM_INT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_SPU_MEM_INT(unsigned long a)17204 static inline uint64_t BDK_BGXX_SPU_MEM_INT(unsigned long a)
17205 {
17206     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
17207         return 0x87e0e0010310ll + 0x1000000ll * ((a) & 0x1);
17208     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
17209         return 0x87e0e0010310ll + 0x1000000ll * ((a) & 0x3);
17210     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
17211         return 0x87e0e0010310ll + 0x1000000ll * ((a) & 0x1);
17212     __bdk_csr_fatal("BGXX_SPU_MEM_INT", 1, a, 0, 0, 0);
17213 }
17214 
17215 #define typedef_BDK_BGXX_SPU_MEM_INT(a) bdk_bgxx_spu_mem_int_t
17216 #define bustype_BDK_BGXX_SPU_MEM_INT(a) BDK_CSR_TYPE_RSL
17217 #define basename_BDK_BGXX_SPU_MEM_INT(a) "BGXX_SPU_MEM_INT"
17218 #define device_bar_BDK_BGXX_SPU_MEM_INT(a) 0x0 /* PF_BAR0 */
17219 #define busnum_BDK_BGXX_SPU_MEM_INT(a) (a)
17220 #define arguments_BDK_BGXX_SPU_MEM_INT(a) (a),-1,-1,-1
17221 
17222 /**
17223  * Register (RSL) bgx#_spu_mem_int_ena_w1c
17224  *
17225  * BGX SPU Memory Interrupt Enable Clear Registers
17226  * This register clears interrupt enable bits.
17227  */
17228 union bdk_bgxx_spu_mem_int_ena_w1c
17229 {
17230     uint64_t u;
17231     struct bdk_bgxx_spu_mem_int_ena_w1c_s
17232     {
17233 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17234         uint64_t reserved_8_63         : 56;
17235         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU_MEM_INT[RX_BUF_SBE]. */
17236         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU_MEM_INT[RX_BUF_DBE]. */
17237 #else /* Word 0 - Little Endian */
17238         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU_MEM_INT[RX_BUF_DBE]. */
17239         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1C/H) Reads or clears enable for BGX(0..1)_SPU_MEM_INT[RX_BUF_SBE]. */
17240         uint64_t reserved_8_63         : 56;
17241 #endif /* Word 0 - End */
17242     } s;
17243     /* struct bdk_bgxx_spu_mem_int_ena_w1c_s cn81xx; */
17244     /* struct bdk_bgxx_spu_mem_int_ena_w1c_s cn88xx; */
17245     struct bdk_bgxx_spu_mem_int_ena_w1c_cn83xx
17246     {
17247 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17248         uint64_t reserved_8_63         : 56;
17249         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU_MEM_INT[RX_BUF_SBE]. */
17250         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU_MEM_INT[RX_BUF_DBE]. */
17251 #else /* Word 0 - Little Endian */
17252         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU_MEM_INT[RX_BUF_DBE]. */
17253         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1C/H) Reads or clears enable for BGX(0..3)_SPU_MEM_INT[RX_BUF_SBE]. */
17254         uint64_t reserved_8_63         : 56;
17255 #endif /* Word 0 - End */
17256     } cn83xx;
17257 };
17258 typedef union bdk_bgxx_spu_mem_int_ena_w1c bdk_bgxx_spu_mem_int_ena_w1c_t;
17259 
17260 static inline uint64_t BDK_BGXX_SPU_MEM_INT_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_SPU_MEM_INT_ENA_W1C(unsigned long a)17261 static inline uint64_t BDK_BGXX_SPU_MEM_INT_ENA_W1C(unsigned long a)
17262 {
17263     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
17264         return 0x87e0e0010320ll + 0x1000000ll * ((a) & 0x1);
17265     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
17266         return 0x87e0e0010320ll + 0x1000000ll * ((a) & 0x3);
17267     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
17268         return 0x87e0e0010320ll + 0x1000000ll * ((a) & 0x1);
17269     __bdk_csr_fatal("BGXX_SPU_MEM_INT_ENA_W1C", 1, a, 0, 0, 0);
17270 }
17271 
17272 #define typedef_BDK_BGXX_SPU_MEM_INT_ENA_W1C(a) bdk_bgxx_spu_mem_int_ena_w1c_t
17273 #define bustype_BDK_BGXX_SPU_MEM_INT_ENA_W1C(a) BDK_CSR_TYPE_RSL
17274 #define basename_BDK_BGXX_SPU_MEM_INT_ENA_W1C(a) "BGXX_SPU_MEM_INT_ENA_W1C"
17275 #define device_bar_BDK_BGXX_SPU_MEM_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
17276 #define busnum_BDK_BGXX_SPU_MEM_INT_ENA_W1C(a) (a)
17277 #define arguments_BDK_BGXX_SPU_MEM_INT_ENA_W1C(a) (a),-1,-1,-1
17278 
17279 /**
17280  * Register (RSL) bgx#_spu_mem_int_ena_w1s
17281  *
17282  * BGX SPU Memory Interrupt Enable Set Registers
17283  * This register sets interrupt enable bits.
17284  */
17285 union bdk_bgxx_spu_mem_int_ena_w1s
17286 {
17287     uint64_t u;
17288     struct bdk_bgxx_spu_mem_int_ena_w1s_s
17289     {
17290 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17291         uint64_t reserved_8_63         : 56;
17292         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU_MEM_INT[RX_BUF_SBE]. */
17293         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU_MEM_INT[RX_BUF_DBE]. */
17294 #else /* Word 0 - Little Endian */
17295         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU_MEM_INT[RX_BUF_DBE]. */
17296         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1S/H) Reads or sets enable for BGX(0..1)_SPU_MEM_INT[RX_BUF_SBE]. */
17297         uint64_t reserved_8_63         : 56;
17298 #endif /* Word 0 - End */
17299     } s;
17300     /* struct bdk_bgxx_spu_mem_int_ena_w1s_s cn81xx; */
17301     /* struct bdk_bgxx_spu_mem_int_ena_w1s_s cn88xx; */
17302     struct bdk_bgxx_spu_mem_int_ena_w1s_cn83xx
17303     {
17304 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17305         uint64_t reserved_8_63         : 56;
17306         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU_MEM_INT[RX_BUF_SBE]. */
17307         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU_MEM_INT[RX_BUF_DBE]. */
17308 #else /* Word 0 - Little Endian */
17309         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU_MEM_INT[RX_BUF_DBE]. */
17310         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1S/H) Reads or sets enable for BGX(0..3)_SPU_MEM_INT[RX_BUF_SBE]. */
17311         uint64_t reserved_8_63         : 56;
17312 #endif /* Word 0 - End */
17313     } cn83xx;
17314 };
17315 typedef union bdk_bgxx_spu_mem_int_ena_w1s bdk_bgxx_spu_mem_int_ena_w1s_t;
17316 
17317 static inline uint64_t BDK_BGXX_SPU_MEM_INT_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_SPU_MEM_INT_ENA_W1S(unsigned long a)17318 static inline uint64_t BDK_BGXX_SPU_MEM_INT_ENA_W1S(unsigned long a)
17319 {
17320     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
17321         return 0x87e0e0010328ll + 0x1000000ll * ((a) & 0x1);
17322     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
17323         return 0x87e0e0010328ll + 0x1000000ll * ((a) & 0x3);
17324     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
17325         return 0x87e0e0010328ll + 0x1000000ll * ((a) & 0x1);
17326     __bdk_csr_fatal("BGXX_SPU_MEM_INT_ENA_W1S", 1, a, 0, 0, 0);
17327 }
17328 
17329 #define typedef_BDK_BGXX_SPU_MEM_INT_ENA_W1S(a) bdk_bgxx_spu_mem_int_ena_w1s_t
17330 #define bustype_BDK_BGXX_SPU_MEM_INT_ENA_W1S(a) BDK_CSR_TYPE_RSL
17331 #define basename_BDK_BGXX_SPU_MEM_INT_ENA_W1S(a) "BGXX_SPU_MEM_INT_ENA_W1S"
17332 #define device_bar_BDK_BGXX_SPU_MEM_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
17333 #define busnum_BDK_BGXX_SPU_MEM_INT_ENA_W1S(a) (a)
17334 #define arguments_BDK_BGXX_SPU_MEM_INT_ENA_W1S(a) (a),-1,-1,-1
17335 
17336 /**
17337  * Register (RSL) bgx#_spu_mem_int_w1s
17338  *
17339  * BGX SPU Memory Interrupt Set Registers
17340  * This register sets interrupt bits.
17341  */
17342 union bdk_bgxx_spu_mem_int_w1s
17343 {
17344     uint64_t u;
17345     struct bdk_bgxx_spu_mem_int_w1s_s
17346     {
17347 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17348         uint64_t reserved_8_63         : 56;
17349         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1S/H) Reads or sets BGX(0..1)_SPU_MEM_INT[RX_BUF_SBE]. */
17350         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1S/H) Reads or sets BGX(0..1)_SPU_MEM_INT[RX_BUF_DBE]. */
17351 #else /* Word 0 - Little Endian */
17352         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1S/H) Reads or sets BGX(0..1)_SPU_MEM_INT[RX_BUF_DBE]. */
17353         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1S/H) Reads or sets BGX(0..1)_SPU_MEM_INT[RX_BUF_SBE]. */
17354         uint64_t reserved_8_63         : 56;
17355 #endif /* Word 0 - End */
17356     } s;
17357     /* struct bdk_bgxx_spu_mem_int_w1s_s cn81xx; */
17358     /* struct bdk_bgxx_spu_mem_int_w1s_s cn88xx; */
17359     struct bdk_bgxx_spu_mem_int_w1s_cn83xx
17360     {
17361 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17362         uint64_t reserved_8_63         : 56;
17363         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1S/H) Reads or sets BGX(0..3)_SPU_MEM_INT[RX_BUF_SBE]. */
17364         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1S/H) Reads or sets BGX(0..3)_SPU_MEM_INT[RX_BUF_DBE]. */
17365 #else /* Word 0 - Little Endian */
17366         uint64_t rx_buf_dbe            : 4;  /**< [  3:  0](R/W1S/H) Reads or sets BGX(0..3)_SPU_MEM_INT[RX_BUF_DBE]. */
17367         uint64_t rx_buf_sbe            : 4;  /**< [  7:  4](R/W1S/H) Reads or sets BGX(0..3)_SPU_MEM_INT[RX_BUF_SBE]. */
17368         uint64_t reserved_8_63         : 56;
17369 #endif /* Word 0 - End */
17370     } cn83xx;
17371 };
17372 typedef union bdk_bgxx_spu_mem_int_w1s bdk_bgxx_spu_mem_int_w1s_t;
17373 
17374 static inline uint64_t BDK_BGXX_SPU_MEM_INT_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_SPU_MEM_INT_W1S(unsigned long a)17375 static inline uint64_t BDK_BGXX_SPU_MEM_INT_W1S(unsigned long a)
17376 {
17377     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
17378         return 0x87e0e0010318ll + 0x1000000ll * ((a) & 0x1);
17379     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
17380         return 0x87e0e0010318ll + 0x1000000ll * ((a) & 0x3);
17381     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
17382         return 0x87e0e0010318ll + 0x1000000ll * ((a) & 0x1);
17383     __bdk_csr_fatal("BGXX_SPU_MEM_INT_W1S", 1, a, 0, 0, 0);
17384 }
17385 
17386 #define typedef_BDK_BGXX_SPU_MEM_INT_W1S(a) bdk_bgxx_spu_mem_int_w1s_t
17387 #define bustype_BDK_BGXX_SPU_MEM_INT_W1S(a) BDK_CSR_TYPE_RSL
17388 #define basename_BDK_BGXX_SPU_MEM_INT_W1S(a) "BGXX_SPU_MEM_INT_W1S"
17389 #define device_bar_BDK_BGXX_SPU_MEM_INT_W1S(a) 0x0 /* PF_BAR0 */
17390 #define busnum_BDK_BGXX_SPU_MEM_INT_W1S(a) (a)
17391 #define arguments_BDK_BGXX_SPU_MEM_INT_W1S(a) (a),-1,-1,-1
17392 
17393 /**
17394  * Register (RSL) bgx#_spu_mem_status
17395  *
17396  * BGX SPU Memory Status Registers
17397  * This register provides memory ECC status from the SPU receive buffer lane FIFOs.
17398  */
17399 union bdk_bgxx_spu_mem_status
17400 {
17401     uint64_t u;
17402     struct bdk_bgxx_spu_mem_status_s
17403     {
17404 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17405         uint64_t reserved_32_63        : 32;
17406         uint64_t rx_buf_ecc_synd       : 32; /**< [ 31:  0](RO/H) SPU receive buffer ECC syndromes for lanes 3-0. 8-bit syndrome sub-field per SerDes lane.
17407                                                                  Each
17408                                                                  8-bit sub-field contains the syndrome of the latest single-bit or double-bit ECC error
17409                                                                  detected by the associated receive buffer lane FIFO, i.e. it is loaded when the
17410                                                                  corresponding
17411                                                                  BGX()_SPU_MEM_INT[RX_BUF_SBE] or BGX()_SPU_MEM_INT[RX_BUF_DBE] bit is set. */
17412 #else /* Word 0 - Little Endian */
17413         uint64_t rx_buf_ecc_synd       : 32; /**< [ 31:  0](RO/H) SPU receive buffer ECC syndromes for lanes 3-0. 8-bit syndrome sub-field per SerDes lane.
17414                                                                  Each
17415                                                                  8-bit sub-field contains the syndrome of the latest single-bit or double-bit ECC error
17416                                                                  detected by the associated receive buffer lane FIFO, i.e. it is loaded when the
17417                                                                  corresponding
17418                                                                  BGX()_SPU_MEM_INT[RX_BUF_SBE] or BGX()_SPU_MEM_INT[RX_BUF_DBE] bit is set. */
17419         uint64_t reserved_32_63        : 32;
17420 #endif /* Word 0 - End */
17421     } s;
17422     /* struct bdk_bgxx_spu_mem_status_s cn; */
17423 };
17424 typedef union bdk_bgxx_spu_mem_status bdk_bgxx_spu_mem_status_t;
17425 
17426 static inline uint64_t BDK_BGXX_SPU_MEM_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_BGXX_SPU_MEM_STATUS(unsigned long a)17427 static inline uint64_t BDK_BGXX_SPU_MEM_STATUS(unsigned long a)
17428 {
17429     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
17430         return 0x87e0e0010308ll + 0x1000000ll * ((a) & 0x1);
17431     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
17432         return 0x87e0e0010308ll + 0x1000000ll * ((a) & 0x3);
17433     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=1))
17434         return 0x87e0e0010308ll + 0x1000000ll * ((a) & 0x1);
17435     __bdk_csr_fatal("BGXX_SPU_MEM_STATUS", 1, a, 0, 0, 0);
17436 }
17437 
17438 #define typedef_BDK_BGXX_SPU_MEM_STATUS(a) bdk_bgxx_spu_mem_status_t
17439 #define bustype_BDK_BGXX_SPU_MEM_STATUS(a) BDK_CSR_TYPE_RSL
17440 #define basename_BDK_BGXX_SPU_MEM_STATUS(a) "BGXX_SPU_MEM_STATUS"
17441 #define device_bar_BDK_BGXX_SPU_MEM_STATUS(a) 0x0 /* PF_BAR0 */
17442 #define busnum_BDK_BGXX_SPU_MEM_STATUS(a) (a)
17443 #define arguments_BDK_BGXX_SPU_MEM_STATUS(a) (a),-1,-1,-1
17444 
17445 /**
17446  * Register (RSL) bgx#_spu_sds#_skew_status
17447  *
17448  * BGX SPU SerDes Lane Skew Status Registers
17449  * This register provides SerDes lane skew status. One register per physical SerDes lane.
17450  */
17451 union bdk_bgxx_spu_sdsx_skew_status
17452 {
17453     uint64_t u;
17454     struct bdk_bgxx_spu_sdsx_skew_status_s
17455     {
17456 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17457         uint64_t reserved_32_63        : 32;
17458         uint64_t skew_status           : 32; /**< [ 31:  0](RO/H) Format defined by BGX_SPU_SDS_SKEW_STATUS_S. */
17459 #else /* Word 0 - Little Endian */
17460         uint64_t skew_status           : 32; /**< [ 31:  0](RO/H) Format defined by BGX_SPU_SDS_SKEW_STATUS_S. */
17461         uint64_t reserved_32_63        : 32;
17462 #endif /* Word 0 - End */
17463     } s;
17464     /* struct bdk_bgxx_spu_sdsx_skew_status_s cn; */
17465 };
17466 typedef union bdk_bgxx_spu_sdsx_skew_status bdk_bgxx_spu_sdsx_skew_status_t;
17467 
17468 static inline uint64_t BDK_BGXX_SPU_SDSX_SKEW_STATUS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPU_SDSX_SKEW_STATUS(unsigned long a,unsigned long b)17469 static inline uint64_t BDK_BGXX_SPU_SDSX_SKEW_STATUS(unsigned long a, unsigned long b)
17470 {
17471     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
17472         return 0x87e0e0010340ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x3);
17473     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
17474         return 0x87e0e0010340ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x3);
17475     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
17476         return 0x87e0e0010340ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x3);
17477     __bdk_csr_fatal("BGXX_SPU_SDSX_SKEW_STATUS", 2, a, b, 0, 0);
17478 }
17479 
17480 #define typedef_BDK_BGXX_SPU_SDSX_SKEW_STATUS(a,b) bdk_bgxx_spu_sdsx_skew_status_t
17481 #define bustype_BDK_BGXX_SPU_SDSX_SKEW_STATUS(a,b) BDK_CSR_TYPE_RSL
17482 #define basename_BDK_BGXX_SPU_SDSX_SKEW_STATUS(a,b) "BGXX_SPU_SDSX_SKEW_STATUS"
17483 #define device_bar_BDK_BGXX_SPU_SDSX_SKEW_STATUS(a,b) 0x0 /* PF_BAR0 */
17484 #define busnum_BDK_BGXX_SPU_SDSX_SKEW_STATUS(a,b) (a)
17485 #define arguments_BDK_BGXX_SPU_SDSX_SKEW_STATUS(a,b) (a),(b),-1,-1
17486 
17487 /**
17488  * Register (RSL) bgx#_spu_sds#_states
17489  *
17490  * BGX SPU SerDes States Registers
17491  * This register provides SerDes lane states. One register per physical SerDes lane.
17492  */
17493 union bdk_bgxx_spu_sdsx_states
17494 {
17495     uint64_t u;
17496     struct bdk_bgxx_spu_sdsx_states_s
17497     {
17498 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17499         uint64_t reserved_52_63        : 12;
17500         uint64_t am_lock_invld_cnt     : 2;  /**< [ 51: 50](RO/H) 40GBASE-R alignment marker lock state machine invalid AM counter. */
17501         uint64_t am_lock_sm            : 2;  /**< [ 49: 48](RO/H) 40GBASE-R alignment marker lock state machine state. */
17502         uint64_t reserved_45_47        : 3;
17503         uint64_t train_sm              : 3;  /**< [ 44: 42](RO/H) Link training state machine state. */
17504         uint64_t train_code_viol       : 1;  /**< [ 41: 41](RO/H) Link training code violation in received control channel. */
17505         uint64_t train_frame_lock      : 1;  /**< [ 40: 40](RO/H) Link training frame lock status. */
17506         uint64_t train_lock_found_1st_marker : 1;/**< [ 39: 39](RO/H) Link training lock state machine found first marker flag. */
17507         uint64_t train_lock_bad_markers : 3; /**< [ 38: 36](RO/H) Link training lock state machine bad markers counter. */
17508         uint64_t reserved_35           : 1;
17509         uint64_t an_arb_sm             : 3;  /**< [ 34: 32](RO/H) Autonegotiation arbitration state machine state. */
17510         uint64_t an_rx_sm              : 2;  /**< [ 31: 30](RO/H) Autonegotiation receive state machine state. */
17511         uint64_t reserved_29           : 1;
17512         uint64_t fec_block_sync        : 1;  /**< [ 28: 28](RO/H) FEC block sync status. */
17513         uint64_t fec_sync_cnt          : 4;  /**< [ 27: 24](RO/H) FEC block sync state machine good/bad parity block counter. */
17514         uint64_t reserved_23           : 1;
17515         uint64_t br_sh_invld_cnt       : 7;  /**< [ 22: 16](RO/H) BASE-R lock state machine invalid sync header counter. */
17516         uint64_t br_block_lock         : 1;  /**< [ 15: 15](RO/H) BASE-R block lock status. */
17517         uint64_t br_sh_cnt             : 11; /**< [ 14:  4](RO/H) BASE-R lock state machine sync header counter */
17518         uint64_t bx_sync_sm            : 4;  /**< [  3:  0](RO/H) BASE-X PCS synchronization state machine state */
17519 #else /* Word 0 - Little Endian */
17520         uint64_t bx_sync_sm            : 4;  /**< [  3:  0](RO/H) BASE-X PCS synchronization state machine state */
17521         uint64_t br_sh_cnt             : 11; /**< [ 14:  4](RO/H) BASE-R lock state machine sync header counter */
17522         uint64_t br_block_lock         : 1;  /**< [ 15: 15](RO/H) BASE-R block lock status. */
17523         uint64_t br_sh_invld_cnt       : 7;  /**< [ 22: 16](RO/H) BASE-R lock state machine invalid sync header counter. */
17524         uint64_t reserved_23           : 1;
17525         uint64_t fec_sync_cnt          : 4;  /**< [ 27: 24](RO/H) FEC block sync state machine good/bad parity block counter. */
17526         uint64_t fec_block_sync        : 1;  /**< [ 28: 28](RO/H) FEC block sync status. */
17527         uint64_t reserved_29           : 1;
17528         uint64_t an_rx_sm              : 2;  /**< [ 31: 30](RO/H) Autonegotiation receive state machine state. */
17529         uint64_t an_arb_sm             : 3;  /**< [ 34: 32](RO/H) Autonegotiation arbitration state machine state. */
17530         uint64_t reserved_35           : 1;
17531         uint64_t train_lock_bad_markers : 3; /**< [ 38: 36](RO/H) Link training lock state machine bad markers counter. */
17532         uint64_t train_lock_found_1st_marker : 1;/**< [ 39: 39](RO/H) Link training lock state machine found first marker flag. */
17533         uint64_t train_frame_lock      : 1;  /**< [ 40: 40](RO/H) Link training frame lock status. */
17534         uint64_t train_code_viol       : 1;  /**< [ 41: 41](RO/H) Link training code violation in received control channel. */
17535         uint64_t train_sm              : 3;  /**< [ 44: 42](RO/H) Link training state machine state. */
17536         uint64_t reserved_45_47        : 3;
17537         uint64_t am_lock_sm            : 2;  /**< [ 49: 48](RO/H) 40GBASE-R alignment marker lock state machine state. */
17538         uint64_t am_lock_invld_cnt     : 2;  /**< [ 51: 50](RO/H) 40GBASE-R alignment marker lock state machine invalid AM counter. */
17539         uint64_t reserved_52_63        : 12;
17540 #endif /* Word 0 - End */
17541     } s;
17542     /* struct bdk_bgxx_spu_sdsx_states_s cn; */
17543 };
17544 typedef union bdk_bgxx_spu_sdsx_states bdk_bgxx_spu_sdsx_states_t;
17545 
17546 static inline uint64_t BDK_BGXX_SPU_SDSX_STATES(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_BGXX_SPU_SDSX_STATES(unsigned long a,unsigned long b)17547 static inline uint64_t BDK_BGXX_SPU_SDSX_STATES(unsigned long a, unsigned long b)
17548 {
17549     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=1) && (b<=3)))
17550         return 0x87e0e0010360ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x3);
17551     if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b<=3)))
17552         return 0x87e0e0010360ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x3);
17553     if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=1) && (b<=3)))
17554         return 0x87e0e0010360ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x3);
17555     __bdk_csr_fatal("BGXX_SPU_SDSX_STATES", 2, a, b, 0, 0);
17556 }
17557 
17558 #define typedef_BDK_BGXX_SPU_SDSX_STATES(a,b) bdk_bgxx_spu_sdsx_states_t
17559 #define bustype_BDK_BGXX_SPU_SDSX_STATES(a,b) BDK_CSR_TYPE_RSL
17560 #define basename_BDK_BGXX_SPU_SDSX_STATES(a,b) "BGXX_SPU_SDSX_STATES"
17561 #define device_bar_BDK_BGXX_SPU_SDSX_STATES(a,b) 0x0 /* PF_BAR0 */
17562 #define busnum_BDK_BGXX_SPU_SDSX_STATES(a,b) (a)
17563 #define arguments_BDK_BGXX_SPU_SDSX_STATES(a,b) (a),(b),-1,-1
17564 
17565 #endif /* __BDK_CSRS_BGX_H__ */
17566