1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <stdlib.h>
18 #include "flash.h"
19 #include "programmer.h"
20 #include "hwaccess_x86_io.h"
21 #include "platform/pci.h"
22
23 #define BIOS_ROM_ADDR 0x04
24 #define BIOS_ROM_DATA 0x08
25 #define INT_STATUS 0x0e
26 #define INTERNAL_CONFIG 0x00
27 #define SELECT_REG_WINDOW 0x800
28
29 #define PCI_VENDOR_ID_3COM 0x10b7
30
31 struct nic3com_data {
32 uint32_t io_base_addr;
33 uint32_t internal_conf;
34 uint16_t id;
35 };
36
37 static const struct dev_entry nics_3com[] = {
38 /* 3C90xB */
39 {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
40 {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
41 {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
42 {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
43 {0x10b7, 0x9006, OK, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
44 {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
45 {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
46 {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
47
48 /* 3C905C */
49 {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
50
51 /* 3C980C */
52 {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
53
54 {0},
55 };
56
nic3com_chip_writeb(const struct flashctx * flash,uint8_t val,chipaddr addr)57 static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
58 chipaddr addr)
59 {
60 struct nic3com_data *data = flash->mst->par.data;
61
62 OUTL((uint32_t)addr, data->io_base_addr + BIOS_ROM_ADDR);
63 OUTB(val, data->io_base_addr + BIOS_ROM_DATA);
64 }
65
nic3com_chip_readb(const struct flashctx * flash,const chipaddr addr)66 static uint8_t nic3com_chip_readb(const struct flashctx *flash,
67 const chipaddr addr)
68 {
69 struct nic3com_data *data = flash->mst->par.data;
70
71 OUTL((uint32_t)addr, data->io_base_addr + BIOS_ROM_ADDR);
72 return INB(data->io_base_addr + BIOS_ROM_DATA);
73 }
74
nic3com_shutdown(void * par_data)75 static int nic3com_shutdown(void *par_data)
76 {
77 struct nic3com_data *data = par_data;
78 const uint16_t id = data->id;
79
80 /* 3COM 3C90xB cards need a special fixup. */
81 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
82 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
83 /* Select register window 3 and restore the receiver status. */
84 OUTW(SELECT_REG_WINDOW + 3, data->io_base_addr + INT_STATUS);
85 OUTL(data->internal_conf, data->io_base_addr + INTERNAL_CONFIG);
86 }
87
88 free(data);
89 return 0;
90 }
91
92 static const struct par_master par_master_nic3com = {
93 .chip_readb = nic3com_chip_readb,
94 .chip_writeb = nic3com_chip_writeb,
95 .shutdown = nic3com_shutdown,
96 };
97
nic3com_init(const struct programmer_cfg * cfg)98 static int nic3com_init(const struct programmer_cfg *cfg)
99 {
100 struct pci_dev *dev = NULL;
101 uint32_t io_base_addr = 0;
102 uint32_t internal_conf = 0;
103 uint16_t id;
104
105 if (rget_io_perms())
106 return 1;
107
108 dev = pcidev_init(cfg, nics_3com, PCI_BASE_ADDRESS_0);
109 if (!dev)
110 return 1;
111
112 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
113 if (!io_base_addr)
114 return 1;
115
116 id = dev->device_id;
117
118 /* 3COM 3C90xB cards need a special fixup. */
119 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
120 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
121 /* Select register window 3 and save the receiver status. */
122 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
123 internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
124
125 /* Set receiver type to MII for full BIOS ROM access. */
126 OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
127 }
128
129 /*
130 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
131 * cards form a 'register window' into one of multiple (usually 8)
132 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
133 */
134 OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
135
136 struct nic3com_data *data = calloc(1, sizeof(*data));
137 if (!data) {
138 msg_perr("Unable to allocate space for PAR master data\n");
139 goto init_err_cleanup_exit;
140 }
141 data->io_base_addr = io_base_addr;
142 data->internal_conf = internal_conf;
143 data->id = id;
144
145 max_rom_decode.parallel = 128 * 1024;
146
147 return register_par_master(&par_master_nic3com, BUS_PARALLEL, data);
148
149 init_err_cleanup_exit:
150 /* 3COM 3C90xB cards need a special fixup. */
151 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
152 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
153 /* Select register window 3 and restore the receiver status. */
154 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
155 OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
156 }
157 return 1;
158 }
159
160 const struct programmer_entry programmer_nic3com = {
161 .name = "nic3com",
162 .type = PCI,
163 .devs.dev = nics_3com,
164 .init = nic3com_init,
165 };
166