1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Mark Marshall
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <stdlib.h>
17 #include <strings.h>
18 #include <string.h>
19 #include "flash.h"
20 #include "programmer.h"
21 #include "hwaccess_physmap.h"
22 #include "platform/pci.h"
23
24 #define PCI_VENDOR_ID_OGP 0x1227
25
26 /* These are the register addresses for the OGD1 / OGA1. If they are
27 * different for later versions of the hardware then we will need
28 * logic to select between the different hardware versions. */
29 #define OGA1_XP10_BPROM_SI 0x0040 /* W */
30 #define OGA1_XP10_BPROM_SO 0x0040 /* R */
31 #define OGA1_XP10_BPROM_CE_BAR 0x0044 /* W */
32 #define OGA1_XP10_BPROM_SCK 0x0048 /* W */
33 #define OGA1_XP10_BPROM_REG_SEL 0x004C /* W */
34 #define OGA1_XP10_CPROM_SI 0x0050 /* W */
35 #define OGA1_XP10_CPROM_SO 0x0050 /* R */
36 #define OGA1_XP10_CPROM_CE_BAR 0x0054 /* W */
37 #define OGA1_XP10_CPROM_SCK 0x0058 /* W */
38 #define OGA1_XP10_CPROM_REG_SEL 0x005C /* W */
39
40 struct ogp_spi_data {
41 uint8_t *spibar;
42
43 uint32_t reg_sel;
44 uint32_t reg_siso;
45 uint32_t reg__ce;
46 uint32_t reg_sck;
47 };
48
49 static const struct dev_entry ogp_spi[] = {
50 {PCI_VENDOR_ID_OGP, 0x0000, OK, "Open Graphics Project", "Development Board OGD1"},
51
52 {0},
53 };
54
ogp_request_spibus(void * spi_data)55 static void ogp_request_spibus(void *spi_data)
56 {
57 struct ogp_spi_data *data = spi_data;
58 pci_mmio_writel(1, data->spibar + data->reg_sel);
59 }
60
ogp_release_spibus(void * spi_data)61 static void ogp_release_spibus(void *spi_data)
62 {
63 struct ogp_spi_data *data = spi_data;
64 pci_mmio_writel(0, data->spibar + data->reg_sel);
65 }
66
ogp_bitbang_set_cs(int val,void * spi_data)67 static void ogp_bitbang_set_cs(int val, void *spi_data)
68 {
69 struct ogp_spi_data *data = spi_data;
70 pci_mmio_writel(val, data->spibar + data->reg__ce);
71 }
72
ogp_bitbang_set_sck(int val,void * spi_data)73 static void ogp_bitbang_set_sck(int val, void *spi_data)
74 {
75 struct ogp_spi_data *data = spi_data;
76 pci_mmio_writel(val, data->spibar + data->reg_sck);
77 }
78
ogp_bitbang_set_mosi(int val,void * spi_data)79 static void ogp_bitbang_set_mosi(int val, void *spi_data)
80 {
81 struct ogp_spi_data *data = spi_data;
82 pci_mmio_writel(val, data->spibar + data->reg_siso);
83 }
84
ogp_bitbang_get_miso(void * spi_data)85 static int ogp_bitbang_get_miso(void *spi_data)
86 {
87 struct ogp_spi_data *data = spi_data;
88 uint32_t tmp;
89
90 tmp = pci_mmio_readl(data->spibar + data->reg_siso);
91 return tmp & 0x1;
92 }
93
94 static const struct bitbang_spi_master bitbang_spi_master_ogp = {
95 .set_cs = ogp_bitbang_set_cs,
96 .set_sck = ogp_bitbang_set_sck,
97 .set_mosi = ogp_bitbang_set_mosi,
98 .get_miso = ogp_bitbang_get_miso,
99 .request_bus = ogp_request_spibus,
100 .release_bus = ogp_release_spibus,
101 .half_period = 0,
102 };
103
ogp_spi_shutdown(void * data)104 static int ogp_spi_shutdown(void *data)
105 {
106 free(data);
107 return 0;
108 }
109
ogp_spi_init(const struct programmer_cfg * cfg)110 static int ogp_spi_init(const struct programmer_cfg *cfg)
111 {
112 struct pci_dev *dev = NULL;
113 char *type;
114 uint8_t *ogp_spibar;
115 uint32_t ogp_reg_sel;
116 uint32_t ogp_reg_siso;
117 uint32_t ogp_reg__ce;
118 uint32_t ogp_reg_sck;
119
120 type = extract_programmer_param_str(cfg, "rom");
121
122 if (!type) {
123 msg_perr("Please use flashrom -p ogp_spi:rom=... to specify "
124 "which flashchip you want to access.\n");
125 return 1;
126 } else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) {
127 ogp_reg_sel = OGA1_XP10_BPROM_REG_SEL;
128 ogp_reg_siso = OGA1_XP10_BPROM_SI;
129 ogp_reg__ce = OGA1_XP10_BPROM_CE_BAR;
130 ogp_reg_sck = OGA1_XP10_BPROM_SCK;
131 } else if (!strcasecmp(type, "cprom") || !strcasecmp(type, "s3")) {
132 ogp_reg_sel = OGA1_XP10_CPROM_REG_SEL;
133 ogp_reg_siso = OGA1_XP10_CPROM_SI;
134 ogp_reg__ce = OGA1_XP10_CPROM_CE_BAR;
135 ogp_reg_sck = OGA1_XP10_CPROM_SCK;
136 } else {
137 msg_perr("Invalid or missing rom= parameter.\n");
138 free(type);
139 return 1;
140 }
141 free(type);
142
143 dev = pcidev_init(cfg, ogp_spi, PCI_BASE_ADDRESS_0);
144 if (!dev)
145 return 1;
146
147 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
148 if (!io_base_addr)
149 return 1;
150
151 ogp_spibar = rphysmap("OGP registers", io_base_addr, 4096);
152 if (ogp_spibar == ERROR_PTR)
153 return 1;
154
155 struct ogp_spi_data *data = calloc(1, sizeof(*data));
156 if (!data) {
157 msg_perr("Unable to allocate space for SPI master data\n");
158 return 1;
159 }
160 data->spibar = ogp_spibar;
161 data->reg_sel = ogp_reg_sel;
162 data->reg_siso = ogp_reg_siso;
163 data->reg__ce = ogp_reg__ce;
164 data->reg_sck = ogp_reg_sck;
165 if (register_shutdown(ogp_spi_shutdown, data)) {
166 free(data);
167 return 1;
168 }
169
170 if (register_spi_bitbang_master(&bitbang_spi_master_ogp, data))
171 return 1;
172
173 return 0;
174 }
175
176 const struct programmer_entry programmer_ogp_spi = {
177 .name = "ogp_spi",
178 .type = PCI,
179 .devs.dev = ogp_spi,
180 .init = ogp_spi_init,
181 };
182