1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ 4 #define __SOC_NVIDIA_TEGRA124_CHIP_H__ 5 6 #include <gpio.h> 7 #include <soc/addressmap.h> 8 9 #define EFAULT 1 10 #define EINVAL 2 11 12 /* this is a misuse of the device tree. We're going to let it go for now but 13 * we should at minimum have a struct for the display controller, since 14 * the chip supports two. 15 */ 16 struct soc_nvidia_tegra124_config { 17 u32 xres; 18 u32 yres; 19 u32 framebuffer_bits_per_pixel; 20 u32 color_depth; 21 u32 panel_bits_per_pixel; 22 /* there are two. It's not unimaginable that we might someday 23 * have two of these structs in a single mainboard. 24 */ 25 u32 display_controller; 26 u32 framebuffer_base; 27 /* Technically, we can compute this. At the same time, some platforms 28 * might want to specify a specific size for their own reasons. If it is 29 * zero the soc code will compute it as xres*yres*framebuffer_bits_per_pixel/4 30 */ 31 u32 framebuffer_size; 32 /* GPIOs -- all, some, or none are used. Unused ones can be ignored 33 * in devicetree.cb since if they are not set there they default to 0, 34 * and 0 for a gpio means 'unused GPIO'. 35 */ 36 gpio_t backlight_en_gpio; 37 gpio_t lvds_shutdown_gpio; 38 gpio_t backlight_vdd_gpio; 39 gpio_t panel_vdd_gpio; 40 41 /* required info. */ 42 /* pwm to use to set display contrast */ 43 int pwm; 44 /* timings -- five numbers, all relative to the previous 45 * event, not to absolute time. e.g., vdd_data_delay is the 46 * delay from vdd on to data, not from power on to data. 47 * This is stated to be four timings in the 48 * u-boot docs. In any event, in coreboot, we generally 49 * only delay long enough to let the panel wake up and then 50 * do the control operations -- meaning, for *coreboot* 51 * we probably only need the vdd_delay, but payloads may 52 * need the other info. 53 */ 54 /* Delay before from power on asserting vdd */ 55 int vdd_delay_ms; 56 57 /* Delay between pwm and backlight_en_gpio is asserted */ 58 int pwm_to_bl_delay_ms; 59 60 /* Delay before HPD high */ 61 int vdd_to_hpd_delay_ms; 62 63 int hpd_unplug_min_us; 64 int hpd_plug_min_us; 65 int hpd_irq_min_us; 66 67 int href_to_sync; 68 int hsync_width; 69 int hback_porch; 70 int hfront_porch; 71 int vref_to_sync; 72 int vsync_width; 73 int vback_porch; 74 int vfront_porch; 75 76 int pixel_clock; 77 78 /* The minimum link configuration settings */ 79 u32 lane_count; 80 u32 enhanced_framing; 81 u32 link_bw; 82 u32 drive_current; 83 u32 preemphasis; 84 u32 postcursor; 85 86 void *dc_data; 87 }; 88 89 #endif /* __SOC_NVIDIA_TEGRA124_CHIP_H__ */ 90