1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DRAMC_REGISTER_H_ 4 #define _DRAMC_REGISTER_H_ 5 6 #include <types.h> 7 8 #define DRIVING_DS2_0 7 /* DS[2:0] 7->6 */ 9 #define DEFAULT_DRIVING 0x99009900 10 11 enum { 12 /* CONF2 = 0x008 */ 13 CONF2_TEST1_EN = BIT(29), 14 CONF2_TEST2R_EN = BIT(30), 15 CONF2_TEST2W_EN = BIT(31), 16 /* PADCTL1 = 0x00c */ 17 PADCTL1_CLK_SHIFT = 24, 18 PADCTL1_CS1_SHIFT = 28, 19 /* PADCTL2 = 0x010 */ 20 MASK_PADCTL2_16BIT = 0x000000ff, 21 MASK_PADCTL2_32BIT = 0x0000ffff, 22 MASK_PADCTL2 = 0xffff0000, 23 PADCTL2_SHIFT = 0, 24 /* TEST2_3 = 0x044 */ 25 TEST2_3_TESTCNT_SHIFT = 0, 26 TEST2_3_TESTCNT_MASK = (0xful << TEST2_3_TESTCNT_SHIFT), 27 TEST2_3_TESTAUDPAT_EN = BIT(7), 28 TEST2_3_ADVREFEN_EN = BIT(30), 29 /* TEST2_4 = 0x048 */ 30 TEST2_4_TESTAUDINC_SHIFT = 0, 31 TEST2_4_TESTAUDINC_MASK = (0x1ful << TEST2_4_TESTAUDINC_SHIFT), 32 TEST2_4_TESTAUDINIT_SHIFT = 8, 33 TEST2_4_TESTAUDINIT_MASK = (0x1ful << TEST2_4_TESTAUDINIT_SHIFT), 34 TEST2_4_TESTAUDBITINV_EN = BIT(14), 35 TEST2_4_TESTAUDMODE_EN = BIT(15), 36 TEST2_4_TESTXTALKPAT_EN = BIT(16), 37 /* DDR2CTL = 0x07c */ 38 DDR2CTL_WOEN_SHIFT = 3, 39 DDR2CTL_DATLAT_SHIFT = 4, 40 /* MISC = 0x80 */ 41 MISC_LATNORMP_SHIFT = 0, 42 MISC_DATLAT_DSEL_SHIFT = 8, 43 /* MRS = 0x088 */ 44 MASK_MR2_OP = 0x00800000, 45 /* R0 R1 DQSIEN = 0x094 */ 46 DQSIEN_DQS0IEN_SHIFT = 0, 47 DQSIEN_DQS1IEN_SHIFT = 8, 48 DQSIEN_DQS2IEN_SHIFT = 16, 49 DQSIEN_DQS3IEN_SHIFT = 24, 50 /* MCKDLY = 0x0d8 */ 51 MCKDLY_DQIENLAT_SHIFT = 4, 52 MCKDLY_DQIENQKEND_SHIFT = 10, 53 MCKDLY_FIXDQIEN_SHIFT = 12, 54 MCKDLY_FIXODT_SHIFT = 23, 55 /* DQSCTL1 = 0x0e0 */ 56 DQSCTL1_DQSINCTL_SHIFT = 24, 57 DQSCTL1_DQSIENMODE_SHIFT = 28, 58 /* PADCTL4 = 0x0e4 */ 59 PADCTL4_CKEFIXON_SHIFT = 2, 60 PADCTL4_DATLAT3_SHIFT = 4, 61 /* PHYCTL1 = 0x0f0 */ 62 PHYCTL1_DATLAT4_SHIFT = 25, 63 PHYCTL1_PHYRST_SHIFT = 28, 64 /* GDDR3CTL1 = 0x0f4 */ 65 GDDR3CTL1_BKSWAP_SHIFT = 20, 66 GDDR3CTL1_RDATRST_SHIFT = 25, 67 GDDR3CTL1_DQMSWAP_SHIFT = 31, 68 /* RKCFG = 0x110 */ 69 MASK_RKCFG_RKSWAP_EN = 0x08, 70 RKCFG_PBREF_DISBYRATE_SHIFT = 6, 71 RKCFG_WDATKEY64_SHIFT = 29, 72 /* DQSCTL2 = 0x118 */ 73 DQSCTL2_DQSINCTL_SHIFT = 0, 74 /* DQSGCTL = 0x124 */ 75 DQSGCTL_DQSGDUALP_SHIFT = 30, 76 /* PHYCLKDUTY = 0x148 */ 77 PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT = 16, 78 PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT = 18, 79 PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT = 28, 80 /* CMDDLY0 = 0x1a8 */ 81 CMDDLY0_RA0_SHIFT = 0, 82 CMDDLY0_RA1_SHIFT = 8, 83 CMDDLY0_RA2_SHIFT = 16, 84 CMDDLY0_RA3_SHIFT = 24, 85 /* CMDDLY1 = 0x1ac */ 86 CMDDLY1_RA7_SHIFT = 24, 87 /* CMDDLY3 = 0x1b4 */ 88 CMDDLY3_BA0_SHIFT = 8, 89 CMDDLY3_BA1_SHIFT = 16, 90 CMDDLY3_BA2_SHIFT = 24, 91 /* CMDDLY4 = 0x1b8 */ 92 CMDDLY4_CS_SHIFT = 0, 93 CMDDLY4_CKE_SHIFT = 8, 94 CMDDLY4_RAS_SHIFT = 16, 95 CMDDLY4_CAS_SHIFT = 24, 96 /* CMDDLY5 = 0x1bc */ 97 CMDDLY5_WE_SHIFT = 8, 98 CMDDLY5_RA13_SHIFT = 16, 99 /* DQSCAL0 = 0x1c0 */ 100 DQSCAL0_RA14_SHIFT = 24, 101 DQSCAL0_STBCALEN_SHIFT = 31, 102 /* DQSCAL1 = 0x1c4 */ 103 DQSCAL1_CKE1_SHIFT = 24, 104 /* IMPCAL = 0x1c8 */ 105 IMP_CALI_EN_SHIFT = 0, 106 IMP_CALI_HW_SHIFT = 1, 107 IMP_CALI_ENN_SHIFT = 4, 108 IMP_CALI_ENP_SHIFT = 5, 109 IMP_CALI_PDN_SHIFT = 6, 110 IMP_CALI_PDP_SHIFT = 7, 111 IMP_CALI_DRVP_SHIFT = 8, 112 IMP_CALI_DRVN_SHIFT = 12, 113 /* JMETER for PLL2, PLL3, PLL4 */ 114 JMETER_EN_BIT= BIT(0), 115 JMETER_COUNTER_SHIFT = 16, 116 JMETER_COUNTER_MASK = (0xffff << JMETER_COUNTER_SHIFT), 117 /* SPCMD = 0x1e4 */ 118 SPCMD_MRWEN_SHIFT = 0, 119 SPCMD_DQSGCNTEN_SHIFT = 8, 120 SPCMD_DQSGCNTRST_SHIFT = 9, 121 /* JMETER for PLL2/3/4 ST */ 122 JMETER_PLL_ZERO_SHIFT = 0, 123 JMETER_PLL_ONE_SHIFT = 16, 124 /* TESTRPT = 0x3fc */ 125 TESTRPT_DM_CMP_CPT_SHIFT = 10, 126 TESTRPT_DM_CMP_ERR_SHIFT = 14, 127 /* SELPH2 = 0x404 */ 128 SELPH2_TXDLY_DQSGATE_SHIFT = 12, 129 SELPH2_TXDLY_DQSGATE_P1_SHIFT = 20, 130 /* SELPH5 = 0x410 */ 131 SELPH5_DLY_DQSGATE_SHIFT = 22, 132 SELPH5_DLY_DQSGATE_P1_SHIFT = 24, 133 /* SELPH6_1 = 0x418 */ 134 SELPH6_1_DLY_R1DQSGATE_SHIFT = 0, 135 SELPH6_1_DLY_R1DQSGATE_P1_SHIFT = 2, 136 SELPH6_1_TXDLY_R1DQSGATE_SHIFT = 4, 137 SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT = 8, 138 /* MEMPLL_S14 = 0x638 */ 139 MASK_MEMPLL_DL = 0xc0ffffff, 140 MEMPLL_FB_DL_SHIFT = 0, 141 MEMPLL_REF_DL_SHIFT = 8, 142 MEMPLL_DL_SHIFT = 24, 143 MEMPLL_MODE_SHIFT = 29, 144 /* MEMPLL_DIVIDER = 0x640 */ 145 MEMCLKENB_SHIFT = 5 146 }; 147 148 struct dramc_ao_regs { 149 uint32_t actim0; /* 0x0 */ 150 uint32_t conf1; /* 0x4 */ 151 uint32_t conf2; /* 0x8 */ 152 uint32_t rsvd_ao1[3]; /* 0xc */ 153 uint32_t r0deldly; /* 0x18 */ 154 uint32_t r1deldly; /* 0x1c */ 155 uint32_t r0difdly; /* 0x20 */ 156 uint32_t r1difdly; /* 0x24 */ 157 uint32_t dllconf; /* 0x28 */ 158 uint32_t rsvd_ao2[6]; /* 0x2c */ 159 uint32_t test2_3; /* 0x44 */ 160 uint32_t test2_4; /* 0x48 */ 161 uint32_t catraining; /* 0x4c */ 162 uint32_t catraining2; /* 0x50 */ 163 uint32_t wodt; /* 0x54 */ 164 uint32_t rsvd_ao3[9]; /* 0x58 */ 165 uint32_t ddr2ctl; /* 0x7c */ 166 uint32_t misc; /* 0x80 */ 167 uint32_t zqcs; /* 0x84 */ 168 uint32_t mrs; /* 0x88 */ 169 uint32_t clk1delay; /* 0x8c */ 170 uint32_t rsvd_ao4[1]; /* 0x90 */ 171 uint32_t dqsien[2]; /* 0x94 */ 172 uint32_t rsvd_ao5[2]; /* 0x9c */ 173 uint32_t iodrv1; /* 0xa4 */ 174 uint32_t iodrv2; /* 0xa8 */ 175 uint32_t iodrv3; /* 0xac */ 176 uint32_t iodrv4; /* 0xb0 */ 177 uint32_t iodrv5; /* 0xb4 */ 178 uint32_t iodrv6; /* 0xb8 */ 179 uint32_t drvctl1; /* 0xbc */ 180 uint32_t dllsel; /* 0xc0 */ 181 uint32_t rsvd_ao7[5]; /* 0xc4 */ 182 uint32_t mckdly; /* 0xd8 */ 183 uint32_t rsvd_ao8[1]; /* 0xdc */ 184 uint32_t dqsctl1; /* 0xe0 */ 185 uint32_t padctl4; /* 0xe4 */ 186 uint32_t rsvd_ao9[2]; /* 0xe8 */ 187 uint32_t phyctl1; /* 0xf0 */ 188 uint32_t gddr3ctl1; /* 0xf4 */ 189 uint32_t padctl7; /* 0xf8 */ 190 uint32_t misctl0; /* 0xfc */ 191 uint32_t ocdk; /* 0x100 */ 192 uint32_t rsvd_ao10[3]; /* 0x104 */ 193 uint32_t rkcfg; /* 0x110 */ 194 uint32_t ckphdet; /* 0x114 */ 195 uint32_t dqsctl2; /* 0x118 */ 196 uint32_t rsvd_ao11[5]; /* 0x11c */ 197 uint32_t clkctl; /* 0x130 */ 198 uint32_t rsvd_ao12[1]; /* 0x134 */ 199 uint32_t dummy; /* 0x138 */ 200 uint32_t write_leveling; /* 0x13c */ 201 uint32_t rsvd_ao13[10]; /* 0x140 */ 202 uint32_t arbctl0; /* 0x168 */ 203 uint32_t rsvd_ao14[21]; /* 0x16c */ 204 uint32_t dqscal0; /* 0x1c0 */ 205 uint32_t dqscal1; /* 0x1c4 */ 206 uint32_t impcal; /* 0x1c8 */ 207 uint32_t rsvd_ao15[4]; /* 0x1cc */ 208 uint32_t dramc_pd_ctrl; /* 0x1dc */ 209 uint32_t lpddr2_3; /* 0x1e0 */ 210 uint32_t spcmd; /* 0x1e4 */ 211 uint32_t actim1; /* 0x1e8 */ 212 uint32_t perfctl0; /* 0x1ec */ 213 uint32_t ac_derating; /* 0x1f0 */ 214 uint32_t rrrate_ctl; /* 0x1f4 */ 215 uint32_t ac_time_05t; /* 0x1f8 */ 216 uint32_t mrr_ctl; /* 0x1fc */ 217 uint32_t rsvd_ao16[4]; /* 0x200 */ 218 uint32_t dqidly[9]; /* 0x210 */ 219 uint32_t rsvd_ao17[115]; /* 0x234 */ 220 uint32_t selph1; /* 0x400 */ 221 uint32_t selph2; /* 0x404 */ 222 uint32_t selph3; /* 0x408 */ 223 uint32_t selph4; /* 0x40c */ 224 uint32_t selph5; /* 0x410 */ 225 uint32_t selph6; /* 0x414 */ 226 uint32_t selph6_1; /* 0x418 */ 227 uint32_t selph7; /* 0x41c */ 228 uint32_t selph8; /* 0x420 */ 229 uint32_t selph9; /* 0x424 */ 230 uint32_t selph10; /* 0x428 */ 231 uint32_t selph11; /* 0x42c */ 232 }; 233 234 check_member(dramc_ao_regs, selph11, 0x42c); 235 236 struct dramc_nao_regs { 237 uint32_t rsvd_nao1[11]; /* 0x0 */ 238 uint32_t test_mode; /* 0x2c */ 239 uint32_t rsvd_nao2[3]; /* 0x30 */ 240 uint32_t test2_1; /* 0x3c */ 241 uint32_t test2_2; /* 0x40 */ 242 uint32_t rsvd_nao3[48]; /* 0x44 */ 243 uint32_t lbwdat0; /* 0x104 */ 244 uint32_t lbwdat1; /* 0x108 */ 245 uint32_t lbwdat2; /* 0x10c */ 246 uint32_t rsvd_nao4[1]; /* 0x110 */ 247 uint32_t ckphdet; /* 0x114 */ 248 uint32_t rsvd_nao5[48]; /* 0x118 */ 249 uint32_t dmmonitor; /* 0x1d8 */ 250 uint32_t rsvd_nao6[41]; /* 0x1dc */ 251 uint32_t r2r_page_hit_counter; /* 0x280 */ 252 uint32_t r2r_page_miss_counter; /* 0x284 */ 253 uint32_t r2r_interbank_counter; /* 0x288 */ 254 uint32_t r2w_page_hit_counter; /* 0x28c */ 255 uint32_t r2w_page_miss_counter; /* 0x290 */ 256 uint32_t r2w_interbank_counter; /* 0x294 */ 257 uint32_t w2r_page_hit_counter; /* 0x298 */ 258 uint32_t w2r_page_miss_counter; /* 0x29c */ 259 uint32_t w2r_page_interbank_counter; /* 0x2a0 */ 260 uint32_t w2w_page_hit_counter; /* 0x2a4 */ 261 uint32_t w2w_page_miss_counter; /* 0x2a8 */ 262 uint32_t w2w_page_interbank_counter; /* 0x2ac */ 263 uint32_t dramc_idle_counter; /* 0x2b0 */ 264 uint32_t freerun_26m_counter; /* 0x2b4 */ 265 uint32_t refresh_pop_counter; /* 0x2b8 */ 266 uint32_t jmeter_st; /* 0x2bc */ 267 uint32_t dq_cal_max[8]; /* 0x2c0 */ 268 uint32_t dqs_cal_min[8]; /* 0x2e0 */ 269 uint32_t dqs_cal_max[8]; /* 0x300 */ 270 uint32_t rsvd_nao7[4]; /* 0x320 */ 271 uint32_t read_bytes_counter; /* 0x330 */ 272 uint32_t write_bytes_counter; /* 0x334 */ 273 uint32_t rsvd_nao8[6]; /* 0x338 */ 274 uint32_t dqical[4]; /* 0x350 */ 275 uint32_t rsvd_nao9[4]; /* 0x360 */ 276 uint32_t cmp_err; /* 0x370 */ 277 uint32_t r0dqsiendly; /* 0x374 */ 278 uint32_t r1dqsiendly; /* 0x378 */ 279 uint32_t rsvd_nao10[9]; /* 0x37c */ 280 uint32_t dqsdly0; /* 0x3a0 */ 281 uint32_t rsvd_nao11[4]; /* 0x3a4 */ 282 uint32_t mrrdata; /* 0x3b4 */ 283 uint32_t spcmdresp; /* 0x3b8 */ 284 uint32_t iorgcnt; /* 0x3bc */ 285 uint32_t dqsgnwcnt[6]; /* 0x3c0 */ 286 uint32_t rsvd_nao12[4]; /* 0x3d8 */ 287 uint32_t ckphcnt; /* 0x3e8 */ 288 uint32_t rsvd_nao13[4]; /* 0x3ec */ 289 uint32_t testrpt; /* 0x3fc */ 290 }; 291 292 check_member(dramc_nao_regs, testrpt, 0x3fc); 293 294 struct dramc_ddrphy_regs { 295 uint32_t rsvd_phy1[3]; /* 0x0 */ 296 uint32_t padctl1; /* 0xc */ 297 uint32_t padctl2; /* 0x10 */ 298 uint32_t padctl3; /* 0x14 */ 299 uint32_t rsvd_phy2[25]; /* 0x18 */ 300 uint32_t ddr2ctl; /* 0x7c */ 301 uint32_t rsvd_phy3[3]; /* 0x80 */ 302 uint32_t clk1delay; /* 0x8c */ 303 uint32_t ioctl; /* 0x90 */ 304 uint32_t rsvd_phy4[7]; /* 0x94 */ 305 uint32_t iodrv4; /* 0xb0 */ 306 uint32_t iodrv5; /* 0xb4 */ 307 uint32_t iodrv6; /* 0xb8 */ 308 uint32_t drvctl1; /* 0xbc */ 309 uint32_t dllsel; /* 0xc0 */ 310 uint32_t rsvd_phy5[2]; /* 0xc4 */ 311 uint32_t tdsel[3]; /* 0xcc */ 312 uint32_t mckdly; /* 0xd8 */ 313 uint32_t dqsctl0; /* 0xdc */ 314 uint32_t dqsctl1; /* 0xe0 */ 315 uint32_t dqsctl4; /* 0xe4 */ 316 uint32_t dqsctl5; /* 0xe8 */ 317 uint32_t dqsctl6; /* 0xec */ 318 uint32_t phyctl1; /* 0xf0 */ 319 uint32_t gddr3ctl1; /* 0xf4 */ 320 uint32_t rsvd_phy6[1]; /* 0xf8 */ 321 uint32_t misctl0; /* 0xfc */ 322 uint32_t ocdk; /* 0x100 */ 323 uint32_t rsvd_phy7[8]; /* 0x104 */ 324 uint32_t dqsgctl; /* 0x124 */ 325 uint32_t rsvd_phy8[6]; /* 0x128 */ 326 uint32_t ddrphydqsgctl; /* 0x140 */ 327 uint32_t dqsgct2; /* 0x144 */ 328 uint32_t phyclkduty; /* 0x148 */ 329 uint32_t rsvd_phy9[3]; /* 0x14c */ 330 uint32_t dqsisel; /* 0x158 */ 331 uint32_t dqmdqs_sel; /* 0x15c */ 332 uint32_t rsvd_phy10[10]; /* 0x160 */ 333 uint32_t jmeterpop1; /* 0x188 */ 334 uint32_t jmeterpop2; /* 0x18c */ 335 uint32_t jmeterpop3; /* 0x190 */ 336 uint32_t jmeterpop4; /* 0x194 */ 337 uint32_t rsvd_phy11[4]; /* 0x198 */ 338 uint32_t cmddly[6]; /* 0x1a8 */ 339 uint32_t dqscal0; /* 0x1c0 */ 340 uint32_t rsvd_phy12[2]; /* 0x1c4 */ 341 uint32_t jmeter[3]; /* 0x1cc */ 342 uint32_t rsvd_phy13[2]; /* 0x1d8 */ 343 uint32_t lpddr2_3; /* 0x1e0 */ 344 uint32_t spcmd; /* 0x1e4 */ 345 uint32_t rsvd_phy14[6]; /* 0x1e8 */ 346 uint32_t dqodly[4]; /* 0x200 */ 347 uint32_t rsvd_phy15[11]; /* 0x210 */ 348 uint32_t lpddr2_4; /* 0x23c */ 349 uint32_t rsvd_phy16[56]; /* 0x240 */ 350 uint32_t jmeter_pll_st[3]; /* 0x320 */ 351 uint32_t jmeter_done_st; /* 0x32c */ 352 uint32_t rsvd_phy17[2]; /* 0x330 */ 353 uint32_t jmeter_pll1_st; /* 0x338 */ 354 uint32_t jmeter_pop_pll2_st; /* 0x33c */ 355 uint32_t jmeter_pop_pll3_st; /* 0x340 */ 356 uint32_t jmeter_pop_pll4_st; /* 0x344 */ 357 uint32_t jmeter_pop_pll1_st; /* 0x348 */ 358 uint32_t rsvd_phy18[13]; /* 0x34c */ 359 uint32_t dq_o1; /* 0x380 */ 360 uint32_t rsvd_phy19[2]; /* 0x384 */ 361 uint32_t stben[4]; /* 0x38c */ 362 uint32_t rsvd_phy20[16]; /* 0x39c */ 363 uint32_t dllcnt0; /* 0x3dc */ 364 uint32_t pllautok; /* 0x3e0 */ 365 uint32_t poppllautok; /* 0x3e4 */ 366 uint32_t rsvd_phy21[18]; /* 0x3e8 */ 367 uint32_t selph12; /* 0x430 */ 368 uint32_t selph13; /* 0x434 */ 369 uint32_t selph14; /* 0x438 */ 370 uint32_t selph15; /* 0x43c */ 371 uint32_t selph16; /* 0x440 */ 372 uint32_t selph17; /* 0x444 */ 373 uint32_t selph18; /* 0x448 */ 374 uint32_t selph19; /* 0x44c */ 375 uint32_t selph20; /* 0x450 */ 376 uint32_t rsvd_phy22[91]; /* 0x454 */ 377 uint32_t peri[4]; /* 0x5c0 */ 378 uint32_t rsvd_phy23[12]; /* 0x5d0 */ 379 uint32_t mempll[15]; /* 0x600 */ 380 uint32_t ddrphy_cg_ctrl; /* 0x63c */ 381 uint32_t mempll_divider; /* 0x640 */ 382 uint32_t vrefctl0; /* 0x644 */ 383 uint32_t rsvd_phy24[18]; /* 0x648 */ 384 uint32_t mempll05_divider; /* 0x690 */ 385 }; 386 387 check_member(dramc_ddrphy_regs, mempll05_divider, 0x690); 388 389 struct emi_regs { 390 uint32_t emi_cona; /* 0x0 */ 391 uint32_t rsvd_emi1; /* 0x4 */ 392 uint32_t emi_conb; /* 0x08 */ 393 uint32_t rsvd_emi2; /* 0x0c */ 394 uint32_t emi_conc; /* 0x10 */ 395 uint32_t rsvd_emi3; /* 0x14 */ 396 uint32_t emi_cond; /* 0x18 */ 397 uint32_t rsvd_emi4; /* 0x1c */ 398 uint32_t emi_cone; /* 0x20 */ 399 uint32_t rsvd_emi5; /* 0x24 */ 400 uint32_t emi_conf; /* 0x28 */ 401 uint32_t rsvd_emi6; /* 0x2c */ 402 uint32_t emi_cong; /* 0x30 */ 403 uint32_t rsvd_emi7; /* 0x34 */ 404 uint32_t emi_conh; /* 0x38 */ 405 uint32_t rsvd_emi8[9]; /* 0x3c */ 406 uint32_t emi_conm; /* 0x60 */ 407 uint32_t rsvd_emi9[5]; /* 0x64 */ 408 uint32_t emi_mdct; /* 0x78 */ 409 uint32_t rsvd_emi10[21]; /* 0x7c */ 410 uint32_t emi_test0; /* 0xd0 */ 411 uint32_t rsvd_emi11; /* 0xd4 */ 412 uint32_t emi_test1; /* 0xd8 */ 413 uint32_t rsvd_emi12; /* 0xdc */ 414 uint32_t emi_testa; /* 0xe0 */ 415 uint32_t rsvd_emi13; /* 0xe4 */ 416 uint32_t emi_testb; /* 0xe8 */ 417 uint32_t rsvd_emi14; /* 0xec */ 418 uint32_t emi_testc; /* 0xf0 */ 419 uint32_t rsvd_emi15; /* 0xf4 */ 420 uint32_t emi_testd; /* 0xf8 */ 421 uint32_t rsvd_emi16; /* 0xfc */ 422 uint32_t emi_arba; /* 0x100 */ 423 uint32_t rsvd_emi17[3]; /* 0x104 */ 424 uint32_t emi_arbc; /* 0x110 */ 425 uint32_t rsvd_emi18; /* 0x114 */ 426 uint32_t emi_arbd; /* 0x118 */ 427 uint32_t rsvd_emi19; /* 0x11c */ 428 uint32_t emi_arbe; /* 0x120 */ 429 uint32_t rsvd_emi20; /* 0x124 */ 430 uint32_t emi_arbf; /* 0x128 */ 431 uint32_t rsvd_emi21; /* 0x12c */ 432 uint32_t emi_arbg; /* 0x130 */ 433 uint32_t rsvd_emi22; /* 0x134 */ 434 uint32_t emi_arbh; /* 0x138 */ 435 uint32_t rsvd_emi23; /* 0x13c */ 436 uint32_t emi_arbi; /* 0x140 */ 437 uint32_t emi_arbi_2nd; /* 0x144 */ 438 uint32_t emi_arbj; /* 0x148 */ 439 uint32_t emi_arbj_2nd; /* 0x14c */ 440 uint32_t emi_arbk; /* 0x150 */ 441 uint32_t emi_arbk_2nd; /* 0x154 */ 442 uint32_t emi_slct; /* 0x158 */ 443 uint32_t rsvd_emi24; /* 0x15C */ 444 uint32_t emi_mpua; /* 0x160 */ 445 uint32_t rsvd_emi25; /* 0x164 */ 446 uint32_t emi_mpub; /* 0x168 */ 447 uint32_t rsvd_emi26; /* 0x16c */ 448 uint32_t emi_mpuc; /* 0x170 */ 449 uint32_t rsvd_emi27; /* 0x174 */ 450 uint32_t emi_mpud; /* 0x178 */ 451 uint32_t rsvd_emi28; /* 0x17C */ 452 uint32_t emi_mpue; /* 0x180 */ 453 uint32_t rsvd_emi29; /* 0x184 */ 454 uint32_t emi_mpuf; /* 0x188 */ 455 uint32_t rsvd_emi30; /* 0x18C */ 456 uint32_t emi_mpug; /* 0x190 */ 457 uint32_t rsvd_emi31; /* 0x194 */ 458 uint32_t emi_mpuh; /* 0x198 */ 459 uint32_t rsvd_emi32; /* 0x19C */ 460 uint32_t emi_mpui; /* 0x1A0 */ 461 uint32_t rsvd_emi33; /* 0x1A4 */ 462 uint32_t emi_mpuj; /* 0x1A8 */ 463 uint32_t rsvd_emi34; /* 0x1AC */ 464 uint32_t emi_mpuk; /* 0x1B0 */ 465 uint32_t rsvd_emi35; /* 0x1B4 */ 466 uint32_t emi_mpul; /* 0x1B8 */ 467 uint32_t rsvd_emi36; /* 0x1BC */ 468 uint32_t emi_mpum; /* 0x1C0 */ 469 uint32_t rsvd_emi37; /* 0x1C4 */ 470 uint32_t emi_mpun; /* 0x1C8 */ 471 uint32_t rsvd_emi38; /* 0x1CC */ 472 uint32_t emi_mpuo; /* 0x1D0 */ 473 uint32_t rsvd_emi39; /* 0x1D4 */ 474 uint32_t emi_mpup; /* 0x1D8 */ 475 uint32_t rsvd_emi40; /* 0x1DC */ 476 uint32_t emi_mpuq; /* 0x1E0 */ 477 uint32_t rsvd_emi41; /* 0x1E4 */ 478 uint32_t emi_mpur; /* 0x1E8 */ 479 uint32_t rsvd_emi42; /* 0x1EC */ 480 uint32_t emi_mpus; /* 0x1F0 */ 481 uint32_t rsvd_emi43; /* 0x1F4 */ 482 uint32_t emi_mput; /* 0x1F8 */ 483 uint32_t rsvd_emi44; /* 0x1FC */ 484 uint32_t emi_mpuu; /* 0x200 */ 485 uint32_t rsvd_emi45[7]; /* 0x204 */ 486 uint32_t emi_mpuy; /* 0x220 */ 487 uint32_t rsvd_emi46[119]; /* 0x224 */ 488 uint32_t emi_bmen; /* 0x400 */ 489 }; 490 491 check_member(emi_regs, emi_bmen, 0x400); 492 493 extern struct dramc_ao_regs *ao_regs; 494 extern struct dramc_nao_regs *nao_regs; 495 extern struct dramc_ddrphy_regs *ddrphy_regs; 496 497 struct dramc_channel { 498 struct dramc_ao_regs *ao_regs; 499 struct dramc_nao_regs *nao_regs; 500 struct dramc_ddrphy_regs *ddrphy_regs; 501 }; 502 503 static struct dramc_channel const ch[2] = { 504 {(void *)CHA_DRAMCAO_BASE, (void *)CHA_DRAMCNAO_BASE, (void *)CHA_DDRPHY_BASE}, 505 {(void *)CHB_DRAMCAO_BASE, (void *)CHB_DRAMCNAO_BASE, (void *)CHB_DDRPHY_BASE} 506 }; 507 508 #endif /* _DRAMC_REGISTER_H_ */ 509