1 /*
2 * Copyright 2008 Corbin Simpson <[email protected]>
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "r500_fragprog.h"
7
8 #include <stdio.h>
9
10 #include "radeon_compiler_util.h"
11 #include "radeon_list.h"
12 #include "radeon_variable.h"
13 #include "r300_reg.h"
14
15 #include "util/compiler.h"
16
17 /**
18 * Rewrite IF instructions to use the ALU result special register.
19 */
r500_transform_IF_instr(struct radeon_compiler * c,struct rc_instruction * inst_if,struct rc_list * var_list)20 static void r500_transform_IF_instr(
21 struct radeon_compiler * c,
22 struct rc_instruction * inst_if,
23 struct rc_list * var_list)
24 {
25
26 struct rc_variable * writer;
27 struct rc_list * writer_list, * list_ptr;
28 unsigned int generic_if = 0;
29 unsigned int alu_chan;
30
31 writer_list = rc_variable_list_get_writers(
32 var_list, inst_if->Type, &inst_if->U.I.SrcReg[0]);
33 if (!writer_list) {
34 generic_if = 1;
35 } else {
36
37 /* Make sure it is safe for the writers to write to
38 * ALU Result */
39 for (list_ptr = writer_list; list_ptr;
40 list_ptr = list_ptr->Next) {
41 struct rc_instruction * inst;
42 writer = list_ptr->Item;
43 /* We are going to modify the destination register
44 * of writer, so if it has a reader other than
45 * inst_if (aka ReaderCount > 1) we must fall back to
46 * our generic IF.
47 * If the writer has a lower IP than inst_if, this
48 * means that inst_if is above the writer in a loop.
49 * I'm not sure why this would ever happen, but
50 * if it does we want to make sure we fall back
51 * to our generic IF. */
52 if (writer->ReaderCount > 1 || writer->Inst->IP < inst_if->IP) {
53 generic_if = 1;
54 break;
55 }
56
57 /* The ALU Result is not preserved across IF
58 * instructions, so if there is another IF
59 * instruction between writer and inst_if, then
60 * we need to fall back to generic IF. */
61 for (inst = writer->Inst; inst != inst_if; inst = inst->Next) {
62 const struct rc_opcode_info * info =
63 rc_get_opcode_info(inst->U.I.Opcode);
64 if (info->IsFlowControl) {
65 generic_if = 1;
66 break;
67 }
68 }
69 if (generic_if) {
70 break;
71 }
72 }
73 }
74
75 if (GET_SWZ(inst_if->U.I.SrcReg[0].Swizzle, 0) == RC_SWIZZLE_X) {
76 alu_chan = RC_ALURESULT_X;
77 } else {
78 alu_chan = RC_ALURESULT_W;
79 }
80 if (generic_if) {
81 struct rc_instruction * inst_mov =
82 rc_insert_new_instruction(c, inst_if->Prev);
83
84 inst_mov->U.I.Opcode = RC_OPCODE_MOV;
85 inst_mov->U.I.DstReg.WriteMask = 0;
86 inst_mov->U.I.DstReg.File = RC_FILE_NONE;
87 inst_mov->U.I.ALUResultCompare = RC_COMPARE_FUNC_NOTEQUAL;
88 inst_mov->U.I.WriteALUResult = alu_chan;
89 inst_mov->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0];
90 if (alu_chan == RC_ALURESULT_X) {
91 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
92 inst_mov->U.I.SrcReg[0].Swizzle,
93 RC_SWIZZLE_X, RC_SWIZZLE_UNUSED,
94 RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED);
95 } else {
96 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
97 inst_mov->U.I.SrcReg[0].Swizzle,
98 RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED,
99 RC_SWIZZLE_UNUSED, RC_SWIZZLE_Z);
100 }
101 } else {
102 rc_compare_func compare_func = RC_COMPARE_FUNC_NEVER;
103 unsigned int preserve_opcode = 0;
104 for (list_ptr = writer_list; list_ptr;
105 list_ptr = list_ptr->Next) {
106 writer = list_ptr->Item;
107 switch(writer->Inst->U.I.Opcode) {
108 case RC_OPCODE_SEQ:
109 compare_func = RC_COMPARE_FUNC_EQUAL;
110 break;
111 case RC_OPCODE_SNE:
112 compare_func = RC_COMPARE_FUNC_NOTEQUAL;
113 break;
114 case RC_OPCODE_SGE:
115 compare_func = RC_COMPARE_FUNC_GEQUAL;
116 break;
117 case RC_OPCODE_SLT:
118 compare_func = RC_COMPARE_FUNC_LESS;
119 break;
120 default:
121 compare_func = RC_COMPARE_FUNC_NOTEQUAL;
122 preserve_opcode = 1;
123 break;
124 }
125 if (!preserve_opcode) {
126 writer->Inst->U.I.Opcode = RC_OPCODE_ADD;
127 writer->Inst->U.I.SrcReg[1].Negate =
128 ~writer->Inst->U.I.SrcReg[1].Negate;
129 }
130 writer->Inst->U.I.DstReg.WriteMask = 0;
131 writer->Inst->U.I.DstReg.File = RC_FILE_NONE;
132 writer->Inst->U.I.WriteALUResult = alu_chan;
133 writer->Inst->U.I.ALUResultCompare = compare_func;
134 }
135 }
136
137 inst_if->U.I.SrcReg[0].File = RC_FILE_SPECIAL;
138 inst_if->U.I.SrcReg[0].Index = RC_SPECIAL_ALU_RESULT;
139 inst_if->U.I.SrcReg[0].Swizzle = RC_MAKE_SWIZZLE(
140 RC_SWIZZLE_X, RC_SWIZZLE_UNUSED,
141 RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED);
142 inst_if->U.I.SrcReg[0].Negate = 0;
143 }
144
r500_transform_IF(struct radeon_compiler * c,void * user)145 void r500_transform_IF(
146 struct radeon_compiler * c,
147 void *user)
148 {
149 struct rc_list * var_list = rc_get_variables(c);
150
151 struct rc_instruction * inst = c->Program.Instructions.Next;
152 while(inst != &c->Program.Instructions) {
153 struct rc_instruction * current = inst;
154 inst = inst->Next;
155
156 if (current->U.I.Opcode == RC_OPCODE_IF)
157 r500_transform_IF_instr(c, current, var_list);
158 }
159 }
160
r500_swizzle_is_native(rc_opcode opcode,struct rc_src_register reg)161 static int r500_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
162 {
163 unsigned int relevant;
164 int i;
165
166 if (opcode == RC_OPCODE_TEX ||
167 opcode == RC_OPCODE_TXB ||
168 opcode == RC_OPCODE_TXP ||
169 opcode == RC_OPCODE_TXD ||
170 opcode == RC_OPCODE_TXL ||
171 opcode == RC_OPCODE_KIL) {
172 if (reg.Abs)
173 return 0;
174
175 if (opcode == RC_OPCODE_KIL && (reg.Swizzle != RC_SWIZZLE_XYZW || reg.Negate != RC_MASK_NONE))
176 return 0;
177
178 for(i = 0; i < 4; ++i) {
179 unsigned int swz = GET_SWZ(reg.Swizzle, i);
180 if (swz == RC_SWIZZLE_UNUSED) {
181 reg.Negate &= ~(1 << i);
182 continue;
183 }
184 if (swz >= 4)
185 return 0;
186 }
187
188 if (reg.Negate)
189 return 0;
190
191 return 1;
192 } else if (opcode == RC_OPCODE_DDX || opcode == RC_OPCODE_DDY) {
193 /* DDX/MDH and DDY/MDV explicitly ignore incoming swizzles;
194 * if it doesn't fit perfectly into a .xyzw case... */
195 if (reg.Swizzle == RC_SWIZZLE_XYZW && !reg.Abs && !reg.Negate)
196 return 1;
197
198 return 0;
199 } else {
200 /* ALU instructions support almost everything */
201 relevant = 0;
202 for(i = 0; i < 3; ++i) {
203 unsigned int swz = GET_SWZ(reg.Swizzle, i);
204 if (swz != RC_SWIZZLE_UNUSED && swz != RC_SWIZZLE_ZERO)
205 relevant |= 1 << i;
206 }
207 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
208 return 0;
209
210 return 1;
211 }
212 }
213
214 /**
215 * Split source register access.
216 *
217 * The only thing we *cannot* do in an ALU instruction is per-component
218 * negation.
219 */
r500_swizzle_split(struct rc_src_register src,unsigned int usemask,struct rc_swizzle_split * split)220 static void r500_swizzle_split(struct rc_src_register src, unsigned int usemask,
221 struct rc_swizzle_split * split)
222 {
223 unsigned int negatebase[2] = { 0, 0 };
224 int i;
225
226 for(i = 0; i < 4; ++i) {
227 unsigned int swz = GET_SWZ(src.Swizzle, i);
228 if (swz == RC_SWIZZLE_UNUSED || !GET_BIT(usemask, i))
229 continue;
230 negatebase[GET_BIT(src.Negate, i)] |= 1 << i;
231 }
232
233 split->NumPhases = 0;
234
235 for(i = 0; i <= 1; ++i) {
236 if (!negatebase[i])
237 continue;
238
239 split->Phase[split->NumPhases++] = negatebase[i];
240 }
241 }
242
243 const struct rc_swizzle_caps r500_swizzle_caps = {
244 .IsNative = r500_swizzle_is_native,
245 .Split = r500_swizzle_split
246 };
247
toswiz(int swiz_val)248 static char *toswiz(int swiz_val) {
249 switch(swiz_val) {
250 case 0: return "R";
251 case 1: return "G";
252 case 2: return "B";
253 case 3: return "A";
254 case 4: return "0";
255 case 5: return "H";
256 case 6: return "1";
257 case 7: return "U";
258 }
259 return NULL;
260 }
261
toop(int op_val)262 static char *toop(int op_val)
263 {
264 char *str = NULL;
265 switch (op_val) {
266 case 0: str = "MAD"; break;
267 case 1: str = "DP3"; break;
268 case 2: str = "DP4"; break;
269 case 3: str = "D2A"; break;
270 case 4: str = "MIN"; break;
271 case 5: str = "MAX"; break;
272 case 6: str = "Reserved"; break;
273 case 7: str = "CND"; break;
274 case 8: str = "CMP"; break;
275 case 9: str = "FRC"; break;
276 case 10: str = "SOP"; break;
277 case 11: str = "MDH"; break;
278 case 12: str = "MDV"; break;
279 }
280 return str;
281 }
282
to_alpha_op(int op_val)283 static char *to_alpha_op(int op_val)
284 {
285 char *str = NULL;
286 switch (op_val) {
287 case 0: str = "MAD"; break;
288 case 1: str = "DP"; break;
289 case 2: str = "MIN"; break;
290 case 3: str = "MAX"; break;
291 case 4: str = "Reserved"; break;
292 case 5: str = "CND"; break;
293 case 6: str = "CMP"; break;
294 case 7: str = "FRC"; break;
295 case 8: str = "EX2"; break;
296 case 9: str = "LN2"; break;
297 case 10: str = "RCP"; break;
298 case 11: str = "RSQ"; break;
299 case 12: str = "SIN"; break;
300 case 13: str = "COS"; break;
301 case 14: str = "MDH"; break;
302 case 15: str = "MDV"; break;
303 }
304 return str;
305 }
306
to_mask(int val)307 static char *to_mask(int val)
308 {
309 char *str = NULL;
310 switch(val) {
311 case 0: str = "NONE"; break;
312 case 1: str = "R"; break;
313 case 2: str = "G"; break;
314 case 3: str = "RG"; break;
315 case 4: str = "B"; break;
316 case 5: str = "RB"; break;
317 case 6: str = "GB"; break;
318 case 7: str = "RGB"; break;
319 case 8: str = "A"; break;
320 case 9: str = "AR"; break;
321 case 10: str = "AG"; break;
322 case 11: str = "ARG"; break;
323 case 12: str = "AB"; break;
324 case 13: str = "ARB"; break;
325 case 14: str = "AGB"; break;
326 case 15: str = "ARGB"; break;
327 }
328 return str;
329 }
330
to_texop(int val)331 static char *to_texop(int val)
332 {
333 switch(val) {
334 case 0: return "NOP";
335 case 1: return "LD";
336 case 2: return "TEXKILL";
337 case 3: return "PROJ";
338 case 4: return "LODBIAS";
339 case 5: return "LOD";
340 case 6: return "DXDY";
341 }
342 return NULL;
343 }
344
r500FragmentProgramDump(struct radeon_compiler * c,void * user)345 void r500FragmentProgramDump(struct radeon_compiler *c, void *user)
346 {
347 struct r300_fragment_program_compiler *compiler = (struct r300_fragment_program_compiler*)c;
348 struct r500_fragment_program_code *code = &compiler->code->code.r500;
349 int n, i;
350 uint32_t inst;
351 uint32_t inst0;
352 char *str = NULL;
353 fprintf(stderr, "R500 Fragment Program:\n--------\n");
354
355 for (n = 0; n < code->inst_end+1; n++) {
356 inst0 = inst = code->inst[n].inst0;
357 fprintf(stderr,"%d\t0:CMN_INST 0x%08x:", n, inst);
358 switch(inst & 0x3) {
359 case R500_INST_TYPE_ALU: str = "ALU"; break;
360 case R500_INST_TYPE_OUT: str = "OUT"; break;
361 case R500_INST_TYPE_FC: str = "FC"; break;
362 case R500_INST_TYPE_TEX: str = "TEX"; break;
363 }
364 fprintf(stderr,"%s %s %s %s %s ", str,
365 inst & R500_INST_TEX_SEM_WAIT ? "TEX_WAIT" : "",
366 inst & R500_INST_LAST ? "LAST" : "",
367 inst & R500_INST_NOP ? "NOP" : "",
368 inst & R500_INST_ALU_WAIT ? "ALU WAIT" : "");
369 fprintf(stderr,"wmask: %s omask: %s\n", to_mask((inst >> 11) & 0xf),
370 to_mask((inst >> 15) & 0xf));
371
372 switch(inst0 & 0x3) {
373 case R500_INST_TYPE_ALU:
374 case R500_INST_TYPE_OUT:
375 fprintf(stderr,"\t1:RGB_ADDR 0x%08x:", code->inst[n].inst1);
376 inst = code->inst[n].inst1;
377
378 fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
379 inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
380 (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
381 (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
382 (inst >> 30));
383
384 fprintf(stderr,"\t2:ALPHA_ADDR 0x%08x:", code->inst[n].inst2);
385 inst = code->inst[n].inst2;
386 fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
387 inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
388 (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
389 (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
390 (inst >> 30));
391 fprintf(stderr,"\t3 RGB_INST: 0x%08x:", code->inst[n].inst3);
392 inst = code->inst[n].inst3;
393 fprintf(stderr,"rgb_A_src:%d %s/%s/%s %d rgb_B_src:%d %s/%s/%s %d targ: %d\n",
394 (inst) & 0x3, toswiz((inst >> 2) & 0x7), toswiz((inst >> 5) & 0x7), toswiz((inst >> 8) & 0x7),
395 (inst >> 11) & 0x3,
396 (inst >> 13) & 0x3, toswiz((inst >> 15) & 0x7), toswiz((inst >> 18) & 0x7), toswiz((inst >> 21) & 0x7),
397 (inst >> 24) & 0x3, (inst >> 29) & 0x3);
398
399
400 fprintf(stderr,"\t4 ALPHA_INST:0x%08x:", code->inst[n].inst4);
401 inst = code->inst[n].inst4;
402 fprintf(stderr,"%s dest:%d%s alp_A_src:%d %s %d alp_B_src:%d %s %d targ %d w:%d\n", to_alpha_op(inst & 0xf),
403 (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
404 (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), (inst >> 17) & 0x3,
405 (inst >> 19) & 0x3, toswiz((inst >> 21) & 0x7), (inst >> 24) & 0x3,
406 (inst >> 29) & 0x3,
407 (inst >> 31) & 0x1);
408
409 fprintf(stderr,"\t5 RGBA_INST: 0x%08x:", code->inst[n].inst5);
410 inst = code->inst[n].inst5;
411 fprintf(stderr,"%s dest:%d%s rgb_C_src:%d %s/%s/%s %d alp_C_src:%d %s %d\n", toop(inst & 0xf),
412 (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
413 (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), toswiz((inst >> 17) & 0x7), toswiz((inst >> 20) & 0x7),
414 (inst >> 23) & 0x3,
415 (inst >> 25) & 0x3, toswiz((inst >> 27) & 0x7), (inst >> 30) & 0x3);
416 break;
417 case R500_INST_TYPE_FC:
418 fprintf(stderr, "\t2:FC_INST 0x%08x:", code->inst[n].inst2);
419 inst = code->inst[n].inst2;
420 /* JUMP_FUNC JUMP_ANY*/
421 fprintf(stderr, "0x%02x %1x ", inst >> 8 & 0xff,
422 (inst & R500_FC_JUMP_ANY) >> 5);
423
424 /* OP */
425 switch(inst & 0x7){
426 case R500_FC_OP_JUMP:
427 fprintf(stderr, "JUMP");
428 break;
429 case R500_FC_OP_LOOP:
430 fprintf(stderr, "LOOP");
431 break;
432 case R500_FC_OP_ENDLOOP:
433 fprintf(stderr, "ENDLOOP");
434 break;
435 case R500_FC_OP_REP:
436 fprintf(stderr, "REP");
437 break;
438 case R500_FC_OP_ENDREP:
439 fprintf(stderr, "ENDREP");
440 break;
441 case R500_FC_OP_BREAKLOOP:
442 fprintf(stderr, "BREAKLOOP");
443 break;
444 case R500_FC_OP_BREAKREP:
445 fprintf(stderr, "BREAKREP");
446 break;
447 case R500_FC_OP_CONTINUE:
448 fprintf(stderr, "CONTINUE");
449 break;
450 }
451 fprintf(stderr," ");
452 /* A_OP */
453 switch(inst & (0x3 << 6)){
454 case R500_FC_A_OP_NONE:
455 fprintf(stderr, "NONE");
456 break;
457 case R500_FC_A_OP_POP:
458 fprintf(stderr, "POP");
459 break;
460 case R500_FC_A_OP_PUSH:
461 fprintf(stderr, "PUSH");
462 break;
463 }
464 /* B_OP0 B_OP1 */
465 for(i=0; i<2; i++){
466 fprintf(stderr, " ");
467 switch(inst & (0x3 << (24 + (i * 2)))){
468 /* R500_FC_B_OP0_NONE
469 * R500_FC_B_OP1_NONE */
470 case 0:
471 fprintf(stderr, "NONE");
472 break;
473 case R500_FC_B_OP0_DECR:
474 case R500_FC_B_OP1_DECR:
475 fprintf(stderr, "DECR");
476 break;
477 case R500_FC_B_OP0_INCR:
478 case R500_FC_B_OP1_INCR:
479 fprintf(stderr, "INCR");
480 break;
481 }
482 }
483 /*POP_CNT B_ELSE */
484 fprintf(stderr, " %d %1x", (inst >> 16) & 0x1f, (inst & R500_FC_B_ELSE) >> 4);
485 inst = code->inst[n].inst3;
486 /* JUMP_ADDR */
487 fprintf(stderr, " %d", inst >> 16);
488
489 if(code->inst[n].inst2 & R500_FC_IGNORE_UNCOVERED){
490 fprintf(stderr, " IGN_UNC");
491 }
492 inst = code->inst[n].inst3;
493 fprintf(stderr, "\n\t3:FC_ADDR 0x%08x:", inst);
494 fprintf(stderr, "BOOL: 0x%02x, INT: 0x%02x, JUMP_ADDR: %d, JMP_GLBL: %1x\n",
495 inst & 0x1f, (inst >> 8) & 0x1f, (inst >> 16) & 0x1ff, inst >> 31);
496 break;
497 case R500_INST_TYPE_TEX:
498 inst = code->inst[n].inst1;
499 fprintf(stderr,"\t1:TEX_INST: 0x%08x: id: %d op:%s, %s, %s %s\n", inst, (inst >> 16) & 0xf,
500 to_texop((inst >> 22) & 0x7), (inst & (1<<25)) ? "ACQ" : "",
501 (inst & (1<<26)) ? "IGNUNC" : "", (inst & (1<<27)) ? "UNSCALED" : "SCALED");
502 inst = code->inst[n].inst2;
503 fprintf(stderr,"\t2:TEX_ADDR: 0x%08x: src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n", inst,
504 inst & 127, inst & (1<<7) ? "(rel)" : "",
505 toswiz((inst >> 8) & 0x3), toswiz((inst >> 10) & 0x3),
506 toswiz((inst >> 12) & 0x3), toswiz((inst >> 14) & 0x3),
507 (inst >> 16) & 127, inst & (1<<23) ? "(rel)" : "",
508 toswiz((inst >> 24) & 0x3), toswiz((inst >> 26) & 0x3),
509 toswiz((inst >> 28) & 0x3), toswiz((inst >> 30) & 0x3));
510
511 fprintf(stderr,"\t3:TEX_DXDY: 0x%08x\n", code->inst[n].inst3);
512 break;
513 }
514 fprintf(stderr,"\n");
515 }
516
517 }
518