1 /*
2 * Copyright 2010 Jerome Glisse <[email protected]>
3 * Authors:
4 * Jerome Glisse
5 * Corbin Simpson
6 * SPDX-License-Identifier: MIT
7 */
8
9 #include "r600_pipe_common.h"
10 #include "r600_cs.h"
11 #include "r600_query.h"
12 #include "util/format/u_format.h"
13 #include "util/u_log.h"
14 #include "util/u_memory.h"
15 #include "util/u_pack_color.h"
16 #include "util/u_surface.h"
17 #include "util/os_time.h"
18 #include "frontend/winsys_handle.h"
19 #include <errno.h>
20 #include <inttypes.h>
21
22 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
23 struct r600_texture *rtex);
24 static enum radeon_surf_mode
25 r600_choose_tiling(struct r600_common_screen *rscreen,
26 const struct pipe_resource *templ);
27
28
r600_prepare_for_dma_blit(struct r600_common_context * rctx,struct r600_texture * rdst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct r600_texture * rsrc,unsigned src_level,const struct pipe_box * src_box)29 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
30 struct r600_texture *rdst,
31 unsigned dst_level, unsigned dstx,
32 unsigned dsty, unsigned dstz,
33 struct r600_texture *rsrc,
34 unsigned src_level,
35 const struct pipe_box *src_box)
36 {
37 if (!rctx->dma.cs.priv)
38 return false;
39
40 if (rdst->surface.bpe != rsrc->surface.bpe)
41 return false;
42
43 /* MSAA: Blits don't exist in the real world. */
44 if (rsrc->resource.b.b.nr_samples > 1 ||
45 rdst->resource.b.b.nr_samples > 1)
46 return false;
47
48 /* Depth-stencil surfaces:
49 * When dst is linear, the DB->CB copy preserves HTILE.
50 * When dst is tiled, the 3D path must be used to update HTILE.
51 */
52 if (rsrc->is_depth || rdst->is_depth)
53 return false;
54
55 /* CMASK as:
56 * src: Both texture and SDMA paths need decompression. Use SDMA.
57 * dst: If overwriting the whole texture, discard CMASK and use
58 * SDMA. Otherwise, use the 3D path.
59 */
60 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
61 /* The CMASK clear is only enabled for the first level. */
62 assert(dst_level == 0);
63 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
64 dstx, dsty, dstz, src_box->width,
65 src_box->height, src_box->depth))
66 return false;
67
68 r600_texture_discard_cmask(rctx->screen, rdst);
69 }
70
71 /* All requirements are met. Prepare textures for SDMA. */
72 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
73 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
74
75 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
76 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
77
78 return true;
79 }
80
81 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
r600_copy_region_with_blit(struct pipe_context * pipe,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)82 static void r600_copy_region_with_blit(struct pipe_context *pipe,
83 struct pipe_resource *dst,
84 unsigned dst_level,
85 unsigned dstx, unsigned dsty, unsigned dstz,
86 struct pipe_resource *src,
87 unsigned src_level,
88 const struct pipe_box *src_box)
89 {
90 struct pipe_blit_info blit;
91
92 memset(&blit, 0, sizeof(blit));
93 blit.src.resource = src;
94 blit.src.format = src->format;
95 blit.src.level = src_level;
96 blit.src.box = *src_box;
97 blit.dst.resource = dst;
98 blit.dst.format = dst->format;
99 blit.dst.level = dst_level;
100 blit.dst.box.x = dstx;
101 blit.dst.box.y = dsty;
102 blit.dst.box.z = dstz;
103 blit.dst.box.width = src_box->width;
104 blit.dst.box.height = src_box->height;
105 blit.dst.box.depth = src_box->depth;
106 blit.mask = util_format_get_mask(src->format) &
107 util_format_get_mask(dst->format);
108 blit.filter = PIPE_TEX_FILTER_NEAREST;
109
110 if (blit.mask) {
111 pipe->blit(pipe, &blit);
112 }
113 }
114
115 /* Copy from a full GPU texture to a transfer's staging one. */
r600_copy_to_staging_texture(struct pipe_context * ctx,struct r600_transfer * rtransfer)116 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
117 {
118 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
119 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
120 struct pipe_resource *dst = &rtransfer->staging->b.b;
121 struct pipe_resource *src = transfer->resource;
122
123 if (src->nr_samples > 1) {
124 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
125 src, transfer->level, &transfer->box);
126 return;
127 }
128
129 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
130 &transfer->box);
131 }
132
133 /* Copy from a transfer's staging texture to a full GPU one. */
r600_copy_from_staging_texture(struct pipe_context * ctx,struct r600_transfer * rtransfer)134 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
135 {
136 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
137 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
138 struct pipe_resource *dst = transfer->resource;
139 struct pipe_resource *src = &rtransfer->staging->b.b;
140 struct pipe_box sbox;
141
142 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
143
144 if (dst->nr_samples > 1) {
145 r600_copy_region_with_blit(ctx, dst, transfer->level,
146 transfer->box.x, transfer->box.y, transfer->box.z,
147 src, 0, &sbox);
148 return;
149 }
150
151 rctx->dma_copy(ctx, dst, transfer->level,
152 transfer->box.x, transfer->box.y, transfer->box.z,
153 src, 0, &sbox);
154 }
155
r600_texture_get_offset(struct r600_common_screen * rscreen,struct r600_texture * rtex,unsigned level,const struct pipe_box * box,unsigned * stride,uintptr_t * layer_stride)156 static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
157 struct r600_texture *rtex, unsigned level,
158 const struct pipe_box *box,
159 unsigned *stride,
160 uintptr_t *layer_stride)
161 {
162 *stride = rtex->surface.u.legacy.level[level].nblk_x *
163 rtex->surface.bpe;
164 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
165 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
166
167 if (!box)
168 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
169
170 /* Each texture is an array of mipmap levels. Each level is
171 * an array of slices. */
172 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256 +
173 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
174 (box->y / rtex->surface.blk_h *
175 rtex->surface.u.legacy.level[level].nblk_x +
176 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
177 }
178
r600_init_surface(struct r600_common_screen * rscreen,struct radeon_surf * surface,const struct pipe_resource * ptex,enum radeon_surf_mode array_mode,unsigned pitch_in_bytes_override,unsigned offset,bool is_imported,bool is_scanout,bool is_flushed_depth)179 static int r600_init_surface(struct r600_common_screen *rscreen,
180 struct radeon_surf *surface,
181 const struct pipe_resource *ptex,
182 enum radeon_surf_mode array_mode,
183 unsigned pitch_in_bytes_override,
184 unsigned offset,
185 bool is_imported,
186 bool is_scanout,
187 bool is_flushed_depth)
188 {
189 const struct util_format_description *desc =
190 util_format_description(ptex->format);
191 bool is_depth, is_stencil;
192 int r;
193 unsigned i, bpe, flags = 0;
194
195 is_depth = util_format_has_depth(desc);
196 is_stencil = util_format_has_stencil(desc);
197
198 if (rscreen->gfx_level >= EVERGREEN && !is_flushed_depth &&
199 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
200 bpe = 4; /* stencil is allocated separately on evergreen */
201 } else {
202 bpe = util_format_get_blocksize(ptex->format);
203 assert(util_is_power_of_two_or_zero(bpe));
204 }
205
206 if (!is_flushed_depth && is_depth) {
207 flags |= RADEON_SURF_ZBUFFER;
208
209 if (is_stencil)
210 flags |= RADEON_SURF_SBUFFER;
211 }
212
213 if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
214 /* This should catch bugs in gallium users setting incorrect flags. */
215 assert(ptex->nr_samples <= 1 &&
216 ptex->array_size == 1 &&
217 ptex->depth0 == 1 &&
218 ptex->last_level == 0 &&
219 !(flags & RADEON_SURF_Z_OR_SBUFFER));
220
221 flags |= RADEON_SURF_SCANOUT;
222 }
223
224 if (ptex->bind & PIPE_BIND_SHARED)
225 flags |= RADEON_SURF_SHAREABLE;
226 if (is_imported)
227 flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
228
229 r = rscreen->ws->surface_init(rscreen->ws, &rscreen->info, ptex,
230 flags, bpe, array_mode, surface);
231 if (r) {
232 return r;
233 }
234
235 if (pitch_in_bytes_override &&
236 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
237 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
238 * for those
239 */
240 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
241 surface->u.legacy.level[0].slice_size_dw =
242 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4;
243 }
244
245 if (offset) {
246 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
247 surface->u.legacy.level[i].offset_256B += offset / 256;
248 }
249
250 return 0;
251 }
252
r600_texture_init_metadata(struct r600_common_screen * rscreen,struct r600_texture * rtex,struct radeon_bo_metadata * metadata)253 static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
254 struct r600_texture *rtex,
255 struct radeon_bo_metadata *metadata)
256 {
257 struct radeon_surf *surface = &rtex->surface;
258
259 memset(metadata, 0, sizeof(*metadata));
260
261 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
262 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
263 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
264 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
265 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
266 metadata->u.legacy.bankw = surface->u.legacy.bankw;
267 metadata->u.legacy.bankh = surface->u.legacy.bankh;
268 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
269 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
270 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
271 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
272 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
273 }
274
r600_surface_import_metadata(struct r600_common_screen * rscreen,struct radeon_surf * surf,struct radeon_bo_metadata * metadata,enum radeon_surf_mode * array_mode,bool * is_scanout)275 static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
276 struct radeon_surf *surf,
277 struct radeon_bo_metadata *metadata,
278 enum radeon_surf_mode *array_mode,
279 bool *is_scanout)
280 {
281 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
282 surf->u.legacy.bankw = metadata->u.legacy.bankw;
283 surf->u.legacy.bankh = metadata->u.legacy.bankh;
284 surf->u.legacy.tile_split = metadata->u.legacy.tile_split;
285 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
286 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
287
288 if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED)
289 *array_mode = RADEON_SURF_MODE_2D;
290 else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
291 *array_mode = RADEON_SURF_MODE_1D;
292 else
293 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
294
295 *is_scanout = metadata->u.legacy.scanout;
296 }
297
r600_eliminate_fast_color_clear(struct r600_common_context * rctx,struct r600_texture * rtex)298 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
299 struct r600_texture *rtex)
300 {
301 struct r600_common_screen *rscreen = rctx->screen;
302 struct pipe_context *ctx = &rctx->b;
303
304 if (ctx == rscreen->aux_context)
305 mtx_lock(&rscreen->aux_context_lock);
306
307 ctx->flush_resource(ctx, &rtex->resource.b.b);
308 ctx->flush(ctx, NULL, 0);
309
310 if (ctx == rscreen->aux_context)
311 mtx_unlock(&rscreen->aux_context_lock);
312 }
313
r600_texture_discard_cmask(struct r600_common_screen * rscreen,struct r600_texture * rtex)314 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
315 struct r600_texture *rtex)
316 {
317 if (!rtex->cmask.size)
318 return;
319
320 assert(rtex->resource.b.b.nr_samples <= 1);
321
322 /* Disable CMASK. */
323 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
324 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
325 rtex->dirty_level_mask = 0;
326
327 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
328
329 if (rtex->cmask_buffer != &rtex->resource)
330 r600_resource_reference(&rtex->cmask_buffer, NULL);
331
332 /* Notify all contexts about the change. */
333 p_atomic_inc(&rscreen->dirty_tex_counter);
334 p_atomic_inc(&rscreen->compressed_colortex_counter);
335 }
336
r600_reallocate_texture_inplace(struct r600_common_context * rctx,struct r600_texture * rtex,unsigned new_bind_flag,bool invalidate_storage)337 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
338 struct r600_texture *rtex,
339 unsigned new_bind_flag,
340 bool invalidate_storage)
341 {
342 struct pipe_screen *screen = rctx->b.screen;
343 struct r600_texture *new_tex;
344 struct pipe_resource templ = rtex->resource.b.b;
345 unsigned i;
346
347 templ.bind |= new_bind_flag;
348
349 /* r600g doesn't react to dirty_tex_descriptor_counter */
350 if (rctx->gfx_level < GFX6)
351 return;
352
353 if (rtex->resource.b.is_shared)
354 return;
355
356 if (new_bind_flag == PIPE_BIND_LINEAR) {
357 if (rtex->surface.is_linear)
358 return;
359
360 /* This fails with MSAA, depth, and compressed textures. */
361 if (r600_choose_tiling(rctx->screen, &templ) !=
362 RADEON_SURF_MODE_LINEAR_ALIGNED)
363 return;
364 }
365
366 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
367 if (!new_tex)
368 return;
369
370 /* Copy the pixels to the new texture. */
371 if (!invalidate_storage) {
372 for (i = 0; i <= templ.last_level; i++) {
373 struct pipe_box box;
374
375 u_box_3d(0, 0, 0,
376 u_minify(templ.width0, i), u_minify(templ.height0, i),
377 util_num_layers(&templ, i), &box);
378
379 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
380 &rtex->resource.b.b, i, &box);
381 }
382 }
383
384 if (new_bind_flag == PIPE_BIND_LINEAR) {
385 r600_texture_discard_cmask(rctx->screen, rtex);
386 }
387
388 /* Replace the structure fields of rtex. */
389 rtex->resource.b.b.bind = templ.bind;
390 radeon_bo_reference(rctx->ws, &rtex->resource.buf, new_tex->resource.buf);
391 rtex->resource.gpu_address = new_tex->resource.gpu_address;
392 rtex->resource.vram_usage = new_tex->resource.vram_usage;
393 rtex->resource.gart_usage = new_tex->resource.gart_usage;
394 rtex->resource.bo_size = new_tex->resource.bo_size;
395 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
396 rtex->resource.domains = new_tex->resource.domains;
397 rtex->resource.flags = new_tex->resource.flags;
398 rtex->size = new_tex->size;
399 rtex->db_render_format = new_tex->db_render_format;
400 rtex->db_compatible = new_tex->db_compatible;
401 rtex->can_sample_z = new_tex->can_sample_z;
402 rtex->can_sample_s = new_tex->can_sample_s;
403 rtex->surface = new_tex->surface;
404 rtex->fmask = new_tex->fmask;
405 rtex->cmask = new_tex->cmask;
406 rtex->cb_color_info = new_tex->cb_color_info;
407 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
408 rtex->htile_offset = new_tex->htile_offset;
409 rtex->depth_cleared = new_tex->depth_cleared;
410 rtex->stencil_cleared = new_tex->stencil_cleared;
411 rtex->non_disp_tiling = new_tex->non_disp_tiling;
412 rtex->framebuffers_bound = new_tex->framebuffers_bound;
413
414 if (new_bind_flag == PIPE_BIND_LINEAR) {
415 assert(!rtex->htile_offset);
416 assert(!rtex->cmask.size);
417 assert(!rtex->fmask.size);
418 assert(!rtex->is_depth);
419 }
420
421 r600_texture_reference(&new_tex, NULL);
422
423 p_atomic_inc(&rctx->screen->dirty_tex_counter);
424 }
425
r600_texture_get_info(struct pipe_screen * screen,struct pipe_resource * resource,unsigned * pstride,unsigned * poffset)426 static void r600_texture_get_info(struct pipe_screen* screen,
427 struct pipe_resource *resource,
428 unsigned *pstride,
429 unsigned *poffset)
430 {
431 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
432 struct r600_texture *rtex = (struct r600_texture*)resource;
433 unsigned stride = 0;
434 unsigned offset = 0;
435
436 if (!rscreen || !rtex)
437 return;
438
439 if (resource->target != PIPE_BUFFER) {
440 offset = (uint64_t)rtex->surface.u.legacy.level[0].offset_256B * 256;
441 stride = rtex->surface.u.legacy.level[0].nblk_x *
442 rtex->surface.bpe;
443 }
444
445 if (pstride)
446 *pstride = stride;
447
448 if (poffset)
449 *poffset = offset;
450 }
451
r600_texture_get_handle(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_resource * resource,struct winsys_handle * whandle,unsigned usage)452 static bool r600_texture_get_handle(struct pipe_screen* screen,
453 struct pipe_context *ctx,
454 struct pipe_resource *resource,
455 struct winsys_handle *whandle,
456 unsigned usage)
457 {
458 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
459 struct r600_common_context *rctx;
460 struct r600_resource *res = (struct r600_resource*)resource;
461 struct r600_texture *rtex = (struct r600_texture*)resource;
462 struct radeon_bo_metadata metadata;
463 bool update_metadata = false;
464 unsigned stride, offset, slice_size;
465
466 ctx = threaded_context_unwrap_sync(ctx);
467 rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
468
469 if (resource->target != PIPE_BUFFER) {
470 /* This is not supported now, but it might be required for OpenCL
471 * interop in the future.
472 */
473 if (resource->nr_samples > 1 || rtex->is_depth)
474 return false;
475
476 /* Move a suballocated texture into a non-suballocated allocation. */
477 if (rscreen->ws->buffer_is_suballocated(res->buf) ||
478 rtex->surface.tile_swizzle) {
479 assert(!res->b.is_shared);
480 r600_reallocate_texture_inplace(rctx, rtex,
481 PIPE_BIND_SHARED, false);
482 rctx->b.flush(&rctx->b, NULL, 0);
483 assert(res->b.b.bind & PIPE_BIND_SHARED);
484 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
485 assert(rtex->surface.tile_swizzle == 0);
486 }
487
488 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
489 rtex->cmask.size) {
490 /* Eliminate fast clear (CMASK) */
491 r600_eliminate_fast_color_clear(rctx, rtex);
492
493 /* Disable CMASK if flush_resource isn't going
494 * to be called.
495 */
496 if (rtex->cmask.size)
497 r600_texture_discard_cmask(rscreen, rtex);
498 }
499
500 /* Set metadata. */
501 if (!res->b.is_shared || update_metadata) {
502 r600_texture_init_metadata(rscreen, rtex, &metadata);
503
504 rscreen->ws->buffer_set_metadata(rscreen->ws, res->buf, &metadata, NULL);
505 }
506
507 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
508 } else {
509 /* Move a suballocated buffer into a non-suballocated allocation. */
510 if (rscreen->ws->buffer_is_suballocated(res->buf)) {
511 assert(!res->b.is_shared);
512
513 /* Allocate a new buffer with PIPE_BIND_SHARED. */
514 struct pipe_resource templ = res->b.b;
515 templ.bind |= PIPE_BIND_SHARED;
516
517 struct pipe_resource *newb =
518 screen->resource_create(screen, &templ);
519 if (!newb)
520 return false;
521
522 /* Copy the old buffer contents to the new one. */
523 struct pipe_box box;
524 u_box_1d(0, newb->width0, &box);
525 rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
526 &res->b.b, 0, &box);
527 /* Move the new buffer storage to the old pipe_resource. */
528 r600_replace_buffer_storage(&rctx->b, &res->b.b, newb);
529 pipe_resource_reference(&newb, NULL);
530
531 assert(res->b.b.bind & PIPE_BIND_SHARED);
532 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
533 }
534
535 /* Buffers */
536 slice_size = 0;
537 }
538
539 r600_texture_get_info(screen, resource, &stride, &offset);
540
541 if (res->b.is_shared) {
542 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
543 * doesn't set it.
544 */
545 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
546 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
547 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
548 } else {
549 res->b.is_shared = true;
550 res->external_usage = usage;
551 }
552
553 whandle->stride = stride;
554 whandle->offset = offset + slice_size * whandle->layer;
555
556 return rscreen->ws->buffer_get_handle(rscreen->ws, res->buf, whandle);
557 }
558
r600_texture_destroy(struct pipe_screen * screen,struct pipe_resource * ptex)559 void r600_texture_destroy(struct pipe_screen *screen, struct pipe_resource *ptex)
560 {
561 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
562 struct r600_texture *rtex = (struct r600_texture*)ptex;
563 struct r600_resource *resource = &rtex->resource;
564
565 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
566 pipe_resource_reference((struct pipe_resource**)&resource->immed_buffer, NULL);
567
568 if (rtex->cmask_buffer != &rtex->resource) {
569 r600_resource_reference(&rtex->cmask_buffer, NULL);
570 }
571 radeon_bo_reference(rscreen->ws, &resource->buf, NULL);
572 FREE(rtex);
573 }
574
575 /* The number of samples can be specified independently of the texture. */
r600_texture_get_fmask_info(struct r600_common_screen * rscreen,struct r600_texture * rtex,unsigned nr_samples,struct r600_fmask_info * out)576 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
577 struct r600_texture *rtex,
578 unsigned nr_samples,
579 struct r600_fmask_info *out)
580 {
581 /* FMASK is allocated like an ordinary texture. */
582 struct pipe_resource templ = rtex->resource.b.b;
583 struct radeon_surf fmask = {};
584 unsigned flags, bpe;
585
586 memset(out, 0, sizeof(*out));
587
588 templ.nr_samples = 1;
589 flags = rtex->surface.flags | RADEON_SURF_FMASK;
590
591 /* Use the same parameters and tile mode. */
592 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
593 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
594 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
595 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
596
597 if (nr_samples <= 4)
598 fmask.u.legacy.bankh = 4;
599
600 switch (nr_samples) {
601 case 2:
602 case 4:
603 bpe = 1;
604 break;
605 case 8:
606 bpe = 4;
607 break;
608 default:
609 R600_ERR("Invalid sample count for FMASK allocation.\n");
610 return;
611 }
612
613 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
614 * This can be fixed by writing a separate FMASK allocator specifically
615 * for R600-R700 asics. */
616 if (rscreen->gfx_level <= R700) {
617 bpe *= 2;
618 }
619
620 if (rscreen->ws->surface_init(rscreen->ws, &rscreen->info, &templ,
621 flags, bpe, RADEON_SURF_MODE_2D, &fmask)) {
622 R600_ERR("Got error in surface_init while allocating FMASK.\n");
623 return;
624 }
625
626 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
627
628 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
629 if (out->slice_tile_max)
630 out->slice_tile_max -= 1;
631
632 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
633 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
634 out->bank_height = fmask.u.legacy.bankh;
635 out->tile_swizzle = fmask.tile_swizzle;
636 out->alignment = MAX2(256, 1 << fmask.surf_alignment_log2);
637 out->size = fmask.surf_size;
638 }
639
r600_texture_allocate_fmask(struct r600_common_screen * rscreen,struct r600_texture * rtex)640 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
641 struct r600_texture *rtex)
642 {
643 r600_texture_get_fmask_info(rscreen, rtex,
644 rtex->resource.b.b.nr_samples, &rtex->fmask);
645
646 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
647 rtex->size = rtex->fmask.offset + rtex->fmask.size;
648 }
649
r600_texture_get_cmask_info(struct r600_common_screen * rscreen,struct r600_texture * rtex,struct r600_cmask_info * out)650 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
651 struct r600_texture *rtex,
652 struct r600_cmask_info *out)
653 {
654 unsigned cmask_tile_width = 8;
655 unsigned cmask_tile_height = 8;
656 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
657 unsigned element_bits = 4;
658 unsigned cmask_cache_bits = 1024;
659 unsigned num_pipes = rscreen->info.num_tile_pipes;
660 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
661
662 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
663 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
664 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
665 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
666 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
667
668 unsigned pitch_elements = align(rtex->resource.b.b.width0, macro_tile_width);
669 unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
670
671 unsigned base_align = num_pipes * pipe_interleave_bytes;
672 unsigned slice_bytes =
673 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
674
675 assert(macro_tile_width % 128 == 0);
676 assert(macro_tile_height % 128 == 0);
677
678 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
679 out->alignment = MAX2(256, base_align);
680 out->size = util_num_layers(&rtex->resource.b.b, 0) *
681 align(slice_bytes, base_align);
682 }
683
r600_texture_allocate_cmask(struct r600_common_screen * rscreen,struct r600_texture * rtex)684 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
685 struct r600_texture *rtex)
686 {
687 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
688
689 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
690 rtex->size = rtex->cmask.offset + rtex->cmask.size;
691
692 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
693 }
694
r600_texture_alloc_cmask_separate(struct r600_common_screen * rscreen,struct r600_texture * rtex)695 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
696 struct r600_texture *rtex)
697 {
698 if (rtex->cmask_buffer)
699 return;
700
701 assert(rtex->cmask.size == 0);
702
703 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
704
705 rtex->cmask_buffer = (struct r600_resource *)
706 r600_aligned_buffer_create(&rscreen->b,
707 R600_RESOURCE_FLAG_UNMAPPABLE,
708 PIPE_USAGE_DEFAULT,
709 rtex->cmask.size,
710 rtex->cmask.alignment);
711 if (rtex->cmask_buffer == NULL) {
712 rtex->cmask.size = 0;
713 return;
714 }
715
716 /* update colorbuffer state bits */
717 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
718
719 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
720
721 p_atomic_inc(&rscreen->compressed_colortex_counter);
722 }
723
eg_resource_alloc_immed(struct r600_common_screen * rscreen,struct r600_resource * res,unsigned immed_size)724 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
725 struct r600_resource *res,
726 unsigned immed_size)
727 {
728 res->immed_buffer = (struct r600_resource *)
729 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
730 PIPE_USAGE_DEFAULT, immed_size);
731 }
732
r600_texture_get_htile_size(struct r600_common_screen * rscreen,struct r600_texture * rtex)733 static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
734 struct r600_texture *rtex)
735 {
736 unsigned cl_width, cl_height, width, height;
737 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
738 unsigned num_pipes = rscreen->info.num_tile_pipes;
739
740 rtex->surface.meta_size = 0;
741
742 /* HW bug on R6xx. */
743 if (rscreen->gfx_level == R600 &&
744 (rtex->resource.b.b.width0 > 7680 ||
745 rtex->resource.b.b.height0 > 7680))
746 return;
747
748 switch (num_pipes) {
749 case 1:
750 cl_width = 32;
751 cl_height = 16;
752 break;
753 case 2:
754 cl_width = 32;
755 cl_height = 32;
756 break;
757 case 4:
758 cl_width = 64;
759 cl_height = 32;
760 break;
761 case 8:
762 cl_width = 64;
763 cl_height = 64;
764 break;
765 case 16:
766 cl_width = 128;
767 cl_height = 64;
768 break;
769 default:
770 assert(0);
771 return;
772 }
773
774 width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
775 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
776
777 slice_elements = (width * height) / (8 * 8);
778 slice_bytes = slice_elements * 4;
779
780 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
781 base_align = num_pipes * pipe_interleave_bytes;
782
783 rtex->surface.meta_alignment_log2 = util_logbase2(base_align);
784 rtex->surface.meta_size =
785 util_num_layers(&rtex->resource.b.b, 0) *
786 align(slice_bytes, base_align);
787 }
788
r600_texture_allocate_htile(struct r600_common_screen * rscreen,struct r600_texture * rtex)789 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
790 struct r600_texture *rtex)
791 {
792 r600_texture_get_htile_size(rscreen, rtex);
793
794 if (!rtex->surface.meta_size)
795 return;
796
797 rtex->htile_offset = align(rtex->size, 1 << rtex->surface.meta_alignment_log2);
798 rtex->size = rtex->htile_offset + rtex->surface.meta_size;
799 }
800
r600_print_texture_info(struct r600_common_screen * rscreen,struct r600_texture * rtex,struct u_log_context * log)801 void r600_print_texture_info(struct r600_common_screen *rscreen,
802 struct r600_texture *rtex, struct u_log_context *log)
803 {
804 int i;
805
806 /* Common parameters. */
807 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
808 "blk_h=%u, array_size=%u, last_level=%u, "
809 "bpe=%u, nsamples=%u, flags=0x%"PRIx64", %s\n",
810 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
811 rtex->resource.b.b.depth0, rtex->surface.blk_w,
812 rtex->surface.blk_h,
813 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
814 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
815 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
816
817 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
818 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
819 rtex->surface.surf_size, 1 << rtex->surface.surf_alignment_log2, rtex->surface.u.legacy.bankw,
820 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
821 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
822 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
823
824 if (rtex->fmask.size)
825 u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
826 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
827 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
828 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
829 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
830
831 if (rtex->cmask.size)
832 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
833 "slice_tile_max=%u\n",
834 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
835 rtex->cmask.slice_tile_max);
836
837 if (rtex->htile_offset)
838 u_log_printf(log, " HTile: offset=%"PRIu64", size=%u "
839 "alignment=%u\n",
840 rtex->htile_offset, rtex->surface.meta_size,
841 1 << rtex->surface.meta_alignment_log2);
842
843 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
844 u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
845 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
846 "mode=%u, tiling_index = %u\n",
847 i, (uint64_t)rtex->surface.u.legacy.level[i].offset_256B * 256,
848 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
849 u_minify(rtex->resource.b.b.width0, i),
850 u_minify(rtex->resource.b.b.height0, i),
851 u_minify(rtex->resource.b.b.depth0, i),
852 rtex->surface.u.legacy.level[i].nblk_x,
853 rtex->surface.u.legacy.level[i].nblk_y,
854 rtex->surface.u.legacy.level[i].mode,
855 rtex->surface.u.legacy.tiling_index[i]);
856
857 if (rtex->surface.has_stencil) {
858 u_log_printf(log, " StencilLayout: tilesplit=%u\n",
859 rtex->surface.u.legacy.stencil_tile_split);
860 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
861 u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
862 "slice_size=%"PRIu64", npix_x=%u, "
863 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
864 "mode=%u, tiling_index = %u\n",
865 i, (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256,
866 (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].slice_size_dw * 4,
867 u_minify(rtex->resource.b.b.width0, i),
868 u_minify(rtex->resource.b.b.height0, i),
869 u_minify(rtex->resource.b.b.depth0, i),
870 rtex->surface.u.legacy.zs.stencil_level[i].nblk_x,
871 rtex->surface.u.legacy.zs.stencil_level[i].nblk_y,
872 rtex->surface.u.legacy.zs.stencil_level[i].mode,
873 rtex->surface.u.legacy.zs.stencil_tiling_index[i]);
874 }
875 }
876 }
877
878 /* Common processing for r600_texture_create and r600_texture_from_handle */
879 static struct r600_texture *
r600_texture_create_object(struct pipe_screen * screen,const struct pipe_resource * base,struct pb_buffer_lean * buf,struct radeon_surf * surface)880 r600_texture_create_object(struct pipe_screen *screen,
881 const struct pipe_resource *base,
882 struct pb_buffer_lean *buf,
883 struct radeon_surf *surface)
884 {
885 struct r600_texture *rtex;
886 struct r600_resource *resource;
887 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
888
889 rtex = CALLOC_STRUCT(r600_texture);
890 if (!rtex)
891 return NULL;
892
893 resource = &rtex->resource;
894 resource->b.b = *base;
895 pipe_reference_init(&resource->b.b.reference, 1);
896 resource->b.b.screen = screen;
897
898 /* don't include stencil-only formats which we don't support for rendering */
899 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
900
901 rtex->surface = *surface;
902 rtex->size = rtex->surface.surf_size;
903 rtex->db_render_format = base->format;
904
905 /* Tiled depth textures utilize the non-displayable tile order.
906 * This must be done after r600_setup_surface.
907 * Applies to R600-Cayman. */
908 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
909 /* Applies to GCN. */
910 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
911
912 if (rtex->is_depth) {
913 if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
914 R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
915 rscreen->gfx_level >= EVERGREEN) {
916 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
917 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
918 } else {
919 if (rtex->resource.b.b.nr_samples <= 1 &&
920 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
921 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT))
922 rtex->can_sample_z = true;
923 }
924
925 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
926 R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
927 rtex->db_compatible = true;
928
929 if (!(rscreen->debug_flags & DBG_NO_HYPERZ))
930 r600_texture_allocate_htile(rscreen, rtex);
931 }
932 } else {
933 if (base->nr_samples > 1) {
934 if (!buf) {
935 r600_texture_allocate_fmask(rscreen, rtex);
936 r600_texture_allocate_cmask(rscreen, rtex);
937 rtex->cmask_buffer = &rtex->resource;
938 }
939 if (!rtex->fmask.size || !rtex->cmask.size) {
940 FREE(rtex);
941 return NULL;
942 }
943 }
944 }
945
946 /* Now create the backing buffer. */
947 if (!buf) {
948 r600_init_resource_fields(rscreen, resource, rtex->size,
949 1 << rtex->surface.surf_alignment_log2);
950
951 if (!r600_alloc_resource(rscreen, resource)) {
952 FREE(rtex);
953 return NULL;
954 }
955 } else {
956 resource->buf = buf;
957 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
958 resource->bo_size = buf->size;
959 resource->bo_alignment = 1 << buf->alignment_log2;
960 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
961 if (resource->domains & RADEON_DOMAIN_VRAM)
962 resource->vram_usage = buf->size;
963 else if (resource->domains & RADEON_DOMAIN_GTT)
964 resource->gart_usage = buf->size;
965 }
966
967 if (rtex->cmask.size) {
968 /* Initialize the cmask to 0xCC (= compressed state). */
969 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
970 rtex->cmask.offset, rtex->cmask.size,
971 0xCCCCCCCC);
972 }
973 if (rtex->htile_offset) {
974 uint32_t clear_value = 0;
975
976 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
977 rtex->htile_offset,
978 rtex->surface.meta_size,
979 clear_value);
980 }
981
982 /* Initialize the CMASK base register value. */
983 rtex->cmask.base_address_reg =
984 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
985
986 if (rscreen->debug_flags & DBG_VM) {
987 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
988 rtex->resource.gpu_address,
989 rtex->resource.gpu_address + rtex->resource.buf->size,
990 base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
991 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
992 }
993
994 if (rscreen->debug_flags & DBG_TEX) {
995 puts("Texture:");
996 struct u_log_context log;
997 u_log_context_init(&log);
998 r600_print_texture_info(rscreen, rtex, &log);
999 u_log_new_page_print(&log, stdout);
1000 fflush(stdout);
1001 u_log_context_destroy(&log);
1002 }
1003
1004 return rtex;
1005 }
1006
1007 static enum radeon_surf_mode
r600_choose_tiling(struct r600_common_screen * rscreen,const struct pipe_resource * templ)1008 r600_choose_tiling(struct r600_common_screen *rscreen,
1009 const struct pipe_resource *templ)
1010 {
1011 const struct util_format_description *desc = util_format_description(templ->format);
1012 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1013 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1014 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1015
1016 /* MSAA resources must be 2D tiled. */
1017 if (templ->nr_samples > 1)
1018 return RADEON_SURF_MODE_2D;
1019
1020 /* Transfer resources should be linear. */
1021 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1022 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1023
1024 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1025 if (rscreen->gfx_level >= R600 && rscreen->gfx_level <= CAYMAN &&
1026 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
1027 (templ->target == PIPE_TEXTURE_2D ||
1028 templ->target == PIPE_TEXTURE_3D))
1029 force_tiling = true;
1030
1031 /* Handle common candidates for the linear mode.
1032 * Compressed textures and DB surfaces must always be tiled.
1033 */
1034 if (!force_tiling &&
1035 !is_depth_stencil &&
1036 !util_format_is_compressed(templ->format)) {
1037 if (rscreen->debug_flags & DBG_NO_TILING)
1038 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1039
1040 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1041 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1042 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1043
1044 if (templ->bind & PIPE_BIND_LINEAR)
1045 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1046
1047 /* 1D textures should be linear - fixes image operations on 1d */
1048 if (templ->target == PIPE_TEXTURE_1D ||
1049 templ->target == PIPE_TEXTURE_1D_ARRAY)
1050 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1051
1052 /* Textures likely to be mapped often. */
1053 if (templ->usage == PIPE_USAGE_STAGING ||
1054 templ->usage == PIPE_USAGE_STREAM)
1055 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1056 }
1057
1058 /* Make small textures 1D tiled. */
1059 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1060 (rscreen->debug_flags & DBG_NO_2D_TILING))
1061 return RADEON_SURF_MODE_1D;
1062
1063 /* The allocator will switch to 1D if needed. */
1064 return RADEON_SURF_MODE_2D;
1065 }
1066
r600_texture_create(struct pipe_screen * screen,const struct pipe_resource * templ)1067 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
1068 const struct pipe_resource *templ)
1069 {
1070 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1071 struct radeon_surf surface = {0};
1072 bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1073 int r;
1074
1075 r = r600_init_surface(rscreen, &surface, templ,
1076 r600_choose_tiling(rscreen, templ), 0, 0,
1077 false, false, is_flushed_depth);
1078 if (r) {
1079 return NULL;
1080 }
1081
1082 return (struct pipe_resource *)
1083 r600_texture_create_object(screen, templ, NULL, &surface);
1084 }
1085
r600_texture_from_handle(struct pipe_screen * screen,const struct pipe_resource * templ,struct winsys_handle * whandle,unsigned usage)1086 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1087 const struct pipe_resource *templ,
1088 struct winsys_handle *whandle,
1089 unsigned usage)
1090 {
1091 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1092 struct pb_buffer_lean *buf = NULL;
1093 enum radeon_surf_mode array_mode;
1094 struct radeon_surf surface = {};
1095 int r;
1096 struct radeon_bo_metadata metadata = {};
1097 struct r600_texture *rtex;
1098 bool is_scanout;
1099
1100 /* Support only 2D textures without mipmaps */
1101 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1102 templ->depth0 != 1 || templ->last_level != 0)
1103 return NULL;
1104
1105 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1106 rscreen->info.max_alignment, false);
1107 if (!buf)
1108 return NULL;
1109
1110 rscreen->ws->buffer_get_metadata(rscreen->ws, buf, &metadata, NULL);
1111 r600_surface_import_metadata(rscreen, &surface, &metadata,
1112 &array_mode, &is_scanout);
1113
1114 r = r600_init_surface(rscreen, &surface, templ, array_mode,
1115 whandle->stride, whandle->offset,
1116 true, is_scanout, false);
1117 if (r) {
1118 return NULL;
1119 }
1120
1121 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1122 if (!rtex)
1123 return NULL;
1124
1125 rtex->resource.b.is_shared = true;
1126 rtex->resource.external_usage = usage;
1127
1128 assert(rtex->surface.tile_swizzle == 0);
1129 return &rtex->resource.b.b;
1130 }
1131
r600_init_flushed_depth_texture(struct pipe_context * ctx,struct pipe_resource * texture,struct r600_texture ** staging)1132 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1133 struct pipe_resource *texture,
1134 struct r600_texture **staging)
1135 {
1136 struct r600_texture *rtex = (struct r600_texture*)texture;
1137 struct pipe_resource resource;
1138 struct r600_texture **flushed_depth_texture = staging ?
1139 staging : &rtex->flushed_depth_texture;
1140 enum pipe_format pipe_format = texture->format;
1141
1142 if (!staging) {
1143 if (rtex->flushed_depth_texture)
1144 return true; /* it's ready */
1145
1146 if (!rtex->can_sample_z && rtex->can_sample_s) {
1147 switch (pipe_format) {
1148 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1149 /* Save memory by not allocating the S plane. */
1150 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1151 break;
1152 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1153 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1154 /* Save memory bandwidth by not copying the
1155 * stencil part during flush.
1156 *
1157 * This potentially increases memory bandwidth
1158 * if an application uses both Z and S texturing
1159 * simultaneously (a flushed Z24S8 texture
1160 * would be stored compactly), but how often
1161 * does that really happen?
1162 */
1163 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1164 break;
1165 default:;
1166 }
1167 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1168 assert(util_format_has_stencil(util_format_description(pipe_format)));
1169
1170 /* DB->CB copies to an 8bpp surface don't work. */
1171 pipe_format = PIPE_FORMAT_X24S8_UINT;
1172 }
1173 }
1174
1175 memset(&resource, 0, sizeof(resource));
1176 resource.target = texture->target;
1177 resource.format = pipe_format;
1178 resource.width0 = texture->width0;
1179 resource.height0 = texture->height0;
1180 resource.depth0 = texture->depth0;
1181 resource.array_size = texture->array_size;
1182 resource.last_level = texture->last_level;
1183 resource.nr_samples = texture->nr_samples;
1184 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1185 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1186 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1187
1188 if (staging)
1189 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1190
1191 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1192 if (*flushed_depth_texture == NULL) {
1193 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1194 return false;
1195 }
1196
1197 (*flushed_depth_texture)->non_disp_tiling = false;
1198 return true;
1199 }
1200
1201 /**
1202 * Initialize the pipe_resource descriptor to be of the same size as the box,
1203 * which is supposed to hold a subregion of the texture "orig" at the given
1204 * mipmap level.
1205 */
r600_init_temp_resource_from_box(struct pipe_resource * res,struct pipe_resource * orig,const struct pipe_box * box,unsigned level,unsigned flags)1206 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1207 struct pipe_resource *orig,
1208 const struct pipe_box *box,
1209 unsigned level, unsigned flags)
1210 {
1211 memset(res, 0, sizeof(*res));
1212 res->format = orig->format;
1213 res->width0 = box->width;
1214 res->height0 = box->height;
1215 res->depth0 = 1;
1216 res->array_size = 1;
1217 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1218 res->flags = flags;
1219
1220 /* We must set the correct texture target and dimensions for a 3D box. */
1221 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1222 res->target = PIPE_TEXTURE_2D_ARRAY;
1223 res->array_size = box->depth;
1224 } else {
1225 res->target = PIPE_TEXTURE_2D;
1226 }
1227 }
1228
r600_can_invalidate_texture(struct r600_common_screen * rscreen,struct r600_texture * rtex,unsigned transfer_usage,const struct pipe_box * box)1229 static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
1230 struct r600_texture *rtex,
1231 unsigned transfer_usage,
1232 const struct pipe_box *box)
1233 {
1234 /* r600g doesn't react to dirty_tex_descriptor_counter */
1235 return rscreen->gfx_level >= GFX6 &&
1236 !rtex->resource.b.is_shared &&
1237 !(transfer_usage & PIPE_MAP_READ) &&
1238 rtex->resource.b.b.last_level == 0 &&
1239 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1240 box->x, box->y, box->z,
1241 box->width, box->height,
1242 box->depth);
1243 }
1244
r600_texture_invalidate_storage(struct r600_common_context * rctx,struct r600_texture * rtex)1245 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1246 struct r600_texture *rtex)
1247 {
1248 struct r600_common_screen *rscreen = rctx->screen;
1249
1250 /* There is no point in discarding depth and tiled buffers. */
1251 assert(!rtex->is_depth);
1252 assert(rtex->surface.is_linear);
1253
1254 /* Reallocate the buffer in the same pipe_resource. */
1255 r600_alloc_resource(rscreen, &rtex->resource);
1256
1257 /* Initialize the CMASK base address (needed even without CMASK). */
1258 rtex->cmask.base_address_reg =
1259 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1260
1261 p_atomic_inc(&rscreen->dirty_tex_counter);
1262
1263 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1264 }
1265
r600_texture_transfer_map(struct pipe_context * ctx,struct pipe_resource * texture,unsigned level,unsigned usage,const struct pipe_box * box,struct pipe_transfer ** ptransfer)1266 void *r600_texture_transfer_map(struct pipe_context *ctx,
1267 struct pipe_resource *texture,
1268 unsigned level,
1269 unsigned usage,
1270 const struct pipe_box *box,
1271 struct pipe_transfer **ptransfer)
1272 {
1273 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1274 struct r600_texture *rtex = (struct r600_texture*)texture;
1275 struct r600_transfer *trans;
1276 struct r600_resource *buf;
1277 unsigned offset = 0;
1278 char *map;
1279 bool use_staging_texture = false;
1280
1281 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1282 assert(box->width && box->height && box->depth);
1283
1284 /* Depth textures use staging unconditionally. */
1285 if (!rtex->is_depth) {
1286 /* Degrade the tile mode if we get too many transfers on APUs.
1287 * On dGPUs, the staging texture is always faster.
1288 * Only count uploads that are at least 4x4 pixels large.
1289 */
1290 if (!rctx->screen->info.has_dedicated_vram &&
1291 level == 0 &&
1292 box->width >= 4 && box->height >= 4 &&
1293 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1294 bool can_invalidate =
1295 r600_can_invalidate_texture(rctx->screen, rtex,
1296 usage, box);
1297
1298 r600_reallocate_texture_inplace(rctx, rtex,
1299 PIPE_BIND_LINEAR,
1300 can_invalidate);
1301 }
1302
1303 /* Tiled textures need to be converted into a linear texture for CPU
1304 * access. The staging texture is always linear and is placed in GART.
1305 *
1306 * Reading from VRAM or GTT WC is slow, always use the staging
1307 * texture in this case.
1308 *
1309 * Use the staging texture for uploads if the underlying BO
1310 * is busy.
1311 */
1312 if (!rtex->surface.is_linear)
1313 use_staging_texture = true;
1314 else if (usage & PIPE_MAP_READ)
1315 use_staging_texture =
1316 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1317 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1318 /* Write & linear only: */
1319 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1320 RADEON_USAGE_READWRITE) ||
1321 !rctx->ws->buffer_wait(rctx->ws, rtex->resource.buf, 0,
1322 RADEON_USAGE_READWRITE)) {
1323 /* It's busy. */
1324 if (r600_can_invalidate_texture(rctx->screen, rtex,
1325 usage, box))
1326 r600_texture_invalidate_storage(rctx, rtex);
1327 else
1328 use_staging_texture = true;
1329 }
1330 }
1331
1332 trans = CALLOC_STRUCT(r600_transfer);
1333 if (!trans)
1334 return NULL;
1335 pipe_resource_reference(&trans->b.b.resource, texture);
1336 trans->b.b.level = level;
1337 trans->b.b.usage = usage;
1338 trans->b.b.box = *box;
1339
1340 if (rtex->is_depth) {
1341 struct r600_texture *staging_depth;
1342
1343 if (rtex->resource.b.b.nr_samples > 1) {
1344 /* MSAA depth buffers need to be converted to single sample buffers.
1345 *
1346 * Mapping MSAA depth buffers can occur if ReadPixels is called
1347 * with a multisample GLX visual.
1348 *
1349 * First downsample the depth buffer to a temporary texture,
1350 * then decompress the temporary one to staging.
1351 *
1352 * Only the region being mapped is transferred.
1353 */
1354 struct pipe_resource resource;
1355
1356 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1357
1358 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1359 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1360 FREE(trans);
1361 return NULL;
1362 }
1363
1364 if (usage & PIPE_MAP_READ) {
1365 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1366 if (!temp) {
1367 R600_ERR("failed to create a temporary depth texture\n");
1368 FREE(trans);
1369 return NULL;
1370 }
1371
1372 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1373 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1374 0, 0, 0, box->depth, 0, 0);
1375 pipe_resource_reference(&temp, NULL);
1376 }
1377
1378 /* Just get the strides. */
1379 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1380 &trans->b.b.stride,
1381 &trans->b.b.layer_stride);
1382 } else {
1383 /* XXX: only readback the rectangle which is being mapped? */
1384 /* XXX: when discard is true, no need to read back from depth texture */
1385 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1386 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1387 FREE(trans);
1388 return NULL;
1389 }
1390
1391 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1392 level, level,
1393 box->z, box->z + box->depth - 1,
1394 0, 0);
1395
1396 offset = r600_texture_get_offset(rctx->screen, staging_depth,
1397 level, box,
1398 &trans->b.b.stride,
1399 &trans->b.b.layer_stride);
1400 }
1401
1402 trans->staging = (struct r600_resource*)staging_depth;
1403 buf = trans->staging;
1404 } else if (use_staging_texture) {
1405 struct pipe_resource resource;
1406 struct r600_texture *staging;
1407
1408 r600_init_temp_resource_from_box(&resource, texture, box, level,
1409 R600_RESOURCE_FLAG_TRANSFER);
1410 resource.usage = (usage & PIPE_MAP_READ) ?
1411 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1412
1413 /* Create the temporary texture. */
1414 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1415 if (!staging) {
1416 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1417 FREE(trans);
1418 return NULL;
1419 }
1420 trans->staging = &staging->resource;
1421
1422 /* Just get the strides. */
1423 r600_texture_get_offset(rctx->screen, staging, 0, NULL,
1424 &trans->b.b.stride,
1425 &trans->b.b.layer_stride);
1426
1427 if (usage & PIPE_MAP_READ)
1428 r600_copy_to_staging_texture(ctx, trans);
1429 else
1430 usage |= PIPE_MAP_UNSYNCHRONIZED;
1431
1432 buf = trans->staging;
1433 } else {
1434 /* the resource is mapped directly */
1435 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1436 &trans->b.b.stride,
1437 &trans->b.b.layer_stride);
1438 buf = &rtex->resource;
1439 }
1440
1441 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1442 r600_resource_reference(&trans->staging, NULL);
1443 FREE(trans);
1444 return NULL;
1445 }
1446
1447 *ptransfer = &trans->b.b;
1448 return map + offset;
1449 }
1450
r600_texture_transfer_unmap(struct pipe_context * ctx,struct pipe_transfer * transfer)1451 void r600_texture_transfer_unmap(struct pipe_context *ctx,
1452 struct pipe_transfer* transfer)
1453 {
1454 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1455 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1456 struct pipe_resource *texture = transfer->resource;
1457 struct r600_texture *rtex = (struct r600_texture*)texture;
1458
1459 if ((transfer->usage & PIPE_MAP_WRITE) && rtransfer->staging) {
1460 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1461 ctx->resource_copy_region(ctx, texture, transfer->level,
1462 transfer->box.x, transfer->box.y, transfer->box.z,
1463 &rtransfer->staging->b.b, transfer->level,
1464 &transfer->box);
1465 } else {
1466 r600_copy_from_staging_texture(ctx, rtransfer);
1467 }
1468 }
1469
1470 if (rtransfer->staging) {
1471 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1472 r600_resource_reference(&rtransfer->staging, NULL);
1473 }
1474
1475 /* Heuristic for {upload, draw, upload, draw, ..}:
1476 *
1477 * Flush the gfx IB if we've allocated too much texture storage.
1478 *
1479 * The idea is that we don't want to build IBs that use too much
1480 * memory and put pressure on the kernel memory manager and we also
1481 * want to make temporary and invalidated buffers go idle ASAP to
1482 * decrease the total memory usage or make them reusable. The memory
1483 * usage will be slightly higher than given here because of the buffer
1484 * cache in the winsys.
1485 *
1486 * The result is that the kernel memory manager is never a bottleneck.
1487 */
1488 if (rctx->num_alloc_tex_transfer_bytes > (uint64_t)rctx->screen->info.gart_size_kb * 1024 / 4) {
1489 rctx->gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1490 rctx->num_alloc_tex_transfer_bytes = 0;
1491 }
1492
1493 pipe_resource_reference(&transfer->resource, NULL);
1494 FREE(transfer);
1495 }
1496
r600_create_surface_custom(struct pipe_context * pipe,struct pipe_resource * texture,const struct pipe_surface * templ,unsigned width0,unsigned height0,unsigned width,unsigned height)1497 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1498 struct pipe_resource *texture,
1499 const struct pipe_surface *templ,
1500 unsigned width0, unsigned height0,
1501 unsigned width, unsigned height)
1502 {
1503 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1504
1505 if (!surface)
1506 return NULL;
1507
1508 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1509 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1510
1511 pipe_reference_init(&surface->base.reference, 1);
1512 pipe_resource_reference(&surface->base.texture, texture);
1513 surface->base.context = pipe;
1514 surface->base.format = templ->format;
1515 surface->base.width = width;
1516 surface->base.height = height;
1517 surface->base.u = templ->u;
1518
1519 surface->width0 = width0;
1520 surface->height0 = height0;
1521
1522 return &surface->base;
1523 }
1524
r600_create_surface(struct pipe_context * pipe,struct pipe_resource * tex,const struct pipe_surface * templ)1525 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1526 struct pipe_resource *tex,
1527 const struct pipe_surface *templ)
1528 {
1529 unsigned level = templ->u.tex.level;
1530 unsigned width = u_minify(tex->width0, level);
1531 unsigned height = u_minify(tex->height0, level);
1532 unsigned width0 = tex->width0;
1533 unsigned height0 = tex->height0;
1534
1535 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1536 const struct util_format_description *tex_desc
1537 = util_format_description(tex->format);
1538 const struct util_format_description *templ_desc
1539 = util_format_description(templ->format);
1540
1541 assert(tex_desc->block.bits == templ_desc->block.bits);
1542
1543 /* Adjust size of surface if and only if the block width or
1544 * height is changed. */
1545 if (tex_desc->block.width != templ_desc->block.width ||
1546 tex_desc->block.height != templ_desc->block.height) {
1547 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1548 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1549
1550 width = nblks_x * templ_desc->block.width;
1551 height = nblks_y * templ_desc->block.height;
1552
1553 width0 = util_format_get_nblocksx(tex->format, width0);
1554 height0 = util_format_get_nblocksy(tex->format, height0);
1555 }
1556 }
1557
1558 return r600_create_surface_custom(pipe, tex, templ,
1559 width0, height0,
1560 width, height);
1561 }
1562
r600_surface_destroy(struct pipe_context * pipe,struct pipe_surface * surface)1563 static void r600_surface_destroy(struct pipe_context *pipe,
1564 struct pipe_surface *surface)
1565 {
1566 struct r600_surface *surf = (struct r600_surface*)surface;
1567 r600_resource_reference(&surf->cb_buffer_fmask, NULL);
1568 r600_resource_reference(&surf->cb_buffer_cmask, NULL);
1569 pipe_resource_reference(&surface->texture, NULL);
1570 FREE(surface);
1571 }
1572
r600_translate_colorswap(enum pipe_format format,bool do_endian_swap)1573 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1574 {
1575 const struct util_format_description *desc = util_format_description(format);
1576
1577 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1578
1579 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1580 return V_0280A0_SWAP_STD;
1581
1582 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1583 return ~0U;
1584
1585 switch (desc->nr_channels) {
1586 case 1:
1587 if (HAS_SWIZZLE(0,X))
1588 return V_0280A0_SWAP_STD; /* X___ */
1589 else if (HAS_SWIZZLE(3,X))
1590 return V_0280A0_SWAP_ALT_REV; /* ___X */
1591 break;
1592 case 2:
1593 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1594 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1595 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1596 return V_0280A0_SWAP_STD; /* XY__ */
1597 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1598 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1599 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1600 /* YX__ */
1601 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1602 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1603 return V_0280A0_SWAP_ALT; /* X__Y */
1604 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1605 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1606 break;
1607 case 3:
1608 if (HAS_SWIZZLE(0,X))
1609 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1610 else if (HAS_SWIZZLE(0,Z))
1611 return V_0280A0_SWAP_STD_REV; /* ZYX */
1612 break;
1613 case 4:
1614 /* check the middle channels, the 1st and 4th channel can be NONE */
1615 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1616 return V_0280A0_SWAP_STD; /* XYZW */
1617 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1618 return V_0280A0_SWAP_STD_REV; /* WZYX */
1619 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1620 return V_0280A0_SWAP_ALT; /* ZYXW */
1621 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1622 /* YZWX */
1623 if (desc->is_array)
1624 return V_0280A0_SWAP_ALT_REV;
1625 else
1626 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1627 }
1628 break;
1629 }
1630 return ~0U;
1631 }
1632
1633 /* FAST COLOR CLEAR */
1634
evergreen_set_clear_color(struct r600_texture * rtex,enum pipe_format surface_format,const union pipe_color_union * color)1635 static void evergreen_set_clear_color(struct r600_texture *rtex,
1636 enum pipe_format surface_format,
1637 const union pipe_color_union *color)
1638 {
1639 union util_color uc;
1640
1641 memset(&uc, 0, sizeof(uc));
1642
1643 if (rtex->surface.bpe == 16) {
1644 /* DCC fast clear only:
1645 * CLEAR_WORD0 = R = G = B
1646 * CLEAR_WORD1 = A
1647 */
1648 assert(color->ui[0] == color->ui[1] &&
1649 color->ui[0] == color->ui[2]);
1650 uc.ui[0] = color->ui[0];
1651 uc.ui[1] = color->ui[3];
1652 } else {
1653 util_pack_color_union(surface_format, &uc, color);
1654 }
1655
1656 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1657 }
1658
evergreen_do_fast_color_clear(struct r600_common_context * rctx,struct pipe_framebuffer_state * fb,struct r600_atom * fb_state,unsigned * buffers,uint8_t * dirty_cbufs,const union pipe_color_union * color)1659 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1660 struct pipe_framebuffer_state *fb,
1661 struct r600_atom *fb_state,
1662 unsigned *buffers, uint8_t *dirty_cbufs,
1663 const union pipe_color_union *color)
1664 {
1665 int i;
1666
1667 /* This function is broken in BE, so just disable this path for now */
1668 #if UTIL_ARCH_BIG_ENDIAN
1669 return;
1670 #endif
1671
1672 if (rctx->render_cond)
1673 return;
1674
1675 for (i = 0; i < fb->nr_cbufs; i++) {
1676 struct r600_texture *tex;
1677 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1678
1679 if (!fb->cbufs[i])
1680 continue;
1681
1682 /* if this colorbuffer is not being cleared */
1683 if (!(*buffers & clear_bit))
1684 continue;
1685
1686 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1687
1688 /* the clear is allowed if all layers are bound */
1689 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1690 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1691 continue;
1692 }
1693
1694 /* cannot clear mipmapped textures */
1695 if (fb->cbufs[i]->texture->last_level != 0) {
1696 continue;
1697 }
1698
1699 /* only supported on tiled surfaces */
1700 if (tex->surface.is_linear) {
1701 continue;
1702 }
1703
1704 /* shared textures can't use fast clear without an explicit flush,
1705 * because there is no way to communicate the clear color among
1706 * all clients
1707 */
1708 if (tex->resource.b.is_shared &&
1709 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1710 continue;
1711
1712 /* Use a slow clear for small surfaces where the cost of
1713 * the eliminate pass can be higher than the benefit of fast
1714 * clear. AMDGPU-pro does this, but the numbers may differ.
1715 *
1716 * This helps on both dGPUs and APUs, even small ones.
1717 */
1718 if (tex->resource.b.b.nr_samples <= 1 &&
1719 tex->resource.b.b.width0 * tex->resource.b.b.height0 <= 300 * 300)
1720 continue;
1721
1722 {
1723 /* 128-bit formats are unusupported */
1724 if (tex->surface.bpe > 8) {
1725 continue;
1726 }
1727
1728 /* ensure CMASK is enabled */
1729 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1730 if (tex->cmask.size == 0) {
1731 continue;
1732 }
1733
1734 /* Do the fast clear. */
1735 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1736 tex->cmask.offset, tex->cmask.size, 0,
1737 R600_COHERENCY_CB_META);
1738
1739 bool need_compressed_update = !tex->dirty_level_mask;
1740
1741 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1742
1743 if (need_compressed_update)
1744 p_atomic_inc(&rctx->screen->compressed_colortex_counter);
1745 }
1746
1747 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1748
1749 if (dirty_cbufs)
1750 *dirty_cbufs |= 1 << i;
1751 rctx->set_atom_dirty(rctx, fb_state, true);
1752 *buffers &= ~clear_bit;
1753 }
1754 }
1755
1756 static struct pipe_memory_object *
r600_memobj_from_handle(struct pipe_screen * screen,struct winsys_handle * whandle,bool dedicated)1757 r600_memobj_from_handle(struct pipe_screen *screen,
1758 struct winsys_handle *whandle,
1759 bool dedicated)
1760 {
1761 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1762 struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
1763 struct pb_buffer_lean *buf = NULL;
1764
1765 if (!memobj)
1766 return NULL;
1767
1768 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1769 rscreen->info.max_alignment, false);
1770 if (!buf) {
1771 free(memobj);
1772 return NULL;
1773 }
1774
1775 memobj->b.dedicated = dedicated;
1776 memobj->buf = buf;
1777 memobj->stride = whandle->stride;
1778 memobj->offset = whandle->offset;
1779
1780 return (struct pipe_memory_object *)memobj;
1781
1782 }
1783
1784 static void
r600_memobj_destroy(struct pipe_screen * screen,struct pipe_memory_object * _memobj)1785 r600_memobj_destroy(struct pipe_screen *screen,
1786 struct pipe_memory_object *_memobj)
1787 {
1788 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1789 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1790
1791 radeon_bo_reference(rscreen->ws, &memobj->buf, NULL);
1792 free(memobj);
1793 }
1794
1795 static struct pipe_resource *
r600_texture_from_memobj(struct pipe_screen * screen,const struct pipe_resource * templ,struct pipe_memory_object * _memobj,uint64_t offset)1796 r600_texture_from_memobj(struct pipe_screen *screen,
1797 const struct pipe_resource *templ,
1798 struct pipe_memory_object *_memobj,
1799 uint64_t offset)
1800 {
1801 int r;
1802 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1803 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1804 struct r600_texture *rtex;
1805 struct radeon_surf surface = {};
1806 struct radeon_bo_metadata metadata = {};
1807 enum radeon_surf_mode array_mode;
1808 bool is_scanout;
1809 struct pb_buffer_lean *buf = NULL;
1810
1811 if (memobj->b.dedicated) {
1812 rscreen->ws->buffer_get_metadata(rscreen->ws, memobj->buf, &metadata, NULL);
1813 r600_surface_import_metadata(rscreen, &surface, &metadata,
1814 &array_mode, &is_scanout);
1815 } else {
1816 /**
1817 * The bo metadata is unset for un-dedicated images. So we fall
1818 * back to linear. See answer to question 5 of the
1819 * VK_KHX_external_memory spec for some details.
1820 *
1821 * It is possible that this case isn't going to work if the
1822 * surface pitch isn't correctly aligned by default.
1823 *
1824 * In order to support it correctly we require multi-image
1825 * metadata to be synchronized between radv and radeonsi. The
1826 * semantics of associating multiple image metadata to a memory
1827 * object on the vulkan export side are not concretely defined
1828 * either.
1829 *
1830 * All the use cases we are aware of at the moment for memory
1831 * objects use dedicated allocations. So lets keep the initial
1832 * implementation simple.
1833 *
1834 * A possible alternative is to attempt to reconstruct the
1835 * tiling information when the TexParameter TEXTURE_TILING_EXT
1836 * is set.
1837 */
1838 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1839 is_scanout = false;
1840
1841 }
1842
1843 r = r600_init_surface(rscreen, &surface, templ,
1844 array_mode, memobj->stride,
1845 offset, true, is_scanout,
1846 false);
1847 if (r)
1848 return NULL;
1849
1850 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
1851 if (!rtex)
1852 return NULL;
1853
1854 /* r600_texture_create_object doesn't increment refcount of
1855 * memobj->buf, so increment it here.
1856 */
1857 radeon_bo_reference(rscreen->ws, &buf, memobj->buf);
1858
1859 rtex->resource.b.is_shared = true;
1860 rtex->resource.external_usage = PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE;
1861
1862 return &rtex->resource.b.b;
1863 }
1864
r600_init_screen_texture_functions(struct r600_common_screen * rscreen)1865 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1866 {
1867 rscreen->b.resource_from_handle = r600_texture_from_handle;
1868 rscreen->b.resource_get_handle = r600_texture_get_handle;
1869 rscreen->b.resource_get_info = r600_texture_get_info;
1870 rscreen->b.resource_from_memobj = r600_texture_from_memobj;
1871 rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
1872 rscreen->b.memobj_destroy = r600_memobj_destroy;
1873 }
1874
r600_init_context_texture_functions(struct r600_common_context * rctx)1875 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1876 {
1877 rctx->b.create_surface = r600_create_surface;
1878 rctx->b.surface_destroy = r600_surface_destroy;
1879 rctx->b.clear_texture = u_default_clear_texture;
1880 }
1881