1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "r600_cs.h"
7 #include "util/u_viewport.h"
8 #include "tgsi/tgsi_scan.h"
9
10 #define R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C
11 #define CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x28be8
12 #define R_02843C_PA_CL_VPORT_XSCALE 0x02843C
13
14 #define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250
15 #define S_028250_TL_X(x) (((unsigned)(x) & 0x7FFF) << 0)
16 #define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF)
17 #define C_028250_TL_X 0xFFFF8000
18 #define S_028250_TL_Y(x) (((unsigned)(x) & 0x7FFF) << 16)
19 #define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF)
20 #define C_028250_TL_Y 0x8000FFFF
21 #define S_028250_WINDOW_OFFSET_DISABLE(x) (((unsigned)(x) & 0x1) << 31)
22 #define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
23 #define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
24 #define S_028254_BR_X(x) (((unsigned)(x) & 0x7FFF) << 0)
25 #define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF)
26 #define C_028254_BR_X 0xFFFF8000
27 #define S_028254_BR_Y(x) (((unsigned)(x) & 0x7FFF) << 16)
28 #define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF)
29 #define C_028254_BR_Y 0x8000FFFF
30 #define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0
31 #define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4
32
33 #define GET_MAX_SCISSOR(rctx) (rctx->gfx_level >= EVERGREEN ? 16384 : 8192)
34
r600_set_scissor_states(struct pipe_context * ctx,unsigned start_slot,unsigned num_scissors,const struct pipe_scissor_state * state)35 static void r600_set_scissor_states(struct pipe_context *ctx,
36 unsigned start_slot,
37 unsigned num_scissors,
38 const struct pipe_scissor_state *state)
39 {
40 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
41 int i;
42
43 for (i = 0; i < num_scissors; i++)
44 rctx->scissors.states[start_slot + i] = state[i];
45
46 if (!rctx->scissor_enabled)
47 return;
48
49 rctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
50 rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
51 }
52
53 /* Since the guard band disables clipping, we have to clip per-pixel
54 * using a scissor.
55 */
r600_get_scissor_from_viewport(struct r600_common_context * rctx,const struct pipe_viewport_state * vp,struct r600_signed_scissor * scissor)56 static void r600_get_scissor_from_viewport(struct r600_common_context *rctx,
57 const struct pipe_viewport_state *vp,
58 struct r600_signed_scissor *scissor)
59 {
60 float tmp, minx, miny, maxx, maxy;
61
62 /* Convert (-1, -1) and (1, 1) from clip space into window space. */
63 minx = -vp->scale[0] + vp->translate[0];
64 miny = -vp->scale[1] + vp->translate[1];
65 maxx = vp->scale[0] + vp->translate[0];
66 maxy = vp->scale[1] + vp->translate[1];
67
68 /* r600_draw_rectangle sets this. Disable the scissor. */
69 if (minx == -1 && miny == -1 && maxx == 1 && maxy == 1) {
70 scissor->minx = scissor->miny = 0;
71 scissor->maxx = scissor->maxy = GET_MAX_SCISSOR(rctx);
72 return;
73 }
74
75 /* Handle inverted viewports. */
76 if (minx > maxx) {
77 tmp = minx;
78 minx = maxx;
79 maxx = tmp;
80 }
81 if (miny > maxy) {
82 tmp = miny;
83 miny = maxy;
84 maxy = tmp;
85 }
86
87 /* Convert to integer and round up the max bounds. */
88 scissor->minx = minx;
89 scissor->miny = miny;
90 scissor->maxx = ceilf(maxx);
91 scissor->maxy = ceilf(maxy);
92 }
93
r600_clamp_scissor(struct r600_common_context * rctx,struct pipe_scissor_state * out,struct r600_signed_scissor * scissor)94 static void r600_clamp_scissor(struct r600_common_context *rctx,
95 struct pipe_scissor_state *out,
96 struct r600_signed_scissor *scissor)
97 {
98 unsigned max_scissor = GET_MAX_SCISSOR(rctx);
99 out->minx = CLAMP(scissor->minx, 0, max_scissor);
100 out->miny = CLAMP(scissor->miny, 0, max_scissor);
101 out->maxx = CLAMP(scissor->maxx, 0, max_scissor);
102 out->maxy = CLAMP(scissor->maxy, 0, max_scissor);
103 }
104
r600_clip_scissor(struct pipe_scissor_state * out,struct pipe_scissor_state * clip)105 static void r600_clip_scissor(struct pipe_scissor_state *out,
106 struct pipe_scissor_state *clip)
107 {
108 out->minx = MAX2(out->minx, clip->minx);
109 out->miny = MAX2(out->miny, clip->miny);
110 out->maxx = MIN2(out->maxx, clip->maxx);
111 out->maxy = MIN2(out->maxy, clip->maxy);
112 }
113
r600_scissor_make_union(struct r600_signed_scissor * out,struct r600_signed_scissor * in)114 static void r600_scissor_make_union(struct r600_signed_scissor *out,
115 struct r600_signed_scissor *in)
116 {
117 out->minx = MIN2(out->minx, in->minx);
118 out->miny = MIN2(out->miny, in->miny);
119 out->maxx = MAX2(out->maxx, in->maxx);
120 out->maxy = MAX2(out->maxy, in->maxy);
121 }
122
evergreen_apply_scissor_bug_workaround(struct r600_common_context * rctx,struct pipe_scissor_state * scissor)123 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
124 struct pipe_scissor_state *scissor)
125 {
126 if (rctx->gfx_level == EVERGREEN || rctx->gfx_level == CAYMAN) {
127 if (scissor->maxx == 0)
128 scissor->minx = 1;
129 if (scissor->maxy == 0)
130 scissor->miny = 1;
131
132 if (rctx->gfx_level == CAYMAN &&
133 scissor->maxx == 1 && scissor->maxy == 1)
134 scissor->maxx = 2;
135 }
136 }
137
r600_emit_one_scissor(struct r600_common_context * rctx,struct radeon_cmdbuf * cs,struct r600_signed_scissor * vp_scissor,struct pipe_scissor_state * scissor)138 static void r600_emit_one_scissor(struct r600_common_context *rctx,
139 struct radeon_cmdbuf *cs,
140 struct r600_signed_scissor *vp_scissor,
141 struct pipe_scissor_state *scissor)
142 {
143 struct pipe_scissor_state final;
144
145 if (rctx->vs_disables_clipping_viewport) {
146 final.minx = final.miny = 0;
147 final.maxx = final.maxy = GET_MAX_SCISSOR(rctx);
148 } else {
149 r600_clamp_scissor(rctx, &final, vp_scissor);
150 }
151
152 if (scissor)
153 r600_clip_scissor(&final, scissor);
154
155 evergreen_apply_scissor_bug_workaround(rctx, &final);
156
157 radeon_emit(cs, S_028250_TL_X(final.minx) |
158 S_028250_TL_Y(final.miny) |
159 S_028250_WINDOW_OFFSET_DISABLE(1));
160 radeon_emit(cs, S_028254_BR_X(final.maxx) |
161 S_028254_BR_Y(final.maxy));
162 }
163
164 /* the range is [-MAX, MAX] */
165 #define GET_MAX_VIEWPORT_RANGE(rctx) (rctx->gfx_level >= EVERGREEN ? 32768 : 16384)
166
r600_emit_guardband(struct r600_common_context * rctx,struct r600_signed_scissor * vp_as_scissor)167 static void r600_emit_guardband(struct r600_common_context *rctx,
168 struct r600_signed_scissor *vp_as_scissor)
169 {
170 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
171 struct pipe_viewport_state vp;
172 float left, top, right, bottom, max_range, guardband_x, guardband_y;
173
174 /* Reconstruct the viewport transformation from the scissor. */
175 vp.translate[0] = (vp_as_scissor->minx + vp_as_scissor->maxx) / 2.0;
176 vp.translate[1] = (vp_as_scissor->miny + vp_as_scissor->maxy) / 2.0;
177 vp.scale[0] = vp_as_scissor->maxx - vp.translate[0];
178 vp.scale[1] = vp_as_scissor->maxy - vp.translate[1];
179
180 /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
181 if (vp_as_scissor->minx == vp_as_scissor->maxx)
182 vp.scale[0] = 0.5;
183 if (vp_as_scissor->miny == vp_as_scissor->maxy)
184 vp.scale[1] = 0.5;
185
186 /* Find the biggest guard band that is inside the supported viewport
187 * range. The guard band is specified as a horizontal and vertical
188 * distance from (0,0) in clip space.
189 *
190 * This is done by applying the inverse viewport transformation
191 * on the viewport limits to get those limits in clip space.
192 *
193 * Use a limit one pixel smaller to allow for some precision error.
194 */
195 max_range = GET_MAX_VIEWPORT_RANGE(rctx) - 1;
196 left = (-max_range - vp.translate[0]) / vp.scale[0];
197 right = ( max_range - vp.translate[0]) / vp.scale[0];
198 top = (-max_range - vp.translate[1]) / vp.scale[1];
199 bottom = ( max_range - vp.translate[1]) / vp.scale[1];
200
201 assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
202
203 guardband_x = MIN2(-left, right);
204 guardband_y = MIN2(-top, bottom);
205
206 /* If any of the GB registers is updated, all of them must be updated. */
207 if (rctx->gfx_level >= CAYMAN)
208 radeon_set_context_reg_seq(cs, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
209 else
210 radeon_set_context_reg_seq(cs, R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
211
212 radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
213 radeon_emit(cs, fui(1.0)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
214 radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
215 radeon_emit(cs, fui(1.0)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
216 }
217
r600_emit_scissors(struct r600_common_context * rctx,struct r600_atom * atom)218 static void r600_emit_scissors(struct r600_common_context *rctx, struct r600_atom *atom)
219 {
220 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
221 struct pipe_scissor_state *states = rctx->scissors.states;
222 unsigned mask = rctx->scissors.dirty_mask;
223 bool scissor_enabled = rctx->scissor_enabled;
224 struct r600_signed_scissor max_vp_scissor;
225 int i;
226
227 /* The simple case: Only 1 viewport is active. */
228 if (!rctx->vs_writes_viewport_index) {
229 struct r600_signed_scissor *vp = &rctx->viewports.as_scissor[0];
230
231 if (!(mask & 1))
232 return;
233
234 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
235 r600_emit_one_scissor(rctx, cs, vp, scissor_enabled ? &states[0] : NULL);
236 r600_emit_guardband(rctx, vp);
237 rctx->scissors.dirty_mask &= ~1; /* clear one bit */
238 return;
239 }
240
241 /* Shaders can draw to any viewport. Make a union of all viewports. */
242 max_vp_scissor = rctx->viewports.as_scissor[0];
243 for (i = 1; i < R600_MAX_VIEWPORTS; i++)
244 r600_scissor_make_union(&max_vp_scissor,
245 &rctx->viewports.as_scissor[i]);
246
247 while (mask) {
248 int start, count, i;
249
250 u_bit_scan_consecutive_range(&mask, &start, &count);
251
252 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
253 start * 4 * 2, count * 2);
254 for (i = start; i < start+count; i++) {
255 r600_emit_one_scissor(rctx, cs, &rctx->viewports.as_scissor[i],
256 scissor_enabled ? &states[i] : NULL);
257 }
258 }
259 r600_emit_guardband(rctx, &max_vp_scissor);
260 rctx->scissors.dirty_mask = 0;
261 }
262
r600_set_viewport_states(struct pipe_context * ctx,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * state)263 static void r600_set_viewport_states(struct pipe_context *ctx,
264 unsigned start_slot,
265 unsigned num_viewports,
266 const struct pipe_viewport_state *state)
267 {
268 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
269 unsigned mask;
270 int i;
271
272 for (i = 0; i < num_viewports; i++) {
273 unsigned index = start_slot + i;
274
275 rctx->viewports.states[index] = state[i];
276 r600_get_scissor_from_viewport(rctx, &state[i],
277 &rctx->viewports.as_scissor[index]);
278 }
279
280 mask = ((1 << num_viewports) - 1) << start_slot;
281 rctx->viewports.dirty_mask |= mask;
282 rctx->viewports.depth_range_dirty_mask |= mask;
283 rctx->scissors.dirty_mask |= mask;
284 rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
285 rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
286 }
287
r600_emit_one_viewport(struct r600_common_context * rctx,struct pipe_viewport_state * state)288 static void r600_emit_one_viewport(struct r600_common_context *rctx,
289 struct pipe_viewport_state *state)
290 {
291 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
292
293 radeon_emit(cs, fui(state->scale[0]));
294 radeon_emit(cs, fui(state->translate[0]));
295 radeon_emit(cs, fui(state->scale[1]));
296 radeon_emit(cs, fui(state->translate[1]));
297 radeon_emit(cs, fui(state->scale[2]));
298 radeon_emit(cs, fui(state->translate[2]));
299 }
300
r600_emit_viewports(struct r600_common_context * rctx)301 static void r600_emit_viewports(struct r600_common_context *rctx)
302 {
303 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
304 struct pipe_viewport_state *states = rctx->viewports.states;
305 unsigned mask = rctx->viewports.dirty_mask;
306
307 /* The simple case: Only 1 viewport is active. */
308 if (!rctx->vs_writes_viewport_index) {
309 if (!(mask & 1))
310 return;
311
312 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
313 r600_emit_one_viewport(rctx, &states[0]);
314 rctx->viewports.dirty_mask &= ~1; /* clear one bit */
315 return;
316 }
317
318 while (mask) {
319 int start, count, i;
320
321 u_bit_scan_consecutive_range(&mask, &start, &count);
322
323 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
324 start * 4 * 6, count * 6);
325 for (i = start; i < start+count; i++)
326 r600_emit_one_viewport(rctx, &states[i]);
327 }
328 rctx->viewports.dirty_mask = 0;
329 }
330
r600_emit_depth_ranges(struct r600_common_context * rctx)331 static void r600_emit_depth_ranges(struct r600_common_context *rctx)
332 {
333 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
334 struct pipe_viewport_state *states = rctx->viewports.states;
335 unsigned mask = rctx->viewports.depth_range_dirty_mask;
336 float zmin, zmax;
337
338 /* The simple case: Only 1 viewport is active. */
339 if (!rctx->vs_writes_viewport_index) {
340 if (!(mask & 1))
341 return;
342
343 util_viewport_zmin_zmax(&states[0], rctx->clip_halfz, &zmin, &zmax);
344
345 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
346 radeon_emit(cs, fui(zmin));
347 radeon_emit(cs, fui(zmax));
348 rctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
349 return;
350 }
351
352 while (mask) {
353 int start, count, i;
354
355 u_bit_scan_consecutive_range(&mask, &start, &count);
356
357 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
358 start * 4 * 2, count * 2);
359 for (i = start; i < start+count; i++) {
360 util_viewport_zmin_zmax(&states[i], rctx->clip_halfz, &zmin, &zmax);
361 radeon_emit(cs, fui(zmin));
362 radeon_emit(cs, fui(zmax));
363 }
364 }
365 rctx->viewports.depth_range_dirty_mask = 0;
366 }
367
r600_emit_viewport_states(struct r600_common_context * rctx,struct r600_atom * atom)368 static void r600_emit_viewport_states(struct r600_common_context *rctx,
369 struct r600_atom *atom)
370 {
371 r600_emit_viewports(rctx);
372 r600_emit_depth_ranges(rctx);
373 }
374
375 /* Set viewport dependencies on pipe_rasterizer_state. */
r600_viewport_set_rast_deps(struct r600_common_context * rctx,bool scissor_enable,bool clip_halfz)376 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
377 bool scissor_enable, bool clip_halfz)
378 {
379 if (rctx->scissor_enabled != scissor_enable) {
380 rctx->scissor_enabled = scissor_enable;
381 rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
382 rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
383 }
384 if (rctx->clip_halfz != clip_halfz) {
385 rctx->clip_halfz = clip_halfz;
386 rctx->viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
387 rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
388 }
389 }
390
391 /**
392 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
393 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
394 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
395 * called to emit the rest.
396 */
r600_update_vs_writes_viewport_index(struct r600_common_context * rctx,struct tgsi_shader_info * info)397 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
398 struct tgsi_shader_info *info)
399 {
400 bool vs_window_space;
401
402 if (!info)
403 return;
404
405 /* When the VS disables clipping and viewport transformation. */
406 vs_window_space =
407 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
408
409 if (rctx->vs_disables_clipping_viewport != vs_window_space) {
410 rctx->vs_disables_clipping_viewport = vs_window_space;
411 rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
412 rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
413 }
414
415 /* Viewport index handling. */
416 rctx->vs_writes_viewport_index = info->writes_viewport_index;
417 if (!rctx->vs_writes_viewport_index)
418 return;
419
420 if (rctx->scissors.dirty_mask)
421 rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
422
423 if (rctx->viewports.dirty_mask ||
424 rctx->viewports.depth_range_dirty_mask)
425 rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
426 }
427
r600_init_viewport_functions(struct r600_common_context * rctx)428 void r600_init_viewport_functions(struct r600_common_context *rctx)
429 {
430 rctx->scissors.atom.emit = r600_emit_scissors;
431 rctx->viewports.atom.emit = r600_emit_viewport_states;
432
433 rctx->scissors.atom.num_dw = (2 + 16 * 2) + 6;
434 rctx->viewports.atom.num_dw = 2 + 16 * 6;
435
436 rctx->b.set_scissor_states = r600_set_scissor_states;
437 rctx->b.set_viewport_states = r600_set_viewport_states;
438 }
439