1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "pipe/p_video_codec.h"
10 #include "radeon_vcn_enc.h"
11 #include "radeon_video.h"
12 #include "si_pipe.h"
13 #include "util/u_video.h"
14
15 #include <stdio.h>
16
17 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
18 #define RENCODE_FW_INTERFACE_MINOR_VERSION 9
19
20 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
21 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
22 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
23 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
24 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
25 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
26 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
27 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
28 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
29 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a
30 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b
31 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c
32 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d
33 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
34 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
35 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX 0x0000001d
36 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
37 #define RENCODE_IB_PARAM_QP_MAP 0x00000021
38 #define RENCODE_IB_PARAM_ENCODE_LATENCY 0x00000022
39 #define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000024
40
41 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
42 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
43 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
44
45 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
46 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
47 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
48 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
49
radeon_enc_session_info(struct radeon_encoder * enc)50 static void radeon_enc_session_info(struct radeon_encoder *enc)
51 {
52 RADEON_ENC_BEGIN(enc->cmd.session_info);
53 RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
54 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
55 RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE);
56 RADEON_ENC_END();
57 }
58
radeon_enc_task_info(struct radeon_encoder * enc,bool need_feedback)59 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
60 {
61 enc->enc_pic.task_info.task_id++;
62
63 if (need_feedback)
64 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
65 else
66 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
67
68 RADEON_ENC_BEGIN(enc->cmd.task_info);
69 enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++];
70 RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
71 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
72 RADEON_ENC_END();
73 }
74
radeon_enc_session_init(struct radeon_encoder * enc)75 static void radeon_enc_session_init(struct radeon_encoder *enc)
76 {
77 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
78 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
79 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
80 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
81 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
82 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
83 }
84 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
85
86 enc->enc_pic.session_init.padding_width =
87 (enc->enc_pic.crop_left + enc->enc_pic.crop_right) * 2;
88 enc->enc_pic.session_init.padding_height =
89 (enc->enc_pic.crop_top + enc->enc_pic.crop_bottom) * 2;
90
91 enc->enc_pic.session_init.display_remote = 0;
92 enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode;
93 enc->enc_pic.session_init.pre_encode_chroma_enabled = !!(enc->enc_pic.quality_modes.pre_encode_mode);
94
95 RADEON_ENC_BEGIN(enc->cmd.session_init);
96 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
97 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
98 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
99 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
100 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
101 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
102 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
103 RADEON_ENC_CS(enc->enc_pic.session_init.display_remote);
104 RADEON_ENC_END();
105 }
106
radeon_enc_layer_control(struct radeon_encoder * enc)107 static void radeon_enc_layer_control(struct radeon_encoder *enc)
108 {
109 enc->enc_pic.layer_ctrl.max_num_temporal_layers = enc->enc_pic.num_temporal_layers;
110 enc->enc_pic.layer_ctrl.num_temporal_layers = enc->enc_pic.num_temporal_layers;
111
112 RADEON_ENC_BEGIN(enc->cmd.layer_control);
113 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
114 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
115 RADEON_ENC_END();
116 }
117
radeon_enc_layer_select(struct radeon_encoder * enc)118 static void radeon_enc_layer_select(struct radeon_encoder *enc)
119 {
120 RADEON_ENC_BEGIN(enc->cmd.layer_select);
121 RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
122 RADEON_ENC_END();
123 }
124
radeon_enc_slice_control(struct radeon_encoder * enc)125 static void radeon_enc_slice_control(struct radeon_encoder *enc)
126 {
127 RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
128 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
129 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
130 RADEON_ENC_END();
131 }
132
radeon_enc_slice_control_hevc(struct radeon_encoder * enc)133 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
134 {
135 RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
136 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
137 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
138 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
139 RADEON_ENC_END();
140 }
141
radeon_enc_spec_misc(struct radeon_encoder * enc)142 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
143 {
144 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
145 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
146 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
147 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
148 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
149 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
150 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
151 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
152 RADEON_ENC_END();
153 }
154
radeon_enc_spec_misc_hevc(struct radeon_encoder * enc)155 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
156 {
157 RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
158 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
159 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
160 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
161 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
162 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
163 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
164 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
165 RADEON_ENC_END();
166 }
167
radeon_enc_rc_session_init(struct radeon_encoder * enc)168 static void radeon_enc_rc_session_init(struct radeon_encoder *enc)
169 {
170 RADEON_ENC_BEGIN(enc->cmd.rc_session_init);
171 RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
172 RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
173 RADEON_ENC_END();
174 }
175
radeon_enc_rc_layer_init(struct radeon_encoder * enc)176 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
177 {
178 unsigned int i = enc->enc_pic.layer_sel.temporal_layer_index;
179 RADEON_ENC_BEGIN(enc->cmd.rc_layer_init);
180 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].target_bit_rate);
181 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bit_rate);
182 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_num);
183 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_den);
184 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].vbv_buffer_size);
185 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture);
186 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer);
187 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional);
188 RADEON_ENC_END();
189 }
190
radeon_enc_deblocking_filter_h264(struct radeon_encoder * enc)191 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
192 {
193 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264);
194 RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
195 RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
196 RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
197 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
198 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
199 RADEON_ENC_END();
200 }
201
radeon_enc_deblocking_filter_hevc(struct radeon_encoder * enc)202 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc)
203 {
204 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
205 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
206 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
207 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
208 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
209 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
210 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
211 RADEON_ENC_END();
212 }
213
radeon_enc_quality_params(struct radeon_encoder * enc)214 static void radeon_enc_quality_params(struct radeon_encoder *enc)
215 {
216 RADEON_ENC_BEGIN(enc->cmd.quality_params);
217 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
218 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
219 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
220 RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
221 RADEON_ENC_END();
222 }
223
radeon_enc_write_sps(struct radeon_encoder * enc,uint8_t * out)224 unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t *out)
225 {
226 struct radeon_enc_pic *pic = &enc->enc_pic;
227 struct pipe_h264_enc_seq_param *sps = &pic->h264.desc->seq;
228
229 radeon_enc_reset(enc);
230 radeon_enc_set_output_buffer(enc, out);
231 radeon_enc_set_emulation_prevention(enc, false);
232 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
233 radeon_enc_code_fixed_bits(enc, 0x67, 8);
234 radeon_enc_byte_align(enc);
235 radeon_enc_set_emulation_prevention(enc, true);
236 radeon_enc_code_fixed_bits(enc, pic->spec_misc.profile_idc, 8);
237 radeon_enc_code_fixed_bits(enc, sps->enc_constraint_set_flags, 6);
238 radeon_enc_code_fixed_bits(enc, 0x0, 2); /* reserved_zero_2bits */
239 radeon_enc_code_fixed_bits(enc, pic->spec_misc.level_idc, 8);
240 radeon_enc_code_ue(enc, 0x0); /* seq_parameter_set_id */
241
242 if (pic->spec_misc.profile_idc == 100 || pic->spec_misc.profile_idc == 110 ||
243 pic->spec_misc.profile_idc == 122 || pic->spec_misc.profile_idc == 244 ||
244 pic->spec_misc.profile_idc == 44 || pic->spec_misc.profile_idc == 83 ||
245 pic->spec_misc.profile_idc == 86 || pic->spec_misc.profile_idc == 118 ||
246 pic->spec_misc.profile_idc == 128 || pic->spec_misc.profile_idc == 138) {
247 radeon_enc_code_ue(enc, 0x1); /* chroma_format_idc */
248 radeon_enc_code_ue(enc, 0x0); /* bit_depth_luma_minus8 */
249 radeon_enc_code_ue(enc, 0x0); /* bit_depth_chroma_minus8 */
250 radeon_enc_code_fixed_bits(enc, 0x0, 2); /* qpprime_y_zero_transform_bypass_flag + seq_scaling_matrix_present_flag */
251 }
252
253 radeon_enc_code_ue(enc, sps->log2_max_frame_num_minus4);
254 radeon_enc_code_ue(enc, sps->pic_order_cnt_type);
255
256 if (sps->pic_order_cnt_type == 0)
257 radeon_enc_code_ue(enc, sps->log2_max_pic_order_cnt_lsb_minus4);
258
259 radeon_enc_code_ue(enc, sps->max_num_ref_frames);
260 radeon_enc_code_fixed_bits(enc, sps->gaps_in_frame_num_value_allowed_flag, 1);
261 radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_width / 16 - 1));
262 radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_height / 16 - 1));
263 bool frame_mbs_only_flag = true;
264 radeon_enc_code_fixed_bits(enc, frame_mbs_only_flag ? 0x1 : 0x0, 1);
265
266 if (!frame_mbs_only_flag)
267 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* mb_adaptive_frame_field_flag */
268
269 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* direct_8x8_inference_flag */
270
271 radeon_enc_code_fixed_bits(enc, sps->enc_frame_cropping_flag, 1);
272 if (sps->enc_frame_cropping_flag) {
273 radeon_enc_code_ue(enc, sps->enc_frame_crop_left_offset);
274 radeon_enc_code_ue(enc, sps->enc_frame_crop_right_offset);
275 radeon_enc_code_ue(enc, sps->enc_frame_crop_top_offset);
276 radeon_enc_code_ue(enc, sps->enc_frame_crop_bottom_offset);
277 }
278
279 radeon_enc_code_fixed_bits(enc, sps->vui_parameters_present_flag, 1);
280 if (sps->vui_parameters_present_flag) {
281 radeon_enc_code_fixed_bits(enc, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
282 if (sps->vui_flags.aspect_ratio_info_present_flag) {
283 radeon_enc_code_fixed_bits(enc, (sps->aspect_ratio_idc), 8);
284 if (sps->aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
285 radeon_enc_code_fixed_bits(enc, (sps->sar_width), 16);
286 radeon_enc_code_fixed_bits(enc, (sps->sar_height), 16);
287 }
288 }
289 radeon_enc_code_fixed_bits(enc, sps->vui_flags.overscan_info_present_flag, 1);
290 if (sps->vui_flags.overscan_info_present_flag)
291 radeon_enc_code_fixed_bits(enc, sps->vui_flags.overscan_appropriate_flag, 1);
292 radeon_enc_code_fixed_bits(enc, sps->vui_flags.video_signal_type_present_flag, 1);
293 if (sps->vui_flags.video_signal_type_present_flag) {
294 radeon_enc_code_fixed_bits(enc, sps->video_format, 3);
295 radeon_enc_code_fixed_bits(enc, sps->video_full_range_flag, 1);
296 radeon_enc_code_fixed_bits(enc, sps->vui_flags.colour_description_present_flag, 1);
297 if (sps->vui_flags.colour_description_present_flag) {
298 radeon_enc_code_fixed_bits(enc, sps->colour_primaries, 8);
299 radeon_enc_code_fixed_bits(enc, sps->transfer_characteristics, 8);
300 radeon_enc_code_fixed_bits(enc, sps->matrix_coefficients, 8);
301 }
302 }
303 radeon_enc_code_fixed_bits(enc, sps->vui_flags.chroma_loc_info_present_flag, 1);
304 if (sps->vui_flags.chroma_loc_info_present_flag) {
305 radeon_enc_code_ue(enc, sps->chroma_sample_loc_type_top_field);
306 radeon_enc_code_ue(enc, sps->chroma_sample_loc_type_bottom_field);
307 }
308 radeon_enc_code_fixed_bits(enc, (sps->vui_flags.timing_info_present_flag), 1);
309 if (sps->vui_flags.timing_info_present_flag) {
310 radeon_enc_code_fixed_bits(enc, (sps->num_units_in_tick), 32);
311 radeon_enc_code_fixed_bits(enc, (sps->time_scale), 32);
312 radeon_enc_code_fixed_bits(enc, (sps->vui_flags.fixed_frame_rate_flag), 1);
313 }
314 radeon_enc_code_fixed_bits(enc, sps->vui_flags.nal_hrd_parameters_present_flag, 1);
315 if (sps->vui_flags.nal_hrd_parameters_present_flag)
316 radeon_enc_hrd_parameters(enc, &sps->nal_hrd_parameters);
317 radeon_enc_code_fixed_bits(enc, sps->vui_flags.vcl_hrd_parameters_present_flag, 1);
318 if (sps->vui_flags.vcl_hrd_parameters_present_flag)
319 radeon_enc_hrd_parameters(enc, &sps->vcl_hrd_parameters);
320 if (sps->vui_flags.nal_hrd_parameters_present_flag || sps->vui_flags.vcl_hrd_parameters_present_flag)
321 radeon_enc_code_fixed_bits(enc, sps->vui_flags.low_delay_hrd_flag, 1);
322 radeon_enc_code_fixed_bits(enc, sps->vui_flags.pic_struct_present_flag, 1);
323 radeon_enc_code_fixed_bits(enc, sps->vui_flags.bitstream_restriction_flag, 1);
324 if (sps->vui_flags.bitstream_restriction_flag) {
325 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* motion_vectors_over_pic_boundaries_flag */
326 radeon_enc_code_ue(enc, 0x0); /* max_bytes_per_pic_denom */
327 radeon_enc_code_ue(enc, 0x0); /* max_bits_per_mb_denom */
328 radeon_enc_code_ue(enc, 16); /* log2_max_mv_length_horizontal */
329 radeon_enc_code_ue(enc, 16); /* log2_max_mv_length_vertical */
330 radeon_enc_code_ue(enc, sps->max_num_reorder_frames);
331 radeon_enc_code_ue(enc, sps->max_dec_frame_buffering);
332 }
333 }
334
335 radeon_enc_code_fixed_bits(enc, 0x1, 1);
336 radeon_enc_byte_align(enc);
337 radeon_enc_flush_headers(enc);
338
339 return enc->bits_buf_pos;
340 }
341
radeon_enc_write_sps_hevc(struct radeon_encoder * enc,uint8_t * out)342 unsigned int radeon_enc_write_sps_hevc(struct radeon_encoder *enc, uint8_t *out)
343 {
344 struct radeon_enc_pic *pic = &enc->enc_pic;
345 struct pipe_h265_enc_seq_param *sps = &pic->hevc.desc->seq;
346 int i;
347
348 radeon_enc_reset(enc);
349 radeon_enc_set_output_buffer(enc, out);
350 radeon_enc_set_emulation_prevention(enc, false);
351 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
352 radeon_enc_code_fixed_bits(enc, 0x4201, 16);
353 radeon_enc_byte_align(enc);
354 radeon_enc_set_emulation_prevention(enc, true);
355 radeon_enc_code_fixed_bits(enc, 0x0, 4); /* sps_video_parameter_set_id */
356 radeon_enc_code_fixed_bits(enc, sps->sps_max_sub_layers_minus1, 3);
357 radeon_enc_code_fixed_bits(enc, sps->sps_temporal_id_nesting_flag, 1);
358 radeon_enc_hevc_profile_tier_level(enc, sps->sps_max_sub_layers_minus1, &sps->profile_tier_level);
359 radeon_enc_code_ue(enc, 0x0); /* sps_seq_parameter_set_id */
360 radeon_enc_code_ue(enc, sps->chroma_format_idc);
361 radeon_enc_code_ue(enc, pic->session_init.aligned_picture_width);
362 radeon_enc_code_ue(enc, pic->session_init.aligned_picture_height);
363
364 if (sps->conformance_window_flag) {
365 radeon_enc_code_fixed_bits(enc, 0x1, 1);
366 radeon_enc_code_ue(enc, sps->conf_win_left_offset);
367 radeon_enc_code_ue(enc, sps->conf_win_right_offset);
368 radeon_enc_code_ue(enc, sps->conf_win_top_offset);
369 radeon_enc_code_ue(enc, sps->conf_win_bottom_offset);
370 } else if (pic->session_init.padding_width != 0 ||
371 pic->session_init.padding_height != 0) {
372 radeon_enc_code_fixed_bits(enc, 0x1, 1);
373 radeon_enc_code_ue(enc, 0);
374 radeon_enc_code_ue(enc, pic->session_init.padding_width / 2);
375 radeon_enc_code_ue(enc, 0);
376 radeon_enc_code_ue(enc, pic->session_init.padding_height / 2);
377 } else
378 radeon_enc_code_fixed_bits(enc, 0x0, 1);
379
380 radeon_enc_code_ue(enc, sps->bit_depth_luma_minus8);
381 radeon_enc_code_ue(enc, sps->bit_depth_chroma_minus8);
382 radeon_enc_code_ue(enc, sps->log2_max_pic_order_cnt_lsb_minus4);
383 radeon_enc_code_fixed_bits(enc, sps->sps_sub_layer_ordering_info_present_flag, 1);
384 i = sps->sps_sub_layer_ordering_info_present_flag ? 0 : sps->sps_max_sub_layers_minus1;
385 for (; i <= sps->sps_max_sub_layers_minus1; i++) {
386 radeon_enc_code_ue(enc, sps->sps_max_dec_pic_buffering_minus1[i]);
387 radeon_enc_code_ue(enc, sps->sps_max_num_reorder_pics[i]);
388 radeon_enc_code_ue(enc, sps->sps_max_latency_increase_plus1[i]);
389 }
390
391 unsigned log2_diff_max_min_luma_coding_block_size =
392 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3);
393 unsigned log2_min_transform_block_size_minus2 =
394 enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3;
395 unsigned log2_diff_max_min_transform_block_size = log2_diff_max_min_luma_coding_block_size;
396 unsigned max_transform_hierarchy_depth_inter = log2_diff_max_min_luma_coding_block_size + 1;
397 unsigned max_transform_hierarchy_depth_intra = max_transform_hierarchy_depth_inter;
398
399 radeon_enc_code_ue(enc, pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
400 radeon_enc_code_ue(enc, log2_diff_max_min_luma_coding_block_size);
401 radeon_enc_code_ue(enc, log2_min_transform_block_size_minus2);
402 radeon_enc_code_ue(enc, log2_diff_max_min_transform_block_size);
403 radeon_enc_code_ue(enc, max_transform_hierarchy_depth_inter);
404 radeon_enc_code_ue(enc, max_transform_hierarchy_depth_intra);
405
406 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* scaling_list_enabled_flag */
407 radeon_enc_code_fixed_bits(enc, !pic->hevc_spec_misc.amp_disabled, 1);
408 radeon_enc_code_fixed_bits(enc, !pic->hevc_deblock.disable_sao, 1);
409 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pcm_enabled_flag */
410
411 radeon_enc_code_ue(enc, sps->num_short_term_ref_pic_sets);
412 for (i = 0; i < sps->num_short_term_ref_pic_sets; i++)
413 radeon_enc_hevc_st_ref_pic_set(enc, i, sps->num_short_term_ref_pic_sets, &sps->st_ref_pic_set[i]);
414
415 radeon_enc_code_fixed_bits(enc, sps->long_term_ref_pics_present_flag, 1);
416 if (sps->long_term_ref_pics_present_flag) {
417 radeon_enc_code_ue(enc, sps->num_long_term_ref_pics_sps);
418 for (i = 0; i < sps->num_long_term_ref_pics_sps; i++) {
419 radeon_enc_code_fixed_bits(enc, sps->lt_ref_pic_poc_lsb_sps[i], sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
420 radeon_enc_code_fixed_bits(enc, sps->used_by_curr_pic_lt_sps_flag[i], 1);
421 }
422 }
423
424 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* sps_temporal_mvp_enabled_flag */
425 radeon_enc_code_fixed_bits(enc, pic->hevc_spec_misc.strong_intra_smoothing_enabled, 1);
426
427 /* VUI parameters present flag */
428 radeon_enc_code_fixed_bits(enc, (sps->vui_parameters_present_flag), 1);
429 if (sps->vui_parameters_present_flag) {
430 /* aspect ratio present flag */
431 radeon_enc_code_fixed_bits(enc, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
432 if (sps->vui_flags.aspect_ratio_info_present_flag) {
433 radeon_enc_code_fixed_bits(enc, (sps->aspect_ratio_idc), 8);
434 if (sps->aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
435 radeon_enc_code_fixed_bits(enc, (sps->sar_width), 16);
436 radeon_enc_code_fixed_bits(enc, (sps->sar_height), 16);
437 }
438 }
439 radeon_enc_code_fixed_bits(enc, sps->vui_flags.overscan_info_present_flag, 1);
440 if (sps->vui_flags.overscan_info_present_flag)
441 radeon_enc_code_fixed_bits(enc, sps->vui_flags.overscan_appropriate_flag, 1);
442 /* video signal type present flag */
443 radeon_enc_code_fixed_bits(enc, sps->vui_flags.video_signal_type_present_flag, 1);
444 if (sps->vui_flags.video_signal_type_present_flag) {
445 radeon_enc_code_fixed_bits(enc, sps->video_format, 3);
446 radeon_enc_code_fixed_bits(enc, sps->video_full_range_flag, 1);
447 radeon_enc_code_fixed_bits(enc, sps->vui_flags.colour_description_present_flag, 1);
448 if (sps->vui_flags.colour_description_present_flag) {
449 radeon_enc_code_fixed_bits(enc, sps->colour_primaries, 8);
450 radeon_enc_code_fixed_bits(enc, sps->transfer_characteristics, 8);
451 radeon_enc_code_fixed_bits(enc, sps->matrix_coefficients, 8);
452 }
453 }
454 /* chroma loc info present flag */
455 radeon_enc_code_fixed_bits(enc, sps->vui_flags.chroma_loc_info_present_flag, 1);
456 if (sps->vui_flags.chroma_loc_info_present_flag) {
457 radeon_enc_code_ue(enc, sps->chroma_sample_loc_type_top_field);
458 radeon_enc_code_ue(enc, sps->chroma_sample_loc_type_bottom_field);
459 }
460 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
461 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
462 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */
463 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* default display windows flag */
464 /* vui timing info present flag */
465 radeon_enc_code_fixed_bits(enc, (sps->vui_flags.timing_info_present_flag), 1);
466 if (sps->vui_flags.timing_info_present_flag) {
467 radeon_enc_code_fixed_bits(enc, (sps->num_units_in_tick), 32);
468 radeon_enc_code_fixed_bits(enc, (sps->time_scale), 32);
469 radeon_enc_code_fixed_bits(enc, sps->vui_flags.poc_proportional_to_timing_flag, 1);
470 if (sps->vui_flags.poc_proportional_to_timing_flag)
471 radeon_enc_code_ue(enc, sps->num_ticks_poc_diff_one_minus1);
472 radeon_enc_code_fixed_bits(enc, sps->vui_flags.hrd_parameters_present_flag, 1);
473 if (sps->vui_flags.hrd_parameters_present_flag)
474 radeon_enc_hevc_hrd_parameters(enc, 1, sps->sps_max_sub_layers_minus1, &sps->hrd_parameters);
475 }
476 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* bitstream restriction flag */
477 }
478 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* sps extension present flag */
479
480 radeon_enc_code_fixed_bits(enc, 0x1, 1);
481 radeon_enc_byte_align(enc);
482
483 radeon_enc_flush_headers(enc);
484 return enc->bits_buf_pos;
485 }
486
radeon_enc_write_pps(struct radeon_encoder * enc,uint8_t * out)487 unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t *out)
488 {
489 radeon_enc_reset(enc);
490 radeon_enc_set_output_buffer(enc, out);
491 radeon_enc_set_emulation_prevention(enc, false);
492 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
493 radeon_enc_code_fixed_bits(enc, 0x68, 8);
494 radeon_enc_byte_align(enc);
495 radeon_enc_set_emulation_prevention(enc, true);
496 radeon_enc_code_ue(enc, 0x0); /* pic_parameter_set_id */
497 radeon_enc_code_ue(enc, 0x0); /* seq_parameter_set_id */
498 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
499 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* bottom_field_pic_order_in_frame_present_flag */
500 radeon_enc_code_ue(enc, 0x0); /* num_slice_groups_minus_1 */
501 radeon_enc_code_ue(enc, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l0_default_active_minus1);
502 radeon_enc_code_ue(enc, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l1_default_active_minus1);
503 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* weighted_pred_flag */
504 radeon_enc_code_fixed_bits(enc, 0x0, 2); /* weighted_bipred_idc */
505 radeon_enc_code_se(enc, 0x0); /* pic_init_qp_minus26 */
506 radeon_enc_code_se(enc, 0x0); /* pic_init_qs_minus26 */
507 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cb_qp_offset); /* chroma_qp_index_offset */
508 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag), 1);
509 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.constrained_intra_pred_flag), 1);
510 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag), 1);
511 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.transform_8x8_mode), 1);
512 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pic_scaling_matrix_present_flag */
513 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cr_qp_offset); /* second_chroma_qp_index_offset */
514
515 radeon_enc_code_fixed_bits(enc, 0x1, 1);
516 radeon_enc_byte_align(enc);
517
518 radeon_enc_flush_headers(enc);
519 return enc->bits_buf_pos;
520 }
521
radeon_enc_write_pps_hevc(struct radeon_encoder * enc,uint8_t * out)522 unsigned int radeon_enc_write_pps_hevc(struct radeon_encoder *enc, uint8_t *out)
523 {
524 struct pipe_h265_enc_pic_param *pps = &enc->enc_pic.hevc.desc->pic;
525
526 radeon_enc_reset(enc);
527 radeon_enc_set_output_buffer(enc, out);
528 radeon_enc_set_emulation_prevention(enc, false);
529 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
530 radeon_enc_code_fixed_bits(enc, 0x4401, 16);
531 radeon_enc_byte_align(enc);
532 radeon_enc_set_emulation_prevention(enc, true);
533 radeon_enc_code_ue(enc, 0x0); /* pps_pic_parameter_set_id */
534 radeon_enc_code_ue(enc, 0x0); /* pps_seq_parameter_set_id */
535 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* dependent_slice_segments_enabled_flag */
536 radeon_enc_code_fixed_bits(enc, pps->output_flag_present_flag, 1);
537 radeon_enc_code_fixed_bits(enc, 0x0, 3); /* num_extra_slice_header_bits */
538 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* sign_data_hiding_enabled_flag */
539 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* cabac_init_present_flag */
540 radeon_enc_code_ue(enc, pps->num_ref_idx_l0_default_active_minus1);
541 radeon_enc_code_ue(enc, pps->num_ref_idx_l1_default_active_minus1);
542 radeon_enc_code_se(enc, 0x0); /* init_qp_minus26 */
543 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
544 radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.transform_skip_disabled, 1);
545 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag, 1);
546 if (enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag)
547 radeon_enc_code_ue(enc, 0); /* diff_cu_qp_delta_depth */
548 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
549 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
550 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pps_slice_chroma_qp_offsets_present_flag */
551 radeon_enc_code_fixed_bits(enc, 0x0, 2); /* weighted_pred_flag + weighted_bipred_flag */
552 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* transquant_bypass_enabled_flag */
553 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* tiles_enabled_flag */
554 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* entropy_coding_sync_enabled_flag */
555 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
556 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* deblocking_filter_control_present_flag */
557 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* deblocking_filter_override_enabled_flag */
558 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
559
560 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
561 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
562 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
563 }
564
565 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pps_scaling_list_data_present_flag */
566 radeon_enc_code_fixed_bits(enc, pps->lists_modification_present_flag, 1);
567 radeon_enc_code_ue(enc, pps->log2_parallel_merge_level_minus2);
568 radeon_enc_code_fixed_bits(enc, 0x0, 2);
569
570 radeon_enc_code_fixed_bits(enc, 0x1, 1);
571 radeon_enc_byte_align(enc);
572
573 radeon_enc_flush_headers(enc);
574 return enc->bits_buf_pos;
575 }
576
radeon_enc_write_vps(struct radeon_encoder * enc,uint8_t * out)577 unsigned int radeon_enc_write_vps(struct radeon_encoder *enc, uint8_t *out)
578 {
579 struct pipe_h265_enc_vid_param *vps = &enc->enc_pic.hevc.desc->vid;
580 int i;
581
582 radeon_enc_reset(enc);
583 radeon_enc_set_output_buffer(enc, out);
584 radeon_enc_set_emulation_prevention(enc, false);
585 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
586 radeon_enc_code_fixed_bits(enc, 0x4001, 16);
587 radeon_enc_byte_align(enc);
588 radeon_enc_set_emulation_prevention(enc, true);
589
590 radeon_enc_code_fixed_bits(enc, 0x0, 4); /* vps_video_parameter_set_id*/
591 radeon_enc_code_fixed_bits(enc, vps->vps_base_layer_internal_flag, 1);
592 radeon_enc_code_fixed_bits(enc, vps->vps_base_layer_available_flag, 1);
593 radeon_enc_code_fixed_bits(enc, 0x0, 6); /* vps_max_layers_minus1 */
594 radeon_enc_code_fixed_bits(enc, vps->vps_max_sub_layers_minus1, 3);
595 radeon_enc_code_fixed_bits(enc, vps->vps_temporal_id_nesting_flag, 1);
596 radeon_enc_code_fixed_bits(enc, 0xffff, 16); /* vps_reserved_0xffff_16bits */
597 radeon_enc_hevc_profile_tier_level(enc, vps->vps_max_sub_layers_minus1, &vps->profile_tier_level);
598 radeon_enc_code_fixed_bits(enc, vps->vps_sub_layer_ordering_info_present_flag, 1);
599 i = vps->vps_sub_layer_ordering_info_present_flag ? 0 : vps->vps_max_sub_layers_minus1;
600 for (; i <= vps->vps_max_sub_layers_minus1; i++) {
601 radeon_enc_code_ue(enc, vps->vps_max_dec_pic_buffering_minus1[i]);
602 radeon_enc_code_ue(enc, vps->vps_max_num_reorder_pics[i]);
603 radeon_enc_code_ue(enc, vps->vps_max_latency_increase_plus1[i]);
604 }
605 radeon_enc_code_fixed_bits(enc, 0x0, 6); /* vps_max_layer_id */
606 radeon_enc_code_ue(enc, 0x0); /* vps_num_layer_sets_minus1 */
607 radeon_enc_code_fixed_bits(enc, vps->vps_timing_info_present_flag, 1);
608 if (vps->vps_timing_info_present_flag) {
609 radeon_enc_code_fixed_bits(enc, vps->vps_num_units_in_tick, 32);
610 radeon_enc_code_fixed_bits(enc, vps->vps_time_scale, 32);
611 radeon_enc_code_fixed_bits(enc, vps->vps_poc_proportional_to_timing_flag, 1);
612 if (vps->vps_poc_proportional_to_timing_flag)
613 radeon_enc_code_ue(enc, vps->vps_num_ticks_poc_diff_one_minus1);
614 radeon_enc_code_ue(enc, 0x0); /* vps_num_hrd_parameters */
615 }
616 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* vps_extension_flag */
617
618 radeon_enc_code_fixed_bits(enc, 0x1, 1);
619 radeon_enc_byte_align(enc);
620
621 radeon_enc_flush_headers(enc);
622 return enc->bits_buf_pos;
623 }
624
radeon_enc_slice_header(struct radeon_encoder * enc)625 static void radeon_enc_slice_header(struct radeon_encoder *enc)
626 {
627 struct pipe_h264_enc_seq_param *sps = &enc->enc_pic.h264.desc->seq;
628 struct pipe_h264_enc_pic_control *pps = &enc->enc_pic.h264.desc->pic_ctrl;
629 struct pipe_h264_enc_slice_param *slice = &enc->enc_pic.h264.desc->slice;
630 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
631 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
632 unsigned int inst_index = 0;
633 unsigned int cdw_start = 0;
634 unsigned int cdw_filled = 0;
635 unsigned int bits_copied = 0;
636 RADEON_ENC_BEGIN(enc->cmd.slice_header);
637 radeon_enc_reset(enc);
638 radeon_enc_set_emulation_prevention(enc, false);
639
640 cdw_start = enc->cs.current.cdw;
641 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR)
642 radeon_enc_code_fixed_bits(enc, 0x65, 8);
643 else if (enc->enc_pic.not_referenced)
644 radeon_enc_code_fixed_bits(enc, 0x01, 8);
645 else
646 radeon_enc_code_fixed_bits(enc, 0x41, 8);
647
648 radeon_enc_flush_headers(enc);
649 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
650 num_bits[inst_index] = enc->bits_output - bits_copied;
651 bits_copied = enc->bits_output;
652 inst_index++;
653
654 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
655 inst_index++;
656
657 switch (enc->enc_pic.picture_type) {
658 case PIPE_H2645_ENC_PICTURE_TYPE_I:
659 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
660 radeon_enc_code_fixed_bits(enc, 0x08, 7);
661 break;
662 case PIPE_H2645_ENC_PICTURE_TYPE_P:
663 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
664 radeon_enc_code_fixed_bits(enc, 0x06, 5);
665 break;
666 case PIPE_H2645_ENC_PICTURE_TYPE_B:
667 radeon_enc_code_fixed_bits(enc, 0x07, 5);
668 break;
669 default:
670 radeon_enc_code_fixed_bits(enc, 0x08, 7);
671 }
672
673 radeon_enc_code_ue(enc, 0x0); /* pic_parameter_set_id */
674 radeon_enc_code_fixed_bits(enc, slice->frame_num, sps->log2_max_frame_num_minus4 + 4);
675
676 if (enc->enc_pic.h264_enc_params.input_picture_structure !=
677 RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
678 radeon_enc_code_fixed_bits(enc, 0x1, 1);
679 radeon_enc_code_fixed_bits(enc,
680 enc->enc_pic.h264_enc_params.input_picture_structure ==
681 RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
682 ? 1
683 : 0,
684 1);
685 }
686
687 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR)
688 radeon_enc_code_ue(enc, slice->idr_pic_id);
689
690 if (sps->pic_order_cnt_type == 0)
691 radeon_enc_code_fixed_bits(enc, slice->pic_order_cnt_lsb, sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
692
693 if (pps->redundant_pic_cnt_present_flag)
694 radeon_enc_code_ue(enc, slice->redundant_pic_cnt);
695
696 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
697 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* direct_spatial_mv_pred_flag */
698
699 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P ||
700 enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) {
701 radeon_enc_code_fixed_bits(enc, slice->num_ref_idx_active_override_flag, 1);
702 if (slice->num_ref_idx_active_override_flag) {
703 radeon_enc_code_ue(enc, slice->num_ref_idx_l0_active_minus1);
704 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
705 radeon_enc_code_ue(enc, slice->num_ref_idx_l1_active_minus1);
706 }
707 radeon_enc_code_fixed_bits(enc, slice->ref_pic_list_modification_flag_l0, 1);
708 if (slice->ref_pic_list_modification_flag_l0) {
709 for (unsigned i = 0; i < slice->num_ref_list0_mod_operations; i++) {
710 struct pipe_h264_ref_list_mod_entry *op =
711 &slice->ref_list0_mod_operations[i];
712 radeon_enc_code_ue(enc, op->modification_of_pic_nums_idc);
713 if (op->modification_of_pic_nums_idc == 0 ||
714 op->modification_of_pic_nums_idc == 1)
715 radeon_enc_code_ue(enc, op->abs_diff_pic_num_minus1);
716 else if (op->modification_of_pic_nums_idc == 2)
717 radeon_enc_code_ue(enc, op->long_term_pic_num);
718 }
719 radeon_enc_code_ue(enc, 0x3); /* modification_of_pic_nums_idc */
720 }
721 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) {
722 radeon_enc_code_fixed_bits(enc, slice->ref_pic_list_modification_flag_l1, 1);
723 if (slice->ref_pic_list_modification_flag_l1) {
724 for (unsigned i = 0; i < slice->num_ref_list1_mod_operations; i++) {
725 struct pipe_h264_ref_list_mod_entry *op =
726 &slice->ref_list1_mod_operations[i];
727 radeon_enc_code_ue(enc, op->modification_of_pic_nums_idc);
728 if (op->modification_of_pic_nums_idc == 0 ||
729 op->modification_of_pic_nums_idc == 1)
730 radeon_enc_code_ue(enc, op->abs_diff_pic_num_minus1);
731 else if (op->modification_of_pic_nums_idc == 2)
732 radeon_enc_code_ue(enc, op->long_term_pic_num);
733 }
734 radeon_enc_code_ue(enc, 0x3); /* modification_of_pic_nums_idc */
735 }
736 }
737 }
738
739 if (!enc->enc_pic.not_referenced) {
740 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) {
741 radeon_enc_code_fixed_bits(enc, slice->no_output_of_prior_pics_flag, 1);
742 radeon_enc_code_fixed_bits(enc, slice->long_term_reference_flag, 1);
743 } else {
744 radeon_enc_code_fixed_bits(enc, slice->adaptive_ref_pic_marking_mode_flag, 1);
745 if (slice->adaptive_ref_pic_marking_mode_flag) {
746 for (unsigned i = 0; i < slice->num_ref_pic_marking_operations; i++) {
747 struct pipe_h264_ref_pic_marking_entry *op =
748 &slice->ref_pic_marking_operations[i];
749 radeon_enc_code_ue(enc, op->memory_management_control_operation);
750 if (op->memory_management_control_operation == 1 ||
751 op->memory_management_control_operation == 3)
752 radeon_enc_code_ue(enc, op->difference_of_pic_nums_minus1);
753 if (op->memory_management_control_operation == 2)
754 radeon_enc_code_ue(enc, op->long_term_pic_num);
755 if (op->memory_management_control_operation == 3 ||
756 op->memory_management_control_operation == 6)
757 radeon_enc_code_ue(enc, op->long_term_frame_idx);
758 if (op->memory_management_control_operation == 4)
759 radeon_enc_code_ue(enc, op->max_long_term_frame_idx_plus1);
760 }
761 radeon_enc_code_ue(enc, 0); /* memory_management_control_operation */
762 }
763 }
764 }
765
766 if ((enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) &&
767 (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_I) &&
768 (enc->enc_pic.spec_misc.cabac_enable))
769 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
770
771 radeon_enc_flush_headers(enc);
772 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
773 num_bits[inst_index] = enc->bits_output - bits_copied;
774 bits_copied = enc->bits_output;
775 inst_index++;
776
777 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
778 inst_index++;
779
780 if (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag) {
781 radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
782 if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
783 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
784 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
785 }
786 }
787
788 radeon_enc_flush_headers(enc);
789 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
790 num_bits[inst_index] = enc->bits_output - bits_copied;
791 bits_copied = enc->bits_output;
792 inst_index++;
793
794 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
795
796 cdw_filled = enc->cs.current.cdw - cdw_start;
797 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
798 RADEON_ENC_CS(0x00000000);
799
800 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
801 RADEON_ENC_CS(instruction[j]);
802 RADEON_ENC_CS(num_bits[j]);
803 }
804
805 RADEON_ENC_END();
806 }
807
radeon_enc_slice_header_hevc(struct radeon_encoder * enc)808 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
809 {
810 struct pipe_h265_enc_seq_param *sps = &enc->enc_pic.hevc.desc->seq;
811 struct pipe_h265_enc_pic_param *pps = &enc->enc_pic.hevc.desc->pic;
812 struct pipe_h265_enc_slice_param *slice = &enc->enc_pic.hevc.desc->slice;
813 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
814 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
815 unsigned int inst_index = 0;
816 unsigned int cdw_start = 0;
817 unsigned int cdw_filled = 0;
818 unsigned int bits_copied = 0;
819 unsigned int num_pic_total_curr = 0;
820 RADEON_ENC_BEGIN(enc->cmd.slice_header);
821 radeon_enc_reset(enc);
822 radeon_enc_set_emulation_prevention(enc, false);
823
824 cdw_start = enc->cs.current.cdw;
825 radeon_enc_code_fixed_bits(enc, 0x0, 1);
826 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
827 radeon_enc_code_fixed_bits(enc, 0x0, 6);
828 radeon_enc_code_fixed_bits(enc, enc->enc_pic.temporal_id + 1, 3);
829
830 radeon_enc_flush_headers(enc);
831 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
832 num_bits[inst_index] = enc->bits_output - bits_copied;
833 bits_copied = enc->bits_output;
834 inst_index++;
835
836 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
837 inst_index++;
838
839 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
840 radeon_enc_code_fixed_bits(enc, slice->no_output_of_prior_pics_flag, 1);
841
842 radeon_enc_code_ue(enc, 0x0); /* slice_pic_parameter_set_id */
843
844 radeon_enc_flush_headers(enc);
845 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
846 num_bits[inst_index] = enc->bits_output - bits_copied;
847 bits_copied = enc->bits_output;
848 inst_index++;
849
850 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
851 inst_index++;
852
853 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
854 inst_index++;
855
856 switch (enc->enc_pic.picture_type) {
857 case PIPE_H2645_ENC_PICTURE_TYPE_I:
858 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
859 radeon_enc_code_ue(enc, 0x2);
860 break;
861 case PIPE_H2645_ENC_PICTURE_TYPE_P:
862 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
863 radeon_enc_code_ue(enc, 0x1);
864 break;
865 case PIPE_H2645_ENC_PICTURE_TYPE_B:
866 radeon_enc_code_ue(enc, 0x0);
867 break;
868 default:
869 radeon_enc_code_ue(enc, 0x1);
870 }
871
872 if (pps->output_flag_present_flag)
873 radeon_enc_code_fixed_bits(enc, slice->pic_output_flag, 1);
874
875 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
876 radeon_enc_code_fixed_bits(enc, slice->slice_pic_order_cnt_lsb, sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
877 radeon_enc_code_fixed_bits(enc, slice->short_term_ref_pic_set_sps_flag, 1);
878 if (!slice->short_term_ref_pic_set_sps_flag) {
879 num_pic_total_curr =
880 radeon_enc_hevc_st_ref_pic_set(enc, sps->num_short_term_ref_pic_sets,
881 sps->num_short_term_ref_pic_sets, &slice->st_ref_pic_set);
882 } else if (sps->num_short_term_ref_pic_sets > 1) {
883 radeon_enc_code_fixed_bits(enc, slice->short_term_ref_pic_set_idx,
884 util_logbase2_ceil(sps->num_short_term_ref_pic_sets));
885 }
886 if (sps->long_term_ref_pics_present_flag) {
887 if (sps->num_long_term_ref_pics_sps > 0)
888 radeon_enc_code_ue(enc, slice->num_long_term_sps);
889 radeon_enc_code_ue(enc, slice->num_long_term_pics);
890 for (unsigned i = 0; i < slice->num_long_term_sps + slice->num_long_term_pics; i++) {
891 if (i < slice->num_long_term_sps) {
892 if (sps->num_long_term_ref_pics_sps > 1)
893 radeon_enc_code_fixed_bits(enc, slice->lt_idx_sps[i], util_logbase2_ceil(sps->num_long_term_ref_pics_sps));
894 } else {
895 radeon_enc_code_fixed_bits(enc, slice->poc_lsb_lt[i], sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
896 radeon_enc_code_fixed_bits(enc, slice->used_by_curr_pic_lt_flag[i], 1);
897 if (slice->used_by_curr_pic_lt_flag[i])
898 num_pic_total_curr++;
899 }
900 radeon_enc_code_fixed_bits(enc, slice->delta_poc_msb_present_flag[i], 1);
901 if (slice->delta_poc_msb_present_flag[i])
902 radeon_enc_code_ue(enc, slice->delta_poc_msb_cycle_lt[i]);
903 }
904 }
905 }
906
907 if (!enc->enc_pic.hevc_deblock.disable_sao) {
908 radeon_enc_flush_headers(enc);
909 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
910 num_bits[inst_index] = enc->bits_output - bits_copied;
911 bits_copied = enc->bits_output;
912 inst_index++;
913
914 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
915 inst_index++;
916 }
917
918 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
919 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
920 radeon_enc_code_fixed_bits(enc, slice->num_ref_idx_active_override_flag, 1);
921 if (slice->num_ref_idx_active_override_flag) {
922 radeon_enc_code_ue(enc, slice->num_ref_idx_l0_active_minus1);
923 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
924 radeon_enc_code_ue(enc, slice->num_ref_idx_l1_active_minus1);
925 }
926 if (pps->lists_modification_present_flag && num_pic_total_curr > 1) {
927 unsigned num_bits = util_logbase2_ceil(num_pic_total_curr);
928 unsigned num_ref_l0_minus1 = slice->num_ref_idx_active_override_flag ?
929 slice->num_ref_idx_l0_active_minus1 : pps->num_ref_idx_l0_default_active_minus1;
930 radeon_enc_code_fixed_bits(enc, slice->ref_pic_lists_modification.ref_pic_list_modification_flag_l0, 1);
931 for (unsigned i = 0; i <= num_ref_l0_minus1; i++)
932 radeon_enc_code_fixed_bits(enc, slice->ref_pic_lists_modification.list_entry_l0[i], num_bits);
933 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) {
934 unsigned num_ref_l1_minus1 = slice->num_ref_idx_active_override_flag ?
935 slice->num_ref_idx_l1_active_minus1 : pps->num_ref_idx_l1_default_active_minus1;
936 radeon_enc_code_fixed_bits(enc, slice->ref_pic_lists_modification.ref_pic_list_modification_flag_l1, 1);
937 for (unsigned i = 0; i <= num_ref_l1_minus1; i++)
938 radeon_enc_code_fixed_bits(enc, slice->ref_pic_lists_modification.list_entry_l1[i], num_bits);
939 }
940 }
941 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
942 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* mvd_l1_zero_flag */
943 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
944 radeon_enc_code_ue(enc, 5 - slice->max_num_merge_cand);
945 }
946
947 radeon_enc_flush_headers(enc);
948 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
949 num_bits[inst_index] = enc->bits_output - bits_copied;
950 bits_copied = enc->bits_output;
951 inst_index++;
952
953 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
954 inst_index++;
955
956 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
957 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
958 !enc->enc_pic.hevc_deblock.disable_sao)) {
959 if (!enc->enc_pic.hevc_deblock.disable_sao) {
960 radeon_enc_flush_headers(enc);
961 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
962 num_bits[inst_index] = enc->bits_output - bits_copied;
963 bits_copied = enc->bits_output;
964 inst_index++;
965
966 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
967 inst_index++;
968 } else {
969 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
970 radeon_enc_flush_headers(enc);
971 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
972 num_bits[inst_index] = enc->bits_output - bits_copied;
973 bits_copied = enc->bits_output;
974 inst_index++;
975 }
976 }
977
978 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
979
980 cdw_filled = enc->cs.current.cdw - cdw_start;
981 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
982 RADEON_ENC_CS(0x00000000);
983
984 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
985 RADEON_ENC_CS(instruction[j]);
986 RADEON_ENC_CS(num_bits[j]);
987 }
988
989 RADEON_ENC_END();
990 }
991
radeon_enc_hrd_parameters(struct radeon_encoder * enc,struct pipe_h264_enc_hrd_params * hrd)992 void radeon_enc_hrd_parameters(struct radeon_encoder *enc,
993 struct pipe_h264_enc_hrd_params *hrd)
994 {
995 radeon_enc_code_ue(enc, hrd->cpb_cnt_minus1);
996 radeon_enc_code_fixed_bits(enc, hrd->bit_rate_scale, 4);
997 radeon_enc_code_fixed_bits(enc, hrd->cpb_size_scale, 4);
998 for (unsigned i = 0; i <= hrd->cpb_cnt_minus1; i++) {
999 radeon_enc_code_ue(enc, hrd->bit_rate_value_minus1[i]);
1000 radeon_enc_code_ue(enc, hrd->cpb_size_value_minus1[i]);
1001 radeon_enc_code_fixed_bits(enc, hrd->cbr_flag[i], 1);
1002 }
1003 radeon_enc_code_fixed_bits(enc, hrd->initial_cpb_removal_delay_length_minus1, 5);
1004 radeon_enc_code_fixed_bits(enc, hrd->cpb_removal_delay_length_minus1, 5);
1005 radeon_enc_code_fixed_bits(enc, hrd->dpb_output_delay_length_minus1, 5);
1006 radeon_enc_code_fixed_bits(enc, hrd->time_offset_length, 5);
1007 }
1008
radeon_enc_hevc_profile_tier(struct radeon_encoder * enc,struct pipe_h265_profile_tier * pt)1009 static void radeon_enc_hevc_profile_tier(struct radeon_encoder *enc,
1010 struct pipe_h265_profile_tier *pt)
1011 {
1012 radeon_enc_code_fixed_bits(enc, pt->general_profile_space, 2);
1013 radeon_enc_code_fixed_bits(enc, pt->general_tier_flag, 1);
1014 radeon_enc_code_fixed_bits(enc, pt->general_profile_idc, 5);
1015 radeon_enc_code_fixed_bits(enc, pt->general_profile_compatibility_flag, 32);
1016 radeon_enc_code_fixed_bits(enc, pt->general_progressive_source_flag, 1);
1017 radeon_enc_code_fixed_bits(enc, pt->general_interlaced_source_flag, 1);
1018 radeon_enc_code_fixed_bits(enc, pt->general_non_packed_constraint_flag, 1);
1019 radeon_enc_code_fixed_bits(enc, pt->general_frame_only_constraint_flag, 1);
1020 /* general_reserved_zero_44bits */
1021 radeon_enc_code_fixed_bits(enc, 0x0, 16);
1022 radeon_enc_code_fixed_bits(enc, 0x0, 16);
1023 radeon_enc_code_fixed_bits(enc, 0x0, 12);
1024 }
1025
radeon_enc_hevc_profile_tier_level(struct radeon_encoder * enc,unsigned int max_num_sub_layers_minus1,struct pipe_h265_profile_tier_level * ptl)1026 void radeon_enc_hevc_profile_tier_level(struct radeon_encoder *enc,
1027 unsigned int max_num_sub_layers_minus1,
1028 struct pipe_h265_profile_tier_level *ptl)
1029 {
1030 unsigned i;
1031
1032 radeon_enc_hevc_profile_tier(enc, &ptl->profile_tier);
1033 radeon_enc_code_fixed_bits(enc, ptl->general_level_idc, 8);
1034
1035 for (i = 0; i < max_num_sub_layers_minus1; ++i) {
1036 radeon_enc_code_fixed_bits(enc, ptl->sub_layer_profile_present_flag[i], 1);
1037 radeon_enc_code_fixed_bits(enc, ptl->sub_layer_level_present_flag[i], 1);
1038 }
1039
1040 if (max_num_sub_layers_minus1 > 0) {
1041 for (i = max_num_sub_layers_minus1; i < 8; ++i)
1042 radeon_enc_code_fixed_bits(enc, 0x0, 2); /* reserved_zero_2bits */
1043 }
1044
1045 for (i = 0; i < max_num_sub_layers_minus1; ++i) {
1046 if (ptl->sub_layer_profile_present_flag[i])
1047 radeon_enc_hevc_profile_tier(enc, &ptl->sub_layer_profile_tier[i]);
1048
1049 if (ptl->sub_layer_level_present_flag[i])
1050 radeon_enc_code_fixed_bits(enc, ptl->sub_layer_level_idc[i], 8);
1051 }
1052 }
1053
radeon_enc_hevc_sub_layer_hrd_parameters(struct radeon_encoder * enc,unsigned int cpb_cnt,unsigned int sub_pic_hrd_params_present_flag,struct pipe_h265_enc_sublayer_hrd_params * hrd)1054 static void radeon_enc_hevc_sub_layer_hrd_parameters(struct radeon_encoder *enc,
1055 unsigned int cpb_cnt,
1056 unsigned int sub_pic_hrd_params_present_flag,
1057 struct pipe_h265_enc_sublayer_hrd_params *hrd)
1058 {
1059 for (unsigned i = 0; i < cpb_cnt; i++) {
1060 radeon_enc_code_ue(enc, hrd->bit_rate_value_minus1[i]);
1061 radeon_enc_code_ue(enc, hrd->cpb_size_value_minus1[i]);
1062 if (sub_pic_hrd_params_present_flag) {
1063 radeon_enc_code_ue(enc, hrd->cpb_size_du_value_minus1[i]);
1064 radeon_enc_code_ue(enc, hrd->bit_rate_du_value_minus1[i]);
1065 }
1066 radeon_enc_code_fixed_bits(enc, hrd->cbr_flag[i], 1);
1067 }
1068 }
1069
radeon_enc_hevc_hrd_parameters(struct radeon_encoder * enc,unsigned int common_inf_present_flag,unsigned int max_sub_layers_minus1,struct pipe_h265_enc_hrd_params * hrd)1070 void radeon_enc_hevc_hrd_parameters(struct radeon_encoder *enc,
1071 unsigned int common_inf_present_flag,
1072 unsigned int max_sub_layers_minus1,
1073 struct pipe_h265_enc_hrd_params *hrd)
1074 {
1075 if (common_inf_present_flag) {
1076 radeon_enc_code_fixed_bits(enc, hrd->nal_hrd_parameters_present_flag, 1);
1077 radeon_enc_code_fixed_bits(enc, hrd->vcl_hrd_parameters_present_flag, 1);
1078 if (hrd->nal_hrd_parameters_present_flag || hrd->vcl_hrd_parameters_present_flag) {
1079 radeon_enc_code_fixed_bits(enc, hrd->sub_pic_hrd_params_present_flag, 1);
1080 if (hrd->sub_pic_hrd_params_present_flag) {
1081 radeon_enc_code_fixed_bits(enc, hrd->tick_divisor_minus2, 8);
1082 radeon_enc_code_fixed_bits(enc, hrd->du_cpb_removal_delay_increment_length_minus1, 5);
1083 radeon_enc_code_fixed_bits(enc, hrd->sub_pic_hrd_params_present_flag, 1);
1084 radeon_enc_code_fixed_bits(enc, hrd->dpb_output_delay_du_length_minus1, 5);
1085 }
1086 radeon_enc_code_fixed_bits(enc, hrd->bit_rate_scale, 4);
1087 radeon_enc_code_fixed_bits(enc, hrd->cpb_rate_scale, 4);
1088 if (hrd->sub_pic_hrd_params_present_flag)
1089 radeon_enc_code_fixed_bits(enc, hrd->cpb_size_du_scale, 4);
1090 radeon_enc_code_fixed_bits(enc, hrd->initial_cpb_removal_delay_length_minus1, 5);
1091 radeon_enc_code_fixed_bits(enc, hrd->au_cpb_removal_delay_length_minus1, 5);
1092 radeon_enc_code_fixed_bits(enc, hrd->dpb_output_delay_length_minus1, 5);
1093 }
1094 }
1095
1096 for (unsigned i = 0; i <= max_sub_layers_minus1; i++) {
1097 radeon_enc_code_fixed_bits(enc, hrd->fixed_pic_rate_general_flag[i], 1);
1098 if (!hrd->fixed_pic_rate_general_flag[i])
1099 radeon_enc_code_fixed_bits(enc, hrd->fixed_pic_rate_within_cvs_flag[i], 1);
1100 if (hrd->fixed_pic_rate_within_cvs_flag[i])
1101 radeon_enc_code_ue(enc, hrd->elemental_duration_in_tc_minus1[i]);
1102 else
1103 radeon_enc_code_fixed_bits(enc, hrd->low_delay_hrd_flag[i], 1);
1104 if (!hrd->low_delay_hrd_flag[i])
1105 radeon_enc_code_ue(enc, hrd->cpb_cnt_minus1[i]);
1106 if (hrd->nal_hrd_parameters_present_flag) {
1107 radeon_enc_hevc_sub_layer_hrd_parameters(enc,
1108 hrd->cpb_cnt_minus1[i] + 1,
1109 hrd->sub_pic_hrd_params_present_flag,
1110 &hrd->nal_hrd_parameters[i]);
1111 }
1112 if (hrd->vcl_hrd_parameters_present_flag) {
1113 radeon_enc_hevc_sub_layer_hrd_parameters(enc,
1114 hrd->cpb_cnt_minus1[i] + 1,
1115 hrd->sub_pic_hrd_params_present_flag,
1116 &hrd->vlc_hrd_parameters[i]);
1117 }
1118 }
1119 }
1120
1121 /* returns NumPicTotalCurr */
radeon_enc_hevc_st_ref_pic_set(struct radeon_encoder * enc,unsigned int index,unsigned int num_short_term_ref_pic_sets,struct pipe_h265_st_ref_pic_set * st_rps)1122 unsigned int radeon_enc_hevc_st_ref_pic_set(struct radeon_encoder *enc,
1123 unsigned int index,
1124 unsigned int num_short_term_ref_pic_sets,
1125 struct pipe_h265_st_ref_pic_set *st_rps)
1126 {
1127 struct pipe_h265_st_ref_pic_set *ref_rps = NULL;
1128 struct pipe_h265_st_ref_pic_set *rps = &st_rps[index];
1129 unsigned i, num_pic_total_curr = 0;
1130
1131 if (index)
1132 radeon_enc_code_fixed_bits(enc, rps->inter_ref_pic_set_prediction_flag, 1);
1133
1134 if (rps->inter_ref_pic_set_prediction_flag) {
1135 if (index == num_short_term_ref_pic_sets)
1136 radeon_enc_code_ue(enc, rps->delta_idx_minus1);
1137 radeon_enc_code_fixed_bits(enc, rps->delta_rps_sign, 1);
1138 radeon_enc_code_ue(enc, rps->abs_delta_rps_minus1);
1139 ref_rps = st_rps + index +
1140 (1 - 2 * rps->delta_rps_sign) * (st_rps->delta_idx_minus1 + 1);
1141 for (i = 0; i <= (ref_rps->num_negative_pics + ref_rps->num_positive_pics); i++) {
1142 radeon_enc_code_fixed_bits(enc, rps->used_by_curr_pic_flag[i], 1);
1143 if (!rps->used_by_curr_pic_flag[i])
1144 radeon_enc_code_fixed_bits(enc, rps->use_delta_flag[i], 1);
1145 }
1146 } else {
1147 radeon_enc_code_ue(enc, rps->num_negative_pics);
1148 radeon_enc_code_ue(enc, rps->num_positive_pics);
1149 for (i = 0; i < rps->num_negative_pics; i++) {
1150 radeon_enc_code_ue(enc, rps->delta_poc_s0_minus1[i]);
1151 radeon_enc_code_fixed_bits(enc, rps->used_by_curr_pic_s0_flag[i], 1);
1152 if (rps->used_by_curr_pic_s0_flag[i])
1153 num_pic_total_curr++;
1154 }
1155 for (i = 0; i < st_rps->num_positive_pics; i++) {
1156 radeon_enc_code_ue(enc, rps->delta_poc_s1_minus1[i]);
1157 radeon_enc_code_fixed_bits(enc, rps->used_by_curr_pic_s1_flag[i], 1);
1158 if (rps->used_by_curr_pic_s1_flag[i])
1159 num_pic_total_curr++;
1160 }
1161 }
1162
1163 return num_pic_total_curr;
1164 }
1165
radeon_enc_ctx(struct radeon_encoder * enc)1166 static void radeon_enc_ctx(struct radeon_encoder *enc)
1167 {
1168 enc->enc_pic.ctx_buf.swizzle_mode = 0;
1169 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
1170
1171 RADEON_ENC_BEGIN(enc->cmd.ctx);
1172 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
1173 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
1174 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
1175 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
1176 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
1177
1178 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1179 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
1180 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
1181 }
1182
1183 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch);
1184 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch);
1185
1186 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1187 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].luma_offset);
1188 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].chroma_offset);
1189 }
1190
1191 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.yuv.luma_offset);
1192 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.yuv.chroma_offset);
1193
1194 RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);
1195 RADEON_ENC_END();
1196 }
1197
radeon_enc_bitstream(struct radeon_encoder * enc)1198 static void radeon_enc_bitstream(struct radeon_encoder *enc)
1199 {
1200 enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
1201 enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
1202 enc->enc_pic.bit_buf.video_bitstream_data_offset = enc->bs_offset;
1203
1204 RADEON_ENC_BEGIN(enc->cmd.bitstream);
1205 RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
1206 RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
1207 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
1208 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
1209 RADEON_ENC_END();
1210 }
1211
radeon_enc_feedback(struct radeon_encoder * enc)1212 static void radeon_enc_feedback(struct radeon_encoder *enc)
1213 {
1214 enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
1215 enc->enc_pic.fb_buf.feedback_buffer_size = 16;
1216 enc->enc_pic.fb_buf.feedback_data_size = 40;
1217
1218 RADEON_ENC_BEGIN(enc->cmd.feedback);
1219 RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
1220 RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
1221 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
1222 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
1223 RADEON_ENC_END();
1224 }
1225
radeon_enc_intra_refresh(struct radeon_encoder * enc)1226 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
1227 {
1228 RADEON_ENC_BEGIN(enc->cmd.intra_refresh);
1229 RADEON_ENC_CS(enc->enc_pic.intra_refresh.intra_refresh_mode);
1230 RADEON_ENC_CS(enc->enc_pic.intra_refresh.offset);
1231 RADEON_ENC_CS(enc->enc_pic.intra_refresh.region_size);
1232 RADEON_ENC_END();
1233 }
1234
radeon_enc_rc_per_pic(struct radeon_encoder * enc)1235 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
1236 {
1237 fprintf(stderr, "Warning: Obsoleted rate control is being used due to outdated VCN firmware on system.\n");
1238 fprintf(stderr, "Updating VCN firmware is highly recommended.\n");
1239 RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
1240 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp_obs);
1241 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app_obs);
1242 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app_obs);
1243 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size_obs);
1244 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
1245 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
1246 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
1247 RADEON_ENC_END();
1248 }
1249
radeon_enc_rc_per_pic_ex(struct radeon_encoder * enc)1250 static void radeon_enc_rc_per_pic_ex(struct radeon_encoder *enc)
1251 {
1252 RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
1253 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp_i);
1254 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp_p);
1255 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp_b);
1256 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_i);
1257 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_i);
1258 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_p);
1259 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_p);
1260 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_b);
1261 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_b);
1262 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size_i);
1263 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size_p);
1264 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size_b);
1265 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
1266 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
1267 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
1268 RADEON_ENC_END();
1269 }
1270
radeon_enc_encode_params(struct radeon_encoder * enc)1271 static void radeon_enc_encode_params(struct radeon_encoder *enc)
1272 {
1273 switch (enc->enc_pic.picture_type) {
1274 case PIPE_H2645_ENC_PICTURE_TYPE_I:
1275 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
1276 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1277 break;
1278 case PIPE_H2645_ENC_PICTURE_TYPE_P:
1279 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1280 break;
1281 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
1282 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1283 break;
1284 case PIPE_H2645_ENC_PICTURE_TYPE_B:
1285 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1286 break;
1287 default:
1288 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1289 }
1290
1291 if (enc->luma->meta_offset) {
1292 RVID_ERR("DCC surfaces not supported.\n");
1293 assert(false);
1294 }
1295
1296 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1297 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma ?
1298 enc->chroma->u.gfx9.surf_pitch : enc->luma->u.gfx9.surf_pitch;
1299 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
1300
1301 RADEON_ENC_BEGIN(enc->cmd.enc_params);
1302 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1303 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1304 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1305 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma ?
1306 enc->chroma->u.gfx9.surf_offset : enc->luma->u.gfx9.surf_pitch);
1307 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1308 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1309 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1310 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1311 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1312 RADEON_ENC_END();
1313 }
1314
radeon_enc_encode_params_h264(struct radeon_encoder * enc)1315 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1316 {
1317 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1318 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1319 enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1320 enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1321
1322 RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
1323 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1324 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1325 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1326 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1327 RADEON_ENC_END();
1328 }
1329
radeon_enc_encode_statistics(struct radeon_encoder * enc)1330 static void radeon_enc_encode_statistics(struct radeon_encoder *enc)
1331 {
1332 if (!enc->stats) return;
1333
1334 enc->enc_pic.enc_statistics.encode_stats_type = RENCODE_STATISTICS_TYPE_0;
1335
1336 RADEON_ENC_BEGIN(enc->cmd.enc_statistics);
1337 RADEON_ENC_CS(enc->enc_pic.enc_statistics.encode_stats_type);
1338 RADEON_ENC_WRITE(enc->stats, RADEON_DOMAIN_GTT, 0);
1339 RADEON_ENC_END();
1340 }
1341
radeon_enc_qp_map(struct radeon_encoder * enc)1342 static void radeon_enc_qp_map(struct radeon_encoder *enc)
1343 {
1344 RADEON_ENC_BEGIN(enc->cmd.enc_qp_map);
1345 RADEON_ENC_CS(enc->enc_pic.enc_qp_map.qp_map_type);
1346 if (enc->enc_pic.enc_qp_map.qp_map_type != RENCODE_QP_MAP_TYPE_NONE)
1347 RADEON_ENC_READWRITE(enc->roi->res->buf, enc->roi->res->domains, 0);
1348 else {
1349 RADEON_ENC_CS(0); /* use null for roi buffer */
1350 RADEON_ENC_CS(0); /* use null for roi buffer */
1351 }
1352 RADEON_ENC_CS(0); /* qp_map pitch set to 0 for the ib */
1353 RADEON_ENC_END();
1354 }
1355
radeon_enc_encode_latency(struct radeon_encoder * enc)1356 static void radeon_enc_encode_latency(struct radeon_encoder *enc)
1357 {
1358 RADEON_ENC_BEGIN(enc->cmd.enc_latency);
1359 RADEON_ENC_CS(enc->enc_pic.enc_latency.encode_latency);
1360 RADEON_ENC_END();
1361 }
1362
radeon_enc_op_init(struct radeon_encoder * enc)1363 static void radeon_enc_op_init(struct radeon_encoder *enc)
1364 {
1365 RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1366 RADEON_ENC_END();
1367 }
1368
radeon_enc_op_close(struct radeon_encoder * enc)1369 static void radeon_enc_op_close(struct radeon_encoder *enc)
1370 {
1371 RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1372 RADEON_ENC_END();
1373 }
1374
radeon_enc_op_enc(struct radeon_encoder * enc)1375 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1376 {
1377 RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1378 RADEON_ENC_END();
1379 }
1380
radeon_enc_op_init_rc(struct radeon_encoder * enc)1381 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1382 {
1383 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1384 RADEON_ENC_END();
1385 }
1386
radeon_enc_op_init_rc_vbv(struct radeon_encoder * enc)1387 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1388 {
1389 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1390 RADEON_ENC_END();
1391 }
1392
radeon_enc_op_preset(struct radeon_encoder * enc)1393 static void radeon_enc_op_preset(struct radeon_encoder *enc)
1394 {
1395 uint32_t preset_mode;
1396
1397 if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_QUALITY)
1398 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
1399 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_BALANCE)
1400 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
1401 else
1402 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
1403
1404 RADEON_ENC_BEGIN(preset_mode);
1405 RADEON_ENC_END();
1406 }
1407
begin(struct radeon_encoder * enc)1408 static void begin(struct radeon_encoder *enc)
1409 {
1410 unsigned i;
1411
1412 enc->session_info(enc);
1413 enc->total_task_size = 0;
1414 enc->task_info(enc, enc->need_feedback);
1415 enc->op_init(enc);
1416
1417 enc->session_init(enc);
1418 enc->slice_control(enc);
1419 enc->spec_misc(enc);
1420 enc->deblocking_filter(enc);
1421
1422 enc->layer_control(enc);
1423 enc->rc_session_init(enc);
1424 enc->quality_params(enc);
1425 enc->encode_latency(enc);
1426
1427 i = 0;
1428 do {
1429 enc->enc_pic.layer_sel.temporal_layer_index = i;
1430 enc->layer_select(enc);
1431 enc->rc_layer_init(enc);
1432 enc->layer_select(enc);
1433 enc->rc_per_pic(enc);
1434 } while (++i < enc->enc_pic.num_temporal_layers);
1435
1436 enc->op_init_rc(enc);
1437 enc->op_init_rc_vbv(enc);
1438 *enc->p_task_size = (enc->total_task_size);
1439 }
1440
radeon_enc_headers_h264(struct radeon_encoder * enc)1441 static void radeon_enc_headers_h264(struct radeon_encoder *enc)
1442 {
1443 enc->slice_header(enc);
1444 enc->encode_params(enc);
1445 enc->encode_params_codec_spec(enc);
1446 }
1447
radeon_enc_headers_hevc(struct radeon_encoder * enc)1448 static void radeon_enc_headers_hevc(struct radeon_encoder *enc)
1449 {
1450 enc->slice_header(enc);
1451 enc->encode_params(enc);
1452 enc->encode_params_codec_spec(enc);
1453 }
1454
encode(struct radeon_encoder * enc)1455 static void encode(struct radeon_encoder *enc)
1456 {
1457 unsigned i;
1458
1459 enc->before_encode(enc);
1460 enc->session_info(enc);
1461 enc->total_task_size = 0;
1462 enc->task_info(enc, enc->need_feedback);
1463
1464 if (enc->need_rate_control || enc->need_rc_per_pic) {
1465 i = 0;
1466 do {
1467 enc->enc_pic.layer_sel.temporal_layer_index = i;
1468 if (enc->need_rate_control) {
1469 enc->layer_select(enc);
1470 enc->rc_layer_init(enc);
1471 }
1472 if (enc->need_rc_per_pic) {
1473 enc->layer_select(enc);
1474 enc->rc_per_pic(enc);
1475 }
1476 } while (++i < enc->enc_pic.num_temporal_layers);
1477 }
1478
1479 enc->encode_headers(enc);
1480 enc->ctx(enc);
1481 enc->bitstream(enc);
1482 enc->feedback(enc);
1483 enc->intra_refresh(enc);
1484 enc->qp_map(enc);
1485
1486 enc->op_preset(enc);
1487 enc->op_enc(enc);
1488 *enc->p_task_size = (enc->total_task_size);
1489 }
1490
destroy(struct radeon_encoder * enc)1491 static void destroy(struct radeon_encoder *enc)
1492 {
1493 enc->session_info(enc);
1494 enc->total_task_size = 0;
1495 enc->task_info(enc, enc->need_feedback);
1496 enc->op_close(enc);
1497 *enc->p_task_size = (enc->total_task_size);
1498 }
1499
radeon_enc_1_2_init(struct radeon_encoder * enc)1500 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1501 {
1502 enc->before_encode = radeon_enc_dummy;
1503 enc->begin = begin;
1504 enc->encode = encode;
1505 enc->destroy = destroy;
1506 enc->session_info = radeon_enc_session_info;
1507 enc->task_info = radeon_enc_task_info;
1508 enc->layer_control = radeon_enc_layer_control;
1509 enc->layer_select = radeon_enc_layer_select;
1510 enc->rc_session_init = radeon_enc_rc_session_init;
1511 enc->rc_layer_init = radeon_enc_rc_layer_init;
1512 enc->quality_params = radeon_enc_quality_params;
1513 enc->ctx = radeon_enc_ctx;
1514 enc->bitstream = radeon_enc_bitstream;
1515 enc->feedback = radeon_enc_feedback;
1516 enc->intra_refresh = radeon_enc_intra_refresh;
1517 if (enc->enc_pic.use_rc_per_pic_ex == true)
1518 enc->rc_per_pic = radeon_enc_rc_per_pic_ex;
1519 else
1520 enc->rc_per_pic = radeon_enc_rc_per_pic;
1521 enc->encode_params = radeon_enc_encode_params;
1522 enc->op_init = radeon_enc_op_init;
1523 enc->op_close = radeon_enc_op_close;
1524 enc->op_enc = radeon_enc_op_enc;
1525 enc->op_init_rc = radeon_enc_op_init_rc;
1526 enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
1527 enc->op_preset = radeon_enc_op_preset;
1528 enc->session_init = radeon_enc_session_init;
1529 enc->encode_statistics = radeon_enc_encode_statistics;
1530 enc->qp_map = radeon_enc_qp_map;
1531 enc->encode_latency = radeon_enc_encode_latency;
1532
1533 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1534 enc->slice_control = radeon_enc_slice_control;
1535 enc->spec_misc = radeon_enc_spec_misc;
1536 enc->deblocking_filter = radeon_enc_deblocking_filter_h264;
1537 enc->slice_header = radeon_enc_slice_header;
1538 enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
1539 enc->encode_headers = radeon_enc_headers_h264;
1540 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1541 enc->slice_control = radeon_enc_slice_control_hevc;
1542 enc->spec_misc = radeon_enc_spec_misc_hevc;
1543 enc->deblocking_filter = radeon_enc_deblocking_filter_hevc;
1544 enc->slice_header = radeon_enc_slice_header_hevc;
1545 enc->encode_headers = radeon_enc_headers_hevc;
1546 enc->encode_params_codec_spec = radeon_enc_dummy;
1547 }
1548
1549 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
1550 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
1551 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
1552 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
1553 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
1554 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
1555 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
1556 if (enc->enc_pic.use_rc_per_pic_ex == true)
1557 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX;
1558 else
1559 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
1560 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
1561 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
1562 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
1563 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
1564 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
1565 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
1566 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
1567 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
1568 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
1569 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
1570 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
1571 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
1572 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
1573 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
1574 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
1575 enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
1576 enc->cmd.enc_qp_map = RENCODE_IB_PARAM_QP_MAP;
1577 enc->cmd.enc_latency = RENCODE_IB_PARAM_ENCODE_LATENCY;
1578
1579 enc->enc_pic.session_info.interface_version =
1580 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1581 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1582 }
1583