1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_MT8192_SRCLKEN_RC_H 4 #define SOC_MEDIATEK_MT8192_SRCLKEN_RC_H 5 6 #include <device/mmio.h> 7 8 struct mtk_rc_regs { 9 u32 srclken_rc_cfg; 10 u32 rc_central_cfg1; 11 u32 rc_central_cfg2; 12 u32 rc_cmd_arb_cfg; 13 u32 rc_pmic_rcen_addr; 14 u32 rc_pmic_rcen_set_clr_addr; 15 u32 rc_dcxo_fpm_cfg; 16 u32 rc_central_cfg3; 17 u32 rc_mxx_srclken_cfg[13]; 18 u32 srclken_sw_con_cfg; 19 u32 rc_central_cfg4; 20 u32 reserved1; 21 u32 rc_protocol_chk_cfg; 22 u32 rc_debug_cfg; 23 u32 reserved2[19]; 24 u32 rc_misc_0; 25 u32 rc_spm_ctrl; 26 u32 rc_subsys_intf_cfg; 27 }; 28 29 check_member(mtk_rc_regs, rc_central_cfg1, 0x4); 30 check_member(mtk_rc_regs, rc_mxx_srclken_cfg[0], 0x20); 31 check_member(mtk_rc_regs, rc_mxx_srclken_cfg[12], 0x50); 32 check_member(mtk_rc_regs, rc_central_cfg4, 0x58); 33 check_member(mtk_rc_regs, rc_protocol_chk_cfg, 0x60); 34 check_member(mtk_rc_regs, rc_misc_0, 0xb4); 35 check_member(mtk_rc_regs, rc_subsys_intf_cfg, 0xbc); 36 37 struct mtk_rc_status_regs { 38 u32 rc_fsm_sta_0; 39 u32 rc_cmd_sta_0; 40 u32 rc_cmd_sta_1; 41 u32 rc_spi_sta_0; 42 u32 rc_pi_po_sta_0; 43 u32 rc_mxx_req_sta_0[14]; 44 u32 reserved2[2]; 45 u32 rc_debug_trace; 46 }; 47 48 check_member(mtk_rc_status_regs, rc_cmd_sta_1, 0x8); 49 check_member(mtk_rc_status_regs, rc_mxx_req_sta_0[0], 0x14); 50 check_member(mtk_rc_status_regs, rc_mxx_req_sta_0[13], 0x48); 51 check_member(mtk_rc_status_regs, rc_debug_trace, 0x54); 52 53 /* SPM Register */ 54 /* SRCLKEN_RC_CFG */ 55 DEFINE_BIT(SW_RESET, 0) 56 DEFINE_BIT(CG_32K_EN, 1) 57 DEFINE_BIT(CG_FCLK_EN, 2) 58 DEFINE_BIT(CG_FCLK_FR_EN, 3) 59 DEFINE_BIT(MUX_FCLK_FR, 4) 60 61 /* RC_CENTRAL_CFG1 */ 62 DEFINE_BIT(SRCLKEN_RC_EN, 0) 63 DEFINE_BIT(RCEN_ISSUE_M, 1) 64 DEFINE_BIT(RC_SPI_ACTIVE, 2) 65 DEFINE_BIT(SRCLKEN_RC_EN_SEL, 3) 66 DEFINE_BITFIELD(VCORE_SETTLE_T, 7, 5) 67 DEFINE_BITFIELD(ULPOSC_SETTLE_T, 11, 8) 68 DEFINE_BITFIELD(NON_DCXO_SETTLE_T, 21, 12) 69 DEFINE_BITFIELD(DCXO_SETTLE_T, 31, 22) 70 71 /* RC_CENTRAL_CFG2 */ 72 DEFINE_BITFIELD(SRCVOLTEN_CTRL, 3, 0) 73 DEFINE_BITFIELD(VREQ_CTRL, 7, 4) 74 DEFINE_BIT(SRCVOLTEN_VREQ_SEL, 8) 75 DEFINE_BIT(SRCVOLTEN_VREQ_M, 9) 76 DEFINE_BITFIELD(ULPOSC_CTRL_M, 15, 12) 77 DEFINE_BITFIELD(PWRAP_SLP_CTRL_M, 24, 21) 78 DEFINE_BIT(PWRAP_SLP_MUX_SEL, 25) 79 80 /* RC_DCXO_FPM_CFG */ 81 DEFINE_BITFIELD(DCXO_FPM_CTRL_M, 3, 0) 82 DEFINE_BIT(SRCVOLTEN_FPM_MSK_B, 4) 83 DEFINE_BITFIELD(SUB_SRCLKEN_FPM_MSK_B, 28, 16) 84 85 /* RC_CENTRAL_CFG3 */ 86 DEFINE_BIT(TO_LPM_SETTLE_EN, 0) 87 DEFINE_BIT(BLK_SCP_DXCO_MD_TARGET, 1) 88 DEFINE_BIT(BLK_COANT_DXCO_MD_TARGET, 2) 89 DEFINE_BIT(TO_BBLPM_SETTLE_EN, 3) 90 DEFINE_BITFIELD(TO_LPM_SETTLE_T, 21, 12) 91 92 /* RC_CENTRAL_CFG4 */ 93 DEFINE_BITFIELD(KEEP_RC_SPI_ACTIVE, 8, 0) 94 DEFINE_BIT(PWRAP_VLD_FORCE, 16) 95 DEFINE_BIT(SLEEP_VLD_MODE, 17) 96 97 /* RC_MXX_SRCLKEN_CFG */ 98 DEFINE_BIT(DCXO_SETTLE_BLK_EN, 1) 99 DEFINE_BIT(BYPASS_CMD_EN, 2) 100 DEFINE_BIT(SW_SRCLKEN_RC, 3) 101 DEFINE_BIT(SW_SRCLKEN_FPM, 4) 102 DEFINE_BIT(SW_SRCLKEN_BBLPM, 5) 103 DEFINE_BIT(XO_SOC_LINK_EN, 6) 104 DEFINE_BIT(REQ_ACK_LOW_IMD_EN, 7) 105 DEFINE_BIT(SRCLKEN_TRACK_M_EN, 8) 106 DEFINE_BITFIELD(CNT_PRD_STEP, 11, 10) 107 DEFINE_BITFIELD(XO_STABLE_PRD, 21, 12) 108 DEFINE_BITFIELD(DCXO_STABLE_PRD, 31, 22) 109 110 enum { 111 SW_SRCLKEN_FPM_MSK = 0x1, 112 SW_SRCLKEN_BBLPM_MSK = 0x1, 113 }; 114 115 /* RC_DEBUG_CFG */ 116 DEFINE_BIT(TRACE_MODE_EN, 24) 117 118 /* SUBSYS_INTF_CFG */ 119 DEFINE_BITFIELD(SRCLKEN_FPM_MASK_B, 12, 0) 120 DEFINE_BITFIELD(SRCLKEN_BBLPM_MASK_B, 28, 16) 121 122 enum { 123 PMIC_PMRC_CON0 = 0x1A6, 124 PMIC_PMRC_CON0_SET = 0x1A8, 125 PMIC_PMRC_CON0_CLR = 0x1AA, 126 }; 127 128 enum chn_id { 129 CHN_SUSPEND = 0, 130 CHN_RF = 1, 131 CHN_DEEPIDLE = 2, 132 CHN_MD = 3, 133 CHN_GPS = 4, 134 CHN_BT = 5, 135 CHN_WIFI = 6, 136 CHN_MCU = 7, 137 CHN_COANT = 8, 138 CHN_NFC = 9, 139 CHN_UFS = 10, 140 CHN_SCP = 11, 141 CHN_RESERVE = 12, 142 MAX_CHN_NUM, 143 }; 144 145 enum { 146 SRCLKENAO_MODE, 147 VREQ_MODE, 148 }; 149 150 enum { 151 MERGE_OR_MODE = 0x0, 152 BYPASS_MODE = 0x1, 153 MERGE_AND_MODE = 0x1 << 1, 154 BYPASS_RC_MODE = 0x2 << 1, 155 BYPASS_OTHER_MODE = 0x3 << 1, 156 ASYNC_MODE = 0x1 << 3, 157 }; 158 159 enum { 160 RC_32K = 0, 161 RC_ULPOSC1, 162 }; 163 164 enum rc_ctrl_m { 165 HW_MODE = 0, 166 SW_MODE = 1, 167 INIT_MODE = 0xff, 168 }; 169 170 enum rc_support { 171 SRCLKEN_RC_ENABLE = 0, 172 SRCLKEN_RC_DISABLE, 173 }; 174 175 struct subsys_rc_con { 176 unsigned int dcxo_prd; 177 unsigned int xo_prd; 178 unsigned int cnt_step; 179 unsigned int track_en; 180 unsigned int req_ack_imd_en; 181 unsigned int xo_soc_link_en; 182 unsigned int sw_bblpm; 183 unsigned int sw_fpm; 184 unsigned int sw_rc; 185 unsigned int bypass_cmd; 186 unsigned int dcxo_settle_blk_en; 187 }; 188 189 int srclken_rc_init(void); 190 191 #endif /* SOC_MEDIATEK_MT8192_SRCLKEN_RC_H */ 192