1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef AM335X_UART_H 4 #define AM335X_UART_H 5 6 #include <stdint.h> 7 8 #define AM335X_UART0_BASE 0x44e09000 9 #define AM335X_UART1_BASE 0x48020000 10 #define AM335X_UART2_BASE 0x48024000 11 #define AM335X_UART3_BASE 0x481A6000 12 #define AM335X_UART4_BASE 0x481A8000 13 #define AM335X_UART5_BASE 0x481AA000 14 15 /* 16 * The meaning of some AM335x UART register offsets changes depending on read 17 * or write operation as well as various modes. See section 19.3.7.1.2 for 18 * register access submode description and 19.5.1 for register descriptions. 19 */ 20 struct am335x_uart { 21 union { 22 /* operational mode */ 23 uint16_t rhr; /* receiver holding (read) */ 24 uint16_t thr; /* transmit holding (write) */ 25 /* config mode A and B */ 26 uint16_t dll; /* divisor latches low */ 27 }; 28 uint8_t rsvd_0x02[2]; 29 union { 30 /* operational mode */ 31 uint16_t ier; /* interrupt enable */ 32 /* config mode A and B */ 33 uint16_t dlh; /* divisor latches high */ 34 }; 35 uint8_t rsvd_0x06[2]; 36 union { 37 /* operational mode, config mode A */ 38 uint16_t iir; /* interrupt ID (read) */ 39 uint16_t fcr; /* FIFO control (write) */ 40 /* config mode B */ 41 uint16_t efr; 42 }; 43 uint8_t rsvd_0x0a[2]; 44 uint16_t lcr; /* line control */ 45 uint8_t rsvd_0x0e[2]; 46 47 /* 0x10 */ 48 union { 49 /* operational mode, config mode A */ 50 uint16_t mcr; /* modem control */ 51 /* config mode B */ 52 uint16_t xon1; /* XON1 character (UART mode) */ 53 uint16_t addr1; /* address 1 (IrDA mode) */ 54 }; 55 uint8_t rsvd_0x12[2]; 56 union { 57 /* operational mode, config mode A */ 58 uint16_t lsr; /* line status, read-only */ 59 /* config mode B */ 60 uint16_t xon2; /* XON2 character (UART mode) */ 61 uint16_t addr2; /* IrDA mode (IrDA mode) */ 62 }; 63 uint8_t rsvd_0x16[2]; 64 65 /* 66 * Bytes 0x18 and 0x1c depend on submode TCR_TLR. When EFR[4] = 1 and 67 * MCR[6] = 1, transmission control register and trigger level register 68 * will be read/written. If not, the modem status register and the 69 * scratchpad register will be affected by read/write. 70 */ 71 union { 72 /* operational mode and config mode A */ 73 uint16_t msr; /* modem status */ 74 /* config mode B */ 75 uint16_t xoff1; /* xoff1 character (UART MODE) */ 76 /* submode TCR_TLR */ 77 uint16_t tcr; /* transmission control */ 78 }; 79 uint8_t rsvd_0x1a[2]; 80 union { 81 uint16_t spr; /* scratchpad */ 82 /* config mode B */ 83 uint16_t xoff2; /* xoff2 character (UART mode) */ 84 /* submode TCR_TLR */ 85 uint16_t tlr; /* trigger level */ 86 }; 87 uint8_t rsvd_0x1e[2]; 88 89 /* 0x20 */ 90 uint16_t mdr1; /* mode definition 1 */ 91 uint8_t rsvd_0x22[2]; 92 uint16_t mdr2; /* mode definition 2 */ 93 uint8_t rsvd_0x26[2]; 94 union { 95 uint16_t sflsr; /* status FIFO line status reg (read) */ 96 uint16_t txfll; /* transmit frame length low (write) */ 97 }; 98 uint8_t rsvd_0x2a[2]; 99 union { 100 uint16_t resume; /* resume halted operation (read) */ 101 uint16_t txflh; /* transmit frame length high (write) */ 102 }; 103 uint8_t rsvd_0x2e[2]; 104 105 /* 0x30 */ 106 union { 107 uint16_t sfregl; /* status FIFO low (read) */ 108 uint16_t rxfll; /* received frame length low (write) */ 109 }; 110 uint8_t rsvd_0x32[2]; 111 union { 112 uint16_t sfregh; /* status FIFO high (read) */ 113 uint16_t rxflh; /* received frame length high (write) */ 114 }; 115 uint8_t rsvd_0x36[2]; 116 uint16_t blr; /* BOF control */ 117 uint8_t rsvd_0x3a[2]; 118 uint16_t acreg; /* auxiliary control */ 119 uint8_t rsvd_0x3e[2]; 120 121 /* 0x40 */ 122 uint16_t scr; /* supplementary control */ 123 uint8_t rsvd_0x42[2]; 124 uint16_t ssr; /* supplementary status */ 125 uint8_t rsvd_0x46[2]; 126 127 uint16_t eblr; /* BOF length (operational mode only) */ 128 uint8_t rsvd_0x4a[6]; 129 130 /* 0x50 */ 131 uint16_t mvr; /* module version (read-only) */ 132 uint8_t rsvd_0x52[2]; 133 uint16_t sysc; /* system config */ 134 uint8_t rsvd_0x56[2]; 135 uint16_t syss; /* system status (read-only) */ 136 uint8_t rsvd_0x5a[2]; 137 uint16_t wer; /* wake-up enable */ 138 uint8_t rsvd_0x5e[2]; 139 140 /* 0x60 */ 141 uint16_t cfps; /* carrier prescale frequency */ 142 uint8_t rsvd_0x62[2]; 143 uint16_t rxfifo_lvl; /* received FIFO level */ 144 uint8_t rsvd_0x66[2]; 145 uint16_t txfifo_lvl; /* transmit FIFO level */ 146 uint8_t rsvd_0x6a[2]; 147 uint16_t ier2; /* RX/TX FIFO empty interrupt enable */ 148 uint8_t rsvd_0x6e[2]; 149 150 /* 0x70 */ 151 uint16_t isr2; /* RX/TX FIFO empty interrupt status */ 152 uint8_t rsvd_0x72[2]; 153 uint16_t freq_sel; /* frequency select */ 154 uint8_t rsvd_0x76[10]; 155 156 /* 0x80 */ 157 uint16_t mdr3; /* mode definition register 3 */ 158 uint8_t rsvd_0x82[2]; 159 uint16_t txdma; /* TX DMA threshold */ 160 161 } __packed; 162 163 #endif /* AM335X_UART_H */ 164