1 /** 2 * \file 3 * 4 * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM. 5 * 6 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef UART_H_INCLUDED 48 #define UART_H_INCLUDED 49 50 #include "compiler.h" 51 52 /// @cond 0 53 /**INDENT-OFF**/ 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 /**INDENT-ON**/ 58 /// @endcond 59 60 /* UART internal div factor for sampling */ 61 #define UART_MCK_DIV 16 62 /* Div factor to get the maximum baud rate */ 63 #define UART_MCK_DIV_MIN_FACTOR 1 64 /* Div factor to get the minimum baud rate */ 65 #define UART_MCK_DIV_MAX_FACTOR 65535 66 67 /*! \brief Option list for UART peripheral initialization */ 68 typedef struct sam_uart_opt { 69 /** MCK for UART */ 70 uint32_t ul_mck; 71 /** Expected baud rate */ 72 uint32_t ul_baudrate; 73 /** Initialize value for UART mode register */ 74 uint32_t ul_mode; 75 } sam_uart_opt_t; 76 77 uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt); 78 void uart_enable_tx(Uart *p_uart); 79 void uart_disable_tx(Uart *p_uart); 80 void uart_reset_tx(Uart *p_uart); 81 void uart_enable_rx(Uart *p_uart); 82 void uart_disable_rx(Uart *p_uart); 83 void uart_reset_rx(Uart *p_uart); 84 void uart_enable(Uart *p_uart); 85 void uart_disable(Uart *p_uart); 86 void uart_reset(Uart *p_uart); 87 void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources); 88 void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources); 89 uint32_t uart_get_interrupt_mask(Uart *p_uart); 90 uint32_t uart_get_status(Uart *p_uart); 91 void uart_reset_status(Uart *p_uart); 92 uint32_t uart_is_tx_ready(Uart *p_uart); 93 uint32_t uart_is_tx_empty(Uart *p_uart); 94 uint32_t uart_is_rx_ready(Uart *p_uart); 95 uint32_t uart_is_tx_buf_empty(Uart *p_uart); 96 void uart_set_clock_divisor(Uart *p_uart, uint16_t us_divisor); 97 uint32_t uart_write(Uart *p_uart, const uint8_t uc_data); 98 uint32_t uart_read(Uart *p_uart, uint8_t *puc_data); 99 #if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) 100 uint32_t uart_is_rx_buf_end(Uart *p_uart); 101 uint32_t uart_is_tx_buf_end(Uart *p_uart); 102 uint32_t uart_is_rx_buf_full(Uart *p_uart); 103 Pdc *uart_get_pdc_base(Uart *p_uart); 104 #endif 105 #if (SAMG53 || SAMG54 || SAMV71 || SAMV70 || SAME70 || SAMS70) 106 void uart_set_sleepwalking(Uart *p_uart, uint8_t ul_low_value, 107 bool cmpmode, bool cmppar, uint8_t ul_high_value); 108 void uart_set_write_protection(Uart *p_uart, bool flag); 109 #endif 110 111 #if (SAM4C || SAM4CP || SAM4CM) 112 enum uart_optical_duty_cycle { 113 UART_MOD_CLK_DUTY_50_00 = UART_MR_OPT_DUTY_DUTY_50, 114 UART_MOD_CLK_DUTY_43_75 = UART_MR_OPT_DUTY_DUTY_43P75, 115 UART_MOD_CLK_DUTY_37_50 = UART_MR_OPT_DUTY_DUTY_37P5, 116 UART_MOD_CLK_DUTY_31_25 = UART_MR_OPT_DUTY_DUTY_31P25, 117 UART_MOD_CLK_DUTY_25_00 = UART_MR_OPT_DUTY_DUTY_25, 118 UART_MOD_CLK_DUTY_18_75 = UART_MR_OPT_DUTY_DUTY_18P75, 119 UART_MOD_CLK_DUTY_12_50 = UART_MR_OPT_DUTY_DUTY_12P5, 120 UART_MOD_CLK_DUTY_06_25 = UART_MR_OPT_DUTY_DUTY_6P25, 121 }; 122 123 enum uart_optical_cmp_threshold { 124 UART_RX_CMP_THRESHOLD_VDDIO_DIV_10_0 = UART_MR_OPT_CMPTH_VDDIO_DIV10, 125 UART_RX_CMP_THRESHOLD_VDDIO_DIV_5_0 = UART_MR_OPT_CMPTH_VDDIO_DIV5, 126 UART_RX_CMP_THRESHOLD_VDDIO_DIV_3_3 = UART_MR_OPT_CMPTH_VDDIO_DIV3P3, 127 UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_5 = UART_MR_OPT_CMPTH_VDDIO_DIV2P5, 128 UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_0 = UART_MR_OPT_CMPTH_VDDIO_DIV2, 129 }; 130 131 struct uart_config_optical { 132 /* UART Receive Data Inverted */ 133 bool rx_inverted; 134 /* UART Modulated Data Inverted */ 135 bool tx_inverted; 136 /* UART Receiver Digital Filter */ 137 bool rx_filter; 138 /* Optical Link Clock Divider */ 139 uint8_t clk_div; 140 /* Optical Link Modulation Clock Duty Cycle */ 141 enum uart_optical_duty_cycle duty; 142 /* Receive Path Comparator Threshold */ 143 enum uart_optical_cmp_threshold threshold; 144 }; 145 146 void uart_enable_optical_interface(Uart *p_uart); 147 void uart_disable_optical_interface(Uart *p_uart); 148 void uart_config_optical_interface(Uart *p_uart, 149 struct uart_config_optical *cfg); 150 #endif 151 152 /// @cond 0 153 /**INDENT-OFF**/ 154 #ifdef __cplusplus 155 } 156 #endif 157 /**INDENT-ON**/ 158 /// @endcond 159 160 #endif /* UART_H_INCLUDED */ 161